How to purchase a UP 3 board

UP 3 Design Examples

RAZZLE - Creates a Fractal type VGA color image with 640 by 480 pixels without using memory.  Very simple design that contains just the basics of VGA video signal generation. Video Demo Movie (mpeg). VHDL source code is included. Currently compiled for a Cyclone EP1C6Q240 FPGA.

Color Bar produces a video image with 27 color bars. Even though the hardware supports only 8 colors directly it is possible to produce 27 colors using a double rate pixel clock. Currently compiled for a Cyclone EP1C6Q240 FPGA.

UP 3 Clock is a clock/timer that uses the UP3's LCD to display the current time. A VHDL-based state machine is used to communicate with the LCD display controller. SW8 resets the time. VHDL source code is included. Currently compiled for a Cyclone EP1C6Q240 FPGA.

LC2 - is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 in a larger model, TOP_LC2  that adds video output. Push buttons reset and single step the processor and a video output display of registers is generated. This state machine VHDL-based model of the LC-2 includes all source files.  Currently compiled for a Cyclone EP1C6Q240 FPGA.

UP3bot design from Rapid Prototyping of Digital Systems Quartus II Edition

Here are several UP 3 demos (*.sof FPGA programming files only) from Rapid Prototyping of Digital Systems Quartus II Editionnow available from Springer Publishing ISBN 0-387-27728-5. Source code and documentation can be found in the book and CD-ROM. Demos are compiled for a UP3 with a Cyclone EP1C6Q240 FPGA.

NOTE: Right click and use Save Target As for the *.sof programming files below:
PS/2 keyboard demo – displays keyboard make and break scan codes in hex on the LCD
PS/2 mouse demo – displays mouse data on the LCD
Moving Ball video display – displays a moving ball on a VGA monitor
MIPS Processor core – runs a short MIPS program on the MIPS processor core from Patterson and Hennessey, Computer Organization and Design on a VGA monitor and the LCD. Pushbuttons reset and single step the processor.

Available in Rapid Prototyping of Digital Systems: A complete NIOS II UP 3 hardware and software tutorial – develops a Nios II hardware design and runs a short C program on a NIOS II processor that blinks the LEDs and tests the UP3's  memory and I/O. Uses SOPC Builder and the NIOS II IDE tool to download and run.
 

UP 3 Hardware Reference Manual
UP 3 Schematic
        UP 3 Cyclone FPGA
Cyclone FPGA Chip Vol 1. -  EP1C6Q240 or EP1C12Q240C8
Cyclone FPGA Chip Vol 1 Part 1. -  EP1C6Q240 or EP1C12Q240C8
Cyclone FPGA Chip Vol 2. -  EP1C6Q240 or EP1C12Q240C8
        UP 3 Memory Devices
Serial Configuration Device for FPGA  -  EPCS1
Flash Memory Chip - 2MB - TC58FVB106AFT-70
SRAM Memory Chip - 128K bytes - IS61C6416
SDRAM Memory Chip - 8MB - IS42S16400B
        UP 3 I/O Devices
System Clock Chip  -  PI6C106
I2C Realtime Clock Chip  -  M41T00
I2C Serial EEPROM  - 16K bits -  IS24C16
Reset Chip - TL7705BCP
LCD Module - GDM1602A   and LCD controller timing here
USB Phy Chip - 1T11A
Serial Port Voltage Level Convertor Chip  -  MAX3243
3V to 5V conversion   Bus switch IDTQS3384

I2C Bus Summary
Serial, Parallel, and USB books & links
Software to monitor Serial and USB ports on a PC
Interfacing external hardware with the Santa Cruz Expansion

First UP3 Design Tutorial from SLS
Second UP3 Design Tutorial from SLS
NIOS II UP3 Design Tutorial from SLS
Introduction to Quartus
Quartus Reference Manual Vol. 1
Quartus Reference Manual Vol. 2
Quartus Reference Manual Vol. 3
NIOS II Processor Manuals
Ram Megafunction User Guide
Quartus Web Version Software
SLS site for UP 3 Board
 
 
 

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