Timing Analyzer report for DE1_i2sound Thu Sep 28 19:55:19 2006 Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Timing Analyzer Summary 3. Timing Analyzer Settings 4. Clock Settings Summary 5. Clock Setup: 'KEY[0]' 6. Clock Setup: 'CLOCK_50' 7. tsu 8. tco 9. tpd 10. th 11. Timing Analyzer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2006 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Timing Analyzer Summary ; +------------------------------+-------+---------------+----------------------------------+--------------------------------------------------+------------------------------------------+------------+----------+--------------+ ; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; +------------------------------+-------+---------------+----------------------------------+--------------------------------------------------+------------------------------------------+------------+----------+--------------+ ; Worst-case tsu ; N/A ; None ; 2.264 ns ; I2C_SDAT ; I2C_AV_Config:u1|I2C_Controller:u0|ACK1 ; -- ; CLOCK_50 ; 0 ; ; Worst-case tco ; N/A ; None ; 16.767 ns ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_SCLK ; CLOCK_50 ; -- ; 0 ; ; Worst-case tpd ; N/A ; None ; 9.521 ns ; AUD_ADCDAT ; AUD_DACLRCK ; -- ; -- ; 0 ; ; Worst-case th ; N/A ; None ; -0.852 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[5] ; -- ; CLOCK_50 ; 0 ; ; Clock Setup: 'CLOCK_50' ; N/A ; None ; 205.72 MHz ( period = 4.861 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|mI2C_DATA[6] ; CLOCK_50 ; CLOCK_50 ; 0 ; ; Clock Setup: 'KEY[0]' ; N/A ; None ; 354.23 MHz ( period = 2.823 ns ) ; VOL[2] ; VOL[1] ; KEY[0] ; KEY[0] ; 0 ; ; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; +------------------------------+-------+---------------+----------------------------------+--------------------------------------------------+------------------------------------------+------------+----------+--------------+ +------------------------------------------------------------------------------------------------------+ ; Timing Analyzer Settings ; +-------------------------------------------------------+--------------------+------+----+-------------+ ; Option ; Setting ; From ; To ; Entity Name ; +-------------------------------------------------------+--------------------+------+----+-------------+ ; Device Name ; EP2C20F484C7 ; ; ; ; ; Timing Models ; Final ; ; ; ; ; Number of source nodes to report per destination node ; 10 ; ; ; ; ; Number of destination nodes to report ; 10 ; ; ; ; ; Number of paths to report ; 200 ; ; ; ; ; Report Minimum Timing Checks ; Off ; ; ; ; ; Use Fast Timing Models ; Off ; ; ; ; ; Report IO Paths Separately ; Off ; ; ; ; ; Default hold multicycle ; Same As Multicycle ; ; ; ; ; Cut paths between unrelated clock domains ; On ; ; ; ; ; Cut off read during write signal paths ; On ; ; ; ; ; Cut off feedback from I/O pins ; On ; ; ; ; ; Report Combined Fast/Slow Timing ; Off ; ; ; ; ; Ignore Clock Settings ; Off ; ; ; ; ; Analyze latches as synchronous elements ; On ; ; ; ; ; Enable Recovery/Removal analysis ; Off ; ; ; ; ; Enable Clock Latency ; Off ; ; ; ; ; Use TimeQuest Timing Analyzer ; Off ; ; ; ; +-------------------------------------------------------+--------------------+------+----+-------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clock Settings Summary ; +--------------------------------------+--------------------+------------+------------------+---------------+--------------+-------------+-----------------------+---------------------+-----------+--------------+ ; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ; +--------------------------------------+--------------------+------------+------------------+---------------+--------------+-------------+-----------------------+---------------------+-----------+--------------+ ; PLL:u0|altpll:altpll_component|_clk0 ; ; PLL output ; 18.41 MHz ; 0.000 ns ; 0.000 ns ; CLOCK_27[0] ; 15 ; 22 ; -2.443 ns ; ; ; CLOCK_27[0] ; ; User Pin ; 27.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; ; KEY[0] ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; ; CLOCK_50 ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; +--------------------------------------+--------------------+------------+------------------+---------------+--------------+-------------+-----------------------+---------------------+-----------+--------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clock Setup: 'KEY[0]' ; +-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+ ; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; +-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+ ; N/A ; 354.23 MHz ( period = 2.823 ns ) ; VOL[2] ; VOL[0] ; KEY[0] ; KEY[0] ; None ; None ; 2.584 ns ; ; N/A ; 354.23 MHz ( period = 2.823 ns ) ; VOL[2] ; VOL[6] ; KEY[0] ; KEY[0] ; None ; None ; 2.584 ns ; ; N/A ; 354.23 MHz ( period = 2.823 ns ) ; VOL[2] ; VOL[4] ; KEY[0] ; KEY[0] ; None ; None ; 2.584 ns ; ; N/A ; 354.23 MHz ( period = 2.823 ns ) ; VOL[2] ; VOL[5] ; KEY[0] ; KEY[0] ; None ; None ; 2.584 ns ; ; N/A ; 354.23 MHz ( period = 2.823 ns ) ; VOL[2] ; VOL[2] ; KEY[0] ; KEY[0] ; None ; None ; 2.584 ns ; ; N/A ; 354.23 MHz ( period = 2.823 ns ) ; VOL[2] ; VOL[3] ; KEY[0] ; KEY[0] ; None ; None ; 2.584 ns ; ; N/A ; 354.23 MHz ( period = 2.823 ns ) ; VOL[2] ; VOL[1] ; KEY[0] ; KEY[0] ; None ; None ; 2.584 ns ; ; N/A ; 375.66 MHz ( period = 2.662 ns ) ; VOL[3] ; VOL[0] ; KEY[0] ; KEY[0] ; None ; None ; 2.423 ns ; ; N/A ; 375.66 MHz ( period = 2.662 ns ) ; VOL[3] ; VOL[6] ; KEY[0] ; KEY[0] ; None ; None ; 2.423 ns ; ; N/A ; 375.66 MHz ( period = 2.662 ns ) ; VOL[3] ; VOL[4] ; KEY[0] ; KEY[0] ; None ; None ; 2.423 ns ; ; N/A ; 375.66 MHz ( period = 2.662 ns ) ; VOL[3] ; VOL[5] ; KEY[0] ; KEY[0] ; None ; None ; 2.423 ns ; ; N/A ; 375.66 MHz ( period = 2.662 ns ) ; VOL[3] ; VOL[2] ; KEY[0] ; KEY[0] ; None ; None ; 2.423 ns ; ; N/A ; 375.66 MHz ( period = 2.662 ns ) ; VOL[3] ; VOL[3] ; KEY[0] ; KEY[0] ; None ; None ; 2.423 ns ; ; N/A ; 375.66 MHz ( period = 2.662 ns ) ; VOL[3] ; VOL[1] ; KEY[0] ; KEY[0] ; None ; None ; 2.423 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[6] ; VOL[0] ; KEY[0] ; KEY[0] ; None ; None ; 1.916 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[6] ; VOL[6] ; KEY[0] ; KEY[0] ; None ; None ; 1.916 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[6] ; VOL[4] ; KEY[0] ; KEY[0] ; None ; None ; 1.916 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[6] ; VOL[5] ; KEY[0] ; KEY[0] ; None ; None ; 1.916 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[6] ; VOL[2] ; KEY[0] ; KEY[0] ; None ; None ; 1.916 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[6] ; VOL[3] ; KEY[0] ; KEY[0] ; None ; None ; 1.916 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[6] ; VOL[1] ; KEY[0] ; KEY[0] ; None ; None ; 1.916 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[0] ; VOL[6] ; KEY[0] ; KEY[0] ; None ; None ; 1.881 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[0] ; VOL[5] ; KEY[0] ; KEY[0] ; None ; None ; 1.801 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[1] ; VOL[6] ; KEY[0] ; KEY[0] ; None ; None ; 1.748 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[4] ; VOL[0] ; KEY[0] ; KEY[0] ; None ; None ; 1.725 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[4] ; VOL[6] ; KEY[0] ; KEY[0] ; None ; None ; 1.725 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[4] ; VOL[4] ; KEY[0] ; KEY[0] ; None ; None ; 1.725 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[4] ; VOL[5] ; KEY[0] ; KEY[0] ; None ; None ; 1.725 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[4] ; VOL[2] ; KEY[0] ; KEY[0] ; None ; None ; 1.725 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[4] ; VOL[3] ; KEY[0] ; KEY[0] ; None ; None ; 1.725 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[4] ; VOL[1] ; KEY[0] ; KEY[0] ; None ; None ; 1.725 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[0] ; VOL[4] ; KEY[0] ; KEY[0] ; None ; None ; 1.721 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[1] ; VOL[5] ; KEY[0] ; KEY[0] ; None ; None ; 1.668 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[0] ; VOL[3] ; KEY[0] ; KEY[0] ; None ; None ; 1.641 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[1] ; VOL[4] ; KEY[0] ; KEY[0] ; None ; None ; 1.588 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[5] ; VOL[0] ; KEY[0] ; KEY[0] ; None ; None ; 1.569 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[5] ; VOL[6] ; KEY[0] ; KEY[0] ; None ; None ; 1.569 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[5] ; VOL[4] ; KEY[0] ; KEY[0] ; None ; None ; 1.569 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[5] ; VOL[5] ; KEY[0] ; KEY[0] ; None ; None ; 1.569 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[5] ; VOL[2] ; KEY[0] ; KEY[0] ; None ; None ; 1.569 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[5] ; VOL[3] ; KEY[0] ; KEY[0] ; None ; None ; 1.569 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[5] ; VOL[1] ; KEY[0] ; KEY[0] ; None ; None ; 1.569 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[0] ; VOL[2] ; KEY[0] ; KEY[0] ; None ; None ; 1.561 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[1] ; VOL[3] ; KEY[0] ; KEY[0] ; None ; None ; 1.508 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[0] ; VOL[1] ; KEY[0] ; KEY[0] ; None ; None ; 1.481 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[1] ; VOL[2] ; KEY[0] ; KEY[0] ; None ; None ; 1.428 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[0] ; VOL[0] ; KEY[0] ; KEY[0] ; None ; None ; 1.051 ns ; ; N/A ; Restricted to 405.02 MHz ( period = 2.469 ns ) ; VOL[1] ; VOL[1] ; KEY[0] ; KEY[0] ; None ; None ; 0.966 ns ; +-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clock Setup: 'CLOCK_50' ; +-----------------------------------------+-----------------------------------------------------+--------------------------------------------------+--------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ ; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; +-----------------------------------------+-----------------------------------------------------+--------------------------------------------------+--------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ ; N/A ; 205.72 MHz ( period = 4.861 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|mI2C_DATA[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.631 ns ; ; N/A ; 205.72 MHz ( period = 4.861 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|mI2C_DATA[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.631 ns ; ; N/A ; 205.72 MHz ( period = 4.861 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|mI2C_DATA[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.631 ns ; ; N/A ; 205.72 MHz ( period = 4.861 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|mI2C_DATA[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.631 ns ; ; N/A ; 205.72 MHz ( period = 4.861 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|mI2C_DATA[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.631 ns ; ; N/A ; 205.72 MHz ( period = 4.861 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|mI2C_DATA[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.631 ns ; ; N/A ; 208.42 MHz ( period = 4.798 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|mI2C_DATA[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.568 ns ; ; N/A ; 208.42 MHz ( period = 4.798 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|mI2C_DATA[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.568 ns ; ; N/A ; 208.42 MHz ( period = 4.798 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|mI2C_DATA[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.568 ns ; ; N/A ; 208.42 MHz ( period = 4.798 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|mI2C_DATA[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.568 ns ; ; N/A ; 208.42 MHz ( period = 4.798 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|mI2C_DATA[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.568 ns ; ; N/A ; 208.42 MHz ( period = 4.798 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|mI2C_DATA[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.568 ns ; ; N/A ; 214.04 MHz ( period = 4.672 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|mI2C_DATA[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.442 ns ; ; N/A ; 214.04 MHz ( period = 4.672 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|mI2C_DATA[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.442 ns ; ; N/A ; 214.04 MHz ( period = 4.672 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|mI2C_DATA[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.442 ns ; ; N/A ; 214.04 MHz ( period = 4.672 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|mI2C_DATA[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.442 ns ; ; N/A ; 214.04 MHz ( period = 4.672 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|mI2C_DATA[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.442 ns ; ; N/A ; 214.04 MHz ( period = 4.672 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|mI2C_DATA[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.442 ns ; ; N/A ; 217.49 MHz ( period = 4.598 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|mI2C_DATA[12] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.367 ns ; ; N/A ; 217.49 MHz ( period = 4.598 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|mI2C_DATA[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.367 ns ; ; N/A ; 217.49 MHz ( period = 4.598 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|mI2C_DATA[9] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.367 ns ; ; N/A ; 217.49 MHz ( period = 4.598 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|mI2C_DATA[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.367 ns ; ; N/A ; 217.49 MHz ( period = 4.598 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|mI2C_DATA[11] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.367 ns ; ; N/A ; 217.49 MHz ( period = 4.598 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|mI2C_DATA[10] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.367 ns ; ; N/A ; 219.20 MHz ( period = 4.562 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; I2C_AV_Config:u1|I2C_Controller:u0|SDO ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.330 ns ; ; N/A ; 220.51 MHz ( period = 4.535 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|mI2C_DATA[12] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.304 ns ; ; N/A ; 220.51 MHz ( period = 4.535 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|mI2C_DATA[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.304 ns ; ; N/A ; 220.51 MHz ( period = 4.535 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|mI2C_DATA[9] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.304 ns ; ; N/A ; 220.51 MHz ( period = 4.535 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|mI2C_DATA[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.304 ns ; ; N/A ; 220.51 MHz ( period = 4.535 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|mI2C_DATA[11] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.304 ns ; ; N/A ; 220.51 MHz ( period = 4.535 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|mI2C_DATA[10] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.304 ns ; ; N/A ; 221.34 MHz ( period = 4.518 ns ) ; I2C_AV_Config:u1|LUT_INDEX[0] ; I2C_AV_Config:u1|mI2C_DATA[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.288 ns ; ; N/A ; 221.34 MHz ( period = 4.518 ns ) ; I2C_AV_Config:u1|LUT_INDEX[0] ; I2C_AV_Config:u1|mI2C_DATA[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.288 ns ; ; N/A ; 221.34 MHz ( period = 4.518 ns ) ; I2C_AV_Config:u1|LUT_INDEX[0] ; I2C_AV_Config:u1|mI2C_DATA[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.288 ns ; ; N/A ; 221.34 MHz ( period = 4.518 ns ) ; I2C_AV_Config:u1|LUT_INDEX[0] ; I2C_AV_Config:u1|mI2C_DATA[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.288 ns ; ; N/A ; 221.34 MHz ( period = 4.518 ns ) ; I2C_AV_Config:u1|LUT_INDEX[0] ; I2C_AV_Config:u1|mI2C_DATA[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.288 ns ; ; N/A ; 221.34 MHz ( period = 4.518 ns ) ; I2C_AV_Config:u1|LUT_INDEX[0] ; I2C_AV_Config:u1|mI2C_DATA[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.288 ns ; ; N/A ; 221.63 MHz ( period = 4.512 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.273 ns ; ; N/A ; 223.61 MHz ( period = 4.472 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.233 ns ; ; N/A ; 225.63 MHz ( period = 4.432 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.193 ns ; ; N/A ; 226.81 MHz ( period = 4.409 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|mI2C_DATA[12] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.178 ns ; ; N/A ; 226.81 MHz ( period = 4.409 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|mI2C_DATA[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.178 ns ; ; N/A ; 226.81 MHz ( period = 4.409 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|mI2C_DATA[9] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.178 ns ; ; N/A ; 226.81 MHz ( period = 4.409 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|mI2C_DATA[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.178 ns ; ; N/A ; 226.81 MHz ( period = 4.409 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|mI2C_DATA[11] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.178 ns ; ; N/A ; 226.81 MHz ( period = 4.409 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|mI2C_DATA[10] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.178 ns ; ; N/A ; 227.69 MHz ( period = 4.392 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.153 ns ; ; N/A ; 228.68 MHz ( period = 4.373 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.134 ns ; ; N/A ; 229.78 MHz ( period = 4.352 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.113 ns ; ; N/A ; 231.91 MHz ( period = 4.312 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.073 ns ; ; N/A ; 232.94 MHz ( period = 4.293 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.054 ns ; ; N/A ; 234.08 MHz ( period = 4.272 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.033 ns ; ; N/A ; 235.02 MHz ( period = 4.255 ns ) ; I2C_AV_Config:u1|LUT_INDEX[0] ; I2C_AV_Config:u1|mI2C_DATA[12] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.024 ns ; ; N/A ; 235.02 MHz ( period = 4.255 ns ) ; I2C_AV_Config:u1|LUT_INDEX[0] ; I2C_AV_Config:u1|mI2C_DATA[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.024 ns ; ; N/A ; 235.02 MHz ( period = 4.255 ns ) ; I2C_AV_Config:u1|LUT_INDEX[0] ; I2C_AV_Config:u1|mI2C_DATA[9] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.024 ns ; ; N/A ; 235.02 MHz ( period = 4.255 ns ) ; I2C_AV_Config:u1|LUT_INDEX[0] ; I2C_AV_Config:u1|mI2C_DATA[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.024 ns ; ; N/A ; 235.02 MHz ( period = 4.255 ns ) ; I2C_AV_Config:u1|LUT_INDEX[0] ; I2C_AV_Config:u1|mI2C_DATA[11] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.024 ns ; ; N/A ; 235.02 MHz ( period = 4.255 ns ) ; I2C_AV_Config:u1|LUT_INDEX[0] ; I2C_AV_Config:u1|mI2C_DATA[10] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.024 ns ; ; N/A ; 236.29 MHz ( period = 4.232 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.993 ns ; ; N/A ; 237.08 MHz ( period = 4.218 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD[4] ; I2C_AV_Config:u1|I2C_Controller:u0|SDO ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.970 ns ; ; N/A ; 237.36 MHz ( period = 4.213 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.974 ns ; ; N/A ; 237.59 MHz ( period = 4.209 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.970 ns ; ; N/A ; 238.55 MHz ( period = 4.192 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.953 ns ; ; N/A ; 240.04 MHz ( period = 4.166 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SDO ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.934 ns ; ; N/A ; 240.85 MHz ( period = 4.152 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.913 ns ; ; N/A ; 241.95 MHz ( period = 4.133 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.894 ns ; ; N/A ; 242.19 MHz ( period = 4.129 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.890 ns ; ; N/A ; 246.73 MHz ( period = 4.053 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.814 ns ; ; N/A ; 246.97 MHz ( period = 4.049 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.810 ns ; ; N/A ; 248.02 MHz ( period = 4.032 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_AV_Config:u1|I2C_Controller:u0|SDO ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.800 ns ; ; N/A ; 249.07 MHz ( period = 4.015 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|LUT_INDEX[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.776 ns ; ; N/A ; 249.19 MHz ( period = 4.013 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|LUT_INDEX[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.774 ns ; ; N/A ; 251.95 MHz ( period = 3.969 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.730 ns ; ; N/A ; 253.04 MHz ( period = 3.952 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|LUT_INDEX[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.713 ns ; ; N/A ; 253.16 MHz ( period = 3.950 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|LUT_INDEX[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.711 ns ; ; N/A ; 255.89 MHz ( period = 3.908 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.669 ns ; ; N/A ; 257.14 MHz ( period = 3.889 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.650 ns ; ; N/A ; 258.06 MHz ( period = 3.875 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD[10] ; I2C_AV_Config:u1|I2C_Controller:u0|SDO ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.636 ns ; ; N/A ; 259.13 MHz ( period = 3.859 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.636 ns ; ; N/A ; 261.23 MHz ( period = 3.828 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.589 ns ; ; N/A ; 261.37 MHz ( period = 3.826 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|LUT_INDEX[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.587 ns ; ; N/A ; 261.51 MHz ( period = 3.824 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|LUT_INDEX[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.585 ns ; ; N/A ; 263.09 MHz ( period = 3.801 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.578 ns ; ; N/A ; 263.44 MHz ( period = 3.796 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|LUT_INDEX[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.557 ns ; ; N/A ; 263.44 MHz ( period = 3.796 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.564 ns ; ; N/A ; 263.44 MHz ( period = 3.796 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[9] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.564 ns ; ; N/A ; 263.44 MHz ( period = 3.796 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.564 ns ; ; N/A ; 266.31 MHz ( period = 3.755 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.516 ns ; ; N/A ; 266.81 MHz ( period = 3.748 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.509 ns ; ; N/A ; 267.52 MHz ( period = 3.738 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.506 ns ; ; N/A ; 267.52 MHz ( period = 3.738 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[9] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.506 ns ; ; N/A ; 267.52 MHz ( period = 3.738 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.506 ns ; ; N/A ; 267.88 MHz ( period = 3.733 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|LUT_INDEX[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.494 ns ; ; N/A ; 269.18 MHz ( period = 3.715 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.476 ns ; ; N/A ; 272.33 MHz ( period = 3.672 ns ) ; I2C_AV_Config:u1|LUT_INDEX[0] ; I2C_AV_Config:u1|LUT_INDEX[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.433 ns ; ; N/A ; 272.48 MHz ( period = 3.670 ns ) ; I2C_AV_Config:u1|LUT_INDEX[0] ; I2C_AV_Config:u1|LUT_INDEX[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.431 ns ; ; N/A ; 272.63 MHz ( period = 3.668 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.429 ns ; ; N/A ; 273.15 MHz ( period = 3.661 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.438 ns ; ; N/A ; 274.35 MHz ( period = 3.645 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_AV_Config:u1|I2C_Controller:u0|SDO ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.413 ns ; ; N/A ; 276.55 MHz ( period = 3.616 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.377 ns ; ; N/A ; 277.24 MHz ( period = 3.607 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|LUT_INDEX[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.368 ns ; ; N/A ; 277.70 MHz ( period = 3.601 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; I2C_AV_Config:u1|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.362 ns ; ; N/A ; 277.70 MHz ( period = 3.601 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; I2C_AV_Config:u1|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.362 ns ; ; N/A ; 277.70 MHz ( period = 3.601 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; I2C_AV_Config:u1|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.362 ns ; ; N/A ; 277.70 MHz ( period = 3.601 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; I2C_AV_Config:u1|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.362 ns ; ; N/A ; 277.70 MHz ( period = 3.601 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; I2C_AV_Config:u1|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.362 ns ; ; N/A ; 277.70 MHz ( period = 3.601 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; I2C_AV_Config:u1|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.362 ns ; ; N/A ; 277.70 MHz ( period = 3.601 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; I2C_AV_Config:u1|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.362 ns ; ; N/A ; 277.70 MHz ( period = 3.601 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; I2C_AV_Config:u1|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.362 ns ; ; N/A ; 277.70 MHz ( period = 3.601 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; I2C_AV_Config:u1|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.362 ns ; ; N/A ; 277.70 MHz ( period = 3.601 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; I2C_AV_Config:u1|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.362 ns ; ; N/A ; 277.70 MHz ( period = 3.601 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.362 ns ; ; N/A ; 277.70 MHz ( period = 3.601 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.362 ns ; ; N/A ; 277.70 MHz ( period = 3.601 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.362 ns ; ; N/A ; 277.70 MHz ( period = 3.601 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; I2C_AV_Config:u1|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.362 ns ; ; N/A ; 277.70 MHz ( period = 3.601 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; I2C_AV_Config:u1|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.362 ns ; ; N/A ; 277.70 MHz ( period = 3.601 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; I2C_AV_Config:u1|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.362 ns ; ; N/A ; 277.93 MHz ( period = 3.598 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.366 ns ; ; N/A ; 277.93 MHz ( period = 3.598 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[9] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.366 ns ; ; N/A ; 277.93 MHz ( period = 3.598 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.366 ns ; ; N/A ; 278.71 MHz ( period = 3.588 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.349 ns ; ; N/A ; 279.17 MHz ( period = 3.582 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|mI2C_GO ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.344 ns ; ; N/A ; 279.17 MHz ( period = 3.582 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|mSetup_ST.01 ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.344 ns ; ; N/A ; 279.17 MHz ( period = 3.582 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|mSetup_ST.10 ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.344 ns ; ; N/A ; 279.17 MHz ( period = 3.582 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|mSetup_ST.00 ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.344 ns ; ; N/A ; 279.80 MHz ( period = 3.574 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; I2C_AV_Config:u1|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.335 ns ; ; N/A ; 279.80 MHz ( period = 3.574 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; I2C_AV_Config:u1|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.335 ns ; ; N/A ; 279.80 MHz ( period = 3.574 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; I2C_AV_Config:u1|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.335 ns ; ; N/A ; 279.80 MHz ( period = 3.574 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; I2C_AV_Config:u1|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.335 ns ; ; N/A ; 279.80 MHz ( period = 3.574 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; I2C_AV_Config:u1|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.335 ns ; ; N/A ; 279.80 MHz ( period = 3.574 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; I2C_AV_Config:u1|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.335 ns ; ; N/A ; 279.80 MHz ( period = 3.574 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; I2C_AV_Config:u1|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.335 ns ; ; N/A ; 279.80 MHz ( period = 3.574 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; I2C_AV_Config:u1|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.335 ns ; ; N/A ; 279.80 MHz ( period = 3.574 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; I2C_AV_Config:u1|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.335 ns ; ; N/A ; 279.80 MHz ( period = 3.574 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; I2C_AV_Config:u1|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.335 ns ; ; N/A ; 279.80 MHz ( period = 3.574 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.335 ns ; ; N/A ; 279.80 MHz ( period = 3.574 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.335 ns ; ; N/A ; 279.80 MHz ( period = 3.574 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.335 ns ; ; N/A ; 279.80 MHz ( period = 3.574 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; I2C_AV_Config:u1|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.335 ns ; ; N/A ; 279.80 MHz ( period = 3.574 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; I2C_AV_Config:u1|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.335 ns ; ; N/A ; 279.80 MHz ( period = 3.574 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; I2C_AV_Config:u1|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.335 ns ; ; N/A ; 282.41 MHz ( period = 3.541 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[5] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.302 ns ; ; N/A ; 284.01 MHz ( period = 3.521 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[12] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.289 ns ; ; N/A ; 284.01 MHz ( period = 3.521 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.289 ns ; ; N/A ; 284.01 MHz ( period = 3.521 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.289 ns ; ; N/A ; 284.01 MHz ( period = 3.521 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.289 ns ; ; N/A ; 284.01 MHz ( period = 3.521 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[10] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.289 ns ; ; N/A ; 284.01 MHz ( period = 3.521 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[11] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.289 ns ; ; N/A ; 284.17 MHz ( period = 3.519 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|mI2C_GO ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.281 ns ; ; N/A ; 284.17 MHz ( period = 3.519 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|mSetup_ST.01 ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.281 ns ; ; N/A ; 284.17 MHz ( period = 3.519 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|mSetup_ST.10 ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.281 ns ; ; N/A ; 284.17 MHz ( period = 3.519 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|mSetup_ST.00 ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.281 ns ; ; N/A ; 285.96 MHz ( period = 3.497 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.274 ns ; ; N/A ; 287.94 MHz ( period = 3.473 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD[9] ; I2C_AV_Config:u1|I2C_Controller:u0|SDO ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.234 ns ; ; N/A ; 288.77 MHz ( period = 3.463 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[12] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.231 ns ; ; N/A ; 288.77 MHz ( period = 3.463 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.231 ns ; ; N/A ; 288.77 MHz ( period = 3.463 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.231 ns ; ; N/A ; 288.77 MHz ( period = 3.463 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.231 ns ; ; N/A ; 288.77 MHz ( period = 3.463 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[10] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.231 ns ; ; N/A ; 288.77 MHz ( period = 3.463 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[11] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.231 ns ; ; N/A ; 288.93 MHz ( period = 3.461 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[5] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.222 ns ; ; N/A ; 289.44 MHz ( period = 3.455 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_AV_Config:u1|I2C_Controller:u0|SCLK ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.222 ns ; ; N/A ; 289.60 MHz ( period = 3.453 ns ) ; I2C_AV_Config:u1|LUT_INDEX[0] ; I2C_AV_Config:u1|LUT_INDEX[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.214 ns ; ; N/A ; 289.69 MHz ( period = 3.452 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.213 ns ; ; N/A ; 290.28 MHz ( period = 3.445 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; I2C_AV_Config:u1|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.206 ns ; ; N/A ; 290.28 MHz ( period = 3.445 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; I2C_AV_Config:u1|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.206 ns ; ; N/A ; 290.28 MHz ( period = 3.445 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; I2C_AV_Config:u1|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.206 ns ; ; N/A ; 290.28 MHz ( period = 3.445 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; I2C_AV_Config:u1|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.206 ns ; ; N/A ; 290.28 MHz ( period = 3.445 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; I2C_AV_Config:u1|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.206 ns ; ; N/A ; 290.28 MHz ( period = 3.445 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; I2C_AV_Config:u1|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.206 ns ; ; N/A ; 290.28 MHz ( period = 3.445 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; I2C_AV_Config:u1|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.206 ns ; ; N/A ; 290.28 MHz ( period = 3.445 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; I2C_AV_Config:u1|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.206 ns ; ; N/A ; 290.28 MHz ( period = 3.445 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; I2C_AV_Config:u1|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.206 ns ; ; N/A ; 290.28 MHz ( period = 3.445 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; I2C_AV_Config:u1|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.206 ns ; ; N/A ; 290.28 MHz ( period = 3.445 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; I2C_AV_Config:u1|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.206 ns ; ; N/A ; 290.28 MHz ( period = 3.445 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; I2C_AV_Config:u1|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.206 ns ; ; N/A ; 290.28 MHz ( period = 3.445 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.206 ns ; ; N/A ; 290.28 MHz ( period = 3.445 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; I2C_AV_Config:u1|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.206 ns ; ; N/A ; 290.28 MHz ( period = 3.445 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; I2C_AV_Config:u1|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.206 ns ; ; N/A ; 290.28 MHz ( period = 3.445 ns ) ; I2C_AV_Config:u1|mI2C_CLK_DIV[2] ; I2C_AV_Config:u1|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.206 ns ; ; N/A ; 290.53 MHz ( period = 3.442 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD[6] ; I2C_AV_Config:u1|I2C_Controller:u0|SDO ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.204 ns ; ; N/A ; 291.21 MHz ( period = 3.434 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD[7] ; I2C_AV_Config:u1|I2C_Controller:u0|SDO ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.195 ns ; ; N/A ; 291.21 MHz ( period = 3.434 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.202 ns ; ; N/A ; 291.21 MHz ( period = 3.434 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[9] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.202 ns ; ; N/A ; 291.21 MHz ( period = 3.434 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.202 ns ; ; N/A ; 292.91 MHz ( period = 3.414 ns ) ; I2C_AV_Config:u1|LUT_INDEX[3] ; I2C_AV_Config:u1|LUT_INDEX[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.175 ns ; ; N/A ; 294.72 MHz ( period = 3.393 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|mI2C_GO ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.155 ns ; ; N/A ; 294.72 MHz ( period = 3.393 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|mSetup_ST.01 ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.155 ns ; ; N/A ; 294.72 MHz ( period = 3.393 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|mSetup_ST.10 ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.155 ns ; ; N/A ; 294.72 MHz ( period = 3.393 ns ) ; I2C_AV_Config:u1|LUT_INDEX[2] ; I2C_AV_Config:u1|mSetup_ST.00 ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.155 ns ; ; N/A ; 295.77 MHz ( period = 3.381 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[5] ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.142 ns ; ; N/A ; 298.24 MHz ( period = 3.353 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[0] ; I2C_AV_Config:u1|I2C_Controller:u0|ACK2 ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.114 ns ; ; N/A ; 298.42 MHz ( period = 3.351 ns ) ; I2C_AV_Config:u1|LUT_INDEX[1] ; I2C_AV_Config:u1|LUT_INDEX[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.112 ns ; ; N/A ; 298.60 MHz ( period = 3.349 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD[11] ; I2C_AV_Config:u1|I2C_Controller:u0|SDO ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.110 ns ; ; N/A ; 299.22 MHz ( period = 3.342 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_AV_Config:u1|I2C_Controller:u0|ACK2 ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.103 ns ; ; N/A ; 300.93 MHz ( period = 3.323 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[12] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.091 ns ; ; N/A ; 300.93 MHz ( period = 3.323 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.091 ns ; ; N/A ; 300.93 MHz ( period = 3.323 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.091 ns ; ; N/A ; 300.93 MHz ( period = 3.323 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.091 ns ; ; N/A ; 300.93 MHz ( period = 3.323 ns ) ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[10] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.091 ns ; ; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; +-----------------------------------------+-----------------------------------------------------+--------------------------------------------------+--------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ +-----------------------------------------------------------------------------------------------------+ ; tsu ; +-------+--------------+------------+----------+-------------------------------------------+----------+ ; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ; +-------+--------------+------------+----------+-------------------------------------------+----------+ ; N/A ; None ; 2.264 ns ; I2C_SDAT ; I2C_AV_Config:u1|I2C_Controller:u0|ACK1 ; CLOCK_50 ; ; N/A ; None ; 2.026 ns ; I2C_SDAT ; I2C_AV_Config:u1|I2C_Controller:u0|ACK2 ; CLOCK_50 ; ; N/A ; None ; 1.758 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[1] ; CLOCK_50 ; ; N/A ; None ; 1.758 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[2] ; CLOCK_50 ; ; N/A ; None ; 1.758 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[4] ; CLOCK_50 ; ; N/A ; None ; 1.758 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[3] ; CLOCK_50 ; ; N/A ; None ; 1.758 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[5] ; CLOCK_50 ; ; N/A ; None ; 1.758 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[6] ; CLOCK_50 ; ; N/A ; None ; 1.687 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[4] ; CLOCK_50 ; ; N/A ; None ; 1.624 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[2] ; CLOCK_50 ; ; N/A ; None ; 1.624 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[9] ; CLOCK_50 ; ; N/A ; None ; 1.624 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[7] ; CLOCK_50 ; ; N/A ; None ; 1.574 ns ; I2C_SDAT ; I2C_AV_Config:u1|I2C_Controller:u0|ACK3 ; CLOCK_50 ; ; N/A ; None ; 1.495 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[12] ; CLOCK_50 ; ; N/A ; None ; 1.495 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[0] ; CLOCK_50 ; ; N/A ; None ; 1.495 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[9] ; CLOCK_50 ; ; N/A ; None ; 1.495 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[7] ; CLOCK_50 ; ; N/A ; None ; 1.495 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[11] ; CLOCK_50 ; ; N/A ; None ; 1.495 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[10] ; CLOCK_50 ; ; N/A ; None ; 1.349 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[12] ; CLOCK_50 ; ; N/A ; None ; 1.349 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[1] ; CLOCK_50 ; ; N/A ; None ; 1.349 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[0] ; CLOCK_50 ; ; N/A ; None ; 1.349 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[3] ; CLOCK_50 ; ; N/A ; None ; 1.349 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[10] ; CLOCK_50 ; ; N/A ; None ; 1.349 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[11] ; CLOCK_50 ; ; N/A ; None ; 1.100 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[6] ; CLOCK_50 ; ; N/A ; None ; 1.100 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[5] ; CLOCK_50 ; +-------+--------------+------------+----------+-------------------------------------------+----------+ +---------------------------------------------------------------------------------------------------------------+ ; tco ; +-------+--------------+------------+--------------------------------------------------+----------+-------------+ ; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ; +-------+--------------+------------+--------------------------------------------------+----------+-------------+ ; N/A ; None ; 16.767 ns ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; I2C_SCLK ; CLOCK_50 ; ; N/A ; None ; 16.700 ns ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; I2C_SCLK ; CLOCK_50 ; ; N/A ; None ; 16.484 ns ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; I2C_SCLK ; CLOCK_50 ; ; N/A ; None ; 16.346 ns ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[0] ; I2C_SCLK ; CLOCK_50 ; ; N/A ; None ; 16.290 ns ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; I2C_SCLK ; CLOCK_50 ; ; N/A ; None ; 15.358 ns ; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[5] ; I2C_SCLK ; CLOCK_50 ; ; N/A ; None ; 14.426 ns ; I2C_AV_Config:u1|I2C_Controller:u0|SCLK ; I2C_SCLK ; CLOCK_50 ; ; N/A ; None ; 13.990 ns ; I2C_AV_Config:u1|I2C_Controller:u0|SDO ; I2C_SDAT ; CLOCK_50 ; ; N/A ; None ; 11.895 ns ; I2C_AV_Config:u1|mI2C_CTRL_CLK ; I2C_SCLK ; CLOCK_50 ; ; N/A ; None ; 11.505 ns ; VOL[6] ; LEDG[6] ; KEY[0] ; ; N/A ; None ; 11.472 ns ; VOL[5] ; LEDG[5] ; KEY[0] ; ; N/A ; None ; 11.465 ns ; VOL[4] ; LEDG[4] ; KEY[0] ; ; N/A ; None ; 11.465 ns ; VOL[1] ; LEDG[1] ; KEY[0] ; ; N/A ; None ; 11.446 ns ; VOL[2] ; LEDG[2] ; KEY[0] ; ; N/A ; None ; 11.443 ns ; VOL[3] ; LEDG[3] ; KEY[0] ; ; N/A ; None ; 11.103 ns ; VOL[0] ; LEDG[0] ; KEY[0] ; ; N/A ; None ; 2.905 ns ; PLL:u0|altpll:altpll_component|_clk0 ; AUD_XCK ; CLOCK_27[0] ; +-------+--------------+------------+--------------------------------------------------+----------+-------------+ +------------------------------------------------------------------------+ ; tpd ; +-------+-------------------+-----------------+------------+-------------+ ; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; +-------+-------------------+-----------------+------------+-------------+ ; N/A ; None ; 9.521 ns ; AUD_ADCDAT ; AUD_DACLRCK ; +-------+-------------------+-----------------+------------+-------------+ +-----------------------------------------------------------------------------------------------------------+ ; th ; +---------------+-------------+-----------+----------+-------------------------------------------+----------+ ; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ; +---------------+-------------+-----------+----------+-------------------------------------------+----------+ ; N/A ; None ; -0.852 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[6] ; CLOCK_50 ; ; N/A ; None ; -0.852 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[5] ; CLOCK_50 ; ; N/A ; None ; -1.101 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[12] ; CLOCK_50 ; ; N/A ; None ; -1.101 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[1] ; CLOCK_50 ; ; N/A ; None ; -1.101 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[0] ; CLOCK_50 ; ; N/A ; None ; -1.101 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[3] ; CLOCK_50 ; ; N/A ; None ; -1.101 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[10] ; CLOCK_50 ; ; N/A ; None ; -1.101 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[11] ; CLOCK_50 ; ; N/A ; None ; -1.247 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[12] ; CLOCK_50 ; ; N/A ; None ; -1.247 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[0] ; CLOCK_50 ; ; N/A ; None ; -1.247 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[9] ; CLOCK_50 ; ; N/A ; None ; -1.247 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[7] ; CLOCK_50 ; ; N/A ; None ; -1.247 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[11] ; CLOCK_50 ; ; N/A ; None ; -1.247 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[10] ; CLOCK_50 ; ; N/A ; None ; -1.326 ns ; I2C_SDAT ; I2C_AV_Config:u1|I2C_Controller:u0|ACK3 ; CLOCK_50 ; ; N/A ; None ; -1.376 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[2] ; CLOCK_50 ; ; N/A ; None ; -1.376 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[9] ; CLOCK_50 ; ; N/A ; None ; -1.376 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[7] ; CLOCK_50 ; ; N/A ; None ; -1.439 ns ; KEY[0] ; I2C_AV_Config:u1|I2C_Controller:u0|SD[4] ; CLOCK_50 ; ; N/A ; None ; -1.510 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[1] ; CLOCK_50 ; ; N/A ; None ; -1.510 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[2] ; CLOCK_50 ; ; N/A ; None ; -1.510 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[4] ; CLOCK_50 ; ; N/A ; None ; -1.510 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[3] ; CLOCK_50 ; ; N/A ; None ; -1.510 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[5] ; CLOCK_50 ; ; N/A ; None ; -1.510 ns ; KEY[0] ; I2C_AV_Config:u1|mI2C_DATA[6] ; CLOCK_50 ; ; N/A ; None ; -1.778 ns ; I2C_SDAT ; I2C_AV_Config:u1|I2C_Controller:u0|ACK2 ; CLOCK_50 ; ; N/A ; None ; -2.016 ns ; I2C_SDAT ; I2C_AV_Config:u1|I2C_Controller:u0|ACK1 ; CLOCK_50 ; +---------------+-------------+-----------+----------+-------------------------------------------+----------+ +--------------------------+ ; Timing Analyzer Messages ; +--------------------------+ Info: ******************************************************************* Info: Running Quartus II Timing Analyzer Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version Info: Processing started: Thu Sep 28 19:55:18 2006 Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DE1_i2sound -c DE1_i2sound --timing_analysis_only Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled Warning: Found pins functioning as undefined clocks and/or memory enables Info: Assuming node "KEY[0]" is an undefined clock Info: Assuming node "CLOCK_50" is an undefined clock Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew Info: Detected ripple clock "I2C_AV_Config:u1|mI2C_CTRL_CLK" as buffer Info: Found timing assignments -- calculating delays Info: No valid register-to-register data paths exist for clock "PLL:u0|altpll:altpll_component|_clk0" Info: No valid register-to-register data paths exist for clock "CLOCK_27[0]" Info: Clock "KEY[0]" has Internal fmax of 354.23 MHz between source register "VOL[2]" and destination register "VOL[0]" (period= 2.823 ns) Info: + Longest register to register delay is 2.584 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X45_Y8_N21; Fanout = 5; REG Node = 'VOL[2]' Info: 2: + IC(0.400 ns) + CELL(0.322 ns) = 0.722 ns; Loc. = LCCOMB_X45_Y8_N6; Fanout = 1; COMB Node = 'VOL[5]~120' Info: 3: + IC(0.313 ns) + CELL(0.545 ns) = 1.580 ns; Loc. = LCCOMB_X45_Y8_N10; Fanout = 7; COMB Node = 'LessThan0~61' Info: 4: + IC(0.264 ns) + CELL(0.740 ns) = 2.584 ns; Loc. = LCFF_X45_Y8_N17; Fanout = 4; REG Node = 'VOL[0]' Info: Total cell delay = 1.607 ns ( 62.19 % ) Info: Total interconnect delay = 0.977 ns ( 37.81 % ) Info: - Smallest clock skew is 0.000 ns Info: + Shortest clock path from clock "KEY[0]" to destination register is 6.927 ns Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_R22; Fanout = 46; CLK Node = 'KEY[0]' Info: 2: + IC(5.461 ns) + CELL(0.602 ns) = 6.927 ns; Loc. = LCFF_X45_Y8_N17; Fanout = 4; REG Node = 'VOL[0]' Info: Total cell delay = 1.466 ns ( 21.16 % ) Info: Total interconnect delay = 5.461 ns ( 78.84 % ) Info: - Longest clock path from clock "KEY[0]" to source register is 6.927 ns Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_R22; Fanout = 46; CLK Node = 'KEY[0]' Info: 2: + IC(5.461 ns) + CELL(0.602 ns) = 6.927 ns; Loc. = LCFF_X45_Y8_N21; Fanout = 5; REG Node = 'VOL[2]' Info: Total cell delay = 1.466 ns ( 21.16 % ) Info: Total interconnect delay = 5.461 ns ( 78.84 % ) Info: + Micro clock to output delay of source is 0.277 ns Info: + Micro setup delay of destination is -0.038 ns Info: Clock "CLOCK_50" has Internal fmax of 205.72 MHz between source register "I2C_AV_Config:u1|LUT_INDEX[3]" and destination register "I2C_AV_Config:u1|mI2C_DATA[1]" (period= 4.861 ns) Info: + Longest register to register delay is 4.631 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y8_N31; Fanout = 13; REG Node = 'I2C_AV_Config:u1|LUT_INDEX[3]' Info: 2: + IC(1.219 ns) + CELL(0.542 ns) = 1.761 ns; Loc. = LCCOMB_X44_Y8_N24; Fanout = 8; COMB Node = 'I2C_AV_Config:u1|LessThan1~53' Info: 3: + IC(0.872 ns) + CELL(0.178 ns) = 2.811 ns; Loc. = LCCOMB_X40_Y8_N8; Fanout = 12; COMB Node = 'I2C_AV_Config:u1|mI2C_DATA[12]~676' Info: 4: + IC(1.062 ns) + CELL(0.758 ns) = 4.631 ns; Loc. = LCFF_X45_Y8_N5; Fanout = 1; REG Node = 'I2C_AV_Config:u1|mI2C_DATA[1]' Info: Total cell delay = 1.478 ns ( 31.92 % ) Info: Total interconnect delay = 3.153 ns ( 68.08 % ) Info: - Smallest clock skew is 0.009 ns Info: + Shortest clock path from clock "CLOCK_50" to destination register is 6.845 ns Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50' Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'CLOCK_50~clkctrl' Info: 3: + IC(0.976 ns) + CELL(0.879 ns) = 3.119 ns; Loc. = LCFF_X39_Y8_N15; Fanout = 3; REG Node = 'I2C_AV_Config:u1|mI2C_CTRL_CLK' Info: 4: + IC(2.156 ns) + CELL(0.000 ns) = 5.275 ns; Loc. = CLKCTRL_G13; Fanout = 44; COMB Node = 'I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl' Info: 5: + IC(0.968 ns) + CELL(0.602 ns) = 6.845 ns; Loc. = LCFF_X45_Y8_N5; Fanout = 1; REG Node = 'I2C_AV_Config:u1|mI2C_DATA[1]' Info: Total cell delay = 2.507 ns ( 36.63 % ) Info: Total interconnect delay = 4.338 ns ( 63.37 % ) Info: - Longest clock path from clock "CLOCK_50" to source register is 6.836 ns Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50' Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'CLOCK_50~clkctrl' Info: 3: + IC(0.976 ns) + CELL(0.879 ns) = 3.119 ns; Loc. = LCFF_X39_Y8_N15; Fanout = 3; REG Node = 'I2C_AV_Config:u1|mI2C_CTRL_CLK' Info: 4: + IC(2.156 ns) + CELL(0.000 ns) = 5.275 ns; Loc. = CLKCTRL_G13; Fanout = 44; COMB Node = 'I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl' Info: 5: + IC(0.959 ns) + CELL(0.602 ns) = 6.836 ns; Loc. = LCFF_X39_Y8_N31; Fanout = 13; REG Node = 'I2C_AV_Config:u1|LUT_INDEX[3]' Info: Total cell delay = 2.507 ns ( 36.67 % ) Info: Total interconnect delay = 4.329 ns ( 63.33 % ) Info: + Micro clock to output delay of source is 0.277 ns Info: + Micro setup delay of destination is -0.038 ns Info: tsu for register "I2C_AV_Config:u1|I2C_Controller:u0|ACK1" (data pin = "I2C_SDAT", clock pin = "CLOCK_50") is 2.264 ns Info: + Longest pin to register delay is 9.138 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_B3; Fanout = 1; PIN Node = 'I2C_SDAT' Info: 2: + IC(0.000 ns) + CELL(0.883 ns) = 0.883 ns; Loc. = IOC_X1_Y27_N3; Fanout = 3; COMB Node = 'I2C_SDAT~1' Info: 3: + IC(6.973 ns) + CELL(0.322 ns) = 8.178 ns; Loc. = LCCOMB_X39_Y8_N6; Fanout = 1; COMB Node = 'I2C_AV_Config:u1|I2C_Controller:u0|Selector0~98' Info: 4: + IC(0.319 ns) + CELL(0.545 ns) = 9.042 ns; Loc. = LCCOMB_X39_Y8_N26; Fanout = 1; COMB Node = 'I2C_AV_Config:u1|I2C_Controller:u0|ACK1~171' Info: 5: + IC(0.000 ns) + CELL(0.096 ns) = 9.138 ns; Loc. = LCFF_X39_Y8_N27; Fanout = 3; REG Node = 'I2C_AV_Config:u1|I2C_Controller:u0|ACK1' Info: Total cell delay = 1.846 ns ( 20.20 % ) Info: Total interconnect delay = 7.292 ns ( 79.80 % ) Info: + Micro setup delay of destination is -0.038 ns Info: - Shortest clock path from clock "CLOCK_50" to destination register is 6.836 ns Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50' Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'CLOCK_50~clkctrl' Info: 3: + IC(0.976 ns) + CELL(0.879 ns) = 3.119 ns; Loc. = LCFF_X39_Y8_N15; Fanout = 3; REG Node = 'I2C_AV_Config:u1|mI2C_CTRL_CLK' Info: 4: + IC(2.156 ns) + CELL(0.000 ns) = 5.275 ns; Loc. = CLKCTRL_G13; Fanout = 44; COMB Node = 'I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl' Info: 5: + IC(0.959 ns) + CELL(0.602 ns) = 6.836 ns; Loc. = LCFF_X39_Y8_N27; Fanout = 3; REG Node = 'I2C_AV_Config:u1|I2C_Controller:u0|ACK1' Info: Total cell delay = 2.507 ns ( 36.67 % ) Info: Total interconnect delay = 4.329 ns ( 63.33 % ) Info: tco from clock "CLOCK_50" to destination pin "I2C_SCLK" through register "I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1]" is 16.767 ns Info: + Longest clock path from clock "CLOCK_50" to source register is 6.837 ns Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50' Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'CLOCK_50~clkctrl' Info: 3: + IC(0.976 ns) + CELL(0.879 ns) = 3.119 ns; Loc. = LCFF_X39_Y8_N15; Fanout = 3; REG Node = 'I2C_AV_Config:u1|mI2C_CTRL_CLK' Info: 4: + IC(2.156 ns) + CELL(0.000 ns) = 5.275 ns; Loc. = CLKCTRL_G13; Fanout = 44; COMB Node = 'I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl' Info: 5: + IC(0.960 ns) + CELL(0.602 ns) = 6.837 ns; Loc. = LCFF_X40_Y8_N23; Fanout = 14; REG Node = 'I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1]' Info: Total cell delay = 2.507 ns ( 36.67 % ) Info: Total interconnect delay = 4.330 ns ( 63.33 % ) Info: + Micro clock to output delay of source is 0.277 ns Info: + Longest register to pin delay is 9.653 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X40_Y8_N23; Fanout = 14; REG Node = 'I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1]' Info: 2: + IC(1.002 ns) + CELL(0.545 ns) = 1.547 ns; Loc. = LCCOMB_X42_Y8_N18; Fanout = 1; COMB Node = 'I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~253' Info: 3: + IC(0.297 ns) + CELL(0.178 ns) = 2.022 ns; Loc. = LCCOMB_X42_Y8_N6; Fanout = 1; COMB Node = 'I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~254' Info: 4: + IC(0.315 ns) + CELL(0.545 ns) = 2.882 ns; Loc. = LCCOMB_X42_Y8_N4; Fanout = 1; COMB Node = 'I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~255' Info: 5: + IC(3.755 ns) + CELL(3.016 ns) = 9.653 ns; Loc. = PIN_A3; Fanout = 0; PIN Node = 'I2C_SCLK' Info: Total cell delay = 4.284 ns ( 44.38 % ) Info: Total interconnect delay = 5.369 ns ( 55.62 % ) Info: Longest tpd from source pin "AUD_ADCDAT" to destination pin "AUD_DACLRCK" is 9.521 ns Info: 1: + IC(0.000 ns) + CELL(0.863 ns) = 0.863 ns; Loc. = PIN_B6; Fanout = 1; PIN Node = 'AUD_ADCDAT' Info: 2: + IC(5.642 ns) + CELL(3.016 ns) = 9.521 ns; Loc. = PIN_A5; Fanout = 0; PIN Node = 'AUD_DACLRCK' Info: Total cell delay = 3.879 ns ( 40.74 % ) Info: Total interconnect delay = 5.642 ns ( 59.26 % ) Info: th for register "I2C_AV_Config:u1|I2C_Controller:u0|SD[6]" (data pin = "KEY[0]", clock pin = "CLOCK_50") is -0.852 ns Info: + Longest clock path from clock "CLOCK_50" to destination register is 6.843 ns Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50' Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'CLOCK_50~clkctrl' Info: 3: + IC(0.976 ns) + CELL(0.879 ns) = 3.119 ns; Loc. = LCFF_X39_Y8_N15; Fanout = 3; REG Node = 'I2C_AV_Config:u1|mI2C_CTRL_CLK' Info: 4: + IC(2.156 ns) + CELL(0.000 ns) = 5.275 ns; Loc. = CLKCTRL_G13; Fanout = 44; COMB Node = 'I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl' Info: 5: + IC(0.966 ns) + CELL(0.602 ns) = 6.843 ns; Loc. = LCFF_X42_Y8_N23; Fanout = 1; REG Node = 'I2C_AV_Config:u1|I2C_Controller:u0|SD[6]' Info: Total cell delay = 2.507 ns ( 36.64 % ) Info: Total interconnect delay = 4.336 ns ( 63.36 % ) Info: + Micro hold delay of destination is 0.286 ns Info: - Shortest pin to register delay is 7.981 ns Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_R22; Fanout = 46; CLK Node = 'KEY[0]' Info: 2: + IC(5.604 ns) + CELL(0.483 ns) = 6.951 ns; Loc. = LCCOMB_X42_Y8_N30; Fanout = 12; COMB Node = 'I2C_AV_Config:u1|I2C_Controller:u0|SD[12]~11' Info: 3: + IC(0.272 ns) + CELL(0.758 ns) = 7.981 ns; Loc. = LCFF_X42_Y8_N23; Fanout = 1; REG Node = 'I2C_AV_Config:u1|I2C_Controller:u0|SD[6]' Info: Total cell delay = 2.105 ns ( 26.38 % ) Info: Total interconnect delay = 5.876 ns ( 73.62 % ) Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings Info: Processing ended: Thu Sep 28 19:55:19 2006 Info: Elapsed time: 00:00:01