Timing Analyzer report for DE1_TOP Thu Jul 06 23:35:59 2006 Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Timing Analyzer Settings 3. Timing Analyzer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2006 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +------------------------------------------------------------------------------------------------------+ ; Timing Analyzer Settings ; +-------------------------------------------------------+--------------------+------+----+-------------+ ; Option ; Setting ; From ; To ; Entity Name ; +-------------------------------------------------------+--------------------+------+----+-------------+ ; Device Name ; EP2C20F484C7 ; ; ; ; ; Timing Models ; Final ; ; ; ; ; Number of source nodes to report per destination node ; 10 ; ; ; ; ; Number of destination nodes to report ; 10 ; ; ; ; ; Number of paths to report ; 200 ; ; ; ; ; Report Minimum Timing Checks ; Off ; ; ; ; ; Use Fast Timing Models ; Off ; ; ; ; ; Report IO Paths Separately ; Off ; ; ; ; ; Default hold multicycle ; Same As Multicycle ; ; ; ; ; Cut paths between unrelated clock domains ; On ; ; ; ; ; Cut off read during write signal paths ; On ; ; ; ; ; Cut off feedback from I/O pins ; On ; ; ; ; ; Report Combined Fast/Slow Timing ; Off ; ; ; ; ; Ignore Clock Settings ; Off ; ; ; ; ; Analyze latches as synchronous elements ; On ; ; ; ; ; Enable Recovery/Removal analysis ; Off ; ; ; ; ; Enable Clock Latency ; Off ; ; ; ; ; Use TimeQuest Timing Analyzer ; Off ; ; ; ; +-------------------------------------------------------+--------------------+------+----+-------------+ +--------------------------+ ; Timing Analyzer Messages ; +--------------------------+ Info: ******************************************************************* Info: Running Quartus II Timing Analyzer Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version Info: Processing started: Thu Jul 06 23:35:59 2006 Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DE1_TOP -c DE1_TOP --timing_analysis_only Warning: No paths found for timing analysis Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning Info: Processing ended: Thu Jul 06 23:35:59 2006 Info: Elapsed time: 00:00:01