Analysis & Synthesis report for DE1_TOP Thu Jul 06 23:35:35 2006 Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Analysis & Synthesis Source Files Read 5. Analysis & Synthesis Resource Usage Summary 6. Analysis & Synthesis Resource Utilization by Entity 7. General Register Statistics 8. Analysis & Synthesis Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2006 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +------------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+-----------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Thu Jul 06 23:35:35 2006 ; ; Quartus II Version ; 6.0 Build 202 06/20/2006 SP 1 SJ Full Version ; ; Revision Name ; DE1_TOP ; ; Top-level Entity Name ; DE1_TOP ; ; Family ; Cyclone II ; ; Total logic elements ; 0 ; ; Total registers ; 0 ; ; Total pins ; 283 ; ; Total virtual pins ; 0 ; ; Total memory bits ; 0 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Total PLLs ; 0 ; +------------------------------------+-----------------------------------------------+ +--------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +--------------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +--------------------------------------------------------------------+--------------------+--------------------+ ; Device ; EP2C20F484C7 ; ; ; Top-level entity name ; DE1_TOP ; DE1_TOP ; ; Family name ; Cyclone II ; Stratix ; ; Use smart compilation ; Off ; Off ; ; Restructure Multiplexers ; Auto ; Auto ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Disable OpenCore Plus hardware evaluation ; Off ; Off ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL93 ; VHDL93 ; ; State Machine Processing ; Auto ; Auto ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; DSP Block Balancing ; Auto ; Auto ; ; Maximum DSP Block Usage ; Unlimited ; Unlimited ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique -- Cyclone II ; Balanced ; Balanced ; ; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Remove Duplicate Logic ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Perform gate-level register retiming ; Off ; Off ; ; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ; ; Auto ROM Replacement ; On ; On ; ; Auto RAM Replacement ; On ; On ; ; Auto Shift Register Replacement ; On ; On ; ; Auto Clock Enable Replacement ; On ; On ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto Resource Sharing ; Off ; Off ; ; Allow Any RAM Size For Recognition ; Off ; Off ; ; Allow Any ROM Size For Recognition ; Off ; Off ; ; Allow Any Shift Register Size For Recognition ; Off ; Off ; ; Maximum Number of M4K Memory Blocks ; Unlimited ; Unlimited ; ; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ; ; Show Parameter Settings Tables in Synthesis Report ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ; ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; ; HDL message level ; Level2 ; Level2 ; +--------------------------------------------------------------------+--------------------+--------------------+ +-----------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +----------------------------------+-----------------+-----------+------------------------------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; +----------------------------------+-----------------+-----------+------------------------------+ ; DE1_TOP.v ; yes ; Other ; C:/DE1/DE1_TOP/DE1_TOP.v ; +----------------------------------+-----------------+-----------+------------------------------+ +-----------------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ ; Total combinational functions ; 0 ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 0 ; ; -- 3 input functions ; 0 ; ; -- <=2 input functions ; 0 ; ; -- Combinational cells for routing ; 0 ; ; Logic elements by mode ; ; ; -- normal mode ; 0 ; ; -- arithmetic mode ; 0 ; ; Total registers ; 0 ; ; I/O pins ; 283 ; +---------------------------------------------+-------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+ ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; +----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+ ; |DE1_TOP ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 283 ; 0 ; |DE1_TOP ; +----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ ; Total registers ; 0 ; ; Number of registers using Synchronous Clear ; 0 ; ; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Clock Enable ; 0 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version Info: Processing started: Thu Jul 06 23:35:32 2006 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE1_TOP -c DE1_TOP Info: Found 1 design units, including 0 entities, in source file ../../altera/quartus60/libraries/vhdl/altera_mf/altera_mf_components.vhd Info: Found design unit 1: altera_mf_components Warning: Can't analyze file -- file C:/DE1/DE1_TOP/ALT_CUSP_PACKAGE.vhd is missing Warning: Can't analyze file -- file C:/DE1/DE1_TOP/TTA_X_clock_reset.vhd is missing Warning: Can't analyze file -- file C:/DE1/DE1_TOP/ALT_GPIO.vhd is missing Warning: Can't analyze file -- file C:/DE1/DE1_TOP/ALT_PC.vhd is missing Warning: Can't analyze file -- file C:/DE1/DE1_TOP/TTA_X_constant.vhd is missing Warning: Can't analyze file -- file C:/DE1/DE1_TOP/test_lbc.vhd is missing Warning: Can't analyze file -- file C:/DE1/DE1_TOP/test.v is missing Warning: Using design file DE1_TOP.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: DE1_TOP Info: Elaborating entity "DE1_TOP" for the top level hierarchy Warning (10034): Output port "UART_TXD" at DE1_TOP.v(145) has no driver Warning (10034): Output port "DRAM_ADDR[11]" at DE1_TOP.v(149) has no driver Warning (10034): Output port "DRAM_ADDR[10]" at DE1_TOP.v(149) has no driver Warning (10034): Output port "DRAM_ADDR[9]" at DE1_TOP.v(149) has no driver Warning (10034): Output port "DRAM_ADDR[8]" at DE1_TOP.v(149) has no driver Warning (10034): Output port "DRAM_ADDR[7]" at DE1_TOP.v(149) has no driver Warning (10034): Output port "DRAM_ADDR[6]" at DE1_TOP.v(149) has no driver Warning (10034): Output port "DRAM_ADDR[5]" at DE1_TOP.v(149) has no driver Warning (10034): Output port "DRAM_ADDR[4]" at DE1_TOP.v(149) has no driver Warning (10034): Output port "DRAM_ADDR[3]" at DE1_TOP.v(149) has no driver Warning (10034): Output port "DRAM_ADDR[2]" at DE1_TOP.v(149) has no driver Warning (10034): Output port "DRAM_ADDR[1]" at DE1_TOP.v(149) has no driver Warning (10034): Output port "DRAM_ADDR[0]" at DE1_TOP.v(149) has no driver Warning (10034): Output port "DRAM_LDQM" at DE1_TOP.v(150) has no driver Warning (10034): Output port "DRAM_UDQM" at DE1_TOP.v(151) has no driver Warning (10034): Output port "DRAM_WE_N" at DE1_TOP.v(152) has no driver Warning (10034): Output port "DRAM_CAS_N" at DE1_TOP.v(153) has no driver Warning (10034): Output port "DRAM_RAS_N" at DE1_TOP.v(154) has no driver Warning (10034): Output port "DRAM_CS_N" at DE1_TOP.v(155) has no driver Warning (10034): Output port "DRAM_BA_0" at DE1_TOP.v(156) has no driver Warning (10034): Output port "DRAM_BA_1" at DE1_TOP.v(157) has no driver Warning (10034): Output port "DRAM_CLK" at DE1_TOP.v(158) has no driver Warning (10034): Output port "DRAM_CKE" at DE1_TOP.v(159) has no driver Warning (10034): Output port "FL_ADDR[21]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[20]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[19]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[18]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[17]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[16]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[15]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[14]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[13]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[12]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[11]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[10]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[9]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[8]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[7]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[6]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[5]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[4]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[3]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[2]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[1]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_ADDR[0]" at DE1_TOP.v(162) has no driver Warning (10034): Output port "FL_WE_N" at DE1_TOP.v(163) has no driver Warning (10034): Output port "FL_RST_N" at DE1_TOP.v(164) has no driver Warning (10034): Output port "FL_OE_N" at DE1_TOP.v(165) has no driver Warning (10034): Output port "FL_CE_N" at DE1_TOP.v(166) has no driver Warning (10034): Output port "SRAM_ADDR[17]" at DE1_TOP.v(169) has no driver Warning (10034): Output port "SRAM_ADDR[16]" at DE1_TOP.v(169) has no driver Warning (10034): Output port "SRAM_ADDR[15]" at DE1_TOP.v(169) has no driver Warning (10034): Output port "SRAM_ADDR[14]" at DE1_TOP.v(169) has no driver Warning (10034): Output port "SRAM_ADDR[13]" at DE1_TOP.v(169) has no driver Warning (10034): Output port "SRAM_ADDR[12]" at DE1_TOP.v(169) has no driver Warning (10034): Output port "SRAM_ADDR[11]" at DE1_TOP.v(169) has no driver Warning (10034): Output port "SRAM_ADDR[10]" at DE1_TOP.v(169) has no driver Warning (10034): Output port "SRAM_ADDR[9]" at DE1_TOP.v(169) has no driver Warning (10034): Output port "SRAM_ADDR[8]" at DE1_TOP.v(169) has no driver Warning (10034): Output port "SRAM_ADDR[7]" at DE1_TOP.v(169) has no driver Warning (10034): Output port "SRAM_ADDR[6]" at DE1_TOP.v(169) has no driver Warning (10034): Output port "SRAM_ADDR[5]" at DE1_TOP.v(169) has no driver Warning (10034): Output port "SRAM_ADDR[4]" at DE1_TOP.v(169) has no driver Warning (10034): Output port "SRAM_ADDR[3]" at DE1_TOP.v(169) has no driver Warning (10034): Output port "SRAM_ADDR[2]" at DE1_TOP.v(169) has no driver Warning (10034): Output port "SRAM_ADDR[1]" at DE1_TOP.v(169) has no driver Warning (10034): Output port "SRAM_ADDR[0]" at DE1_TOP.v(169) has no driver Warning (10034): Output port "SRAM_UB_N" at DE1_TOP.v(170) has no driver Warning (10034): Output port "SRAM_LB_N" at DE1_TOP.v(171) has no driver Warning (10034): Output port "SRAM_WE_N" at DE1_TOP.v(172) has no driver Warning (10034): Output port "SRAM_CE_N" at DE1_TOP.v(173) has no driver Warning (10034): Output port "SRAM_OE_N" at DE1_TOP.v(174) has no driver Warning (10034): Output port "SD_CLK" at DE1_TOP.v(179) has no driver Warning (10034): Output port "I2C_SCLK" at DE1_TOP.v(182) has no driver Warning (10034): Output port "TDO" at DE1_TOP.v(190) has no driver Warning (10034): Output port "VGA_HS" at DE1_TOP.v(192) has no driver Warning (10034): Output port "VGA_VS" at DE1_TOP.v(193) has no driver Warning (10034): Output port "VGA_R[3]" at DE1_TOP.v(194) has no driver Warning (10034): Output port "VGA_R[2]" at DE1_TOP.v(194) has no driver Warning (10034): Output port "VGA_R[1]" at DE1_TOP.v(194) has no driver Warning (10034): Output port "VGA_R[0]" at DE1_TOP.v(194) has no driver Warning (10034): Output port "VGA_G[3]" at DE1_TOP.v(195) has no driver Warning (10034): Output port "VGA_G[2]" at DE1_TOP.v(195) has no driver Warning (10034): Output port "VGA_G[1]" at DE1_TOP.v(195) has no driver Warning (10034): Output port "VGA_G[0]" at DE1_TOP.v(195) has no driver Warning (10034): Output port "VGA_B[3]" at DE1_TOP.v(196) has no driver Warning (10034): Output port "VGA_B[2]" at DE1_TOP.v(196) has no driver Warning (10034): Output port "VGA_B[1]" at DE1_TOP.v(196) has no driver Warning (10034): Output port "VGA_B[0]" at DE1_TOP.v(196) has no driver Warning (10034): Output port "AUD_DACDAT" at DE1_TOP.v(201) has no driver Warning (10034): Output port "AUD_XCK" at DE1_TOP.v(203) has no driver Warning: The bidir "SD_DAT3" has no source; inserted an always disabled tri-state buffer. Warning: The bidir "SD_CMD" has no source; inserted an always disabled tri-state buffer. Warning: Output pins are stuck at VCC or GND Warning: Pin "HEX0[0]" stuck at GND Warning: Pin "HEX0[1]" stuck at GND Warning: Pin "HEX0[2]" stuck at GND Warning: Pin "HEX0[3]" stuck at GND Warning: Pin "HEX0[4]" stuck at GND Warning: Pin "HEX0[5]" stuck at GND Warning: Pin "HEX0[6]" stuck at GND Warning: Pin "HEX1[0]" stuck at GND Warning: Pin "HEX1[1]" stuck at GND Warning: Pin "HEX1[2]" stuck at GND Warning: Pin "HEX1[3]" stuck at GND Warning: Pin "HEX1[4]" stuck at GND Warning: Pin "HEX1[5]" stuck at GND Warning: Pin "HEX1[6]" stuck at GND Warning: Pin "HEX2[0]" stuck at GND Warning: Pin "HEX2[1]" stuck at GND Warning: Pin "HEX2[2]" stuck at GND Warning: Pin "HEX2[3]" stuck at GND Warning: Pin "HEX2[4]" stuck at GND Warning: Pin "HEX2[5]" stuck at GND Warning: Pin "HEX2[6]" stuck at GND Warning: Pin "HEX3[0]" stuck at GND Warning: Pin "HEX3[1]" stuck at GND Warning: Pin "HEX3[2]" stuck at GND Warning: Pin "HEX3[3]" stuck at GND Warning: Pin "HEX3[4]" stuck at GND Warning: Pin "HEX3[5]" stuck at GND Warning: Pin "HEX3[6]" stuck at GND Warning: Pin "LEDG[0]" stuck at VCC Warning: Pin "LEDG[1]" stuck at VCC Warning: Pin "LEDG[2]" stuck at VCC Warning: Pin "LEDG[3]" stuck at VCC Warning: Pin "LEDG[4]" stuck at VCC Warning: Pin "LEDG[5]" stuck at VCC Warning: Pin "LEDG[6]" stuck at VCC Warning: Pin "LEDG[7]" stuck at VCC Warning: Pin "LEDR[0]" stuck at VCC Warning: Pin "LEDR[1]" stuck at VCC Warning: Pin "LEDR[2]" stuck at VCC Warning: Pin "LEDR[3]" stuck at VCC Warning: Pin "LEDR[4]" stuck at VCC Warning: Pin "LEDR[5]" stuck at VCC Warning: Pin "LEDR[6]" stuck at VCC Warning: Pin "LEDR[7]" stuck at VCC Warning: Pin "LEDR[8]" stuck at VCC Warning: Pin "LEDR[9]" stuck at VCC Warning: Pin "UART_TXD" stuck at GND Warning: Pin "DRAM_ADDR[0]" stuck at GND Warning: Pin "DRAM_ADDR[1]" stuck at GND Warning: Pin "DRAM_ADDR[2]" stuck at GND Warning: Pin "DRAM_ADDR[3]" stuck at GND Warning: Pin "DRAM_ADDR[4]" stuck at GND Warning: Pin "DRAM_ADDR[5]" stuck at GND Warning: Pin "DRAM_ADDR[6]" stuck at GND Warning: Pin "DRAM_ADDR[7]" stuck at GND Warning: Pin "DRAM_ADDR[8]" stuck at GND Warning: Pin "DRAM_ADDR[9]" stuck at GND Warning: Pin "DRAM_ADDR[10]" stuck at GND Warning: Pin "DRAM_ADDR[11]" stuck at GND Warning: Pin "DRAM_LDQM" stuck at GND Warning: Pin "DRAM_UDQM" stuck at GND Warning: Pin "DRAM_WE_N" stuck at GND Warning: Pin "DRAM_CAS_N" stuck at GND Warning: Pin "DRAM_RAS_N" stuck at GND Warning: Pin "DRAM_CS_N" stuck at GND Warning: Pin "DRAM_BA_0" stuck at GND Warning: Pin "DRAM_BA_1" stuck at GND Warning: Pin "DRAM_CLK" stuck at GND Warning: Pin "DRAM_CKE" stuck at GND Warning: Pin "FL_ADDR[0]" stuck at GND Warning: Pin "FL_ADDR[1]" stuck at GND Warning: Pin "FL_ADDR[2]" stuck at GND Warning: Pin "FL_ADDR[3]" stuck at GND Warning: Pin "FL_ADDR[4]" stuck at GND Warning: Pin "FL_ADDR[5]" stuck at GND Warning: Pin "FL_ADDR[6]" stuck at GND Warning: Pin "FL_ADDR[7]" stuck at GND Warning: Pin "FL_ADDR[8]" stuck at GND Warning: Pin "FL_ADDR[9]" stuck at GND Warning: Pin "FL_ADDR[10]" stuck at GND Warning: Pin "FL_ADDR[11]" stuck at GND Warning: Pin "FL_ADDR[12]" stuck at GND Warning: Pin "FL_ADDR[13]" stuck at GND Warning: Pin "FL_ADDR[14]" stuck at GND Warning: Pin "FL_ADDR[15]" stuck at GND Warning: Pin "FL_ADDR[16]" stuck at GND Warning: Pin "FL_ADDR[17]" stuck at GND Warning: Pin "FL_ADDR[18]" stuck at GND Warning: Pin "FL_ADDR[19]" stuck at GND Warning: Pin "FL_ADDR[20]" stuck at GND Warning: Pin "FL_ADDR[21]" stuck at GND Warning: Pin "FL_WE_N" stuck at GND Warning: Pin "FL_RST_N" stuck at GND Warning: Pin "FL_OE_N" stuck at GND Warning: Pin "FL_CE_N" stuck at GND Warning: Pin "SRAM_ADDR[0]" stuck at GND Warning: Pin "SRAM_ADDR[1]" stuck at GND Warning: Pin "SRAM_ADDR[2]" stuck at GND Warning: Pin "SRAM_ADDR[3]" stuck at GND Warning: Pin "SRAM_ADDR[4]" stuck at GND Warning: Pin "SRAM_ADDR[5]" stuck at GND Warning: Pin "SRAM_ADDR[6]" stuck at GND Warning: Pin "SRAM_ADDR[7]" stuck at GND Warning: Pin "SRAM_ADDR[8]" stuck at GND Warning: Pin "SRAM_ADDR[9]" stuck at GND Warning: Pin "SRAM_ADDR[10]" stuck at GND Warning: Pin "SRAM_ADDR[11]" stuck at GND Warning: Pin "SRAM_ADDR[12]" stuck at GND Warning: Pin "SRAM_ADDR[13]" stuck at GND Warning: Pin "SRAM_ADDR[14]" stuck at GND Warning: Pin "SRAM_ADDR[15]" stuck at GND Warning: Pin "SRAM_ADDR[16]" stuck at GND Warning: Pin "SRAM_ADDR[17]" stuck at GND Warning: Pin "SRAM_UB_N" stuck at GND Warning: Pin "SRAM_LB_N" stuck at GND Warning: Pin "SRAM_WE_N" stuck at GND Warning: Pin "SRAM_CE_N" stuck at GND Warning: Pin "SRAM_OE_N" stuck at GND Warning: Pin "SD_CLK" stuck at GND Warning: Pin "TDO" stuck at GND Warning: Pin "I2C_SCLK" stuck at GND Warning: Pin "VGA_HS" stuck at GND Warning: Pin "VGA_VS" stuck at GND Warning: Pin "VGA_R[0]" stuck at GND Warning: Pin "VGA_R[1]" stuck at GND Warning: Pin "VGA_R[2]" stuck at GND Warning: Pin "VGA_R[3]" stuck at GND Warning: Pin "VGA_G[0]" stuck at GND Warning: Pin "VGA_G[1]" stuck at GND Warning: Pin "VGA_G[2]" stuck at GND Warning: Pin "VGA_G[3]" stuck at GND Warning: Pin "VGA_B[0]" stuck at GND Warning: Pin "VGA_B[1]" stuck at GND Warning: Pin "VGA_B[2]" stuck at GND Warning: Pin "VGA_B[3]" stuck at GND Warning: Pin "AUD_DACDAT" stuck at GND Warning: Pin "AUD_XCK" stuck at GND Warning: Design contains 27 input pin(s) that do not drive logic Warning: No output dependent on input pin "CLOCK_24[0]" Warning: No output dependent on input pin "CLOCK_24[1]" Warning: No output dependent on input pin "CLOCK_27[0]" Warning: No output dependent on input pin "CLOCK_27[1]" Warning: No output dependent on input pin "CLOCK_50" Warning: No output dependent on input pin "EXT_CLOCK" Warning: No output dependent on input pin "KEY[0]" Warning: No output dependent on input pin "KEY[1]" Warning: No output dependent on input pin "KEY[2]" Warning: No output dependent on input pin "KEY[3]" Warning: No output dependent on input pin "SW[0]" Warning: No output dependent on input pin "SW[1]" Warning: No output dependent on input pin "SW[2]" Warning: No output dependent on input pin "SW[3]" Warning: No output dependent on input pin "SW[4]" Warning: No output dependent on input pin "SW[5]" Warning: No output dependent on input pin "SW[6]" Warning: No output dependent on input pin "SW[7]" Warning: No output dependent on input pin "SW[8]" Warning: No output dependent on input pin "SW[9]" Warning: No output dependent on input pin "UART_RXD" Warning: No output dependent on input pin "TDI" Warning: No output dependent on input pin "TCK" Warning: No output dependent on input pin "TCS" Warning: No output dependent on input pin "PS2_DAT" Warning: No output dependent on input pin "PS2_CLK" Warning: No output dependent on input pin "AUD_ADCDAT" Info: Implemented 283 device resources after synthesis - the final resource count might be different Info: Implemented 27 input pins Info: Implemented 137 output pins Info: Implemented 119 bidirectional pins Info: Quartus II Analysis & Synthesis was successful. 0 errors, 267 warnings Info: Processing ended: Thu Jul 06 23:35:35 2006 Info: Elapsed time: 00:00:03