-- Copyright (C) 1991-2006 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. --QB1_rDIG[0] is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|rDIG[0] QB1_rDIG[0] = DFFEAS(Z1_d_writedata[0], F1__clk1, N1_data_out, , W1L1, , , , ); --QB1_rDIG[1] is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|rDIG[1] QB1_rDIG[1] = DFFEAS(Z1_d_writedata[1], F1__clk1, N1_data_out, , W1L1, , , , ); --QB1_rDIG[2] is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|rDIG[2] QB1_rDIG[2] = DFFEAS(Z1_d_writedata[2], F1__clk1, N1_data_out, , W1L1, , , , ); --QB1_rDIG[3] is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|rDIG[3] QB1_rDIG[3] = DFFEAS(Z1_d_writedata[3], F1__clk1, N1_data_out, , W1L1, , , , ); --RB1L1 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u0|oSEG[0]~70 RB1L1 = QB1_rDIG[2] & !QB1_rDIG[1] & (QB1_rDIG[0] $ !QB1_rDIG[3]) # !QB1_rDIG[2] & QB1_rDIG[0] & (QB1_rDIG[1] $ !QB1_rDIG[3]); --RB1L2 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u0|oSEG[1]~71 RB1L2 = QB1_rDIG[1] & (QB1_rDIG[0] & (QB1_rDIG[3]) # !QB1_rDIG[0] & QB1_rDIG[2]) # !QB1_rDIG[1] & QB1_rDIG[2] & (QB1_rDIG[0] $ QB1_rDIG[3]); --RB1L3 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u0|oSEG[2]~72 RB1L3 = QB1_rDIG[2] & QB1_rDIG[3] & (QB1_rDIG[1] # !QB1_rDIG[0]) # !QB1_rDIG[2] & !QB1_rDIG[0] & QB1_rDIG[1] & !QB1_rDIG[3]; --RB1L4 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u0|oSEG[3]~73 RB1L4 = QB1_rDIG[0] & (QB1_rDIG[1] $ !QB1_rDIG[2]) # !QB1_rDIG[0] & (QB1_rDIG[1] & !QB1_rDIG[2] & QB1_rDIG[3] # !QB1_rDIG[1] & QB1_rDIG[2] & !QB1_rDIG[3]); --RB1L5 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u0|oSEG[4]~74 RB1L5 = QB1_rDIG[1] & QB1_rDIG[0] & (!QB1_rDIG[3]) # !QB1_rDIG[1] & (QB1_rDIG[2] & (!QB1_rDIG[3]) # !QB1_rDIG[2] & QB1_rDIG[0]); --RB1L6 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u0|oSEG[5]~75 RB1L6 = QB1_rDIG[0] & (QB1_rDIG[3] $ (QB1_rDIG[1] # !QB1_rDIG[2])) # !QB1_rDIG[0] & QB1_rDIG[1] & !QB1_rDIG[2] & !QB1_rDIG[3]; --RB1L7 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u0|oSEG[6]~76 RB1L7 = QB1_rDIG[0] & (QB1_rDIG[3] # QB1_rDIG[1] $ QB1_rDIG[2]) # !QB1_rDIG[0] & (QB1_rDIG[1] # QB1_rDIG[2] $ QB1_rDIG[3]); --QB1_rDIG[4] is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|rDIG[4] QB1_rDIG[4] = DFFEAS(Z1_d_writedata[4], F1__clk1, N1_data_out, , W1L1, , , , ); --QB1_rDIG[5] is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|rDIG[5] QB1_rDIG[5] = DFFEAS(Z1_d_writedata[5], F1__clk1, N1_data_out, , W1L1, , , , ); --QB1_rDIG[6] is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|rDIG[6] QB1_rDIG[6] = DFFEAS(Z1_d_writedata[6], F1__clk1, N1_data_out, , W1L1, , , , ); --QB1_rDIG[7] is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|rDIG[7] QB1_rDIG[7] = DFFEAS(Z1_d_writedata[7], F1__clk1, N1_data_out, , W1L1, , , , ); --RB2L1 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u1|oSEG[0]~70 RB2L1 = QB1_rDIG[6] & !QB1_rDIG[5] & (QB1_rDIG[4] $ !QB1_rDIG[7]) # !QB1_rDIG[6] & QB1_rDIG[4] & (QB1_rDIG[5] $ !QB1_rDIG[7]); --RB2L2 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u1|oSEG[1]~71 RB2L2 = QB1_rDIG[5] & (QB1_rDIG[4] & (QB1_rDIG[7]) # !QB1_rDIG[4] & QB1_rDIG[6]) # !QB1_rDIG[5] & QB1_rDIG[6] & (QB1_rDIG[4] $ QB1_rDIG[7]); --RB2L3 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u1|oSEG[2]~72 RB2L3 = QB1_rDIG[6] & QB1_rDIG[7] & (QB1_rDIG[5] # !QB1_rDIG[4]) # !QB1_rDIG[6] & !QB1_rDIG[4] & QB1_rDIG[5] & !QB1_rDIG[7]; --RB2L4 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u1|oSEG[3]~73 RB2L4 = QB1_rDIG[4] & (QB1_rDIG[5] $ !QB1_rDIG[6]) # !QB1_rDIG[4] & (QB1_rDIG[5] & !QB1_rDIG[6] & QB1_rDIG[7] # !QB1_rDIG[5] & QB1_rDIG[6] & !QB1_rDIG[7]); --RB2L5 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u1|oSEG[4]~74 RB2L5 = QB1_rDIG[5] & QB1_rDIG[4] & (!QB1_rDIG[7]) # !QB1_rDIG[5] & (QB1_rDIG[6] & (!QB1_rDIG[7]) # !QB1_rDIG[6] & QB1_rDIG[4]); --RB2L6 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u1|oSEG[5]~75 RB2L6 = QB1_rDIG[4] & (QB1_rDIG[7] $ (QB1_rDIG[5] # !QB1_rDIG[6])) # !QB1_rDIG[4] & QB1_rDIG[5] & !QB1_rDIG[6] & !QB1_rDIG[7]; --RB2L7 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u1|oSEG[6]~76 RB2L7 = QB1_rDIG[4] & (QB1_rDIG[7] # QB1_rDIG[5] $ QB1_rDIG[6]) # !QB1_rDIG[4] & (QB1_rDIG[5] # QB1_rDIG[6] $ QB1_rDIG[7]); --QB1_rDIG[8] is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|rDIG[8] QB1_rDIG[8] = DFFEAS(Z1_d_writedata[8], F1__clk1, N1_data_out, , W1L1, , , , ); --QB1_rDIG[9] is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|rDIG[9] QB1_rDIG[9] = DFFEAS(Z1_d_writedata[9], F1__clk1, N1_data_out, , W1L1, , , , ); --QB1_rDIG[10] is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|rDIG[10] QB1_rDIG[10] = DFFEAS(Z1_d_writedata[10], F1__clk1, N1_data_out, , W1L1, , , , ); --QB1_rDIG[11] is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|rDIG[11] QB1_rDIG[11] = DFFEAS(Z1_d_writedata[11], F1__clk1, N1_data_out, , W1L1, , , , ); --RB3L1 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u2|oSEG[0]~70 RB3L1 = QB1_rDIG[10] & !QB1_rDIG[9] & (QB1_rDIG[8] $ !QB1_rDIG[11]) # !QB1_rDIG[10] & QB1_rDIG[8] & (QB1_rDIG[9] $ !QB1_rDIG[11]); --RB3L2 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u2|oSEG[1]~71 RB3L2 = QB1_rDIG[9] & (QB1_rDIG[8] & (QB1_rDIG[11]) # !QB1_rDIG[8] & QB1_rDIG[10]) # !QB1_rDIG[9] & QB1_rDIG[10] & (QB1_rDIG[8] $ QB1_rDIG[11]); --RB3L3 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u2|oSEG[2]~72 RB3L3 = QB1_rDIG[10] & QB1_rDIG[11] & (QB1_rDIG[9] # !QB1_rDIG[8]) # !QB1_rDIG[10] & !QB1_rDIG[8] & QB1_rDIG[9] & !QB1_rDIG[11]; --RB3L4 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u2|oSEG[3]~73 RB3L4 = QB1_rDIG[8] & (QB1_rDIG[9] $ !QB1_rDIG[10]) # !QB1_rDIG[8] & (QB1_rDIG[9] & !QB1_rDIG[10] & QB1_rDIG[11] # !QB1_rDIG[9] & QB1_rDIG[10] & !QB1_rDIG[11]); --RB3L5 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u2|oSEG[4]~74 RB3L5 = QB1_rDIG[9] & QB1_rDIG[8] & (!QB1_rDIG[11]) # !QB1_rDIG[9] & (QB1_rDIG[10] & (!QB1_rDIG[11]) # !QB1_rDIG[10] & QB1_rDIG[8]); --RB3L6 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u2|oSEG[5]~75 RB3L6 = QB1_rDIG[8] & (QB1_rDIG[11] $ (QB1_rDIG[9] # !QB1_rDIG[10])) # !QB1_rDIG[8] & QB1_rDIG[9] & !QB1_rDIG[10] & !QB1_rDIG[11]; --RB3L7 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u2|oSEG[6]~76 RB3L7 = QB1_rDIG[8] & (QB1_rDIG[11] # QB1_rDIG[9] $ QB1_rDIG[10]) # !QB1_rDIG[8] & (QB1_rDIG[9] # QB1_rDIG[10] $ QB1_rDIG[11]); --QB1_rDIG[12] is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|rDIG[12] QB1_rDIG[12] = DFFEAS(Z1_d_writedata[12], F1__clk1, N1_data_out, , W1L1, , , , ); --QB1_rDIG[13] is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|rDIG[13] QB1_rDIG[13] = DFFEAS(Z1_d_writedata[13], F1__clk1, N1_data_out, , W1L1, , , , ); --QB1_rDIG[14] is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|rDIG[14] QB1_rDIG[14] = DFFEAS(Z1_d_writedata[14], F1__clk1, N1_data_out, , W1L1, , , , ); --QB1_rDIG[15] is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|rDIG[15] QB1_rDIG[15] = DFFEAS(Z1_d_writedata[15], F1__clk1, N1_data_out, , W1L1, , , , ); --RB4L1 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u3|oSEG[0]~70 RB4L1 = QB1_rDIG[14] & !QB1_rDIG[13] & (QB1_rDIG[12] $ !QB1_rDIG[15]) # !QB1_rDIG[14] & QB1_rDIG[12] & (QB1_rDIG[13] $ !QB1_rDIG[15]); --RB4L2 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u3|oSEG[1]~71 RB4L2 = QB1_rDIG[13] & (QB1_rDIG[12] & (QB1_rDIG[15]) # !QB1_rDIG[12] & QB1_rDIG[14]) # !QB1_rDIG[13] & QB1_rDIG[14] & (QB1_rDIG[12] $ QB1_rDIG[15]); --RB4L3 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u3|oSEG[2]~72 RB4L3 = QB1_rDIG[14] & QB1_rDIG[15] & (QB1_rDIG[13] # !QB1_rDIG[12]) # !QB1_rDIG[14] & !QB1_rDIG[12] & QB1_rDIG[13] & !QB1_rDIG[15]; --RB4L4 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u3|oSEG[3]~73 RB4L4 = QB1_rDIG[12] & (QB1_rDIG[13] $ !QB1_rDIG[14]) # !QB1_rDIG[12] & (QB1_rDIG[13] & !QB1_rDIG[14] & QB1_rDIG[15] # !QB1_rDIG[13] & QB1_rDIG[14] & !QB1_rDIG[15]); --RB4L5 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u3|oSEG[4]~74 RB4L5 = QB1_rDIG[13] & QB1_rDIG[12] & (!QB1_rDIG[15]) # !QB1_rDIG[13] & (QB1_rDIG[14] & (!QB1_rDIG[15]) # !QB1_rDIG[14] & QB1_rDIG[12]); --RB4L6 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u3|oSEG[5]~75 RB4L6 = QB1_rDIG[12] & (QB1_rDIG[15] $ (QB1_rDIG[13] # !QB1_rDIG[14])) # !QB1_rDIG[12] & QB1_rDIG[13] & !QB1_rDIG[14] & !QB1_rDIG[15]; --RB4L7 is system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u3|oSEG[6]~76 RB4L7 = QB1_rDIG[12] & (QB1_rDIG[15] # QB1_rDIG[13] $ QB1_rDIG[14]) # !QB1_rDIG[12] & (QB1_rDIG[13] # QB1_rDIG[14] $ QB1_rDIG[15]); --R1_data_out[0] is system_0:u0|LEDG:the_LEDG|data_out[0] R1_data_out[0] = DFFEAS(Z1_d_writedata[0], F1__clk1, N1_data_out, , R1L2, , , , ); --R1_data_out[1] is system_0:u0|LEDG:the_LEDG|data_out[1] R1_data_out[1] = DFFEAS(Z1_d_writedata[1], F1__clk1, N1_data_out, , R1L2, , , , ); --R1_data_out[2] is system_0:u0|LEDG:the_LEDG|data_out[2] R1_data_out[2] = DFFEAS(Z1_d_writedata[2], F1__clk1, N1_data_out, , R1L2, , , , ); --R1_data_out[3] is system_0:u0|LEDG:the_LEDG|data_out[3] R1_data_out[3] = DFFEAS(Z1_d_writedata[3], F1__clk1, N1_data_out, , R1L2, , , , ); --R1_data_out[4] is system_0:u0|LEDG:the_LEDG|data_out[4] R1_data_out[4] = DFFEAS(Z1_d_writedata[4], F1__clk1, N1_data_out, , R1L2, , , , ); --R1_data_out[5] is system_0:u0|LEDG:the_LEDG|data_out[5] R1_data_out[5] = DFFEAS(Z1_d_writedata[5], F1__clk1, N1_data_out, , R1L2, , , , ); --R1_data_out[6] is system_0:u0|LEDG:the_LEDG|data_out[6] R1_data_out[6] = DFFEAS(Z1_d_writedata[6], F1__clk1, N1_data_out, , R1L2, , , , ); --R1_data_out[7] is system_0:u0|LEDG:the_LEDG|data_out[7] R1_data_out[7] = DFFEAS(Z1_d_writedata[7], F1__clk1, N1_data_out, , R1L2, , , , ); --T1_data_out[0] is system_0:u0|LEDR:the_LEDR|data_out[0] T1_data_out[0] = DFFEAS(Z1_d_writedata[0], F1__clk1, N1_data_out, , T1L2, , , , ); --T1_data_out[1] is system_0:u0|LEDR:the_LEDR|data_out[1] T1_data_out[1] = DFFEAS(Z1_d_writedata[1], F1__clk1, N1_data_out, , T1L2, , , , ); --T1_data_out[2] is system_0:u0|LEDR:the_LEDR|data_out[2] T1_data_out[2] = DFFEAS(Z1_d_writedata[2], F1__clk1, N1_data_out, , T1L2, , , , ); --T1_data_out[3] is system_0:u0|LEDR:the_LEDR|data_out[3] T1_data_out[3] = DFFEAS(Z1_d_writedata[3], F1__clk1, N1_data_out, , T1L2, , , , ); --T1_data_out[4] is system_0:u0|LEDR:the_LEDR|data_out[4] T1_data_out[4] = DFFEAS(Z1_d_writedata[4], F1__clk1, N1_data_out, , T1L2, , , , ); --T1_data_out[5] is system_0:u0|LEDR:the_LEDR|data_out[5] T1_data_out[5] = DFFEAS(Z1_d_writedata[5], F1__clk1, N1_data_out, , T1L2, , , , ); --T1_data_out[6] is system_0:u0|LEDR:the_LEDR|data_out[6] T1_data_out[6] = DFFEAS(Z1_d_writedata[6], F1__clk1, N1_data_out, , T1L2, , , , ); --T1_data_out[7] is system_0:u0|LEDR:the_LEDR|data_out[7] T1_data_out[7] = DFFEAS(Z1_d_writedata[7], F1__clk1, N1_data_out, , T1L2, , , , ); --T1_data_out[8] is system_0:u0|LEDR:the_LEDR|data_out[8] T1_data_out[8] = DFFEAS(Z1_d_writedata[8], F1__clk1, N1_data_out, , T1L2, , , , ); --T1_data_out[9] is system_0:u0|LEDR:the_LEDR|data_out[9] T1_data_out[9] = DFFEAS(Z1_d_writedata[9], F1__clk1, N1_data_out, , T1L2, , , , ); --NE1_txd is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|txd NE1_txd = DFFEAS(NE1L53, F1__clk1, N1_data_out, , , , , , ); --HB1_m_addr[0] is system_0:u0|sdram_0:the_sdram_0|m_addr[0] HB1_m_addr[0] = DFFEAS(HB1L25, F1__clk1, N1_data_out, , HB1L302, VCC, , , HB1_m_state.001000000); --HB1_m_addr[1] is system_0:u0|sdram_0:the_sdram_0|m_addr[1] HB1_m_addr[1] = DFFEAS(HB1L28, F1__clk1, N1_data_out, , HB1L302, VCC, , , HB1_m_state.001000000); --HB1_m_addr[2] is system_0:u0|sdram_0:the_sdram_0|m_addr[2] HB1_m_addr[2] = DFFEAS(HB1L31, F1__clk1, N1_data_out, , HB1L302, VCC, , , HB1_m_state.001000000); --HB1_m_addr[3] is system_0:u0|sdram_0:the_sdram_0|m_addr[3] HB1_m_addr[3] = DFFEAS(HB1L34, F1__clk1, N1_data_out, , HB1L302, VCC, , , HB1_m_state.001000000); --HB1_m_addr[4] is system_0:u0|sdram_0:the_sdram_0|m_addr[4] HB1_m_addr[4] = DFFEAS(HB1L37, F1__clk1, N1_data_out, , HB1L302, VCC, , , HB1_m_state.001000000); --HB1_m_addr[5] is system_0:u0|sdram_0:the_sdram_0|m_addr[5] HB1_m_addr[5] = DFFEAS(HB1L40, F1__clk1, N1_data_out, , HB1L302, VCC, , , HB1_m_state.001000000); --HB1_m_addr[6] is system_0:u0|sdram_0:the_sdram_0|m_addr[6] HB1_m_addr[6] = DFFEAS(HB1L43, F1__clk1, N1_data_out, , HB1L302, VCC, , , HB1_m_state.001000000); --HB1_m_addr[7] is system_0:u0|sdram_0:the_sdram_0|m_addr[7] HB1_m_addr[7] = DFFEAS(HB1L46, F1__clk1, N1_data_out, , HB1L302, VCC, , , HB1_m_state.001000000); --HB1_m_addr[8] is system_0:u0|sdram_0:the_sdram_0|m_addr[8] HB1_m_addr[8] = DFFEAS(HB1L177, F1__clk1, N1_data_out, , HB1L302, , , , ); --HB1_m_addr[9] is system_0:u0|sdram_0:the_sdram_0|m_addr[9] HB1_m_addr[9] = DFFEAS(HB1L178, F1__clk1, N1_data_out, , HB1L302, , , , ); --HB1_m_addr[10] is system_0:u0|sdram_0:the_sdram_0|m_addr[10] HB1_m_addr[10] = DFFEAS(HB1L179, F1__clk1, N1_data_out, , HB1L302, , , , ); --HB1_m_addr[11] is system_0:u0|sdram_0:the_sdram_0|m_addr[11] HB1_m_addr[11] = DFFEAS(HB1L180, F1__clk1, N1_data_out, , HB1L302, , , , ); --HB1_m_dqm[0] is system_0:u0|sdram_0:the_sdram_0|m_dqm[0] HB1_m_dqm[0] = DFFEAS(HB1L52, F1__clk1, N1_data_out, , HB1L392, , , , ); --HB1_m_dqm[1] is system_0:u0|sdram_0:the_sdram_0|m_dqm[1] HB1_m_dqm[1] = DFFEAS(HB1L54, F1__clk1, N1_data_out, , HB1L392, , , , ); --HB1_m_cmd[0] is system_0:u0|sdram_0:the_sdram_0|m_cmd[0] HB1_m_cmd[0] = DFFEAS(HB1L56, F1__clk1, N1_data_out, , , , , , ); --HB1_m_cmd[1] is system_0:u0|sdram_0:the_sdram_0|m_cmd[1] HB1_m_cmd[1] = DFFEAS(HB1L58, F1__clk1, N1_data_out, , , , , , ); --HB1_m_cmd[2] is system_0:u0|sdram_0:the_sdram_0|m_cmd[2] HB1_m_cmd[2] = DFFEAS(HB1L59, F1__clk1, N1_data_out, , , , , , ); --HB1_m_cmd[3] is system_0:u0|sdram_0:the_sdram_0|m_cmd[3] HB1_m_cmd[3] = DFFEAS(HB1L63, F1__clk1, N1_data_out, , , , , , ); --HB1_m_bank[0] is system_0:u0|sdram_0:the_sdram_0|m_bank[0] HB1_m_bank[0] = DFFEAS(HB1L64, F1__clk1, N1_data_out, , HB1L392, , , , ); --HB1_m_bank[1] is system_0:u0|sdram_0:the_sdram_0|m_bank[1] HB1_m_bank[1] = DFFEAS(HB1L65, F1__clk1, N1_data_out, , HB1L392, , , , ); --F1__clk0 is SDRAM_PLL:PLL1|altpll:altpll_component|_clk0 F1__clk0 = PLL.CLK0(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_50), .INCLK()); --F1__clk1 is SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 F1__clk1 = PLL.CLK1(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_50), .INCLK()); --MB1_tri_state_bridge_0_address[0] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[0] MB1_tri_state_bridge_0_address[0] = DFFEAS(MB1L77, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[1] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[1] MB1_tri_state_bridge_0_address[1] = DFFEAS(MB1L78, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[2] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[2] MB1_tri_state_bridge_0_address[2] = DFFEAS(MB1L79, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[3] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[3] MB1_tri_state_bridge_0_address[3] = DFFEAS(MB1L80, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[4] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[4] MB1_tri_state_bridge_0_address[4] = DFFEAS(MB1L81, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[5] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[5] MB1_tri_state_bridge_0_address[5] = DFFEAS(MB1L82, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[6] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[6] MB1_tri_state_bridge_0_address[6] = DFFEAS(MB1L83, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[7] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[7] MB1_tri_state_bridge_0_address[7] = DFFEAS(MB1L84, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[8] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[8] MB1_tri_state_bridge_0_address[8] = DFFEAS(MB1L85, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[9] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[9] MB1_tri_state_bridge_0_address[9] = DFFEAS(MB1L86, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[10] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[10] MB1_tri_state_bridge_0_address[10] = DFFEAS(MB1L87, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[11] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[11] MB1_tri_state_bridge_0_address[11] = DFFEAS(MB1L88, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[12] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[12] MB1_tri_state_bridge_0_address[12] = DFFEAS(MB1L89, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[13] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[13] MB1_tri_state_bridge_0_address[13] = DFFEAS(MB1L90, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[14] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[14] MB1_tri_state_bridge_0_address[14] = DFFEAS(MB1L91, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[15] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[15] MB1_tri_state_bridge_0_address[15] = DFFEAS(MB1L92, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[16] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[16] MB1_tri_state_bridge_0_address[16] = DFFEAS(MB1L93, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[17] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[17] MB1_tri_state_bridge_0_address[17] = DFFEAS(MB1L94, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[18] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[18] MB1_tri_state_bridge_0_address[18] = DFFEAS(MB1L95, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[19] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[19] MB1_tri_state_bridge_0_address[19] = DFFEAS(MB1L96, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[20] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[20] MB1_tri_state_bridge_0_address[20] = DFFEAS(MB1L97, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_address[21] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[21] MB1_tri_state_bridge_0_address[21] = DFFEAS(MB1L98, F1__clk1, N1_data_out, , , , , , ); --MB1_write_n_to_the_cfi_flash_0 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|write_n_to_the_cfi_flash_0 MB1_write_n_to_the_cfi_flash_0 = DFFEAS(MB1L101, F1__clk1, N1_data_out, , , , , , ); --MB1_tri_state_bridge_0_readn is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_readn MB1_tri_state_bridge_0_readn = DFFEAS(MB1L99, F1__clk1, N1_data_out, , , , , , ); --MB1_select_n_to_the_cfi_flash_0 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|select_n_to_the_cfi_flash_0 MB1_select_n_to_the_cfi_flash_0 = DFFEAS(MB1L76, F1__clk1, N1_data_out, , , , , , ); --AB1_cpu_0_data_master_dbs_address[1] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1] AB1_cpu_0_data_master_dbs_address[1] = DFFEAS(AB1L10, F1__clk1, N1_data_out, , , , , , ); --BB1_cpu_0_instruction_master_dbs_address[1] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_dbs_address[1] BB1_cpu_0_instruction_master_dbs_address[1] = DFFEAS(BB1L13, F1__clk1, N1_data_out, , , , , , ); --Z1_d_address[22] is system_0:u0|cpu_0:the_cpu_0|d_address[22] Z1_d_address[22] = AMPP_FUNCTION(F1__clk1, Z1L3214, N1_data_out, Z1L3021); --Z1_d_address[23] is system_0:u0|cpu_0:the_cpu_0|d_address[23] Z1_d_address[23] = AMPP_FUNCTION(F1__clk1, Z1L3215, N1_data_out, Z1L3021); --Z1_d_address[21] is system_0:u0|cpu_0:the_cpu_0|d_address[21] Z1_d_address[21] = AMPP_FUNCTION(F1__clk1, Z1L3213, N1_data_out, Z1L3021); --Z1_d_address[20] is system_0:u0|cpu_0:the_cpu_0|d_address[20] Z1_d_address[20] = AMPP_FUNCTION(F1__clk1, Z1L3212, N1_data_out, Z1L3021); --LB1L1 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|Equal~220 LB1L1 = Z1_d_address[22] & !Z1_d_address[23] & !Z1_d_address[21] & !Z1_d_address[20]; --Z1_d_write is system_0:u0|cpu_0:the_cpu_0|d_write Z1_d_write = AMPP_FUNCTION(F1__clk1, Z1L953, N1_data_out); --Z1_d_read is system_0:u0|cpu_0:the_cpu_0|d_read Z1_d_read = AMPP_FUNCTION(F1__clk1, Z1_d_read_nxt, N1_data_out); --Z1_d_address[19] is system_0:u0|cpu_0:the_cpu_0|d_address[19] Z1_d_address[19] = AMPP_FUNCTION(F1__clk1, Z1L3211, N1_data_out, Z1L3021); --LB1_cpu_0_data_master_requests_sram_0_avalonS is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_requests_sram_0_avalonS LB1_cpu_0_data_master_requests_sram_0_avalonS = LB1L1 & !Z1_d_address[19] & (Z1_d_write # Z1_d_read); --LB1_sram_0_avalonS_slavearbiterlockenable is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_slavearbiterlockenable LB1_sram_0_avalonS_slavearbiterlockenable = DFFEAS(LB1L80, F1__clk1, N1_data_out, , , , , , ); --LB1_last_cycle_cpu_0_instruction_master_granted_slave_sram_0_avalonS is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|last_cycle_cpu_0_instruction_master_granted_slave_sram_0_avalonS LB1_last_cycle_cpu_0_instruction_master_granted_slave_sram_0_avalonS = DFFEAS(LB1L21, F1__clk1, N1_data_out, , , , , , ); --Z1_ic_fill_tag[10] is system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[10] Z1_ic_fill_tag[10] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[20], N1_data_out, Z1L1099); --Z1_ic_fill_tag[11] is system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[11] Z1_ic_fill_tag[11] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[21], N1_data_out, Z1L1099); --Z1_ic_fill_tag[9] is system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[9] Z1_ic_fill_tag[9] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[19], N1_data_out, Z1L1099); --Z1_ic_fill_tag[8] is system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[8] Z1_ic_fill_tag[8] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[18], N1_data_out, Z1L1099); --LB1L73 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_in_a_read_cycle~45 LB1L73 = Z1_ic_fill_tag[10] & !Z1_ic_fill_tag[11] & !Z1_ic_fill_tag[9] & !Z1_ic_fill_tag[8]; --Z1_i_read is system_0:u0|cpu_0:the_cpu_0|i_read Z1_i_read = AMPP_FUNCTION(F1__clk1, Z1L3244, N1_data_out); --Z1_ic_fill_tag[7] is system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[7] Z1_ic_fill_tag[7] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[17], N1_data_out, Z1L1099); --LB1L68 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_firsttransfer~98 LB1L68 = LB1_last_cycle_cpu_0_instruction_master_granted_slave_sram_0_avalonS & LB1L73 & Z1_i_read & !Z1_ic_fill_tag[7]; --AB1_cpu_0_data_master_no_byte_enables_and_last_term is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_no_byte_enables_and_last_term AB1_cpu_0_data_master_no_byte_enables_and_last_term = DFFEAS(AB1L290, F1__clk1, N1_data_out, , , , , !Z1_d_write, ); --Z1_d_byteenable[1] is system_0:u0|cpu_0:the_cpu_0|d_byteenable[1] Z1_d_byteenable[1] = AMPP_FUNCTION(F1__clk1, Z1L3057, N1_data_out, Z1_A_en_d1); --Z1_d_byteenable[3] is system_0:u0|cpu_0:the_cpu_0|d_byteenable[3] Z1_d_byteenable[3] = AMPP_FUNCTION(F1__clk1, Z1L3059, N1_data_out, Z1_A_en_d1); --Z1_d_byteenable[2] is system_0:u0|cpu_0:the_cpu_0|d_byteenable[2] Z1_d_byteenable[2] = AMPP_FUNCTION(F1__clk1, Z1L3058, N1_data_out, Z1_A_en_d1); --Z1_d_byteenable[0] is system_0:u0|cpu_0:the_cpu_0|d_byteenable[0] Z1_d_byteenable[0] = AMPP_FUNCTION(F1__clk1, Z1L3056, N1_data_out, Z1_A_en_d1); --LB1L6 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_byteenable_sram_0_avalonS[0]~48 LB1L6 = AB1_cpu_0_data_master_dbs_address[1] & Z1_d_byteenable[2] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_byteenable[0]); --JB1L10 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1~315 JB1L10 = !LB1L6 & (AB1_cpu_0_data_master_dbs_address[1] & (!Z1_d_byteenable[3]) # !AB1_cpu_0_data_master_dbs_address[1] & !Z1_d_byteenable[1]); --LB1L7 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_qualified_request_sram_0_avalonS~120 LB1L7 = Z1_d_write & (AB1_cpu_0_data_master_no_byte_enables_and_last_term # JB1L10); --LB1L8 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_qualified_request_sram_0_avalonS~121 LB1L8 = LB1_cpu_0_data_master_requests_sram_0_avalonS & !LB1L7 & (!LB1L68 # !LB1_sram_0_avalonS_slavearbiterlockenable); --LB1_sram_0_avalonS_arb_addend[1] is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_arb_addend[1] LB1_sram_0_avalonS_arb_addend[1] = DFFEAS(LB1L46, F1__clk1, N1_data_out, , , , , , ); --LB1L74 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_in_a_read_cycle~46 LB1L74 = LB1L73 & Z1_i_read & !Z1_ic_fill_tag[7]; --LB1L10 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_requests_sram_0_avalonS~0 LB1L10 = Z1_d_write # Z1_d_read; --LB1_last_cycle_cpu_0_data_master_granted_slave_sram_0_avalonS is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|last_cycle_cpu_0_data_master_granted_slave_sram_0_avalonS LB1_last_cycle_cpu_0_data_master_granted_slave_sram_0_avalonS = DFFEAS(LB1L18, F1__clk1, N1_data_out, , , , , , ); --LB1L5 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_arbiterlock~19 LB1L5 = LB1L1 & LB1L10 & LB1_last_cycle_cpu_0_data_master_granted_slave_sram_0_avalonS & !Z1_d_address[19]; --JE1_fifo_contains_ones_n is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|fifo_contains_ones_n JE1_fifo_contains_ones_n = DFFEAS(JE1L33, F1__clk1, N1_data_out, , JE1L13, , , , ); --BB1_cpu_0_instruction_master_latency_counter[1] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_latency_counter[1] BB1_cpu_0_instruction_master_latency_counter[1] = DFFEAS(BB1L249, F1__clk1, N1_data_out, , , , , , ); --BB1_cpu_0_instruction_master_latency_counter[0] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_latency_counter[0] BB1_cpu_0_instruction_master_latency_counter[0] = DFFEAS(BB1L248, F1__clk1, N1_data_out, , , , , , ); --BB1L256 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|r_1~177 BB1L256 = Z1_i_read & (JE1_fifo_contains_ones_n # BB1_cpu_0_instruction_master_latency_counter[1] # BB1_cpu_0_instruction_master_latency_counter[0]); --LB1L14 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_instruction_master_qualified_request_sram_0_avalonS~379 LB1L14 = LB1L74 & !BB1L256 & (!LB1L5 # !LB1_sram_0_avalonS_slavearbiterlockenable); --LB1_sram_0_avalonS_arb_addend[0] is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_arb_addend[0] LB1_sram_0_avalonS_arb_addend[0] = DFFEAS(LB1L43, F1__clk1, N1_data_out, , , , , , ); --LB1L70 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_grant_vector[1]~31 LB1L70 = LB1L8 & (LB1_sram_0_avalonS_arb_addend[1] # !LB1L14 & !LB1_sram_0_avalonS_arb_addend[0]); --LB1L22 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[0]~180 LB1L22 = LB1L70 & AB1_cpu_0_data_master_dbs_address[1] # !LB1L70 & (BB1_cpu_0_instruction_master_dbs_address[1]); --Z1_d_address[2] is system_0:u0|cpu_0:the_cpu_0|d_address[2] Z1_d_address[2] = AMPP_FUNCTION(F1__clk1, Z1_A_mem_baddr[2], N1_data_out, Z1L3021); --Z1_ic_fill_ap_offset[0] is system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_offset[0] Z1_ic_fill_ap_offset[0] = AMPP_FUNCTION(F1__clk1, Z1L3297, N1_data_out, Z1L3296); --LB1L23 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[1]~181 LB1L23 = LB1L70 & Z1_d_address[2] # !LB1L70 & (Z1_ic_fill_ap_offset[0]); --Z1_d_address[3] is system_0:u0|cpu_0:the_cpu_0|d_address[3] Z1_d_address[3] = AMPP_FUNCTION(F1__clk1, Z1_A_mem_baddr[3], N1_data_out, Z1L3021); --Z1_ic_fill_ap_offset[1] is system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_offset[1] Z1_ic_fill_ap_offset[1] = AMPP_FUNCTION(F1__clk1, Z1L3298, N1_data_out, Z1L3296); --LB1L24 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[2]~182 LB1L24 = LB1L70 & Z1_d_address[3] # !LB1L70 & (Z1_ic_fill_ap_offset[1]); --Z1_d_address[4] is system_0:u0|cpu_0:the_cpu_0|d_address[4] Z1_d_address[4] = AMPP_FUNCTION(F1__clk1, Z1_A_mem_baddr[4], N1_data_out, Z1L3021); --Z1_ic_fill_ap_offset[2] is system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_offset[2] Z1_ic_fill_ap_offset[2] = AMPP_FUNCTION(F1__clk1, Z1L3299, N1_data_out, Z1L3296); --LB1L25 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[3]~183 LB1L25 = LB1L70 & Z1_d_address[4] # !LB1L70 & (Z1_ic_fill_ap_offset[2]); --Z1_d_address[5] is system_0:u0|cpu_0:the_cpu_0|d_address[5] Z1_d_address[5] = AMPP_FUNCTION(F1__clk1, Z1_A_mem_baddr[5], N1_data_out, Z1L3021); --Z1_ic_fill_line[0] is system_0:u0|cpu_0:the_cpu_0|ic_fill_line[0] Z1_ic_fill_line[0] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[3], N1_data_out, Z1L1099); --LB1L26 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[4]~184 LB1L26 = LB1L70 & Z1_d_address[5] # !LB1L70 & (Z1_ic_fill_line[0]); --Z1_d_address[6] is system_0:u0|cpu_0:the_cpu_0|d_address[6] Z1_d_address[6] = AMPP_FUNCTION(F1__clk1, Z1_A_mem_baddr[6], N1_data_out, Z1L3021); --Z1_ic_fill_line[1] is system_0:u0|cpu_0:the_cpu_0|ic_fill_line[1] Z1_ic_fill_line[1] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[4], N1_data_out, Z1L1099); --LB1L27 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[5]~185 LB1L27 = LB1L70 & Z1_d_address[6] # !LB1L70 & (Z1_ic_fill_line[1]); --Z1_d_address[7] is system_0:u0|cpu_0:the_cpu_0|d_address[7] Z1_d_address[7] = AMPP_FUNCTION(F1__clk1, Z1_A_mem_baddr[7], N1_data_out, Z1L3021); --Z1_ic_fill_line[2] is system_0:u0|cpu_0:the_cpu_0|ic_fill_line[2] Z1_ic_fill_line[2] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[5], N1_data_out, Z1L1099); --LB1L28 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[6]~186 LB1L28 = LB1L70 & Z1_d_address[7] # !LB1L70 & (Z1_ic_fill_line[2]); --Z1_d_address[8] is system_0:u0|cpu_0:the_cpu_0|d_address[8] Z1_d_address[8] = AMPP_FUNCTION(F1__clk1, Z1_A_mem_baddr[8], N1_data_out, Z1L3021); --Z1_ic_fill_line[3] is system_0:u0|cpu_0:the_cpu_0|ic_fill_line[3] Z1_ic_fill_line[3] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[6], N1_data_out, Z1L1099); --LB1L29 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[7]~187 LB1L29 = LB1L70 & Z1_d_address[8] # !LB1L70 & (Z1_ic_fill_line[3]); --Z1_d_address[9] is system_0:u0|cpu_0:the_cpu_0|d_address[9] Z1_d_address[9] = AMPP_FUNCTION(F1__clk1, Z1_A_mem_baddr[9], N1_data_out, Z1L3021); --Z1_ic_fill_line[4] is system_0:u0|cpu_0:the_cpu_0|ic_fill_line[4] Z1_ic_fill_line[4] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[7], N1_data_out, Z1L1099); --LB1L30 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[8]~188 LB1L30 = LB1L70 & Z1_d_address[9] # !LB1L70 & (Z1_ic_fill_line[4]); --Z1_d_address[10] is system_0:u0|cpu_0:the_cpu_0|d_address[10] Z1_d_address[10] = AMPP_FUNCTION(F1__clk1, Z1_A_mem_baddr[10], N1_data_out, Z1L3021); --Z1_ic_fill_line[5] is system_0:u0|cpu_0:the_cpu_0|ic_fill_line[5] Z1_ic_fill_line[5] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[8], N1_data_out, Z1L1099); --LB1L31 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[9]~189 LB1L31 = LB1L70 & Z1_d_address[10] # !LB1L70 & (Z1_ic_fill_line[5]); --Z1_d_address[11] is system_0:u0|cpu_0:the_cpu_0|d_address[11] Z1_d_address[11] = AMPP_FUNCTION(F1__clk1, Z1L3203, N1_data_out, Z1L3021); --Z1_ic_fill_line[6] is system_0:u0|cpu_0:the_cpu_0|ic_fill_line[6] Z1_ic_fill_line[6] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[9], N1_data_out, Z1L1099); --LB1L32 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[10]~190 LB1L32 = LB1L70 & Z1_d_address[11] # !LB1L70 & (Z1_ic_fill_line[6]); --Z1_d_address[12] is system_0:u0|cpu_0:the_cpu_0|d_address[12] Z1_d_address[12] = AMPP_FUNCTION(F1__clk1, Z1L3204, N1_data_out, Z1L3021); --Z1_ic_fill_tag[0] is system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[0] Z1_ic_fill_tag[0] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[10], N1_data_out, Z1L1099); --LB1L33 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[11]~191 LB1L33 = LB1L70 & Z1_d_address[12] # !LB1L70 & (Z1_ic_fill_tag[0]); --Z1_d_address[13] is system_0:u0|cpu_0:the_cpu_0|d_address[13] Z1_d_address[13] = AMPP_FUNCTION(F1__clk1, Z1L3205, N1_data_out, Z1L3021); --Z1_ic_fill_tag[1] is system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[1] Z1_ic_fill_tag[1] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[11], N1_data_out, Z1L1099); --LB1L34 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[12]~192 LB1L34 = LB1L70 & Z1_d_address[13] # !LB1L70 & (Z1_ic_fill_tag[1]); --Z1_d_address[14] is system_0:u0|cpu_0:the_cpu_0|d_address[14] Z1_d_address[14] = AMPP_FUNCTION(F1__clk1, Z1L3206, N1_data_out, Z1L3021); --Z1_ic_fill_tag[2] is system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[2] Z1_ic_fill_tag[2] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[12], N1_data_out, Z1L1099); --LB1L35 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[13]~193 LB1L35 = LB1L70 & Z1_d_address[14] # !LB1L70 & (Z1_ic_fill_tag[2]); --Z1_d_address[15] is system_0:u0|cpu_0:the_cpu_0|d_address[15] Z1_d_address[15] = AMPP_FUNCTION(F1__clk1, Z1L3207, N1_data_out, Z1L3021); --Z1_ic_fill_tag[3] is system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[3] Z1_ic_fill_tag[3] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[13], N1_data_out, Z1L1099); --LB1L36 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[14]~194 LB1L36 = LB1L70 & Z1_d_address[15] # !LB1L70 & (Z1_ic_fill_tag[3]); --Z1_d_address[16] is system_0:u0|cpu_0:the_cpu_0|d_address[16] Z1_d_address[16] = AMPP_FUNCTION(F1__clk1, Z1L3208, N1_data_out, Z1L3021); --Z1_ic_fill_tag[4] is system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[4] Z1_ic_fill_tag[4] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[14], N1_data_out, Z1L1099); --LB1L37 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[15]~195 LB1L37 = LB1L70 & Z1_d_address[16] # !LB1L70 & (Z1_ic_fill_tag[4]); --Z1_d_address[17] is system_0:u0|cpu_0:the_cpu_0|d_address[17] Z1_d_address[17] = AMPP_FUNCTION(F1__clk1, Z1L3209, N1_data_out, Z1L3021); --Z1_ic_fill_tag[5] is system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[5] Z1_ic_fill_tag[5] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[15], N1_data_out, Z1L1099); --LB1L38 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[16]~196 LB1L38 = LB1L70 & Z1_d_address[17] # !LB1L70 & (Z1_ic_fill_tag[5]); --Z1_d_address[18] is system_0:u0|cpu_0:the_cpu_0|d_address[18] Z1_d_address[18] = AMPP_FUNCTION(F1__clk1, Z1L3210, N1_data_out, Z1L3021); --Z1_ic_fill_tag[6] is system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[6] Z1_ic_fill_tag[6] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[16], N1_data_out, Z1L1099); --LB1L39 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[17]~197 LB1L39 = LB1L70 & Z1_d_address[18] # !LB1L70 & (Z1_ic_fill_tag[6]); --LB1L65 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_counter_load_value~200 LB1L65 = Z1_d_write & LB1L70; --LB1_sram_0_avalonS_wait_counter[1] is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_wait_counter[1] LB1_sram_0_avalonS_wait_counter[1] = DFFEAS(LB1L62, F1__clk1, N1_data_out, , , , , , ); --LB1_d1_reasons_to_wait is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|d1_reasons_to_wait LB1_d1_reasons_to_wait = DFFEAS(LB1L67, F1__clk1, N1_data_out, , , , , , ); --LB1L58 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_begins_xfer~44 LB1L58 = !LB1_d1_reasons_to_wait & (LB1L8 # LB1L14); --LB1_sram_0_avalonS_wait_counter[2] is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_wait_counter[2] LB1_sram_0_avalonS_wait_counter[2] = DFFEAS(LB1L64, F1__clk1, N1_data_out, , , , , , ); --LB1L85 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_write_n~29 LB1L85 = LB1L65 & LB1_sram_0_avalonS_wait_counter[1] & !LB1L58 & !LB1_sram_0_avalonS_wait_counter[2]; --LB1L59 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_chipselect_n~0 LB1L59 = LB1_sram_0_avalonS_arb_addend[1] & (LB1L8 # LB1L14) # !LB1_sram_0_avalonS_arb_addend[1] & !LB1_sram_0_avalonS_arb_addend[0] & (LB1L8 # LB1L14); --LB1_cpu_0_instruction_master_granted_sram_0_avalonS is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_instruction_master_granted_sram_0_avalonS LB1_cpu_0_instruction_master_granted_sram_0_avalonS = LB1L14 & (LB1_sram_0_avalonS_arb_addend[1] & !LB1L8 # !LB1_sram_0_avalonS_arb_addend[0]) # !LB1L14 & (LB1_sram_0_avalonS_arb_addend[0] # !LB1_sram_0_avalonS_arb_addend[1] & LB1L8); --LB1_sram_0_avalonS_in_a_read_cycle is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_in_a_read_cycle LB1_sram_0_avalonS_in_a_read_cycle = Z1_d_read & (LB1L70 # LB1L14 & LB1_cpu_0_instruction_master_granted_sram_0_avalonS) # !Z1_d_read & LB1L14 & LB1_cpu_0_instruction_master_granted_sram_0_avalonS; --A1L334 is altera_internal_jtag~TDO A1L334 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L23); --A1L335 is altera_internal_jtag~TMSUTAP A1L335 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L23); --A1L333 is altera_internal_jtag~TCKUTAP A1L333 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L23); --altera_internal_jtag is altera_internal_jtag altera_internal_jtag = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L23); --A1L332 is altera_internal_jtag~SHIFTUSER A1L332 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L23); --A1L336 is altera_internal_jtag~UPDATEUSER A1L336 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L23); --A1L331 is altera_internal_jtag~RUNIDLEUSER A1L331 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L23); --Z1_d_writedata[0] is system_0:u0|cpu_0:the_cpu_0|d_writedata[0] Z1_d_writedata[0] = AMPP_FUNCTION(F1__clk1, Z1L3129, N1_data_out, Z1_A_en_d1); --N1_data_out is system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|data_out N1_data_out = DFFEAS(N1_data_in_d1, F1__clk1, !E1L1, , , , , , ); --AB1_cpu_0_data_master_waitrequest is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest AB1_cpu_0_data_master_waitrequest = DFFEAS(AB1L234, F1__clk1, N1_data_out, , , , , , ); --P1L1 is system_0:u0|KEY:the_KEY|always1~28 P1L1 = Z1_d_write & !AB1_cpu_0_data_master_waitrequest; --GB1L1 is system_0:u0|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave|Equal~180 GB1L1 = Z1_d_address[19] & !Z1_d_address[13] & !Z1_d_address[14] & !Z1_d_address[15]; --GB1L2 is system_0:u0|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave|Equal~181 GB1L2 = !Z1_d_address[17] & !Z1_d_address[18]; --GB1L3 is system_0:u0|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave|Equal~182 GB1L3 = LB1L1 & GB1L1 & GB1L2 & !Z1_d_address[16]; --GB1L4 is system_0:u0|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave|Equal~183 GB1L4 = !Z1_d_address[7] & !Z1_d_address[8] & !Z1_d_address[9] & !Z1_d_address[10]; --GB1L5 is system_0:u0|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave|Equal~184 GB1L5 = Z1_d_address[12] & !Z1_d_address[11]; --GB1L6 is system_0:u0|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave|Equal~185 GB1L6 = Z1_d_address[5] & GB1L3 & GB1L4 & GB1L5; --LE1L1 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|Equal~91 LE1L1 = Z1_d_address[3] & !Z1_d_address[2] & !Z1_d_address[4]; --W1L1 is system_0:u0|SEG7_avalonS_arbitrator:the_SEG7_avalonS|SEG7_avalonS_write~18 W1L1 = Z1_d_address[6] & P1L1 & GB1L6 & LE1L1; --Z1_d_writedata[1] is system_0:u0|cpu_0:the_cpu_0|d_writedata[1] Z1_d_writedata[1] = AMPP_FUNCTION(F1__clk1, Z1L3130, N1_data_out, Z1_A_en_d1); --Z1_d_writedata[2] is system_0:u0|cpu_0:the_cpu_0|d_writedata[2] Z1_d_writedata[2] = AMPP_FUNCTION(F1__clk1, Z1L3131, N1_data_out, Z1_A_en_d1); --Z1_d_writedata[3] is system_0:u0|cpu_0:the_cpu_0|d_writedata[3] Z1_d_writedata[3] = AMPP_FUNCTION(F1__clk1, Z1L3132, N1_data_out, Z1_A_en_d1); --Z1_d_writedata[4] is system_0:u0|cpu_0:the_cpu_0|d_writedata[4] Z1_d_writedata[4] = AMPP_FUNCTION(F1__clk1, Z1L3133, N1_data_out, Z1_A_en_d1); --Z1_d_writedata[5] is system_0:u0|cpu_0:the_cpu_0|d_writedata[5] Z1_d_writedata[5] = AMPP_FUNCTION(F1__clk1, Z1L3134, N1_data_out, Z1_A_en_d1); --Z1_d_writedata[6] is system_0:u0|cpu_0:the_cpu_0|d_writedata[6] Z1_d_writedata[6] = AMPP_FUNCTION(F1__clk1, Z1L3135, N1_data_out, Z1_A_en_d1); --Z1_d_writedata[7] is system_0:u0|cpu_0:the_cpu_0|d_writedata[7] Z1_d_writedata[7] = AMPP_FUNCTION(F1__clk1, Z1L3136, N1_data_out, Z1_A_en_d1); --Z1_d_writedata[8] is system_0:u0|cpu_0:the_cpu_0|d_writedata[8] Z1_d_writedata[8] = AMPP_FUNCTION(F1__clk1, Z1L3137, N1_data_out, Z1_A_en_d1); --Z1_d_writedata[9] is system_0:u0|cpu_0:the_cpu_0|d_writedata[9] Z1_d_writedata[9] = AMPP_FUNCTION(F1__clk1, Z1L3138, N1_data_out, Z1_A_en_d1); --Z1_d_writedata[10] is system_0:u0|cpu_0:the_cpu_0|d_writedata[10] Z1_d_writedata[10] = AMPP_FUNCTION(F1__clk1, Z1L3139, N1_data_out, Z1_A_en_d1); --Z1_d_writedata[11] is system_0:u0|cpu_0:the_cpu_0|d_writedata[11] Z1_d_writedata[11] = AMPP_FUNCTION(F1__clk1, Z1L3140, N1_data_out, Z1_A_en_d1); --Z1_d_writedata[12] is system_0:u0|cpu_0:the_cpu_0|d_writedata[12] Z1_d_writedata[12] = AMPP_FUNCTION(F1__clk1, Z1L3141, N1_data_out, Z1_A_en_d1); --Z1_d_writedata[13] is system_0:u0|cpu_0:the_cpu_0|d_writedata[13] Z1_d_writedata[13] = AMPP_FUNCTION(F1__clk1, Z1L3142, N1_data_out, Z1_A_en_d1); --Z1_d_writedata[14] is system_0:u0|cpu_0:the_cpu_0|d_writedata[14] Z1_d_writedata[14] = AMPP_FUNCTION(F1__clk1, Z1L3143, N1_data_out, Z1_A_en_d1); --Z1_d_writedata[15] is system_0:u0|cpu_0:the_cpu_0|d_writedata[15] Z1_d_writedata[15] = AMPP_FUNCTION(F1__clk1, Z1L3144, N1_data_out, Z1_A_en_d1); --R1L1 is system_0:u0|LEDG:the_LEDG|Equal~67 R1L1 = Z1_d_address[2] # Z1_d_address[3]; --T1L1 is system_0:u0|LEDR:the_LEDR|always0~26 T1L1 = P1L1 & GB1L6 & !Z1_d_address[6] & !R1L1; --R1L2 is system_0:u0|LEDG:the_LEDG|always0~23 R1L2 = Z1_d_byteenable[0] & T1L1 & !Z1_d_address[4]; --T1L2 is system_0:u0|LEDR:the_LEDR|always0~27 T1L2 = Z1_d_address[4] & T1L1; --LE1_control_reg[9] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|control_reg[9] LE1_control_reg[9] = DFFEAS(Z1_d_writedata[9], F1__clk1, N1_data_out, , LE1L15, , , , ); --NE1_pre_txd is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|pre_txd NE1_pre_txd = DFFEAS(NE1L43, F1__clk1, N1_data_out, , , , , , ); --NE1L53 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|txd~0 NE1L53 = LE1_control_reg[9] # NE1_pre_txd; --HB1_active_addr[9] is system_0:u0|sdram_0:the_sdram_0|active_addr[9] HB1_active_addr[9] = DFFEAS(HB1L9, F1__clk1, , , HB1L208, , , , ); --HB1_m_state.000000010 is system_0:u0|sdram_0:the_sdram_0|m_state.000000010 HB1_m_state.000000010 = DFFEAS(HB1L181, F1__clk1, N1_data_out, , , , , , ); --HB1_f_pop is system_0:u0|sdram_0:the_sdram_0|f_pop HB1_f_pop = DFFEAS(HB1L68, F1__clk1, N1_data_out, , , , , , ); --GE1_entries[1] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entries[1] GE1_entries[1] = DFFEAS(GE1L6, F1__clk1, N1_data_out, , , , , , ); --GE1_entries[0] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entries[0] GE1_entries[0] = DFFEAS(GE1L4, F1__clk1, N1_data_out, , , , , , ); --GE1L1 is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|empty~91 GE1L1 = GE1_entries[1] # GE1_entries[0]; --HB1_active_rnw is system_0:u0|sdram_0:the_sdram_0|active_rnw HB1_active_rnw = DFFEAS(HB1L8, F1__clk1, , , HB1L208, , , , ); --GE1_entry_1[40] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[40] GE1_entry_1[40] = DFFEAS(JB1_sdram_0_s1_in_a_write_cycle, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[40] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[40] GE1_entry_0[40] = DFFEAS(JB1_sdram_0_s1_in_a_write_cycle, F1__clk1, , , GE1L47, , , , ); --GE1_rd_address is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address GE1_rd_address = DFFEAS(GE1L95, F1__clk1, N1_data_out, , , , , , ); --HB1L8 is system_0:u0|sdram_0:the_sdram_0|Select~8112 HB1L8 = GE1_rd_address & GE1_entry_1[40] # !GE1_rd_address & (GE1_entry_0[40]); --GE1_entry_1[27] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[27] GE1_entry_1[27] = DFFEAS(JB1L36, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[27] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[27] GE1_entry_0[27] = DFFEAS(JB1L36, F1__clk1, , , GE1L47, , , , ); --HB1L9 is system_0:u0|sdram_0:the_sdram_0|Select~8113 HB1L9 = GE1_rd_address & GE1_entry_1[27] # !GE1_rd_address & (GE1_entry_0[27]); --HB1L376 is system_0:u0|sdram_0:the_sdram_0|pending~267 HB1L376 = HB1_active_addr[9] & HB1L9 & (HB1_active_rnw $ !HB1L8) # !HB1_active_addr[9] & !HB1L9 & (HB1_active_rnw $ !HB1L8); --HB1_active_addr[14] is system_0:u0|sdram_0:the_sdram_0|active_addr[14] HB1_active_addr[14] = DFFEAS(HB1L11, F1__clk1, , , HB1L208, , , , ); --HB1_active_addr[13] is system_0:u0|sdram_0:the_sdram_0|active_addr[13] HB1_active_addr[13] = DFFEAS(HB1L10, F1__clk1, , , HB1L208, , , , ); --GE1_entry_1[31] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[31] GE1_entry_1[31] = DFFEAS(JB1L40, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[31] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[31] GE1_entry_0[31] = DFFEAS(JB1L40, F1__clk1, , , GE1L47, , , , ); --HB1L10 is system_0:u0|sdram_0:the_sdram_0|Select~8114 HB1L10 = GE1_rd_address & GE1_entry_1[31] # !GE1_rd_address & (GE1_entry_0[31]); --GE1_entry_1[32] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[32] GE1_entry_1[32] = DFFEAS(JB1L41, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[32] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[32] GE1_entry_0[32] = DFFEAS(JB1L41, F1__clk1, , , GE1L47, , , , ); --HB1L11 is system_0:u0|sdram_0:the_sdram_0|Select~8115 HB1L11 = GE1_rd_address & GE1_entry_1[32] # !GE1_rd_address & (GE1_entry_0[32]); --HB1L377 is system_0:u0|sdram_0:the_sdram_0|pending~268 HB1L377 = HB1_active_addr[14] & HB1L11 & (HB1_active_addr[13] $ !HB1L10) # !HB1_active_addr[14] & !HB1L11 & (HB1_active_addr[13] $ !HB1L10); --HB1_active_addr[11] is system_0:u0|sdram_0:the_sdram_0|active_addr[11] HB1_active_addr[11] = DFFEAS(HB1L13, F1__clk1, , , HB1L208, , , , ); --HB1_active_addr[8] is system_0:u0|sdram_0:the_sdram_0|active_addr[8] HB1_active_addr[8] = DFFEAS(HB1L12, F1__clk1, , , HB1L208, , , , ); --GE1_entry_1[26] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[26] GE1_entry_1[26] = DFFEAS(JB1L35, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[26] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[26] GE1_entry_0[26] = DFFEAS(JB1L35, F1__clk1, , , GE1L47, , , , ); --HB1L12 is system_0:u0|sdram_0:the_sdram_0|Select~8116 HB1L12 = GE1_rd_address & GE1_entry_1[26] # !GE1_rd_address & (GE1_entry_0[26]); --GE1_entry_1[29] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[29] GE1_entry_1[29] = DFFEAS(JB1L38, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[29] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[29] GE1_entry_0[29] = DFFEAS(JB1L38, F1__clk1, , , GE1L47, , , , ); --HB1L13 is system_0:u0|sdram_0:the_sdram_0|Select~8117 HB1L13 = GE1_rd_address & GE1_entry_1[29] # !GE1_rd_address & (GE1_entry_0[29]); --HB1L378 is system_0:u0|sdram_0:the_sdram_0|pending~269 HB1L378 = HB1_active_addr[11] & HB1L13 & (HB1_active_addr[8] $ !HB1L12) # !HB1_active_addr[11] & !HB1L13 & (HB1_active_addr[8] $ !HB1L12); --HB1_active_addr[16] is system_0:u0|sdram_0:the_sdram_0|active_addr[16] HB1_active_addr[16] = DFFEAS(HB1L15, F1__clk1, , , HB1L208, , , , ); --HB1_active_addr[15] is system_0:u0|sdram_0:the_sdram_0|active_addr[15] HB1_active_addr[15] = DFFEAS(HB1L14, F1__clk1, , , HB1L208, , , , ); --GE1_entry_1[33] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[33] GE1_entry_1[33] = DFFEAS(JB1L42, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[33] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[33] GE1_entry_0[33] = DFFEAS(JB1L42, F1__clk1, , , GE1L47, , , , ); --HB1L14 is system_0:u0|sdram_0:the_sdram_0|Select~8118 HB1L14 = GE1_rd_address & GE1_entry_1[33] # !GE1_rd_address & (GE1_entry_0[33]); --GE1_entry_1[34] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[34] GE1_entry_1[34] = DFFEAS(JB1L43, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[34] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[34] GE1_entry_0[34] = DFFEAS(JB1L43, F1__clk1, , , GE1L47, , , , ); --HB1L15 is system_0:u0|sdram_0:the_sdram_0|Select~8119 HB1L15 = GE1_rd_address & GE1_entry_1[34] # !GE1_rd_address & (GE1_entry_0[34]); --HB1L379 is system_0:u0|sdram_0:the_sdram_0|pending~270 HB1L379 = HB1_active_addr[16] & HB1L15 & (HB1_active_addr[15] $ !HB1L14) # !HB1_active_addr[16] & !HB1L15 & (HB1_active_addr[15] $ !HB1L14); --HB1L380 is system_0:u0|sdram_0:the_sdram_0|pending~271 HB1L380 = HB1L376 & HB1L377 & HB1L378 & HB1L379; --HB1_active_addr[17] is system_0:u0|sdram_0:the_sdram_0|active_addr[17] HB1_active_addr[17] = DFFEAS(HB1L17, F1__clk1, , , HB1L208, , , , ); --HB1_active_addr[10] is system_0:u0|sdram_0:the_sdram_0|active_addr[10] HB1_active_addr[10] = DFFEAS(HB1L16, F1__clk1, , , HB1L208, , , , ); --GE1_entry_1[28] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[28] GE1_entry_1[28] = DFFEAS(JB1L37, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[28] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[28] GE1_entry_0[28] = DFFEAS(JB1L37, F1__clk1, , , GE1L47, , , , ); --HB1L16 is system_0:u0|sdram_0:the_sdram_0|Select~8120 HB1L16 = GE1_rd_address & GE1_entry_1[28] # !GE1_rd_address & (GE1_entry_0[28]); --GE1_entry_1[35] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[35] GE1_entry_1[35] = DFFEAS(JB1L44, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[35] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[35] GE1_entry_0[35] = DFFEAS(JB1L44, F1__clk1, , , GE1L47, , , , ); --HB1L17 is system_0:u0|sdram_0:the_sdram_0|Select~8121 HB1L17 = GE1_rd_address & GE1_entry_1[35] # !GE1_rd_address & (GE1_entry_0[35]); --HB1L381 is system_0:u0|sdram_0:the_sdram_0|pending~272 HB1L381 = HB1_active_addr[17] & HB1L17 & (HB1_active_addr[10] $ !HB1L16) # !HB1_active_addr[17] & !HB1L17 & (HB1_active_addr[10] $ !HB1L16); --HB1_active_addr[21] is system_0:u0|sdram_0:the_sdram_0|active_addr[21] HB1_active_addr[21] = DFFEAS(HB1L18, F1__clk1, , , HB1L208, , , , ); --GE1_entry_1[39] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[39] GE1_entry_1[39] = DFFEAS(JB1L48, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[39] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[39] GE1_entry_0[39] = DFFEAS(JB1L48, F1__clk1, , , GE1L47, , , , ); --HB1L18 is system_0:u0|sdram_0:the_sdram_0|Select~8122 HB1L18 = GE1_rd_address & GE1_entry_1[39] # !GE1_rd_address & (GE1_entry_0[39]); --GE1_entry_0[38] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[38] GE1_entry_0[38] = DFFEAS(JB1L47, F1__clk1, , , GE1L47, , , , ); --GE1_entry_1[38] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[38] GE1_entry_1[38] = DFFEAS(JB1L47, F1__clk1, , , GE1L90, , , , ); --HB1_active_addr[20] is system_0:u0|sdram_0:the_sdram_0|active_addr[20] HB1_active_addr[20] = DFFEAS(HB1L69, F1__clk1, , , HB1L208, , , , ); --HB1L423 is system_0:u0|sdram_0:the_sdram_0|row_match~363 HB1L423 = HB1_active_addr[20] $ (GE1_rd_address & (GE1_entry_1[38]) # !GE1_rd_address & GE1_entry_0[38]); --HB1L382 is system_0:u0|sdram_0:the_sdram_0|pending~273 HB1L382 = HB1L381 & !HB1L423 & (HB1_active_addr[21] $ !HB1L18); --HB1_active_addr[18] is system_0:u0|sdram_0:the_sdram_0|active_addr[18] HB1_active_addr[18] = DFFEAS(HB1L20, F1__clk1, , , HB1L208, , , , ); --HB1_active_addr[12] is system_0:u0|sdram_0:the_sdram_0|active_addr[12] HB1_active_addr[12] = DFFEAS(HB1L19, F1__clk1, , , HB1L208, , , , ); --GE1_entry_1[30] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[30] GE1_entry_1[30] = DFFEAS(JB1L39, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[30] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[30] GE1_entry_0[30] = DFFEAS(JB1L39, F1__clk1, , , GE1L47, , , , ); --HB1L19 is system_0:u0|sdram_0:the_sdram_0|Select~8123 HB1L19 = GE1_rd_address & GE1_entry_1[30] # !GE1_rd_address & (GE1_entry_0[30]); --GE1_entry_1[36] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[36] GE1_entry_1[36] = DFFEAS(JB1L45, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[36] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[36] GE1_entry_0[36] = DFFEAS(JB1L45, F1__clk1, , , GE1L47, , , , ); --HB1L20 is system_0:u0|sdram_0:the_sdram_0|Select~8124 HB1L20 = GE1_rd_address & GE1_entry_1[36] # !GE1_rd_address & (GE1_entry_0[36]); --HB1L383 is system_0:u0|sdram_0:the_sdram_0|pending~274 HB1L383 = HB1_active_addr[18] & HB1L20 & (HB1_active_addr[12] $ !HB1L19) # !HB1_active_addr[18] & !HB1L20 & (HB1_active_addr[12] $ !HB1L19); --HB1_active_addr[19] is system_0:u0|sdram_0:the_sdram_0|active_addr[19] HB1_active_addr[19] = DFFEAS(HB1L21, F1__clk1, , , HB1L208, , , , ); --GE1_entry_1[37] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[37] GE1_entry_1[37] = DFFEAS(JB1L46, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[37] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[37] GE1_entry_0[37] = DFFEAS(JB1L46, F1__clk1, , , GE1L47, , , , ); --HB1L21 is system_0:u0|sdram_0:the_sdram_0|Select~8125 HB1L21 = GE1_rd_address & GE1_entry_1[37] # !GE1_rd_address & (GE1_entry_0[37]); --HB1_active_cs_n is system_0:u0|sdram_0:the_sdram_0|active_cs_n HB1_active_cs_n = DFFEAS(HB1L211, F1__clk1, , , , , , , ); --HB1L384 is system_0:u0|sdram_0:the_sdram_0|pending~275 HB1L384 = HB1L383 & !HB1_active_cs_n & (HB1_active_addr[19] $ !HB1L21); --HB1L22 is system_0:u0|sdram_0:the_sdram_0|Select~8126 HB1L22 = GE1L1 & HB1L380 & HB1L382 & HB1L384; --HB1_m_state.000001000 is system_0:u0|sdram_0:the_sdram_0|m_state.000001000 HB1_m_state.000001000 = DFFEAS(HB1L364, F1__clk1, N1_data_out, , HB1L367, , , , ); --HB1_m_state.000010000 is system_0:u0|sdram_0:the_sdram_0|m_state.000010000 HB1_m_state.000010000 = DFFEAS(HB1L368, F1__clk1, N1_data_out, , HB1L367, , , , ); --HB1L358 is system_0:u0|sdram_0:the_sdram_0|m_state.000000001~94 HB1L358 = !HB1_m_state.000001000 & !HB1_m_state.000010000; --HB1L299 is system_0:u0|sdram_0:the_sdram_0|m_addr[0]~119 HB1L299 = HB1L358 & HB1_m_state.000000010 # !HB1L358 & (HB1_f_pop & HB1L22); --HB1_active_addr[0] is system_0:u0|sdram_0:the_sdram_0|active_addr[0] HB1_active_addr[0] = DFFEAS(HB1L24, F1__clk1, , , HB1L208, , , , ); --HB1_i_addr[11] is system_0:u0|sdram_0:the_sdram_0|i_addr[11] HB1_i_addr[11] = DFFEAS(HB1_i_state.111, F1__clk1, N1_data_out, , , , , , ); --HB1L23 is system_0:u0|sdram_0:the_sdram_0|Select~8127 HB1L23 = HB1L299 & (!HB1L358) # !HB1L299 & (HB1L358 & (!HB1_i_addr[11]) # !HB1L358 & HB1_active_addr[0]); --GE1_entry_1[18] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[18] GE1_entry_1[18] = DFFEAS(JB1L27, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[18] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[18] GE1_entry_0[18] = DFFEAS(JB1L27, F1__clk1, , , GE1L47, , , , ); --HB1L24 is system_0:u0|sdram_0:the_sdram_0|Select~8128 HB1L24 = GE1_rd_address & GE1_entry_1[18] # !GE1_rd_address & (GE1_entry_0[18]); --HB1L25 is system_0:u0|sdram_0:the_sdram_0|Select~8129 HB1L25 = HB1L299 & (HB1L23 & (HB1L24) # !HB1L23 & HB1_active_addr[9]) # !HB1L299 & (HB1L23); --HB1_m_state.001000000 is system_0:u0|sdram_0:the_sdram_0|m_state.001000000 HB1_m_state.001000000 = DFFEAS(HB1L182, F1__clk1, N1_data_out, , , , , , ); --HB1_m_state.010000000 is system_0:u0|sdram_0:the_sdram_0|m_state.010000000 HB1_m_state.010000000 = DFFEAS(HB1L74, F1__clk1, N1_data_out, , , , , , ); --HB1_init_done is system_0:u0|sdram_0:the_sdram_0|init_done HB1_init_done = DFFEAS(HB1L296, F1__clk1, N1_data_out, , , , , , ); --HB1_m_state.000000001 is system_0:u0|sdram_0:the_sdram_0|m_state.000000001 HB1_m_state.000000001 = DFFEAS(HB1L76, F1__clk1, N1_data_out, , , , , , ); --HB1L300 is system_0:u0|sdram_0:the_sdram_0|m_addr[0]~120 HB1L300 = HB1_init_done & !HB1_m_state.000000001; --HB1_m_state.100000000 is system_0:u0|sdram_0:the_sdram_0|m_state.100000000 HB1_m_state.100000000 = DFFEAS(HB1L77, F1__clk1, N1_data_out, , , , , , ); --HB1_m_state.000000100 is system_0:u0|sdram_0:the_sdram_0|m_state.000000100 HB1_m_state.000000100 = DFFEAS(HB1L80, F1__clk1, N1_data_out, , , , , , ); --HB1_m_state.000100000 is system_0:u0|sdram_0:the_sdram_0|m_state.000100000 HB1_m_state.000100000 = DFFEAS(HB1L82, F1__clk1, N1_data_out, , , , , , ); --HB1L301 is system_0:u0|sdram_0:the_sdram_0|m_addr[0]~121 HB1L301 = !HB1_m_state.100000000 & !HB1_m_state.000000100 & !HB1_m_state.000100000; --HB1_active_addr[1] is system_0:u0|sdram_0:the_sdram_0|active_addr[1] HB1_active_addr[1] = DFFEAS(HB1L27, F1__clk1, , , HB1L208, , , , ); --HB1L26 is system_0:u0|sdram_0:the_sdram_0|Select~8130 HB1L26 = HB1L299 & (!HB1L358) # !HB1L299 & (HB1L358 & (!HB1_i_addr[11]) # !HB1L358 & HB1_active_addr[1]); --GE1_entry_1[19] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[19] GE1_entry_1[19] = DFFEAS(JB1L28, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[19] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[19] GE1_entry_0[19] = DFFEAS(JB1L28, F1__clk1, , , GE1L47, , , , ); --HB1L27 is system_0:u0|sdram_0:the_sdram_0|Select~8131 HB1L27 = GE1_rd_address & GE1_entry_1[19] # !GE1_rd_address & (GE1_entry_0[19]); --HB1L28 is system_0:u0|sdram_0:the_sdram_0|Select~8132 HB1L28 = HB1L299 & (HB1L26 & (HB1L27) # !HB1L26 & HB1_active_addr[10]) # !HB1L299 & (HB1L26); --HB1_active_addr[2] is system_0:u0|sdram_0:the_sdram_0|active_addr[2] HB1_active_addr[2] = DFFEAS(HB1L30, F1__clk1, , , HB1L208, , , , ); --HB1L29 is system_0:u0|sdram_0:the_sdram_0|Select~8133 HB1L29 = HB1L299 & (!HB1L358) # !HB1L299 & (HB1L358 & (!HB1_i_addr[11]) # !HB1L358 & HB1_active_addr[2]); --GE1_entry_1[20] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[20] GE1_entry_1[20] = DFFEAS(JB1L29, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[20] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[20] GE1_entry_0[20] = DFFEAS(JB1L29, F1__clk1, , , GE1L47, , , , ); --HB1L30 is system_0:u0|sdram_0:the_sdram_0|Select~8134 HB1L30 = GE1_rd_address & GE1_entry_1[20] # !GE1_rd_address & (GE1_entry_0[20]); --HB1L31 is system_0:u0|sdram_0:the_sdram_0|Select~8135 HB1L31 = HB1L299 & (HB1L29 & (HB1L30) # !HB1L29 & HB1_active_addr[11]) # !HB1L299 & (HB1L29); --HB1_active_addr[3] is system_0:u0|sdram_0:the_sdram_0|active_addr[3] HB1_active_addr[3] = DFFEAS(HB1L33, F1__clk1, , , HB1L208, , , , ); --HB1L32 is system_0:u0|sdram_0:the_sdram_0|Select~8136 HB1L32 = HB1L299 & (!HB1L358) # !HB1L299 & (HB1L358 & (!HB1_i_addr[11]) # !HB1L358 & HB1_active_addr[3]); --GE1_entry_1[21] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[21] GE1_entry_1[21] = DFFEAS(JB1L30, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[21] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[21] GE1_entry_0[21] = DFFEAS(JB1L30, F1__clk1, , , GE1L47, , , , ); --HB1L33 is system_0:u0|sdram_0:the_sdram_0|Select~8137 HB1L33 = GE1_rd_address & GE1_entry_1[21] # !GE1_rd_address & (GE1_entry_0[21]); --HB1L34 is system_0:u0|sdram_0:the_sdram_0|Select~8138 HB1L34 = HB1L299 & (HB1L32 & (HB1L33) # !HB1L32 & HB1_active_addr[12]) # !HB1L299 & (HB1L32); --GE1_entry_1[22] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[22] GE1_entry_1[22] = DFFEAS(JB1L31, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[22] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[22] GE1_entry_0[22] = DFFEAS(JB1L31, F1__clk1, , , GE1L47, , , , ); --HB1L35 is system_0:u0|sdram_0:the_sdram_0|Select~8139 HB1L35 = GE1_rd_address & GE1_entry_1[22] # !GE1_rd_address & (GE1_entry_0[22]); --HB1_active_addr[4] is system_0:u0|sdram_0:the_sdram_0|active_addr[4] HB1_active_addr[4] = DFFEAS(HB1L35, F1__clk1, , , HB1L208, , , , ); --HB1L36 is system_0:u0|sdram_0:the_sdram_0|Select~8140 HB1L36 = HB1_f_pop & (HB1L22 & HB1L35 # !HB1L22 & (HB1_active_addr[4])) # !HB1_f_pop & (HB1_active_addr[4]); --HB1L37 is system_0:u0|sdram_0:the_sdram_0|Select~8141 HB1L37 = HB1L358 & (HB1_active_addr[13] # !HB1_m_state.000000010) # !HB1L358 & (HB1L36); --GE1_entry_1[23] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[23] GE1_entry_1[23] = DFFEAS(JB1L32, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[23] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[23] GE1_entry_0[23] = DFFEAS(JB1L32, F1__clk1, , , GE1L47, , , , ); --HB1L38 is system_0:u0|sdram_0:the_sdram_0|Select~8142 HB1L38 = GE1_rd_address & GE1_entry_1[23] # !GE1_rd_address & (GE1_entry_0[23]); --HB1_active_addr[5] is system_0:u0|sdram_0:the_sdram_0|active_addr[5] HB1_active_addr[5] = DFFEAS(HB1L38, F1__clk1, , , HB1L208, , , , ); --HB1L39 is system_0:u0|sdram_0:the_sdram_0|Select~8143 HB1L39 = HB1_f_pop & (HB1L22 & HB1L38 # !HB1L22 & (HB1_active_addr[5])) # !HB1_f_pop & (HB1_active_addr[5]); --HB1L40 is system_0:u0|sdram_0:the_sdram_0|Select~8144 HB1L40 = HB1L358 & (HB1_active_addr[14] # !HB1_m_state.000000010) # !HB1L358 & (HB1L39); --HB1_active_addr[6] is system_0:u0|sdram_0:the_sdram_0|active_addr[6] HB1_active_addr[6] = DFFEAS(HB1L42, F1__clk1, , , HB1L208, , , , ); --HB1L41 is system_0:u0|sdram_0:the_sdram_0|Select~8145 HB1L41 = HB1L299 & (!HB1L358) # !HB1L299 & (HB1L358 & (!HB1_i_addr[11]) # !HB1L358 & HB1_active_addr[6]); --GE1_entry_1[24] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[24] GE1_entry_1[24] = DFFEAS(JB1L33, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[24] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[24] GE1_entry_0[24] = DFFEAS(JB1L33, F1__clk1, , , GE1L47, , , , ); --HB1L42 is system_0:u0|sdram_0:the_sdram_0|Select~8146 HB1L42 = GE1_rd_address & GE1_entry_1[24] # !GE1_rd_address & (GE1_entry_0[24]); --HB1L43 is system_0:u0|sdram_0:the_sdram_0|Select~8147 HB1L43 = HB1L299 & (HB1L41 & (HB1L42) # !HB1L41 & HB1_active_addr[15]) # !HB1L299 & (HB1L41); --HB1_active_addr[7] is system_0:u0|sdram_0:the_sdram_0|active_addr[7] HB1_active_addr[7] = DFFEAS(HB1L45, F1__clk1, , , HB1L208, , , , ); --HB1L44 is system_0:u0|sdram_0:the_sdram_0|Select~8148 HB1L44 = HB1L299 & (!HB1L358) # !HB1L299 & (HB1L358 & (!HB1_i_addr[11]) # !HB1L358 & HB1_active_addr[7]); --GE1_entry_1[25] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[25] GE1_entry_1[25] = DFFEAS(JB1L34, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[25] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[25] GE1_entry_0[25] = DFFEAS(JB1L34, F1__clk1, , , GE1L47, , , , ); --HB1L45 is system_0:u0|sdram_0:the_sdram_0|Select~8149 HB1L45 = GE1_rd_address & GE1_entry_1[25] # !GE1_rd_address & (GE1_entry_0[25]); --HB1L46 is system_0:u0|sdram_0:the_sdram_0|Select~8150 HB1L46 = HB1L299 & (HB1L44 & (HB1L45) # !HB1L44 & HB1_active_addr[16]) # !HB1L299 & (HB1L44); --HB1L47 is system_0:u0|sdram_0:the_sdram_0|Select~8151 HB1L47 = HB1_m_state.000000010 & HB1_active_addr[17] # !HB1_m_state.000000010 & (!HB1_i_addr[11]); --HB1L48 is system_0:u0|sdram_0:the_sdram_0|Select~8152 HB1L48 = HB1_m_state.000000010 & HB1_active_addr[18] # !HB1_m_state.000000010 & (!HB1_i_addr[11]); --HB1L49 is system_0:u0|sdram_0:the_sdram_0|Select~8153 HB1L49 = HB1_m_state.000000010 & HB1_active_addr[19] # !HB1_m_state.000000010 & (!HB1_i_addr[11]); --HB1L50 is system_0:u0|sdram_0:the_sdram_0|Select~8154 HB1L50 = HB1_m_state.000000010 & HB1_active_addr[20] # !HB1_m_state.000000010 & (!HB1_i_addr[11]); --HB1_active_dqm[0] is system_0:u0|sdram_0:the_sdram_0|active_dqm[0] HB1_active_dqm[0] = DFFEAS(HB1L51, F1__clk1, , , HB1L208, , , , ); --GE1_entry_1[16] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[16] GE1_entry_1[16] = DFFEAS(HB1L264, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[16] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[16] GE1_entry_0[16] = DFFEAS(HB1L264, F1__clk1, , , GE1L47, , , , ); --HB1L51 is system_0:u0|sdram_0:the_sdram_0|Select~8155 HB1L51 = GE1_rd_address & GE1_entry_1[16] # !GE1_rd_address & (GE1_entry_0[16]); --HB1L385 is system_0:u0|sdram_0:the_sdram_0|pending~276 HB1L385 = HB1L380 & HB1L382 & HB1L384; --HB1L52 is system_0:u0|sdram_0:the_sdram_0|Select~8156 HB1L52 = HB1_f_select & (HB1_m_state.000000010 & HB1_active_dqm[0] # !HB1_m_state.000000010 & (HB1L51)) # !HB1_f_select & HB1_active_dqm[0]; --HB1L392 is system_0:u0|sdram_0:the_sdram_0|reduce_or~72 HB1L392 = HB1_m_state.000001000 # HB1_m_state.000010000 # HB1_m_state.000000010; --HB1_active_dqm[1] is system_0:u0|sdram_0:the_sdram_0|active_dqm[1] HB1_active_dqm[1] = DFFEAS(HB1L53, F1__clk1, , , HB1L208, , , , ); --GE1_entry_1[17] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[17] GE1_entry_1[17] = DFFEAS(HB1L265, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[17] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[17] GE1_entry_0[17] = DFFEAS(HB1L265, F1__clk1, , , GE1L47, , , , ); --HB1L53 is system_0:u0|sdram_0:the_sdram_0|Select~8157 HB1L53 = GE1_rd_address & GE1_entry_1[17] # !GE1_rd_address & (GE1_entry_0[17]); --HB1L54 is system_0:u0|sdram_0:the_sdram_0|Select~8158 HB1L54 = HB1_f_select & (HB1_m_state.000000010 & HB1_active_dqm[1] # !HB1_m_state.000000010 & (HB1L53)) # !HB1_f_select & HB1_active_dqm[1]; --HB1_i_cmd[0] is system_0:u0|sdram_0:the_sdram_0|i_cmd[0] HB1_i_cmd[0] = DFFEAS(HB1L84, F1__clk1, N1_data_out, , , , , , ); --HB1L55 is system_0:u0|sdram_0:the_sdram_0|Select~8159 HB1L55 = HB1_m_state.000000001 & (HB1_m_state.001000000) # !HB1_m_state.000000001 & !HB1_init_done & HB1_i_cmd[0]; --HB1L56 is system_0:u0|sdram_0:the_sdram_0|Select~8160 HB1L56 = HB1_m_state.000010000 & HB1L262 & (HB1_m_state.000000001 # HB1L55) # !HB1_m_state.000010000 & (HB1L55); --HB1_i_cmd[1] is system_0:u0|sdram_0:the_sdram_0|i_cmd[1] HB1_i_cmd[1] = DFFEAS(HB1L86, F1__clk1, N1_data_out, , , , , , ); --HB1L57 is system_0:u0|sdram_0:the_sdram_0|Select~8161 HB1L57 = HB1_m_state.000000001 & (HB1_m_state.010000000) # !HB1_m_state.000000001 & !HB1_init_done & HB1_i_cmd[1]; --HB1L58 is system_0:u0|sdram_0:the_sdram_0|Select~8162 HB1L58 = HB1L358 & (HB1L57) # !HB1L358 & HB1L262 & (HB1_m_state.000000001 # HB1L57); --HB1L359 is system_0:u0|sdram_0:the_sdram_0|m_state.000000001~95 HB1L359 = !HB1_m_state.000000010 & !HB1_m_state.001000000 & !HB1_m_state.010000000; --HB1_i_cmd[2] is system_0:u0|sdram_0:the_sdram_0|i_cmd[2] HB1_i_cmd[2] = DFFEAS(HB1L87, F1__clk1, N1_data_out, , , , , , ); --HB1L59 is system_0:u0|sdram_0:the_sdram_0|Select~8163 HB1L59 = HB1_m_state.000000001 & !HB1L359 # !HB1_m_state.000000001 & (!HB1_init_done & HB1_i_cmd[2]); --HB1_i_cmd[3] is system_0:u0|sdram_0:the_sdram_0|i_cmd[3] HB1_i_cmd[3] = DFFEAS(HB1L88, F1__clk1, N1_data_out, , , , , , ); --HB1_refresh_request is system_0:u0|sdram_0:the_sdram_0|refresh_request HB1_refresh_request = DFFEAS(HB1L422, F1__clk1, N1_data_out, , , , , , ); --HB1L60 is system_0:u0|sdram_0:the_sdram_0|Select~8164 HB1L60 = !HB1_m_state.000000001 & (HB1_init_done & (!HB1_refresh_request) # !HB1_init_done & !HB1_i_cmd[3]); --HB1L61 is system_0:u0|sdram_0:the_sdram_0|Select~8165 HB1L61 = HB1_m_state.000000001 & !HB1_m_state.001000000 & !HB1_m_state.010000000 & !HB1_m_state.000000100; --HB1_m_next.010000000 is system_0:u0|sdram_0:the_sdram_0|m_next.010000000 HB1_m_next.010000000 = DFFEAS(HB1L92, F1__clk1, N1_data_out, , , , , , ); --HB1L62 is system_0:u0|sdram_0:the_sdram_0|Select~8166 HB1L62 = HB1_m_state.001000000 & (HB1_m_state.000000100 & !HB1_m_next.010000000 # !HB1_refresh_request) # !HB1_m_state.001000000 & HB1_m_state.000000100 & (!HB1_m_next.010000000); --HB1L63 is system_0:u0|sdram_0:the_sdram_0|Select~8167 HB1L63 = !HB1L60 & (!HB1L61 & !HB1L62 # !HB1_active_cs_n); --HB1L64 is system_0:u0|sdram_0:the_sdram_0|Select~8168 HB1L64 = HB1_f_select & (HB1_m_state.000000010 & HB1_active_addr[8] # !HB1_m_state.000000010 & (HB1L12)) # !HB1_f_select & HB1_active_addr[8]; --HB1L65 is system_0:u0|sdram_0:the_sdram_0|Select~8169 HB1L65 = HB1_f_select & (HB1_m_state.000000010 & HB1_active_addr[21] # !HB1_m_state.000000010 & (HB1L18)) # !HB1_f_select & HB1_active_addr[21]; --AB1_cpu_0_data_master_dbs_address[0] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[0] AB1_cpu_0_data_master_dbs_address[0] = DFFEAS(AB1L8, F1__clk1, N1_data_out, , , , , , ); --BB1_cpu_0_instruction_master_dbs_address[0] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_dbs_address[0] BB1_cpu_0_instruction_master_dbs_address[0] = DFFEAS(BB1L11, F1__clk1, N1_data_out, , , , , , ); --MB1L38 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_requests_cfi_flash_0_s1~266 MB1L38 = !Z1_d_address[23] & !Z1_d_address[22] & (Z1_d_write # Z1_d_read); --MB1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_slavearbiterlockenable MB1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable = DFFEAS(MB1L156, F1__clk1, N1_data_out, , , , , , ); --MB1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 MB1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 = DFFEAS(MB1L75, F1__clk1, N1_data_out, , , , , , ); --MB1L147 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_firsttransfer~99 MB1L147 = Z1_i_read & MB1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 & !Z1_ic_fill_tag[11] & !Z1_ic_fill_tag[10]; --MB1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] MB1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] = DFFEAS(MB1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0], F1__clk1, N1_data_out, , , , , , ); --MB1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] MB1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] = DFFEAS(MB1L37, F1__clk1, N1_data_out, , , , , , ); --MB1L31 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~176 MB1L31 = Z1_d_read & (MB1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] # MB1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0]); --MB1L32 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~177 MB1L32 = MB1L38 & !MB1L31 & (!MB1L147 # !MB1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable); --MB1L29 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_byteenable_cfi_flash_0_s1~307 MB1L29 = AB1_cpu_0_data_master_dbs_address[0] & (AB1_cpu_0_data_master_dbs_address[1] & Z1_d_byteenable[3] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_byteenable[1])); --MB1L30 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_byteenable_cfi_flash_0_s1~308 MB1L30 = MB1L29 # LB1L6 & !AB1_cpu_0_data_master_dbs_address[0]; --MB1L33 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~178 MB1L33 = MB1L32 & (MB1L30 & !AB1_cpu_0_data_master_no_byte_enables_and_last_term # !Z1_d_write); --MB1_tri_state_bridge_0_avalon_slave_arb_addend[1] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[1] MB1_tri_state_bridge_0_avalon_slave_arb_addend[1] = DFFEAS(MB1L132, F1__clk1, N1_data_out, , , , , , ); --MB1L41 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_cfi_flash_0_s1~119 MB1L41 = Z1_i_read & (JE1_fifo_contains_ones_n # BB1_cpu_0_instruction_master_latency_counter[1] & BB1_cpu_0_instruction_master_latency_counter[0]); --MB1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 MB1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 = DFFEAS(MB1L72, F1__clk1, N1_data_out, , , , , , ); --MB1L42 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_cfi_flash_0_s1~120 MB1L42 = MB1L41 # MB1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable & MB1L38 & MB1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1; --MB1L43 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_cfi_flash_0_s1~121 MB1L43 = Z1_i_read & !Z1_ic_fill_tag[11] & !Z1_ic_fill_tag[10] & !MB1L42; --MB1_tri_state_bridge_0_avalon_slave_arb_addend[0] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[0] MB1_tri_state_bridge_0_avalon_slave_arb_addend[0] = DFFEAS(MB1L129, F1__clk1, N1_data_out, , , , , , ); --MB1L149 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_grant_vector[1]~31 MB1L149 = MB1L33 & (MB1_tri_state_bridge_0_avalon_slave_arb_addend[1] # !MB1L43 & !MB1_tri_state_bridge_0_avalon_slave_arb_addend[0]); --MB1L77 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[0]~198 MB1L77 = MB1L149 & AB1_cpu_0_data_master_dbs_address[0] # !MB1L149 & (BB1_cpu_0_instruction_master_dbs_address[0]); --MB1L78 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[1]~199 MB1L78 = MB1L149 & AB1_cpu_0_data_master_dbs_address[1] # !MB1L149 & (BB1_cpu_0_instruction_master_dbs_address[1]); --MB1L79 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[2]~200 MB1L79 = MB1L149 & Z1_d_address[2] # !MB1L149 & (Z1_ic_fill_ap_offset[0]); --MB1L80 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[3]~201 MB1L80 = MB1L149 & Z1_d_address[3] # !MB1L149 & (Z1_ic_fill_ap_offset[1]); --MB1L81 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[4]~202 MB1L81 = MB1L149 & Z1_d_address[4] # !MB1L149 & (Z1_ic_fill_ap_offset[2]); --MB1L82 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[5]~203 MB1L82 = MB1L149 & Z1_d_address[5] # !MB1L149 & (Z1_ic_fill_line[0]); --MB1L83 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[6]~204 MB1L83 = MB1L149 & Z1_d_address[6] # !MB1L149 & (Z1_ic_fill_line[1]); --MB1L84 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[7]~205 MB1L84 = MB1L149 & Z1_d_address[7] # !MB1L149 & (Z1_ic_fill_line[2]); --MB1L85 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[8]~206 MB1L85 = MB1L149 & Z1_d_address[8] # !MB1L149 & (Z1_ic_fill_line[3]); --MB1L86 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[9]~207 MB1L86 = MB1L149 & Z1_d_address[9] # !MB1L149 & (Z1_ic_fill_line[4]); --MB1L87 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[10]~208 MB1L87 = MB1L149 & Z1_d_address[10] # !MB1L149 & (Z1_ic_fill_line[5]); --MB1L88 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[11]~209 MB1L88 = MB1L149 & Z1_d_address[11] # !MB1L149 & (Z1_ic_fill_line[6]); --MB1L89 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[12]~210 MB1L89 = MB1L149 & Z1_d_address[12] # !MB1L149 & (Z1_ic_fill_tag[0]); --MB1L90 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[13]~211 MB1L90 = MB1L149 & Z1_d_address[13] # !MB1L149 & (Z1_ic_fill_tag[1]); --MB1L91 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[14]~212 MB1L91 = MB1L149 & Z1_d_address[14] # !MB1L149 & (Z1_ic_fill_tag[2]); --MB1L92 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[15]~213 MB1L92 = MB1L149 & Z1_d_address[15] # !MB1L149 & (Z1_ic_fill_tag[3]); --MB1L93 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[16]~214 MB1L93 = MB1L149 & Z1_d_address[16] # !MB1L149 & (Z1_ic_fill_tag[4]); --MB1L94 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[17]~215 MB1L94 = MB1L149 & Z1_d_address[17] # !MB1L149 & (Z1_ic_fill_tag[5]); --MB1L95 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[18]~216 MB1L95 = MB1L149 & Z1_d_address[18] # !MB1L149 & (Z1_ic_fill_tag[6]); --MB1L96 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[19]~217 MB1L96 = MB1L149 & Z1_d_address[19] # !MB1L149 & (Z1_ic_fill_tag[7]); --MB1L97 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[20]~218 MB1L97 = MB1L149 & Z1_d_address[20] # !MB1L149 & (Z1_ic_fill_tag[8]); --MB1L98 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[21]~219 MB1L98 = MB1L149 & Z1_d_address[21] # !MB1L149 & (Z1_ic_fill_tag[9]); --MB1_in_a_write_cycle is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|in_a_write_cycle MB1_in_a_write_cycle = Z1_d_write & MB1L149; --MB1_cfi_flash_0_s1_wait_counter[4] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[4] MB1_cfi_flash_0_s1_wait_counter[4] = DFFEAS(MB1L18, F1__clk1, N1_data_out, , , , , , ); --MB1_cfi_flash_0_s1_wait_counter[3] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[3] MB1_cfi_flash_0_s1_wait_counter[3] = DFFEAS(MB1L17, F1__clk1, N1_data_out, , , , , , ); --MB1_cfi_flash_0_s1_wait_counter[2] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[2] MB1_cfi_flash_0_s1_wait_counter[2] = DFFEAS(MB1L16, F1__clk1, N1_data_out, , , , , , ); --MB1L100 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_write_n_to_the_cfi_flash_0~104 MB1L100 = !MB1_cfi_flash_0_s1_wait_counter[3] & !MB1_cfi_flash_0_s1_wait_counter[2]; --MB1_d1_reasons_to_wait is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_reasons_to_wait MB1_d1_reasons_to_wait = DFFEAS(MB1L146, F1__clk1, N1_data_out, , , , , , ); --MB1L144 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_begins_xfer~47 MB1L144 = !MB1_d1_reasons_to_wait & (MB1L33 # MB1L43); --MB1L101 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_write_n_to_the_cfi_flash_0~105 MB1L101 = MB1_in_a_write_cycle & !MB1L144 & (MB1_cfi_flash_0_s1_wait_counter[4] $ !MB1L100); --MB1L40 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_granted_cfi_flash_0_s1~77 MB1L40 = MB1L43 & (MB1_tri_state_bridge_0_avalon_slave_arb_addend[1] & !MB1L33 # !MB1_tri_state_bridge_0_avalon_slave_arb_addend[0]); --MB1L21 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_in_a_read_cycle~49 MB1L21 = Z1_d_read & MB1L149; --MB1L99 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_readn~29 MB1L99 = !MB1L144 & !MB1_cfi_flash_0_s1_wait_counter[4] & (MB1L40 # MB1L21); --MB1L76 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_select_n_to_the_cfi_flash_0~0 MB1L76 = MB1_tri_state_bridge_0_avalon_slave_arb_addend[1] & (MB1L33 # MB1L43) # !MB1_tri_state_bridge_0_avalon_slave_arb_addend[1] & !MB1_tri_state_bridge_0_avalon_slave_arb_addend[0] & (MB1L33 # MB1L43); --AB1L11 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_increment[1]~44 AB1L11 = LB1L10 & (Z1_d_address[23] # LB1L1 & !Z1_d_address[19]); --AB1L1 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|add~120 AB1L1 = AB1_cpu_0_data_master_dbs_address[0] & MB1L38; --JB1_cpu_0_data_master_requests_sdram_0_s1 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_requests_sdram_0_s1 JB1_cpu_0_data_master_requests_sdram_0_s1 = Z1_d_address[23] & (Z1_d_write # Z1_d_read); --AB1L279 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~544 AB1L279 = JB1_cpu_0_data_master_requests_sdram_0_s1 & (!AB1_cpu_0_data_master_waitrequest) # !JB1_cpu_0_data_master_requests_sdram_0_s1 & LB1_cpu_0_data_master_requests_sram_0_avalonS; --AB1L280 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~545 AB1L280 = Z1_d_write & JB1L10 & AB1L279 & !AB1_cpu_0_data_master_no_byte_enables_and_last_term; --AB1L281 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~546 AB1L281 = !Z1_d_write & !Z1_d_read # !AB1_cpu_0_data_master_waitrequest # !Z1_d_address[23]; --AB1L282 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~547 AB1L282 = MB1L38 & !AB1_cpu_0_data_master_no_byte_enables_and_last_term; --JB1L11 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1~316 JB1L11 = Z1_d_write & !AB1_cpu_0_data_master_no_byte_enables_and_last_term & (!AB1_cpu_0_data_master_waitrequest) # !Z1_d_write & (!AB1_cpu_0_data_master_waitrequest # !Z1_d_read); --HE1_fifo_contains_ones_n is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|fifo_contains_ones_n HE1_fifo_contains_ones_n = DFFEAS(HE1L40, F1__clk1, N1_data_out, , JE1L13, , , , ); --JB1L12 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1~317 JB1L12 = JB1_cpu_0_data_master_requests_sdram_0_s1 & JB1L11 & (!HE1_fifo_contains_ones_n # !Z1_d_read); --JB1_sdram_0_s1_slavearbiterlockenable is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_slavearbiterlockenable JB1_sdram_0_s1_slavearbiterlockenable = DFFEAS(JB1L76, F1__clk1, N1_data_out, , , , , , ); --JB1_last_cycle_cpu_0_instruction_master_granted_slave_sdram_0_s1 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|last_cycle_cpu_0_instruction_master_granted_slave_sdram_0_s1 JB1_last_cycle_cpu_0_instruction_master_granted_slave_sdram_0_s1 = DFFEAS(JB1L26, F1__clk1, N1_data_out, , , , , , ); --JB1L15 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_instruction_master_arbiterlock~12 JB1L15 = Z1_ic_fill_tag[11] & Z1_i_read & JB1_sdram_0_s1_slavearbiterlockenable & JB1_last_cycle_cpu_0_instruction_master_granted_slave_sdram_0_s1; --JB1_cpu_0_data_master_qualified_request_sdram_0_s1 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1 JB1_cpu_0_data_master_qualified_request_sdram_0_s1 = JB1L12 & !JB1L15 & (!JB1L10 # !Z1_d_write); --JB1_sdram_0_s1_arb_addend[1] is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_addend[1] JB1_sdram_0_s1_arb_addend[1] = DFFEAS(JB1L55, F1__clk1, N1_data_out, , , , , , ); --JB1_last_cycle_cpu_0_data_master_granted_slave_sdram_0_s1 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|last_cycle_cpu_0_data_master_granted_slave_sdram_0_s1 JB1_last_cycle_cpu_0_data_master_granted_slave_sdram_0_s1 = DFFEAS(JB1L24, F1__clk1, N1_data_out, , , , , , ); --JB1L6 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_arbiterlock~19 JB1L6 = Z1_d_address[23] & JB1_last_cycle_cpu_0_data_master_granted_slave_sdram_0_s1 & (Z1_d_write # Z1_d_read); --BB1L21 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_latency_counter[0]~34 BB1L21 = !BB1_cpu_0_instruction_master_latency_counter[1] & !BB1_cpu_0_instruction_master_latency_counter[0]; --JB1L17 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_instruction_master_qualified_request_sdram_0_s1~105 JB1L17 = JB1_sdram_0_s1_slavearbiterlockenable & (JB1L6 # Z1_i_read & !BB1L21) # !JB1_sdram_0_s1_slavearbiterlockenable & (Z1_i_read & !BB1L21); --JB1L18 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_instruction_master_qualified_request_sdram_0_s1~106 JB1L18 = Z1_ic_fill_tag[11] & Z1_i_read & !JB1L17; --JB1_sdram_0_s1_arb_addend[0] is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_addend[0] JB1_sdram_0_s1_arb_addend[0] = DFFEAS(JB1L52, F1__clk1, N1_data_out, , , , , , ); --JB1L7 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_granted_sdram_0_s1~24 JB1L7 = JB1_cpu_0_data_master_qualified_request_sdram_0_s1 & (JB1_sdram_0_s1_arb_addend[1] # !JB1L18 & !JB1_sdram_0_s1_arb_addend[0]); --GE1L93 is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|full~79 GE1L93 = GE1_entries[1] & !GE1_entries[0]; --AB1L283 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~548 AB1L283 = AB1L282 & (JB1L7 & !GE1L93 # !MB1L30) # !AB1L282 & JB1L7 & (!GE1L93); --MB1_cfi_flash_0_s1_wait_counter[1] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[1] MB1_cfi_flash_0_s1_wait_counter[1] = DFFEAS(MB1L15, F1__clk1, N1_data_out, , , , , , ); --AB1L355 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|r_2~285 AB1L355 = !MB1_cfi_flash_0_s1_wait_counter[4] & !MB1_cfi_flash_0_s1_wait_counter[3] & !MB1_cfi_flash_0_s1_wait_counter[2] & !MB1_cfi_flash_0_s1_wait_counter[1]; --MB1_cfi_flash_0_s1_wait_counter[0] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[0] MB1_cfi_flash_0_s1_wait_counter[0] = DFFEAS(MB1L14, F1__clk1, N1_data_out, , , , , , ); --BB1L252 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|pre_dbs_count_enable~66 BB1L252 = MB1_d1_reasons_to_wait & AB1L355 & !MB1_cfi_flash_0_s1_wait_counter[0]; --AB1L284 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~549 AB1L284 = Z1_d_write & (AB1L283 # MB1L149 & BB1L252); --HB1_za_valid is system_0:u0|sdram_0:the_sdram_0|za_valid HB1_za_valid = DFFEAS(HB1_rd_valid[2], F1__clk1, N1_data_out, , , , , , ); --HE1_stage_0 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|stage_0 HE1_stage_0 = DFFEAS(HE1L28, F1__clk1, , , HE1L20, , , , ); --AB1L285 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~550 AB1L285 = MB1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] # HE1_fifo_contains_ones_n & HB1_za_valid & HE1_stage_0; --LB1_sram_0_avalonS_wait_counter[0] is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_wait_counter[0] LB1_sram_0_avalonS_wait_counter[0] = DFFEAS(LB1L60, F1__clk1, N1_data_out, , , , , , ); --BB1L253 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|pre_dbs_count_enable~67 BB1L253 = LB1_d1_reasons_to_wait & !LB1_sram_0_avalonS_wait_counter[2] & !LB1_sram_0_avalonS_wait_counter[1] & !LB1_sram_0_avalonS_wait_counter[0]; --AB1L286 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~551 AB1L286 = AB1L285 # LB1L10 & LB1L70 & BB1L253; --AB1L287 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~552 AB1L287 = AB1L280 # AB1L281 & (AB1L284 # AB1L286); --AB1L10 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1]~725 AB1L10 = AB1_cpu_0_data_master_dbs_address[1] $ (AB1L287 & (AB1L11 $ AB1L1)); --LB1L12 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_instruction_master_granted_sram_0_avalonS~77 LB1L12 = LB1L14 & (LB1_sram_0_avalonS_arb_addend[1] & !LB1L8 # !LB1_sram_0_avalonS_arb_addend[0]); --JB1L16 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_instruction_master_granted_sdram_0_s1~26 JB1L16 = JB1L18 & (JB1_sdram_0_s1_arb_addend[1] & !JB1_cpu_0_data_master_qualified_request_sdram_0_s1 # !JB1_sdram_0_s1_arb_addend[0]); --BB1L254 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|pre_dbs_count_enable~68 BB1L254 = LB1L12 & (BB1L253 # JB1L16 & !GE1L93) # !LB1L12 & (JB1L16 & !GE1L93); --BB1_pre_dbs_count_enable is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|pre_dbs_count_enable BB1_pre_dbs_count_enable = BB1L254 # MB1L40 & BB1L252; --MB1L48 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_requests_cfi_flash_0_s1~36 MB1L48 = Z1_i_read & !Z1_ic_fill_tag[11] & !Z1_ic_fill_tag[10]; --BB1L14 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_dbs_increment[1]~43 BB1L14 = Z1_ic_fill_tag[10] & !Z1_ic_fill_tag[9] & !Z1_ic_fill_tag[8]; --BB1L15 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_dbs_increment[1]~44 BB1L15 = Z1_ic_fill_tag[11] # BB1L14 & !Z1_ic_fill_tag[7]; --BB1L1 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|add~277 BB1L1 = Z1_i_read & (BB1L15 $ (MB1L48 & BB1_cpu_0_instruction_master_dbs_address[0])) # !Z1_i_read & MB1L48 & BB1_cpu_0_instruction_master_dbs_address[0]; --BB1L13 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_dbs_address[1]~564 BB1L13 = BB1_cpu_0_instruction_master_dbs_address[1] $ (BB1_pre_dbs_count_enable & BB1L1); --Z1_A_mem_baddr[22] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[22] Z1_A_mem_baddr[22] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[22], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_tag[11] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_tag[11] Z1_A_dc_victim_tag[11] = AMPP_FUNCTION(F1__clk1, Z1L2266, N1_data_out, Z1_A_stall); --Z1_A_ctrl_ld_st_bypass is system_0:u0|cpu_0:the_cpu_0|A_ctrl_ld_st_bypass Z1_A_ctrl_ld_st_bypass = AMPP_FUNCTION(F1__clk1, Z1_M_ctrl_ld_st_bypass, N1_data_out, Z1_A_stall); --Z1_A_dc_av_rd_req is system_0:u0|cpu_0:the_cpu_0|A_dc_av_rd_req Z1_A_dc_av_rd_req = AMPP_FUNCTION(F1__clk1, Z1L2201, N1_data_out, Z1_A_stall); --Z1_av_rd_done is system_0:u0|cpu_0:the_cpu_0|av_rd_done Z1_av_rd_done = AMPP_FUNCTION(F1__clk1, Z1_av_process_readdata, N1_data_out); --Z1L522 is system_0:u0|cpu_0:the_cpu_0|A_rd_stall~1 Z1L522 = AMPP_FUNCTION(Z1_A_dc_av_rd_req, Z1_av_rd_done); --Z1_A_dc_av_wr_req is system_0:u0|cpu_0:the_cpu_0|A_dc_av_wr_req Z1_A_dc_av_wr_req = AMPP_FUNCTION(F1__clk1, Z1L2204, N1_data_out, Z1_A_stall); --Z1_av_wr_done is system_0:u0|cpu_0:the_cpu_0|av_wr_done Z1_av_wr_done = AMPP_FUNCTION(F1__clk1, Z1L3026, N1_data_out, Z1_A_stall); --Z1L953 is system_0:u0|cpu_0:the_cpu_0|A_wr_stall~28 Z1L953 = AMPP_FUNCTION(Z1_A_dc_av_wr_req, AB1_cpu_0_data_master_waitrequest, Z1_av_wr_done); --Z1_av_process_readdata is system_0:u0|cpu_0:the_cpu_0|av_process_readdata Z1_av_process_readdata = AMPP_FUNCTION(F1__clk1, Z1_av_rd_data_transfer, N1_data_out); --Z1_d_read_nxt is system_0:u0|cpu_0:the_cpu_0|d_read_nxt Z1_d_read_nxt = AMPP_FUNCTION(Z1L522, AB1_cpu_0_data_master_waitrequest, Z1L953, Z1_av_process_readdata); --Z1L3214 is system_0:u0|cpu_0:the_cpu_0|dc_tag_field_nxt[11]~1200 Z1L3214 = AMPP_FUNCTION(Z1_A_mem_baddr[22], Z1_A_dc_victim_tag[11], Z1_A_ctrl_ld_st_bypass, Z1_d_read_nxt); --Z1_A_en_d1 is system_0:u0|cpu_0:the_cpu_0|A_en_d1 Z1_A_en_d1 = AMPP_FUNCTION(F1__clk1, Z1L129, N1_data_out); --Z1L3021 is system_0:u0|cpu_0:the_cpu_0|always127~0 Z1L3021 = AMPP_FUNCTION(Z1_A_en_d1, Z1_d_read_nxt); --Z1_A_mem_baddr[23] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[23] Z1_A_mem_baddr[23] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[23], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_tag[12] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_tag[12] Z1_A_dc_victim_tag[12] = AMPP_FUNCTION(F1__clk1, Z1L2267, N1_data_out, Z1_A_stall); --Z1L3215 is system_0:u0|cpu_0:the_cpu_0|dc_tag_field_nxt[12]~1201 Z1L3215 = AMPP_FUNCTION(Z1_A_mem_baddr[23], Z1_A_dc_victim_tag[12], Z1_A_ctrl_ld_st_bypass, Z1_d_read_nxt); --Z1_A_mem_baddr[21] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[21] Z1_A_mem_baddr[21] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[21], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_tag[10] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_tag[10] Z1_A_dc_victim_tag[10] = AMPP_FUNCTION(F1__clk1, Z1L2265, N1_data_out, Z1_A_stall); --Z1L3213 is system_0:u0|cpu_0:the_cpu_0|dc_tag_field_nxt[10]~1202 Z1L3213 = AMPP_FUNCTION(Z1_A_mem_baddr[21], Z1_A_dc_victim_tag[10], Z1_A_ctrl_ld_st_bypass, Z1_d_read_nxt); --Z1_A_mem_baddr[20] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[20] Z1_A_mem_baddr[20] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[20], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_tag[9] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_tag[9] Z1_A_dc_victim_tag[9] = AMPP_FUNCTION(F1__clk1, Z1L2264, N1_data_out, Z1_A_stall); --Z1L3212 is system_0:u0|cpu_0:the_cpu_0|dc_tag_field_nxt[9]~1203 Z1L3212 = AMPP_FUNCTION(Z1_A_mem_baddr[20], Z1_A_dc_victim_tag[9], Z1_A_ctrl_ld_st_bypass, Z1_d_read_nxt); --Z1_A_mem_baddr[19] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[19] Z1_A_mem_baddr[19] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[19], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_tag[8] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_tag[8] Z1_A_dc_victim_tag[8] = AMPP_FUNCTION(F1__clk1, Z1L2263, N1_data_out, Z1_A_stall); --Z1L3211 is system_0:u0|cpu_0:the_cpu_0|dc_tag_field_nxt[8]~1204 Z1L3211 = AMPP_FUNCTION(Z1_A_mem_baddr[19], Z1_A_dc_victim_tag[8], Z1_A_ctrl_ld_st_bypass, Z1_d_read_nxt); --LB1_sram_0_avalonS_arb_share_counter[2] is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_arb_share_counter[2] LB1_sram_0_avalonS_arb_share_counter[2] = DFFEAS(LB1L55, F1__clk1, N1_data_out, , LB1L47, , , , ); --LB1_sram_0_avalonS_arb_share_counter[0] is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_arb_share_counter[0] LB1_sram_0_avalonS_arb_share_counter[0] = DFFEAS(LB1L53, F1__clk1, N1_data_out, , LB1L47, , , , ); --LB1_sram_0_avalonS_arb_share_counter[1] is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_arb_share_counter[1] LB1_sram_0_avalonS_arb_share_counter[1] = DFFEAS(LB1L54, F1__clk1, N1_data_out, , LB1L47, , , , ); --LB1L69 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_firsttransfer~99 LB1L69 = LB1_sram_0_avalonS_slavearbiterlockenable & (LB1L68 # LB1_cpu_0_data_master_requests_sram_0_avalonS & LB1_last_cycle_cpu_0_data_master_granted_slave_sram_0_avalonS); --LB1L52 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_arb_share_counter_next_value[0]~137 LB1L52 = LB1_sram_0_avalonS_arb_share_counter[2] # LB1_sram_0_avalonS_arb_share_counter[0] # LB1_sram_0_avalonS_arb_share_counter[1] # !LB1L69; --LB1L2 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|add~663 LB1L2 = LB1L69 & LB1_sram_0_avalonS_arb_share_counter[1] # !LB1L69 & (LB1L59); --LB1L3 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|add~664 LB1L3 = LB1L69 & LB1_sram_0_avalonS_arb_share_counter[0] # !LB1L69 & (!LB1L59); --LB1L4 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|add~665 LB1L4 = !LB1L68 & !LB1L5 # !LB1_sram_0_avalonS_arb_share_counter[2] # !LB1_sram_0_avalonS_slavearbiterlockenable; --LB1L79 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_slavearbiterlockenable~70 LB1L79 = LB1L52 & (LB1L2 # !LB1L4 # !LB1L3); --LB1L66 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_end_xfer~0 LB1L66 = LB1L12 # LB1L70 & (Z1_d_write # Z1_d_read); --AB1L356 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|r_2~286 AB1L356 = !LB1_sram_0_avalonS_wait_counter[2] & !LB1_sram_0_avalonS_wait_counter[1]; --LB1L67 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_end_xfer~21 LB1L67 = LB1L66 & (LB1L58 # LB1_sram_0_avalonS_wait_counter[0] # !AB1L356); --LB1L80 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_slavearbiterlockenable~71 LB1L80 = LB1L67 & LB1_sram_0_avalonS_slavearbiterlockenable # !LB1L67 & (LB1L79); --LB1_sram_0_avalonS_saved_chosen_master_vector[0] is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_saved_chosen_master_vector[0] LB1_sram_0_avalonS_saved_chosen_master_vector[0] = DFFEAS(LB1L12, F1__clk1, N1_data_out, , LB1L57, , , , ); --LB1L56 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_arb_winner[0]~39 LB1L56 = LB1L69 & LB1_sram_0_avalonS_saved_chosen_master_vector[0] # !LB1L69 & (LB1L12 # LB1_sram_0_avalonS_saved_chosen_master_vector[0] & !LB1L70); --LB1L20 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|last_cycle_cpu_0_instruction_master_granted_slave_sram_0_avalonS~34 LB1L20 = LB1_d1_reasons_to_wait # LB1L69 # !LB1L8 & !LB1L14; --LB1L21 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|last_cycle_cpu_0_instruction_master_granted_slave_sram_0_avalonS~35 LB1L21 = LB1L74 & (LB1L56 # LB1_last_cycle_cpu_0_instruction_master_granted_slave_sram_0_avalonS & LB1L20); --Z1_D_pc[20] is system_0:u0|cpu_0:the_cpu_0|D_pc[20] Z1_D_pc[20] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[20], N1_data_out, Z1_F_stall); --Z1_D_kill is system_0:u0|cpu_0:the_cpu_0|D_kill Z1_D_kill = AMPP_FUNCTION(F1__clk1, Z1L2038, N1_data_out, Z1_F_stall); --Z1_D_inst_ram_hit is system_0:u0|cpu_0:the_cpu_0|D_inst_ram_hit Z1_D_inst_ram_hit = AMPP_FUNCTION(F1__clk1, Z1_F_ic_hit, N1_data_out, Z1_F_stall); --Z1_ic_fill_active is system_0:u0|cpu_0:the_cpu_0|ic_fill_active Z1_ic_fill_active = AMPP_FUNCTION(F1__clk1, Z1L3282, N1_data_out); --Z1_M_pipe_flush is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush Z1_M_pipe_flush = AMPP_FUNCTION(F1__clk1, Z1L2335, N1_data_out, Z1_A_stall); --Z1L1099 is system_0:u0|cpu_0:the_cpu_0|D_ic_fill_starting~45 Z1L1099 = AMPP_FUNCTION(Z1_D_kill, Z1_D_inst_ram_hit, Z1_ic_fill_active, Z1_M_pipe_flush); --Z1_D_pc[21] is system_0:u0|cpu_0:the_cpu_0|D_pc[21] Z1_D_pc[21] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[21], N1_data_out, Z1_F_stall); --Z1_D_pc[19] is system_0:u0|cpu_0:the_cpu_0|D_pc[19] Z1_D_pc[19] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[19], N1_data_out, Z1_F_stall); --Z1_D_pc[18] is system_0:u0|cpu_0:the_cpu_0|D_pc[18] Z1_D_pc[18] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[18], N1_data_out, Z1_F_stall); --Z1_ic_fill_ap_cnt[3] is system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_cnt[3] Z1_ic_fill_ap_cnt[3] = AMPP_FUNCTION(F1__clk1, Z1L3291, N1_data_out, Z1L3296); --BB1L257 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|r_1~178 BB1L257 = JB1L18 & JB1_sdram_0_s1_arb_addend[0] & (JB1_cpu_0_data_master_qualified_request_sdram_0_s1 # !JB1_sdram_0_s1_arb_addend[1]) # !JB1L18 & !JB1_sdram_0_s1_arb_addend[0] & (JB1_sdram_0_s1_arb_addend[1] # !JB1_cpu_0_data_master_qualified_request_sdram_0_s1); --BB1L178 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_run~170 BB1L178 = LB1_cpu_0_instruction_master_granted_sram_0_avalonS & (!BB1L257 # !JB1L18) # !LB1_cpu_0_instruction_master_granted_sram_0_avalonS & !LB1L14 & (!BB1L257 # !JB1L18); --EB1_epcs_controller_epcs_control_port_arb_addend[1] is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_addend[1] EB1_epcs_controller_epcs_control_port_arb_addend[1] = DFFEAS(EB1L21, F1__clk1, N1_data_out, , , , , , ); --EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_0_data_master_requests_epcs_controller_epcs_control_port EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port = LB1L10 & Z1_d_address[11] & GB1L3 & !Z1_d_address[12]; --EB1L28 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_in_a_read_cycle~14 EB1L28 = Z1_i_read & !JE1_fifo_contains_ones_n & !BB1_cpu_0_instruction_master_latency_counter[1] & !BB1_cpu_0_instruction_master_latency_counter[0]; --EB1L1 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|Equal~185 EB1L1 = Z1_ic_fill_tag[7] & !Z1_ic_fill_tag[0] & !Z1_ic_fill_tag[1] & !Z1_ic_fill_tag[2]; --EB1L2 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|Equal~186 EB1L2 = !Z1_ic_fill_tag[3] & !Z1_ic_fill_tag[4] & !Z1_ic_fill_tag[5] & !Z1_ic_fill_tag[6]; --EB1L3 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|Equal~187 EB1L3 = LB1L73 & Z1_ic_fill_line[6] & EB1L1 & EB1L2; --EB1L29 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_in_a_read_cycle~15 EB1L29 = EB1L28 & EB1L3; --EB1_epcs_controller_epcs_control_port_arb_addend[0] is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_addend[0] EB1_epcs_controller_epcs_control_port_arb_addend[0] = DFFEAS(EB1L18, F1__clk1, N1_data_out, , , , , , ); --EB1_cpu_0_instruction_master_granted_epcs_controller_epcs_control_port is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_0_instruction_master_granted_epcs_controller_epcs_control_port EB1_cpu_0_instruction_master_granted_epcs_controller_epcs_control_port = EB1L29 & (EB1_epcs_controller_epcs_control_port_arb_addend[1] & !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port # !EB1_epcs_controller_epcs_control_port_arb_addend[0]) # !EB1L29 & (EB1_epcs_controller_epcs_control_port_arb_addend[0] # !EB1_epcs_controller_epcs_control_port_arb_addend[1] & EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --MB1_cpu_0_instruction_master_granted_cfi_flash_0_s1 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_granted_cfi_flash_0_s1 MB1_cpu_0_instruction_master_granted_cfi_flash_0_s1 = MB1L43 & (MB1_tri_state_bridge_0_avalon_slave_arb_addend[1] & !MB1L33 # !MB1_tri_state_bridge_0_avalon_slave_arb_addend[0]) # !MB1L43 & (MB1_tri_state_bridge_0_avalon_slave_arb_addend[0] # !MB1_tri_state_bridge_0_avalon_slave_arb_addend[1] & MB1L33); --BB1L179 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_run~171 BB1L179 = EB1_cpu_0_instruction_master_granted_epcs_controller_epcs_control_port & (MB1_cpu_0_instruction_master_granted_cfi_flash_0_s1 # !MB1L43) # !EB1_cpu_0_instruction_master_granted_epcs_controller_epcs_control_port & !EB1L29 & (MB1_cpu_0_instruction_master_granted_cfi_flash_0_s1 # !MB1L43); --CB1_d1_reasons_to_wait is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|d1_reasons_to_wait CB1_d1_reasons_to_wait = DFFEAS(CB1L29, F1__clk1, N1_data_out, , , , , , ); --CB1L1 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|Equal~127 CB1L1 = LB1L73 & EB1L1 & EB1L2 & !Z1_ic_fill_line[6]; --BB1L180 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_run~172 BB1L180 = !BB1L256 & (CB1_d1_reasons_to_wait # !Z1_i_read) # !CB1L1; --BB1L258 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|r_2~5 BB1L258 = BB1_cpu_0_instruction_master_dbs_address[1] & BB1L253; --LB1L13 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_instruction_master_qualified_request_sram_0_avalonS~2 LB1L13 = BB1L256 # LB1_sram_0_avalonS_slavearbiterlockenable & LB1_cpu_0_data_master_requests_sram_0_avalonS & LB1_last_cycle_cpu_0_data_master_granted_slave_sram_0_avalonS; --BB1L181 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_run~173 BB1L181 = BB1L180 & (BB1L258 & !LB1L13 # !LB1L74); --EB1_d1_reasons_to_wait is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|d1_reasons_to_wait EB1_d1_reasons_to_wait = DFFEAS(EB1L25, F1__clk1, N1_data_out, , , , , , ); --BB1L182 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_run~174 BB1L182 = !BB1L256 & (EB1_d1_reasons_to_wait # !Z1_i_read) # !EB1L3; --BB1L259 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|r_2~16 BB1L259 = BB1_cpu_0_instruction_master_dbs_address[1] & BB1_cpu_0_instruction_master_dbs_address[0] & BB1L252 # !MB1L43; --JB1L19 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_instruction_master_qualified_request_sdram_0_s1~107 JB1L19 = Z1_ic_fill_tag[11] & Z1_i_read; --BB1L183 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_run~175 BB1L183 = MB1L48 & !MB1L42 & (!JB1L17 # !JB1L19) # !MB1L48 & (!JB1L17 # !JB1L19); --BB1L255 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|r_1~22 BB1L255 = JB1L17 # BB1_cpu_0_instruction_master_dbs_address[1] & !GE1L93 # !JB1L19; --BB1L184 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_run~176 BB1L184 = BB1L182 & BB1L259 & BB1L183 & BB1L255; --CB1_cpu_0_jtag_debug_module_arb_addend[1] is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[1] CB1_cpu_0_jtag_debug_module_arb_addend[1] = DFFEAS(CB1L21, F1__clk1, N1_data_out, , , , , , ); --CB1_cpu_0_data_master_requests_cpu_0_jtag_debug_module is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_data_master_requests_cpu_0_jtag_debug_module CB1_cpu_0_data_master_requests_cpu_0_jtag_debug_module = LB1L10 & GB1L3 & !Z1_d_address[11] & !Z1_d_address[12]; --CB1L28 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_end_xfer~41 CB1L28 = EB1L28 & CB1L1; --CB1_cpu_0_jtag_debug_module_arb_addend[0] is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[0] CB1_cpu_0_jtag_debug_module_arb_addend[0] = DFFEAS(CB1L18, F1__clk1, N1_data_out, , , , , , ); --CB1_cpu_0_instruction_master_granted_cpu_0_jtag_debug_module is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_instruction_master_granted_cpu_0_jtag_debug_module CB1_cpu_0_instruction_master_granted_cpu_0_jtag_debug_module = CB1L28 & (CB1_cpu_0_jtag_debug_module_arb_addend[1] & !CB1_cpu_0_data_master_requests_cpu_0_jtag_debug_module # !CB1_cpu_0_jtag_debug_module_arb_addend[0]) # !CB1L28 & (CB1_cpu_0_jtag_debug_module_arb_addend[0] # !CB1_cpu_0_jtag_debug_module_arb_addend[1] & CB1_cpu_0_data_master_requests_cpu_0_jtag_debug_module); --BB1L185 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_run~177 BB1L185 = BB1L181 & BB1L184 & (CB1_cpu_0_instruction_master_granted_cpu_0_jtag_debug_module # !CB1L28); --BB1_cpu_0_instruction_master_run is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_run BB1_cpu_0_instruction_master_run = BB1L178 & BB1L179 & BB1L185; --Z1L3244 is system_0:u0|cpu_0:the_cpu_0|i_read_nxt~15 Z1L3244 = AMPP_FUNCTION(Z1_i_read, Z1_ic_fill_ap_cnt[3], BB1_cpu_0_instruction_master_run, Z1L1099); --Z1_D_pc[17] is system_0:u0|cpu_0:the_cpu_0|D_pc[17] Z1_D_pc[17] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[17], N1_data_out, Z1_F_stall); --AB1L288 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|last_dbs_term_and_run~353 AB1L288 = JB1L10 & (Z1_d_address[23] # LB1L1 & !Z1_d_address[19]); --AB1L289 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|last_dbs_term_and_run~354 AB1L289 = LB1_cpu_0_data_master_requests_sram_0_avalonS # JB1_cpu_0_data_master_requests_sdram_0_s1 # MB1L30; --AB1L290 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|last_dbs_term_and_run~355 AB1L290 = AB1_cpu_0_data_master_dbs_address[1] & (AB1_cpu_0_data_master_dbs_address[0] & (!AB1L289) # !AB1_cpu_0_data_master_dbs_address[0] & AB1L288); --Z1_A_mem_byte_en[1] is system_0:u0|cpu_0:the_cpu_0|A_mem_byte_en[1] Z1_A_mem_byte_en[1] = AMPP_FUNCTION(F1__clk1, Z1_M_mem_byte_en[1], N1_data_out, Z1_A_stall); --Z1L3057 is system_0:u0|cpu_0:the_cpu_0|d_byteenable_nxt[1]~12 Z1L3057 = AMPP_FUNCTION(Z1_A_mem_byte_en[1], Z1_A_ctrl_ld_st_bypass); --Z1_A_mem_byte_en[3] is system_0:u0|cpu_0:the_cpu_0|A_mem_byte_en[3] Z1_A_mem_byte_en[3] = AMPP_FUNCTION(F1__clk1, Z1_M_mem_byte_en[3], N1_data_out, Z1_A_stall); --Z1L3059 is system_0:u0|cpu_0:the_cpu_0|d_byteenable_nxt[3]~13 Z1L3059 = AMPP_FUNCTION(Z1_A_mem_byte_en[3], Z1_A_ctrl_ld_st_bypass); --Z1_A_mem_byte_en[2] is system_0:u0|cpu_0:the_cpu_0|A_mem_byte_en[2] Z1_A_mem_byte_en[2] = AMPP_FUNCTION(F1__clk1, Z1_M_mem_byte_en[2], N1_data_out, Z1_A_stall); --Z1L3058 is system_0:u0|cpu_0:the_cpu_0|d_byteenable_nxt[2]~14 Z1L3058 = AMPP_FUNCTION(Z1_A_mem_byte_en[2], Z1_A_ctrl_ld_st_bypass); --Z1_A_mem_byte_en[0] is system_0:u0|cpu_0:the_cpu_0|A_mem_byte_en[0] Z1_A_mem_byte_en[0] = AMPP_FUNCTION(F1__clk1, Z1_M_mem_byte_en[0], N1_data_out, Z1_A_stall); --Z1L3056 is system_0:u0|cpu_0:the_cpu_0|d_byteenable_nxt[0]~15 Z1L3056 = AMPP_FUNCTION(Z1_A_mem_byte_en[0], Z1_A_ctrl_ld_st_bypass); --BB1L138 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdatavalid~97 BB1L138 = !LB1L58 & !LB1_sram_0_avalonS_wait_counter[2] & !LB1_sram_0_avalonS_wait_counter[1] & !LB1_sram_0_avalonS_wait_counter[0]; --LB1L45 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_arb_addend[1]~474 LB1L45 = LB1L66 & (BB1L138 & LB1L56 # !BB1L138 & (LB1L70)) # !LB1L66 & LB1L56; --LB1L46 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_arb_addend[1]~475 LB1L46 = LB1L59 & LB1L45 # !LB1L59 & (LB1_sram_0_avalonS_arb_addend[1]); --LB1_sram_0_avalonS_saved_chosen_master_vector[1] is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_saved_chosen_master_vector[1] LB1_sram_0_avalonS_saved_chosen_master_vector[1] = DFFEAS(LB1L70, F1__clk1, N1_data_out, , LB1L57, , , , ); --LB1L17 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|last_cycle_cpu_0_data_master_granted_slave_sram_0_avalonS~129 LB1L17 = LB1L69 & LB1_sram_0_avalonS_saved_chosen_master_vector[1] # !LB1L69 & (LB1L70 # LB1_sram_0_avalonS_saved_chosen_master_vector[1] & !LB1L12); --LB1L18 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|last_cycle_cpu_0_data_master_granted_slave_sram_0_avalonS~130 LB1L18 = LB1_cpu_0_data_master_requests_sram_0_avalonS & (LB1L17 # LB1_last_cycle_cpu_0_data_master_granted_slave_sram_0_avalonS & LB1L20); --JE1_how_many_ones[2] is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|how_many_ones[2] JE1_how_many_ones[2] = DFFEAS(JE1L7, F1__clk1, N1_data_out, , JE1L13, , , , ); --JE1_how_many_ones[1] is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|how_many_ones[1] JE1_how_many_ones[1] = DFFEAS(JE1L11, F1__clk1, N1_data_out, , JE1L13, , , , ); --JE1_how_many_ones[0] is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|how_many_ones[0] JE1_how_many_ones[0] = DFFEAS(JE1L12, F1__clk1, N1_data_out, , JE1L13, , , , ); --JE1L1 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|add~182 JE1L1 = JE1_how_many_ones[0] $ VCC; --JE1L2 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|add~183 JE1L2 = CARRY(JE1_how_many_ones[0]); --JE1L3 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|add~184 JE1L3 = JE1_how_many_ones[1] & (JE1L42 & !JE1L2 # !JE1L42 & JE1L2 & VCC) # !JE1_how_many_ones[1] & (JE1L42 & (JE1L2 # GND) # !JE1L42 & !JE1L2); --JE1L4 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|add~185 JE1L4 = CARRY(JE1_how_many_ones[1] & JE1L42 & !JE1L2 # !JE1_how_many_ones[1] & (JE1L42 # !JE1L2)); --JE1L5 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|add~186 JE1L5 = (JE1_how_many_ones[2] $ JE1L42 $ JE1L4) # GND; --JE1L6 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|add~187 JE1L6 = CARRY(JE1_how_many_ones[2] & (!JE1L4 # !JE1L42) # !JE1_how_many_ones[2] & !JE1L42 & !JE1L4); --JE1_stage_0 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|stage_0 JE1_stage_0 = DFFEAS(JE1L27, F1__clk1, , , HE1L20, , , , ); --JE1L41 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|updated_one_count~131 JE1L41 = HB1_za_valid & JE1_stage_0; --JE1L7 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|add~188 JE1L7 = JE1_how_many_ones[2] & (JE1L5 # JE1L41 $ !JE1L42) # !JE1_how_many_ones[2] & JE1L5 & (JE1L41 $ JE1L42); --JE1_how_many_ones[3] is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|how_many_ones[3] JE1_how_many_ones[3] = DFFEAS(JE1L10, F1__clk1, N1_data_out, , JE1L13, , , , ); --JE1L8 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|add~189 JE1L8 = JE1_how_many_ones[3] $ JE1L42 $ !JE1L6; --JE1L10 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|add~191 JE1L10 = JE1_how_many_ones[3] & (JE1L8 # JE1L41 $ !JE1L42) # !JE1_how_many_ones[3] & JE1L8 & (JE1L41 $ JE1L42); --JE1L11 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|add~192 JE1L11 = JE1_how_many_ones[1] & (JE1L3 # JE1L41 $ !JE1L42) # !JE1_how_many_ones[1] & JE1L3 & (JE1L41 $ JE1L42); --JE1L12 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|add~193 JE1L12 = JE1_how_many_ones[0] & (JE1L1 # JE1L41 $ !JE1L42) # !JE1_how_many_ones[0] & JE1L1 & (JE1L41 $ JE1L42); --JE1L33 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|reduce_or~24 JE1L33 = JE1L7 # JE1L10 # JE1L11 # JE1L12; --JB1L5 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|comb~34 JB1L5 = !GE1L93 & (JB1L16 # Z1_d_read & JB1L7); --JE1L13 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|always15~0 JE1L13 = HB1_za_valid # JB1L5; --BB1L250 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|p1_cpu_0_instruction_master_latency_counter~0 BB1L250 = Z1_i_read & BB1L178 & BB1L179 & BB1L185; --BB1L249 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|p1_cpu_0_instruction_master_latency_counter[1]~38 BB1L249 = BB1L250 & MB1L48 # !BB1L250 & (BB1_cpu_0_instruction_master_latency_counter[1] & BB1_cpu_0_instruction_master_latency_counter[0]); --BB1L248 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|p1_cpu_0_instruction_master_latency_counter[0]~39 BB1L248 = BB1_cpu_0_instruction_master_latency_counter[1] & !BB1_cpu_0_instruction_master_latency_counter[0] & !BB1L250; --LB1L42 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_arb_addend[0]~476 LB1L42 = LB1L66 & (BB1L138 & (!LB1L56) # !BB1L138 & LB1L12) # !LB1L66 & (!LB1L56); --LB1L43 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_arb_addend[0]~477 LB1L43 = LB1L59 & !LB1L42 # !LB1L59 & (LB1_sram_0_avalonS_arb_addend[0]); --Z1_A_mem_baddr[2] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[2] Z1_A_mem_baddr[2] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[2], N1_data_out, Z1_A_stall); --Z1_D_pc[0] is system_0:u0|cpu_0:the_cpu_0|D_pc[0] Z1_D_pc[0] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[0], N1_data_out, Z1_F_stall); --Z1L3297 is system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_offset_nxt[0]~144 Z1L3297 = AMPP_FUNCTION(Z1_D_pc[0], BB1L250, Z1_ic_fill_ap_offset[0]); --Z1L3296 is system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_offset[2]~21 Z1L3296 = AMPP_FUNCTION(Z1L1099, BB1L250); --Z1_A_mem_baddr[3] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[3] Z1_A_mem_baddr[3] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[3], N1_data_out, Z1_A_stall); --Z1_D_pc[1] is system_0:u0|cpu_0:the_cpu_0|D_pc[1] Z1_D_pc[1] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[1], N1_data_out, Z1_F_stall); --Z1L3298 is system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_offset_nxt[1]~145 Z1L3298 = AMPP_FUNCTION(Z1_D_pc[1], BB1L250, Z1_ic_fill_ap_offset[0], Z1_ic_fill_ap_offset[1]); --Z1_A_mem_baddr[4] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[4] Z1_A_mem_baddr[4] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[4], N1_data_out, Z1_A_stall); --Z1_D_pc[2] is system_0:u0|cpu_0:the_cpu_0|D_pc[2] Z1_D_pc[2] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[2], N1_data_out, Z1_F_stall); --Z1L2804 is system_0:u0|cpu_0:the_cpu_0|add~2941 Z1L2804 = AMPP_FUNCTION(Z1_ic_fill_ap_offset[0], Z1_ic_fill_ap_offset[1]); --Z1L3299 is system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_offset_nxt[2]~146 Z1L3299 = AMPP_FUNCTION(Z1_D_pc[2], BB1L250, Z1_ic_fill_ap_offset[2], Z1L2804); --Z1_A_mem_baddr[5] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[5] Z1_A_mem_baddr[5] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[5], N1_data_out, Z1_A_stall); --Z1_D_pc[3] is system_0:u0|cpu_0:the_cpu_0|D_pc[3] Z1_D_pc[3] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[3], N1_data_out, Z1_F_stall); --Z1_A_mem_baddr[6] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[6] Z1_A_mem_baddr[6] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[6], N1_data_out, Z1_A_stall); --Z1_D_pc[4] is system_0:u0|cpu_0:the_cpu_0|D_pc[4] Z1_D_pc[4] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[4], N1_data_out, Z1_F_stall); --Z1_A_mem_baddr[7] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[7] Z1_A_mem_baddr[7] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[7], N1_data_out, Z1_A_stall); --Z1_D_pc[5] is system_0:u0|cpu_0:the_cpu_0|D_pc[5] Z1_D_pc[5] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[5], N1_data_out, Z1_F_stall); --Z1_A_mem_baddr[8] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[8] Z1_A_mem_baddr[8] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[8], N1_data_out, Z1_A_stall); --Z1_D_pc[6] is system_0:u0|cpu_0:the_cpu_0|D_pc[6] Z1_D_pc[6] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[6], N1_data_out, Z1_F_stall); --Z1_A_mem_baddr[9] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[9] Z1_A_mem_baddr[9] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[9], N1_data_out, Z1_A_stall); --Z1_D_pc[7] is system_0:u0|cpu_0:the_cpu_0|D_pc[7] Z1_D_pc[7] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[7], N1_data_out, Z1_F_stall); --Z1_A_mem_baddr[10] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[10] Z1_A_mem_baddr[10] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[10], N1_data_out, Z1_A_stall); --Z1_D_pc[8] is system_0:u0|cpu_0:the_cpu_0|D_pc[8] Z1_D_pc[8] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[8], N1_data_out, Z1_F_stall); --Z1_A_mem_baddr[11] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[11] Z1_A_mem_baddr[11] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[11], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_tag[0] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_tag[0] Z1_A_dc_victim_tag[0] = AMPP_FUNCTION(F1__clk1, Z1L2255, N1_data_out, Z1_A_stall); --Z1L3203 is system_0:u0|cpu_0:the_cpu_0|dc_tag_field_nxt[0]~1205 Z1L3203 = AMPP_FUNCTION(Z1_A_mem_baddr[11], Z1_A_dc_victim_tag[0], Z1_A_ctrl_ld_st_bypass, Z1_d_read_nxt); --Z1_D_pc[9] is system_0:u0|cpu_0:the_cpu_0|D_pc[9] Z1_D_pc[9] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[9], N1_data_out, Z1_F_stall); --Z1_A_mem_baddr[12] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[12] Z1_A_mem_baddr[12] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[12], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_tag[1] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_tag[1] Z1_A_dc_victim_tag[1] = AMPP_FUNCTION(F1__clk1, Z1L2256, N1_data_out, Z1_A_stall); --Z1L3204 is system_0:u0|cpu_0:the_cpu_0|dc_tag_field_nxt[1]~1206 Z1L3204 = AMPP_FUNCTION(Z1_A_mem_baddr[12], Z1_A_dc_victim_tag[1], Z1_A_ctrl_ld_st_bypass, Z1_d_read_nxt); --Z1_D_pc[10] is system_0:u0|cpu_0:the_cpu_0|D_pc[10] Z1_D_pc[10] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[10], N1_data_out, Z1_F_stall); --Z1_A_mem_baddr[13] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[13] Z1_A_mem_baddr[13] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[13], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_tag[2] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_tag[2] Z1_A_dc_victim_tag[2] = AMPP_FUNCTION(F1__clk1, Z1L2257, N1_data_out, Z1_A_stall); --Z1L3205 is system_0:u0|cpu_0:the_cpu_0|dc_tag_field_nxt[2]~1207 Z1L3205 = AMPP_FUNCTION(Z1_A_mem_baddr[13], Z1_A_dc_victim_tag[2], Z1_A_ctrl_ld_st_bypass, Z1_d_read_nxt); --Z1_D_pc[11] is system_0:u0|cpu_0:the_cpu_0|D_pc[11] Z1_D_pc[11] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[11], N1_data_out, Z1_F_stall); --Z1_A_mem_baddr[14] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[14] Z1_A_mem_baddr[14] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[14], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_tag[3] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_tag[3] Z1_A_dc_victim_tag[3] = AMPP_FUNCTION(F1__clk1, Z1L2258, N1_data_out, Z1_A_stall); --Z1L3206 is system_0:u0|cpu_0:the_cpu_0|dc_tag_field_nxt[3]~1208 Z1L3206 = AMPP_FUNCTION(Z1_A_mem_baddr[14], Z1_A_dc_victim_tag[3], Z1_A_ctrl_ld_st_bypass, Z1_d_read_nxt); --Z1_D_pc[12] is system_0:u0|cpu_0:the_cpu_0|D_pc[12] Z1_D_pc[12] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[12], N1_data_out, Z1_F_stall); --Z1_A_mem_baddr[15] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[15] Z1_A_mem_baddr[15] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[15], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_tag[4] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_tag[4] Z1_A_dc_victim_tag[4] = AMPP_FUNCTION(F1__clk1, Z1L2259, N1_data_out, Z1_A_stall); --Z1L3207 is system_0:u0|cpu_0:the_cpu_0|dc_tag_field_nxt[4]~1209 Z1L3207 = AMPP_FUNCTION(Z1_A_mem_baddr[15], Z1_A_dc_victim_tag[4], Z1_A_ctrl_ld_st_bypass, Z1_d_read_nxt); --Z1_D_pc[13] is system_0:u0|cpu_0:the_cpu_0|D_pc[13] Z1_D_pc[13] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[13], N1_data_out, Z1_F_stall); --Z1_A_mem_baddr[16] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[16] Z1_A_mem_baddr[16] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[16], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_tag[5] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_tag[5] Z1_A_dc_victim_tag[5] = AMPP_FUNCTION(F1__clk1, Z1L2260, N1_data_out, Z1_A_stall); --Z1L3208 is system_0:u0|cpu_0:the_cpu_0|dc_tag_field_nxt[5]~1210 Z1L3208 = AMPP_FUNCTION(Z1_A_mem_baddr[16], Z1_A_dc_victim_tag[5], Z1_A_ctrl_ld_st_bypass, Z1_d_read_nxt); --Z1_D_pc[14] is system_0:u0|cpu_0:the_cpu_0|D_pc[14] Z1_D_pc[14] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[14], N1_data_out, Z1_F_stall); --Z1_A_mem_baddr[17] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[17] Z1_A_mem_baddr[17] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[17], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_tag[6] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_tag[6] Z1_A_dc_victim_tag[6] = AMPP_FUNCTION(F1__clk1, Z1L2261, N1_data_out, Z1_A_stall); --Z1L3209 is system_0:u0|cpu_0:the_cpu_0|dc_tag_field_nxt[6]~1211 Z1L3209 = AMPP_FUNCTION(Z1_A_mem_baddr[17], Z1_A_dc_victim_tag[6], Z1_A_ctrl_ld_st_bypass, Z1_d_read_nxt); --Z1_D_pc[15] is system_0:u0|cpu_0:the_cpu_0|D_pc[15] Z1_D_pc[15] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[15], N1_data_out, Z1_F_stall); --Z1_A_mem_baddr[18] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[18] Z1_A_mem_baddr[18] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[18], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_tag[7] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_tag[7] Z1_A_dc_victim_tag[7] = AMPP_FUNCTION(F1__clk1, Z1L2262, N1_data_out, Z1_A_stall); --Z1L3210 is system_0:u0|cpu_0:the_cpu_0|dc_tag_field_nxt[7]~1212 Z1L3210 = AMPP_FUNCTION(Z1_A_mem_baddr[18], Z1_A_dc_victim_tag[7], Z1_A_ctrl_ld_st_bypass, Z1_d_read_nxt); --Z1_D_pc[16] is system_0:u0|cpu_0:the_cpu_0|D_pc[16] Z1_D_pc[16] = AMPP_FUNCTION(F1__clk1, Z1_F_pc[16], N1_data_out, Z1_F_stall); --LB1L61 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_counter_load_value[1]~201 LB1L61 = LB1_sram_0_avalonS_wait_counter[1] & LB1_sram_0_avalonS_wait_counter[0] # !LB1_sram_0_avalonS_wait_counter[1] & !LB1_sram_0_avalonS_wait_counter[0] & LB1_sram_0_avalonS_wait_counter[2]; --LB1L62 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_counter_load_value[1]~202 LB1L62 = LB1L58 & !LB1L65 & (LB1L61 # LB1_sram_0_avalonS_in_a_read_cycle) # !LB1L58 & LB1L61; --LB1L63 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_counter_load_value[2]~203 LB1L63 = LB1_sram_0_avalonS_wait_counter[2] & (LB1_sram_0_avalonS_wait_counter[1] # LB1_sram_0_avalonS_wait_counter[0]); --LB1L64 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_counter_load_value[2]~204 LB1L64 = LB1L58 & (LB1L65 # LB1L63 & !LB1_sram_0_avalonS_in_a_read_cycle) # !LB1L58 & (LB1L63); --D1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo D1_hub_tdo = AMPP_FUNCTION(!A1L333, D1L22, !L1_state[8]); --Z1_A_st_data[0] is system_0:u0|cpu_0:the_cpu_0|A_st_data[0] Z1_A_st_data[0] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[0], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[0] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[0] Z1_A_dc_victim_rd_data[0] = AMPP_FUNCTION(F1__clk1, Z1L2223, N1_data_out, Z1_A_stall); --Z1_A_ctrl_st_bypass is system_0:u0|cpu_0:the_cpu_0|A_ctrl_st_bypass Z1_A_ctrl_st_bypass = AMPP_FUNCTION(F1__clk1, Z1_M_ctrl_st_bypass, N1_data_out, Z1_A_stall); --Z1L3129 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[0]~288 Z1L3129 = AMPP_FUNCTION(Z1_A_st_data[0], Z1_A_dc_victim_rd_data[0], Z1_A_ctrl_st_bypass); --N1_data_in_d1 is system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|data_in_d1 N1_data_in_d1 = DFFEAS(VCC, F1__clk1, !E1L1, , , , , , ); --XC1_resetrequest is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetrequest XC1_resetrequest = AMPP_FUNCTION(F1__clk1, FD1L41Q, D1_CLRN_SIGNAL, FD1L196); --C1_oRESET is Reset_Delay:delay1|oRESET C1_oRESET = DFFEAS(C1L82, CLOCK_50, , , , , , , ); --E1L1 is system_0:u0|reset_n_sources~1 E1L1 = XC1_resetrequest # !C1_oRESET; --AB1L224 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~368 AB1L224 = Z1_d_write & (GE1_entries[1] & !GE1_entries[0] # !AB1_cpu_0_data_master_dbs_address[1]); --JB1L8 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_granted_sdram_0_s1~25 JB1L8 = JB1_sdram_0_s1_arb_addend[1] & (JB1L18 # JB1_cpu_0_data_master_qualified_request_sdram_0_s1 # !JB1_sdram_0_s1_arb_addend[0]) # !JB1_sdram_0_s1_arb_addend[1] & (JB1_cpu_0_data_master_qualified_request_sdram_0_s1 $ (JB1L18 # JB1_sdram_0_s1_arb_addend[0])); --AB1L225 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~369 AB1L225 = JB1_cpu_0_data_master_qualified_request_sdram_0_s1 & (Z1_d_read # AB1L224 # !JB1L8); --AB1L226 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~370 AB1L226 = LB1L10 & (!AB1L356 # !LB1_sram_0_avalonS_wait_counter[0] # !AB1_cpu_0_data_master_dbs_address[1]); --LB1L71 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_grant_vector[1]~32 LB1L71 = LB1_sram_0_avalonS_arb_addend[1] & (LB1L14 # LB1L8 # !LB1_sram_0_avalonS_arb_addend[0]) # !LB1_sram_0_avalonS_arb_addend[1] & (LB1L8 $ (LB1L14 # LB1_sram_0_avalonS_arb_addend[0])); --AB1L227 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~371 AB1L227 = AB1L225 # LB1L8 & (AB1L226 # !LB1L71); --MB1L150 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_grant_vector[1]~32 MB1L150 = MB1_tri_state_bridge_0_avalon_slave_arb_addend[1] & (MB1L43 # MB1L33 # !MB1_tri_state_bridge_0_avalon_slave_arb_addend[0]) # !MB1_tri_state_bridge_0_avalon_slave_arb_addend[1] & (MB1L33 $ (MB1L43 # MB1_tri_state_bridge_0_avalon_slave_arb_addend[0])); --AB1L228 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~372 AB1L228 = MB1L33 & (Z1_d_read # !MB1L150); --JB1_cpu_0_data_master_read_data_valid_sdram_0_s1 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_read_data_valid_sdram_0_s1 JB1_cpu_0_data_master_read_data_valid_sdram_0_s1 = HE1_fifo_contains_ones_n & HB1_za_valid & HE1_stage_0; --AB1L229 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~373 AB1L229 = JB1_cpu_0_data_master_requests_sdram_0_s1 & !JB1_cpu_0_data_master_qualified_request_sdram_0_s1 & (!JB1_cpu_0_data_master_read_data_valid_sdram_0_s1 # !AB1_cpu_0_data_master_dbs_address[1]); --AB1L354 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|r_1~126 AB1L354 = AB1_cpu_0_data_master_dbs_address[1] & Z1_d_write & !Z1_d_byteenable[3] & !Z1_d_byteenable[2]; --AB1L230 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~374 AB1L230 = !AB1L354 & (AB1L229 # LB1_cpu_0_data_master_requests_sram_0_avalonS & !LB1L8); --AB1L357 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|r_2~287 AB1L357 = AB1_cpu_0_data_master_dbs_address[1] & AB1_cpu_0_data_master_dbs_address[0]; --AB1L358 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|r_2~288 AB1L358 = AB1L357 & (MB1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] # Z1_d_write & !Z1_d_byteenable[3]); --AB1L359 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|r_2~289 AB1L359 = MB1_cfi_flash_0_s1_wait_counter[0] & AB1L355 & AB1L357 # !Z1_d_write; --AB1L231 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~375 AB1L231 = MB1L33 & (!AB1L359) # !MB1L33 & MB1L38 & !AB1L358; --CB1L2 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|add~416 CB1L2 = CB1_cpu_0_data_master_requests_cpu_0_jtag_debug_module & !CB1_cpu_0_jtag_debug_module_arb_addend[1] & (CB1_cpu_0_jtag_debug_module_arb_addend[0] # CB1L28) # !CB1_cpu_0_data_master_requests_cpu_0_jtag_debug_module & !CB1L28 & (CB1_cpu_0_jtag_debug_module_arb_addend[0] $ !CB1_cpu_0_jtag_debug_module_arb_addend[1]); --AB1L232 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~376 AB1L232 = AB1L230 # AB1L231 # CB1_cpu_0_data_master_requests_cpu_0_jtag_debug_module & CB1L2; --EB1L4 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|add~416 EB1L4 = EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port & !EB1_epcs_controller_epcs_control_port_arb_addend[1] & (EB1L29 # EB1_epcs_controller_epcs_control_port_arb_addend[0]); --GB1L7 is system_0:u0|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave|Equal~186 GB1L7 = !Z1_d_address[3] & !Z1_d_address[4]; --FB1_av_waitrequest is system_0:u0|jtag_uart_0:the_jtag_uart_0|av_waitrequest FB1_av_waitrequest = DFFEAS(FB1L42, F1__clk1, N1_data_out, , , , , , ); --GB1L8 is system_0:u0|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave|Equal~187 GB1L8 = Z1_d_address[6] & GB1L6 & GB1L7 & !FB1_av_waitrequest; --AB1L233 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~377 AB1L233 = AB1_cpu_0_data_master_waitrequest # EB1L4 # GB1L8 # !LB1L10; --AB1L234 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~378 AB1L234 = !AB1L227 & !AB1L228 & !AB1L232 & !AB1L233; --Z1_A_st_data[1] is system_0:u0|cpu_0:the_cpu_0|A_st_data[1] Z1_A_st_data[1] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[1], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[1] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[1] Z1_A_dc_victim_rd_data[1] = AMPP_FUNCTION(F1__clk1, Z1L2224, N1_data_out, Z1_A_stall); --Z1L3130 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[1]~289 Z1L3130 = AMPP_FUNCTION(Z1_A_st_data[1], Z1_A_dc_victim_rd_data[1], Z1_A_ctrl_st_bypass); --Z1_A_st_data[2] is system_0:u0|cpu_0:the_cpu_0|A_st_data[2] Z1_A_st_data[2] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[2], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[2] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[2] Z1_A_dc_victim_rd_data[2] = AMPP_FUNCTION(F1__clk1, Z1L2225, N1_data_out, Z1_A_stall); --Z1L3131 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[2]~290 Z1L3131 = AMPP_FUNCTION(Z1_A_st_data[2], Z1_A_dc_victim_rd_data[2], Z1_A_ctrl_st_bypass); --Z1_A_st_data[3] is system_0:u0|cpu_0:the_cpu_0|A_st_data[3] Z1_A_st_data[3] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[3], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[3] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[3] Z1_A_dc_victim_rd_data[3] = AMPP_FUNCTION(F1__clk1, Z1L2226, N1_data_out, Z1_A_stall); --Z1L3132 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[3]~291 Z1L3132 = AMPP_FUNCTION(Z1_A_st_data[3], Z1_A_dc_victim_rd_data[3], Z1_A_ctrl_st_bypass); --Z1_A_st_data[4] is system_0:u0|cpu_0:the_cpu_0|A_st_data[4] Z1_A_st_data[4] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[4], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[4] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[4] Z1_A_dc_victim_rd_data[4] = AMPP_FUNCTION(F1__clk1, Z1L2227, N1_data_out, Z1_A_stall); --Z1L3133 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[4]~292 Z1L3133 = AMPP_FUNCTION(Z1_A_st_data[4], Z1_A_dc_victim_rd_data[4], Z1_A_ctrl_st_bypass); --Z1_A_st_data[5] is system_0:u0|cpu_0:the_cpu_0|A_st_data[5] Z1_A_st_data[5] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[5], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[5] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[5] Z1_A_dc_victim_rd_data[5] = AMPP_FUNCTION(F1__clk1, Z1L2228, N1_data_out, Z1_A_stall); --Z1L3134 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[5]~293 Z1L3134 = AMPP_FUNCTION(Z1_A_st_data[5], Z1_A_dc_victim_rd_data[5], Z1_A_ctrl_st_bypass); --Z1_A_st_data[6] is system_0:u0|cpu_0:the_cpu_0|A_st_data[6] Z1_A_st_data[6] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[6], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[6] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[6] Z1_A_dc_victim_rd_data[6] = AMPP_FUNCTION(F1__clk1, Z1L2229, N1_data_out, Z1_A_stall); --Z1L3135 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[6]~294 Z1L3135 = AMPP_FUNCTION(Z1_A_st_data[6], Z1_A_dc_victim_rd_data[6], Z1_A_ctrl_st_bypass); --Z1_A_st_data[7] is system_0:u0|cpu_0:the_cpu_0|A_st_data[7] Z1_A_st_data[7] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[7], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[7] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[7] Z1_A_dc_victim_rd_data[7] = AMPP_FUNCTION(F1__clk1, Z1L2230, N1_data_out, Z1_A_stall); --Z1L3136 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[7]~295 Z1L3136 = AMPP_FUNCTION(Z1_A_st_data[7], Z1_A_dc_victim_rd_data[7], Z1_A_ctrl_st_bypass); --Z1_A_st_data[8] is system_0:u0|cpu_0:the_cpu_0|A_st_data[8] Z1_A_st_data[8] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[8], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[8] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[8] Z1_A_dc_victim_rd_data[8] = AMPP_FUNCTION(F1__clk1, Z1L2231, N1_data_out, Z1_A_stall); --Z1L3137 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[8]~296 Z1L3137 = AMPP_FUNCTION(Z1_A_st_data[8], Z1_A_dc_victim_rd_data[8], Z1_A_ctrl_st_bypass); --Z1_A_st_data[9] is system_0:u0|cpu_0:the_cpu_0|A_st_data[9] Z1_A_st_data[9] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[9], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[9] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[9] Z1_A_dc_victim_rd_data[9] = AMPP_FUNCTION(F1__clk1, Z1L2232, N1_data_out, Z1_A_stall); --Z1L3138 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[9]~297 Z1L3138 = AMPP_FUNCTION(Z1_A_st_data[9], Z1_A_dc_victim_rd_data[9], Z1_A_ctrl_st_bypass); --Z1_A_st_data[10] is system_0:u0|cpu_0:the_cpu_0|A_st_data[10] Z1_A_st_data[10] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[10], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[10] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[10] Z1_A_dc_victim_rd_data[10] = AMPP_FUNCTION(F1__clk1, Z1L2233, N1_data_out, Z1_A_stall); --Z1L3139 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[10]~298 Z1L3139 = AMPP_FUNCTION(Z1_A_st_data[10], Z1_A_dc_victim_rd_data[10], Z1_A_ctrl_st_bypass); --Z1_A_st_data[11] is system_0:u0|cpu_0:the_cpu_0|A_st_data[11] Z1_A_st_data[11] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[11], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[11] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[11] Z1_A_dc_victim_rd_data[11] = AMPP_FUNCTION(F1__clk1, Z1L2234, N1_data_out, Z1_A_stall); --Z1L3140 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[11]~299 Z1L3140 = AMPP_FUNCTION(Z1_A_st_data[11], Z1_A_dc_victim_rd_data[11], Z1_A_ctrl_st_bypass); --Z1_A_st_data[12] is system_0:u0|cpu_0:the_cpu_0|A_st_data[12] Z1_A_st_data[12] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[12], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[12] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[12] Z1_A_dc_victim_rd_data[12] = AMPP_FUNCTION(F1__clk1, Z1L2235, N1_data_out, Z1_A_stall); --Z1L3141 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[12]~300 Z1L3141 = AMPP_FUNCTION(Z1_A_st_data[12], Z1_A_dc_victim_rd_data[12], Z1_A_ctrl_st_bypass); --Z1_A_st_data[13] is system_0:u0|cpu_0:the_cpu_0|A_st_data[13] Z1_A_st_data[13] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[13], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[13] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[13] Z1_A_dc_victim_rd_data[13] = AMPP_FUNCTION(F1__clk1, Z1L2236, N1_data_out, Z1_A_stall); --Z1L3142 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[13]~301 Z1L3142 = AMPP_FUNCTION(Z1_A_st_data[13], Z1_A_dc_victim_rd_data[13], Z1_A_ctrl_st_bypass); --Z1_A_st_data[14] is system_0:u0|cpu_0:the_cpu_0|A_st_data[14] Z1_A_st_data[14] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[14], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[14] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[14] Z1_A_dc_victim_rd_data[14] = AMPP_FUNCTION(F1__clk1, Z1L2237, N1_data_out, Z1_A_stall); --Z1L3143 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[14]~302 Z1L3143 = AMPP_FUNCTION(Z1_A_st_data[14], Z1_A_dc_victim_rd_data[14], Z1_A_ctrl_st_bypass); --Z1_A_st_data[15] is system_0:u0|cpu_0:the_cpu_0|A_st_data[15] Z1_A_st_data[15] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[15], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[15] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[15] Z1_A_dc_victim_rd_data[15] = AMPP_FUNCTION(F1__clk1, Z1L2238, N1_data_out, Z1_A_stall); --Z1L3144 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[15]~303 Z1L3144 = AMPP_FUNCTION(Z1_A_st_data[15], Z1_A_dc_victim_rd_data[15], Z1_A_ctrl_st_bypass); --LE1L2 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|Equal~92 LE1L2 = Z1_d_address[2] & Z1_d_address[3] & !Z1_d_address[4]; --Q1L1 is system_0:u0|KEY_s1_arbitrator:the_KEY_s1|Equal~63 Q1L1 = GB1L3 & GB1L4 & GB1L5 & !Z1_d_address[5]; --LE1L15 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|control_wr_strobe~21 LE1L15 = Z1_d_write & LE1L2 & Q1L1 & !Z1_d_address[6]; --NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] = DFFEAS(NE1L73, F1__clk1, N1_data_out, , NE1L74, , , , ); --NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] = DFFEAS(NE1_do_load_shifter, F1__clk1, N1_data_out, , NE1L74, , , , ); --NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8] NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8] = DFFEAS(NE1L61, F1__clk1, N1_data_out, , NE1L74, , , , ); --NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] = DFFEAS(NE1L60, F1__clk1, N1_data_out, , NE1L74, , , , ); --NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] = DFFEAS(NE1L59, F1__clk1, N1_data_out, , NE1L74, , , , ); --NE1L40 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|pre_txd~61 NE1L40 = !NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] & !NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8] & !NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] & !NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6]; --NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] = DFFEAS(NE1L58, F1__clk1, N1_data_out, , NE1L74, , , , ); --NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] = DFFEAS(NE1L57, F1__clk1, N1_data_out, , NE1L74, , , , ); --NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] = DFFEAS(NE1L56, F1__clk1, N1_data_out, , NE1L74, , , , ); --NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] = DFFEAS(NE1L55, F1__clk1, N1_data_out, , NE1L74, , , , ); --NE1L41 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|pre_txd~62 NE1L41 = !NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] & !NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] & !NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] & !NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2]; --NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] = DFFEAS(NE1L54, F1__clk1, N1_data_out, , NE1L74, , , , ); --NE1L42 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|pre_txd~63 NE1L42 = NE1L40 & NE1L41 & !NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1]; --NE1L43 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|pre_txd~64 NE1L43 = !NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] & (NE1_pre_txd # !NE1L42); --HB1L207 is system_0:u0|sdram_0:the_sdram_0|active_addr[20]~425 HB1L207 = HB1_m_state.100000000 & HB1L385 & (GE1L1 # HB1L300) # !HB1_m_state.100000000 & (GE1L1 & HB1L300); --HB1L66 is system_0:u0|sdram_0:the_sdram_0|Select~8170 HB1L66 = HB1_refresh_request # !HB1_m_state.000001000 & !HB1_m_state.000010000 # !HB1L22; --HB1L208 is system_0:u0|sdram_0:the_sdram_0|active_addr[20]~426 HB1L208 = N1_data_out & (HB1L207 & !HB1_refresh_request # !HB1L66); --HB1L67 is system_0:u0|sdram_0:the_sdram_0|Select~8171 HB1L67 = HB1_m_state.100000000 & !HB1_refresh_request; --HB1L68 is system_0:u0|sdram_0:the_sdram_0|Select~8172 HB1L68 = HB1L181 # HB1L22 & HB1L67 # !HB1L66; --HB1L263 is system_0:u0|sdram_0:the_sdram_0|comb~0 HB1L263 = JB1L16 # JB1L7 & (Z1_d_write # Z1_d_read); --GE1L6 is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entries[1]~664 GE1L6 = GE1_entries[0] & (GE1_entries[1] $ (!HB1_f_select & HB1L263)) # !GE1_entries[0] & (GE1_entries[1] & !HB1_f_select # !GE1_entries[1] & HB1_f_select & !HB1L263); --GE1L4 is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entries[0]~665 GE1L4 = HB1_f_select $ (GE1_entries[0] & (!HB1L263) # !GE1_entries[0] & !GE1_entries[1] & HB1L263); --JB1_sdram_0_s1_in_a_write_cycle is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_in_a_write_cycle JB1_sdram_0_s1_in_a_write_cycle = !JB1L7 # !Z1_d_write; --GE1_wr_address is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|wr_address GE1_wr_address = DFFEAS(GE1L97, F1__clk1, N1_data_out, , , , , , ); --GE1L95 is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address~14 GE1L95 = GE1_rd_address $ (HB1_f_pop & GE1L1 & HB1L385); --JB1L36 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[9]~220 JB1L36 = JB1L7 & Z1_d_address[10] # !JB1L7 & (Z1_ic_fill_line[5]); --JB1L40 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[13]~221 JB1L40 = JB1L7 & Z1_d_address[14] # !JB1L7 & (Z1_ic_fill_tag[2]); --JB1L41 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[14]~222 JB1L41 = JB1L7 & Z1_d_address[15] # !JB1L7 & (Z1_ic_fill_tag[3]); --JB1L35 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[8]~223 JB1L35 = JB1L7 & Z1_d_address[9] # !JB1L7 & (Z1_ic_fill_line[4]); --JB1L38 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[11]~224 JB1L38 = JB1L7 & Z1_d_address[12] # !JB1L7 & (Z1_ic_fill_tag[0]); --JB1L42 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[15]~225 JB1L42 = JB1L7 & Z1_d_address[16] # !JB1L7 & (Z1_ic_fill_tag[4]); --JB1L43 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[16]~226 JB1L43 = JB1L7 & Z1_d_address[17] # !JB1L7 & (Z1_ic_fill_tag[5]); --JB1L37 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[10]~227 JB1L37 = JB1L7 & Z1_d_address[11] # !JB1L7 & (Z1_ic_fill_line[6]); --JB1L44 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[17]~228 JB1L44 = JB1L7 & Z1_d_address[18] # !JB1L7 & (Z1_ic_fill_tag[6]); --JB1L48 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[21]~229 JB1L48 = JB1L7 & Z1_d_address[22] # !JB1L7 & (Z1_ic_fill_tag[10]); --JB1L47 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[20]~230 JB1L47 = JB1L7 & Z1_d_address[21] # !JB1L7 & (Z1_ic_fill_tag[9]); --HB1L69 is system_0:u0|sdram_0:the_sdram_0|Select~8173 HB1L69 = GE1_rd_address & GE1_entry_1[38] # !GE1_rd_address & (GE1_entry_0[38]); --JB1L39 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[12]~231 JB1L39 = JB1L7 & Z1_d_address[13] # !JB1L7 & (Z1_ic_fill_tag[1]); --JB1L45 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[18]~232 JB1L45 = JB1L7 & Z1_d_address[19] # !JB1L7 & (Z1_ic_fill_tag[7]); --JB1L46 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[19]~233 JB1L46 = JB1L7 & Z1_d_address[20] # !JB1L7 & (Z1_ic_fill_tag[8]); --HB1L70 is system_0:u0|sdram_0:the_sdram_0|Select~8174 HB1L70 = HB1_init_done & HB1_refresh_request & !HB1_m_state.000000001; --HB1L71 is system_0:u0|sdram_0:the_sdram_0|Select~8175 HB1L71 = HB1_init_done & !HB1_m_state.000000001 & (GE1_entries[1] # GE1_entries[0]); --HB1L211 is system_0:u0|sdram_0:the_sdram_0|active_cs_n~176 HB1L211 = N1_data_out & (HB1L70 # HB1_active_cs_n & !HB1L71) # !N1_data_out & (HB1_active_cs_n); --HB1_m_next.000001000 is system_0:u0|sdram_0:the_sdram_0|m_next.000001000 HB1_m_next.000001000 = DFFEAS(HB1L348, F1__clk1, N1_data_out, , HB1L352, , , !HB1_m_state.000000010, ); --HB1_m_count[2] is system_0:u0|sdram_0:the_sdram_0|m_count[2] HB1_m_count[2] = DFFEAS(HB1L96, F1__clk1, N1_data_out, , , , , , ); --HB1_m_count[1] is system_0:u0|sdram_0:the_sdram_0|m_count[1] HB1_m_count[1] = DFFEAS(HB1L100, F1__clk1, N1_data_out, , , , , , ); --HB1L72 is system_0:u0|sdram_0:the_sdram_0|Select~8176 HB1L72 = HB1_m_count[2] # HB1_m_count[1] # !HB1_m_state.000000100; --HB1L73 is system_0:u0|sdram_0:the_sdram_0|Select~8177 HB1L73 = HB1_m_state.100000000 & (GE1_entries[1] # GE1_entries[0] # HB1_refresh_request); --HB1L363 is system_0:u0|sdram_0:the_sdram_0|m_state.000001000~464 HB1L363 = HB1L385 & HB1L73 & !HB1_refresh_request; --HB1L364 is system_0:u0|sdram_0:the_sdram_0|m_state.000001000~465 HB1L364 = HB1L8 & (HB1L363 # HB1_m_next.000001000 & HB1L369) # !HB1L8 & HB1_m_next.000001000 & HB1L369; --HB1L365 is system_0:u0|sdram_0:the_sdram_0|m_state.000001000~466 HB1L365 = !HB1_m_state.000000001 & (GE1L1 # HB1_refresh_request # !HB1_init_done); --HB1L366 is system_0:u0|sdram_0:the_sdram_0|m_state.000001000~467 HB1L366 = HB1L73 # HB1L365 # !HB1L72 # !HB1L359; --HB1L367 is system_0:u0|sdram_0:the_sdram_0|m_state.000001000~468 HB1L367 = HB1L366 # !HB1L358 & (HB1_refresh_request # !HB1L22); --HB1_m_next.000010000 is system_0:u0|sdram_0:the_sdram_0|m_next.000010000 HB1_m_next.000010000 = DFFEAS(HB1L353, F1__clk1, N1_data_out, , HB1L352, , , !HB1_m_state.000000010, ); --HB1L368 is system_0:u0|sdram_0:the_sdram_0|m_state.000001000~469 HB1L368 = HB1L369 & (HB1_m_next.000010000 # HB1L363 & !HB1L8) # !HB1L369 & (HB1L363 & !HB1L8); --HB1_i_state.111 is system_0:u0|sdram_0:the_sdram_0|i_state.111 HB1_i_state.111 = DFFEAS(HB1L101, F1__clk1, N1_data_out, , , , , , ); --JB1L27 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[0]~234 JB1L27 = JB1L7 & AB1_cpu_0_data_master_dbs_address[1] # !JB1L7 & (BB1_cpu_0_instruction_master_dbs_address[1]); --HB1L6 is system_0:u0|sdram_0:the_sdram_0|LessThan~81 HB1L6 = HB1_m_count[2] # HB1_m_count[1]; --HB1L74 is system_0:u0|sdram_0:the_sdram_0|Select~8178 HB1L74 = HB1_m_state.000000100 & HB1_m_next.010000000 & !HB1_m_count[2] & !HB1_m_count[1]; --HB1_i_state.101 is system_0:u0|sdram_0:the_sdram_0|i_state.101 HB1_i_state.101 = DFFEAS(HB1L293, F1__clk1, N1_data_out, , , , , , ); --HB1L296 is system_0:u0|sdram_0:the_sdram_0|init_done~728 HB1L296 = HB1_init_done # HB1_i_state.101; --HB1_m_next.000000001 is system_0:u0|sdram_0:the_sdram_0|m_next.000000001 HB1_m_next.000000001 = DFFEAS(HB1L105, F1__clk1, N1_data_out, , , , , , ); --HB1L75 is system_0:u0|sdram_0:the_sdram_0|Select~8179 HB1L75 = HB1_init_done & (GE1_entries[1] # GE1_entries[0] # HB1_refresh_request); --HB1L76 is system_0:u0|sdram_0:the_sdram_0|Select~8180 HB1L76 = HB1L72 & (HB1_m_state.000000001 # HB1L75) # !HB1L72 & HB1_m_next.000000001; --HB1L77 is system_0:u0|sdram_0:the_sdram_0|Select~8181 HB1L77 = HB1L67 & (!HB1L358 # !GE1L1) # !HB1L67 & !HB1L358 & (!GE1L1 # !HB1L385); --HB1L78 is system_0:u0|sdram_0:the_sdram_0|Select~8182 HB1L78 = HB1_m_state.100000000 & (HB1_refresh_request # HB1_m_state.000000100 & HB1L6) # !HB1_m_state.100000000 & HB1_m_state.000000100 & HB1L6; --HB1L79 is system_0:u0|sdram_0:the_sdram_0|Select~8183 HB1L79 = HB1_m_state.000001000 & (HB1_m_state.000000100 # HB1_refresh_request) # !HB1_m_state.000001000 & HB1_m_state.000010000 & (HB1_m_state.000000100 # HB1_refresh_request); --HB1L80 is system_0:u0|sdram_0:the_sdram_0|Select~8184 HB1L80 = HB1L78 # HB1L22 & HB1L79 # !HB1L359; --HB1L81 is system_0:u0|sdram_0:the_sdram_0|Select~8185 HB1L81 = HB1_m_state.000100000 & (HB1_m_count[2] # HB1_m_count[1]); --HB1L82 is system_0:u0|sdram_0:the_sdram_0|Select~8186 HB1L82 = HB1L81 # GE1L1 & HB1L67 & !HB1L385; --JB1L28 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[1]~235 JB1L28 = JB1L7 & Z1_d_address[2] # !JB1L7 & (Z1_ic_fill_ap_offset[0]); --JB1L29 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[2]~236 JB1L29 = JB1L7 & Z1_d_address[3] # !JB1L7 & (Z1_ic_fill_ap_offset[1]); --JB1L30 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[3]~237 JB1L30 = JB1L7 & Z1_d_address[4] # !JB1L7 & (Z1_ic_fill_ap_offset[2]); --JB1L31 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[4]~238 JB1L31 = JB1L7 & Z1_d_address[5] # !JB1L7 & (Z1_ic_fill_line[0]); --JB1L32 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[5]~239 JB1L32 = JB1L7 & Z1_d_address[6] # !JB1L7 & (Z1_ic_fill_line[1]); --JB1L33 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[6]~240 JB1L33 = JB1L7 & Z1_d_address[7] # !JB1L7 & (Z1_ic_fill_line[2]); --JB1L34 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_address[7]~241 JB1L34 = JB1L7 & Z1_d_address[8] # !JB1L7 & (Z1_ic_fill_line[3]); --HB1L264 is system_0:u0|sdram_0:the_sdram_0|comb~26 HB1L264 = !LB1L6 & Z1_d_write & JB1L7; --HB1L265 is system_0:u0|sdram_0:the_sdram_0|comb~27 HB1L265 = !JB1_sdram_0_s1_in_a_write_cycle & (AB1_cpu_0_data_master_dbs_address[1] & !Z1_d_byteenable[3] # !AB1_cpu_0_data_master_dbs_address[1] & (!Z1_d_byteenable[1])); --HB1_i_state.011 is system_0:u0|sdram_0:the_sdram_0|i_state.011 HB1_i_state.011 = DFFEAS(HB1L107, F1__clk1, N1_data_out, , , , , , ); --HB1_i_state.000 is system_0:u0|sdram_0:the_sdram_0|i_state.000 HB1_i_state.000 = DFFEAS(HB1L108, F1__clk1, N1_data_out, , , , , , ); --HB1_i_state.010 is system_0:u0|sdram_0:the_sdram_0|i_state.010 HB1_i_state.010 = DFFEAS(HB1L109, F1__clk1, N1_data_out, , , , , , ); --HB1L83 is system_0:u0|sdram_0:the_sdram_0|Select~8187 HB1L83 = HB1_i_state.000 & !HB1_i_state.010; --HB1L84 is system_0:u0|sdram_0:the_sdram_0|Select~8188 HB1L84 = !HB1_i_state.011 & HB1L83 & (HB1_i_cmd[0] # !HB1_i_state.101); --HB1_i_state.001 is system_0:u0|sdram_0:the_sdram_0|i_state.001 HB1_i_state.001 = DFFEAS(HB1L110, F1__clk1, N1_data_out, , , , , , ); --HB1L85 is system_0:u0|sdram_0:the_sdram_0|Select~8189 HB1L85 = HB1_i_state.000 & !HB1_i_state.011; --HB1L86 is system_0:u0|sdram_0:the_sdram_0|Select~8190 HB1L86 = !HB1_i_state.001 & HB1L85 & (HB1_i_cmd[1] # !HB1_i_state.101); --HB1L87 is system_0:u0|sdram_0:the_sdram_0|Select~8191 HB1L87 = !HB1_i_state.011 & HB1_i_state.000 & (HB1_i_cmd[2] # !HB1_i_state.101); --HB1L88 is system_0:u0|sdram_0:the_sdram_0|Select~8192 HB1L88 = HB1_i_state.000 & (HB1_i_cmd[3] # !HB1_i_state.101); --HB1_refresh_counter[13] is system_0:u0|sdram_0:the_sdram_0|refresh_counter[13] HB1_refresh_counter[13] = DFFEAS(HB1L412, F1__clk1, N1_data_out, , , , , , ); --HB1_refresh_counter[10] is system_0:u0|sdram_0:the_sdram_0|refresh_counter[10] HB1_refresh_counter[10] = DFFEAS(HB1L408, F1__clk1, N1_data_out, , , , , , ); --HB1_refresh_counter[12] is system_0:u0|sdram_0:the_sdram_0|refresh_counter[12] HB1_refresh_counter[12] = DFFEAS(HB1L413, F1__clk1, N1_data_out, , , , , , ); --HB1_refresh_counter[11] is system_0:u0|sdram_0:the_sdram_0|refresh_counter[11] HB1_refresh_counter[11] = DFFEAS(HB1L414, F1__clk1, N1_data_out, , , , , , ); --HB1L1 is system_0:u0|sdram_0:the_sdram_0|Equal~231 HB1L1 = HB1_refresh_counter[13] & HB1_refresh_counter[10] & !HB1_refresh_counter[12] & !HB1_refresh_counter[11]; --HB1_refresh_counter[9] is system_0:u0|sdram_0:the_sdram_0|refresh_counter[9] HB1_refresh_counter[9] = DFFEAS(HB1L406, F1__clk1, N1_data_out, , , , , , ); --HB1_refresh_counter[8] is system_0:u0|sdram_0:the_sdram_0|refresh_counter[8] HB1_refresh_counter[8] = DFFEAS(HB1L415, F1__clk1, N1_data_out, , , , , , ); --HB1_refresh_counter[7] is system_0:u0|sdram_0:the_sdram_0|refresh_counter[7] HB1_refresh_counter[7] = DFFEAS(HB1L416, F1__clk1, N1_data_out, , , , , , ); --HB1_refresh_counter[6] is system_0:u0|sdram_0:the_sdram_0|refresh_counter[6] HB1_refresh_counter[6] = DFFEAS(HB1L417, F1__clk1, N1_data_out, , , , , , ); --HB1L2 is system_0:u0|sdram_0:the_sdram_0|Equal~232 HB1L2 = HB1_refresh_counter[9] & HB1_refresh_counter[8] & !HB1_refresh_counter[7] & !HB1_refresh_counter[6]; --HB1_refresh_counter[4] is system_0:u0|sdram_0:the_sdram_0|refresh_counter[4] HB1_refresh_counter[4] = DFFEAS(HB1L400, F1__clk1, N1_data_out, , , , , , ); --HB1_refresh_counter[5] is system_0:u0|sdram_0:the_sdram_0|refresh_counter[5] HB1_refresh_counter[5] = DFFEAS(HB1L418, F1__clk1, N1_data_out, , , , , , ); --HB1_refresh_counter[3] is system_0:u0|sdram_0:the_sdram_0|refresh_counter[3] HB1_refresh_counter[3] = DFFEAS(HB1L239, F1__clk1, N1_data_out, , , , , , ); --HB1_refresh_counter[2] is system_0:u0|sdram_0:the_sdram_0|refresh_counter[2] HB1_refresh_counter[2] = DFFEAS(HB1L419, F1__clk1, N1_data_out, , , , , , ); --HB1L3 is system_0:u0|sdram_0:the_sdram_0|Equal~233 HB1L3 = HB1_refresh_counter[4] & !HB1_refresh_counter[5] & !HB1_refresh_counter[3] & !HB1_refresh_counter[2]; --HB1_refresh_counter[1] is system_0:u0|sdram_0:the_sdram_0|refresh_counter[1] HB1_refresh_counter[1] = DFFEAS(HB1L235, F1__clk1, N1_data_out, , , , , , ); --HB1_refresh_counter[0] is system_0:u0|sdram_0:the_sdram_0|refresh_counter[0] HB1_refresh_counter[0] = DFFEAS(HB1L420, F1__clk1, N1_data_out, , , , , , ); --HB1L4 is system_0:u0|sdram_0:the_sdram_0|Equal~234 HB1L4 = !HB1_refresh_counter[1] & !HB1_refresh_counter[0]; --HB1L5 is system_0:u0|sdram_0:the_sdram_0|Equal~235 HB1L5 = HB1L1 & HB1L2 & HB1L3 & HB1L4; --HB1_ack_refresh_request is system_0:u0|sdram_0:the_sdram_0|ack_refresh_request HB1_ack_refresh_request = DFFEAS(HB1L111, F1__clk1, N1_data_out, , , , , , ); --HB1L422 is system_0:u0|sdram_0:the_sdram_0|refresh_request~122 HB1L422 = HB1_init_done & !HB1_ack_refresh_request & (HB1_refresh_request # HB1L5); --HB1L89 is system_0:u0|sdram_0:the_sdram_0|Select~8193 HB1L89 = !HB1_m_state.000000100 & !HB1_m_state.000100000; --HB1L356 is system_0:u0|sdram_0:the_sdram_0|m_next~142 HB1L356 = HB1_refresh_request # !HB1L385 & (GE1_entries[1] # GE1_entries[0]); --HB1L90 is system_0:u0|sdram_0:the_sdram_0|Select~8194 HB1L90 = !HB1L358 & (!HB1_refresh_request # !HB1L385 # !GE1L1); --HB1L91 is system_0:u0|sdram_0:the_sdram_0|Select~8195 HB1L91 = !HB1_m_state.001000000 & !HB1L90 & (HB1L356 # !HB1_m_state.100000000); --HB1L92 is system_0:u0|sdram_0:the_sdram_0|Select~8196 HB1L92 = HB1L300 & (HB1_m_next.010000000 # HB1_refresh_request) # !HB1L300 & HB1_m_next.010000000 & HB1L183; --AB1L8 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[0]~726 AB1L8 = AB1_cpu_0_data_master_dbs_address[0] $ (MB1L38 & AB1L287); --BB1L11 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_dbs_address[0]~565 BB1L11 = BB1_cpu_0_instruction_master_dbs_address[0] $ (MB1L48 & BB1_pre_dbs_count_enable); --MB1_tri_state_bridge_0_avalon_slave_arb_share_counter[1] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter[1] MB1_tri_state_bridge_0_avalon_slave_arb_share_counter[1] = DFFEAS(MB1L139, F1__clk1, N1_data_out, , MB1L133, , , , ); --MB1_tri_state_bridge_0_avalon_slave_arb_share_counter[0] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter[0] MB1_tri_state_bridge_0_avalon_slave_arb_share_counter[0] = DFFEAS(MB1L138, F1__clk1, N1_data_out, , MB1L133, , , , ); --MB1_tri_state_bridge_0_avalon_slave_arb_share_counter[2] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter[2] MB1_tri_state_bridge_0_avalon_slave_arb_share_counter[2] = DFFEAS(MB1L141, F1__clk1, N1_data_out, , MB1L133, , , , ); --MB1L148 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_firsttransfer~100 MB1L148 = MB1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable & (MB1L147 # MB1L38 & MB1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1); --MB1L140 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter_next_value[2]~221 MB1L140 = MB1_tri_state_bridge_0_avalon_slave_arb_share_counter[1] # MB1_tri_state_bridge_0_avalon_slave_arb_share_counter[0] # MB1_tri_state_bridge_0_avalon_slave_arb_share_counter[2] # !MB1L148; --MB1L1 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~792 MB1L1 = MB1L148 & MB1_tri_state_bridge_0_avalon_slave_arb_share_counter[0] # !MB1L148 & (!MB1L149 & !MB1L40); --MB1L139 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter_next_value[1]~222 MB1L139 = MB1L140 & (MB1L1 $ (!MB1L148 # !MB1_tri_state_bridge_0_avalon_slave_arb_share_counter[1])); --MB1L145 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_end_xfer~0 MB1L145 = MB1L40 # MB1L149 & (Z1_d_write # Z1_d_read); --MB1L146 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_end_xfer~27 MB1L146 = MB1L145 & (MB1L144 # MB1_cfi_flash_0_s1_wait_counter[0] # !AB1L355); --MB1L155 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_slavearbiterlockenable~38 MB1L155 = !MB1L146 & (MB1L139 # MB1L140 & !MB1L1); --MB1L2 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~793 MB1L2 = MB1L148 & MB1_tri_state_bridge_0_avalon_slave_arb_share_counter[2] # !MB1L148 & (MB1L149 # MB1L40); --MB1L3 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~794 MB1L3 = MB1_tri_state_bridge_0_avalon_slave_arb_share_counter[1] & MB1L148; --MB1L141 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter_next_value[2]~223 MB1L141 = MB1L140 & (MB1L2 $ (!MB1L3 & !MB1L1)); --MB1L156 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_slavearbiterlockenable~39 MB1L156 = MB1L155 # MB1L146 & MB1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable # !MB1L146 & (MB1L141); --MB1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0] MB1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0] = DFFEAS(MB1L40, F1__clk1, N1_data_out, , MB1L143, , , , ); --MB1L142 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_winner[0]~39 MB1L142 = MB1L148 & MB1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0] # !MB1L148 & (MB1L40 # MB1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0] & !MB1L149); --MB1L74 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1~34 MB1L74 = MB1_d1_reasons_to_wait # MB1L148 # !MB1L33 & !MB1L43; --MB1L75 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1~35 MB1L75 = MB1L48 & (MB1L142 # MB1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 & MB1L74); --MB1L28 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter_eq_0~76 MB1L28 = MB1_cfi_flash_0_s1_wait_counter[0] # !AB1L355; --MB1L37 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register_in~12 MB1L37 = Z1_d_read & MB1L149 & !MB1L144 & !MB1L28; --MB1L131 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[1]~730 MB1L131 = MB1L146 & MB1L149 # !MB1L146 & (MB1L142); --MB1L132 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[1]~731 MB1L132 = MB1L76 & MB1L131 # !MB1L76 & (MB1_tri_state_bridge_0_avalon_slave_arb_addend[1]); --MB1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1] MB1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1] = DFFEAS(MB1L149, F1__clk1, N1_data_out, , MB1L143, , , , ); --MB1L71 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1~131 MB1L71 = MB1L148 & MB1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1] # !MB1L148 & (MB1L149 # MB1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1] & !MB1L40); --MB1L72 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1~132 MB1L72 = MB1L38 & (MB1L71 # MB1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 & MB1L74); --MB1L128 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[0]~732 MB1L128 = MB1L146 & MB1L40 # !MB1L146 & (!MB1L142); --MB1L129 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[0]~733 MB1L129 = MB1L76 & !MB1L128 # !MB1L76 & (MB1_tri_state_bridge_0_avalon_slave_arb_addend[0]); --MB1L19 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_counter_load_value~219 MB1L19 = MB1L144 & (MB1L40 # Z1_d_read & MB1L149); --MB1L20 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_counter_load_value~220 MB1L20 = Z1_d_write & MB1L149 & MB1L144; --MB1L4 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~795 MB1L4 = MB1_cfi_flash_0_s1_wait_counter[0] $ VCC; --MB1L5 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~796 MB1L5 = CARRY(MB1_cfi_flash_0_s1_wait_counter[0]); --MB1L6 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~797 MB1L6 = MB1_cfi_flash_0_s1_wait_counter[1] & MB1L5 & VCC # !MB1_cfi_flash_0_s1_wait_counter[1] & !MB1L5; --MB1L7 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~798 MB1L7 = CARRY(!MB1_cfi_flash_0_s1_wait_counter[1] & !MB1L5); --MB1L8 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~799 MB1L8 = MB1_cfi_flash_0_s1_wait_counter[2] & (GND # !MB1L7) # !MB1_cfi_flash_0_s1_wait_counter[2] & (MB1L7 $ GND); --MB1L9 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~800 MB1L9 = CARRY(MB1_cfi_flash_0_s1_wait_counter[2] # !MB1L7); --MB1L10 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~801 MB1L10 = MB1_cfi_flash_0_s1_wait_counter[3] & MB1L9 & VCC # !MB1_cfi_flash_0_s1_wait_counter[3] & !MB1L9; --MB1L11 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~802 MB1L11 = CARRY(!MB1_cfi_flash_0_s1_wait_counter[3] & !MB1L9); --MB1L12 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~803 MB1L12 = MB1_cfi_flash_0_s1_wait_counter[4] $ MB1L11; --MB1L18 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_counter_load_value[4]~221 MB1L18 = MB1L19 # MB1L20 # MB1L12 & MB1L28; --MB1L17 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_counter_load_value[3]~222 MB1L17 = MB1L28 & MB1L10 & (!MB1L145 # !MB1L144); --MB1L16 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_counter_load_value[2]~223 MB1L16 = !MB1L19 & (MB1L20 # MB1L28 & MB1L8); --HE1_how_many_ones[2] is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|how_many_ones[2] HE1_how_many_ones[2] = DFFEAS(HE1L7, F1__clk1, N1_data_out, , JE1L13, , , , ); --HE1L48 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|updated_one_count~129 HE1L48 = JB1L7 & !GE1L93 & (Z1_d_read # JB1L16); --HE1_how_many_ones[1] is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|how_many_ones[1] HE1_how_many_ones[1] = DFFEAS(HE1L11, F1__clk1, N1_data_out, , JE1L13, , , , ); --HE1_how_many_ones[0] is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|how_many_ones[0] HE1_how_many_ones[0] = DFFEAS(HE1L12, F1__clk1, N1_data_out, , JE1L13, , , , ); --HE1L1 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|add~182 HE1L1 = HE1_how_many_ones[0] $ VCC; --HE1L2 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|add~183 HE1L2 = CARRY(HE1_how_many_ones[0]); --HE1L3 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|add~184 HE1L3 = HE1_how_many_ones[1] & (HE1L48 & !HE1L2 # !HE1L48 & HE1L2 & VCC) # !HE1_how_many_ones[1] & (HE1L48 & (HE1L2 # GND) # !HE1L48 & !HE1L2); --HE1L4 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|add~185 HE1L4 = CARRY(HE1_how_many_ones[1] & HE1L48 & !HE1L2 # !HE1_how_many_ones[1] & (HE1L48 # !HE1L2)); --HE1L5 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|add~186 HE1L5 = (HE1_how_many_ones[2] $ HE1L48 $ HE1L4) # GND; --HE1L6 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|add~187 HE1L6 = CARRY(HE1_how_many_ones[2] & (!HE1L4 # !HE1L48) # !HE1_how_many_ones[2] & !HE1L48 & !HE1L4); --HE1L49 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|updated_one_count~130 HE1L49 = HB1_za_valid & HE1_stage_0; --HE1L7 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|add~188 HE1L7 = HE1_how_many_ones[2] & (HE1L5 # HE1L49 $ !HE1L48) # !HE1_how_many_ones[2] & HE1L5 & (HE1L49 $ HE1L48); --HE1_how_many_ones[3] is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|how_many_ones[3] HE1_how_many_ones[3] = DFFEAS(HE1L10, F1__clk1, N1_data_out, , JE1L13, , , , ); --HE1L8 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|add~189 HE1L8 = HE1_how_many_ones[3] $ HE1L48 $ !HE1L6; --HE1L10 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|add~191 HE1L10 = HE1_how_many_ones[3] & (HE1L8 # HE1L49 $ !HE1L48) # !HE1_how_many_ones[3] & HE1L8 & (HE1L49 $ HE1L48); --HE1L11 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|add~192 HE1L11 = HE1_how_many_ones[1] & (HE1L3 # HE1L49 $ !HE1L48) # !HE1_how_many_ones[1] & HE1L3 & (HE1L49 $ HE1L48); --HE1L12 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|add~193 HE1L12 = HE1_how_many_ones[0] & (HE1L1 # HE1L49 $ !HE1L48) # !HE1_how_many_ones[0] & HE1L1 & (HE1L49 $ HE1L48); --HE1L40 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|reduce_or~24 HE1L40 = HE1L7 # HE1L10 # HE1L11 # HE1L12; --JB1_sdram_0_s1_arb_share_counter[2] is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_share_counter[2] JB1_sdram_0_s1_arb_share_counter[2] = DFFEAS(JB1L64, F1__clk1, N1_data_out, , JB1L56, , , , ); --JB1_sdram_0_s1_arb_share_counter[0] is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_share_counter[0] JB1_sdram_0_s1_arb_share_counter[0] = DFFEAS(JB1L62, F1__clk1, N1_data_out, , JB1L56, , , , ); --JB1_sdram_0_s1_arb_share_counter[1] is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_share_counter[1] JB1_sdram_0_s1_arb_share_counter[1] = DFFEAS(JB1L63, F1__clk1, N1_data_out, , JB1L56, , , , ); --JB1L69 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_firsttransfer~87 JB1L69 = JB1_sdram_0_s1_slavearbiterlockenable & (JB1L6 # JB1_last_cycle_cpu_0_instruction_master_granted_slave_sdram_0_s1 & JB1L19); --JB1L61 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_share_counter_next_value[0]~173 JB1L61 = JB1_sdram_0_s1_arb_share_counter[2] # JB1_sdram_0_s1_arb_share_counter[0] # JB1_sdram_0_s1_arb_share_counter[1] # !JB1L69; --JB1L1 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|add~621 JB1L1 = JB1_sdram_0_s1_arb_share_counter[0] # JB1_sdram_0_s1_arb_share_counter[1] # !JB1L69; --JB1L64 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_share_counter_next_value[2]~174 JB1L64 = JB1L61 & (JB1L1 $ (!JB1L69 # !JB1_sdram_0_s1_arb_share_counter[2])); --JB1L2 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|add~622 JB1L2 = JB1L69 & JB1_sdram_0_s1_arb_share_counter[1]; --JB1L3 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|add~623 JB1L3 = JB1_sdram_0_s1_arb_addend[0] & (!JB1_cpu_0_data_master_qualified_request_sdram_0_s1 & !JB1L18 # !JB1_sdram_0_s1_arb_addend[1]) # !JB1_sdram_0_s1_arb_addend[0] & !JB1_cpu_0_data_master_qualified_request_sdram_0_s1 & !JB1L18; --JB1L66 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_winner~0 JB1L66 = !JB1L69 & !JB1L3; --JB1L4 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|add~624 JB1L4 = JB1L69 & JB1_sdram_0_s1_arb_share_counter[0] # !JB1L69 & (JB1L3); --JB1L75 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_slavearbiterlockenable~66 JB1L75 = JB1L61 & (JB1L2 # JB1L66 # !JB1L4); --JB1L76 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_slavearbiterlockenable~67 JB1L76 = JB1L68 & JB1_sdram_0_s1_slavearbiterlockenable # !JB1L68 & (JB1L64 # JB1L75); --JB1_sdram_0_s1_saved_chosen_master_vector[0] is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_saved_chosen_master_vector[0] JB1_sdram_0_s1_saved_chosen_master_vector[0] = DFFEAS(JB1L16, F1__clk1, N1_data_out, , JB1L66, , , , ); --JB1L65 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_winner[0]~39 JB1L65 = JB1L69 & JB1_sdram_0_s1_saved_chosen_master_vector[0] # !JB1L69 & (JB1L16 # JB1_sdram_0_s1_saved_chosen_master_vector[0] & !JB1L7); --JB1_d1_reasons_to_wait is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|d1_reasons_to_wait JB1_d1_reasons_to_wait = DFFEAS(JB1L68, F1__clk1, N1_data_out, , , , , , ); --JB1L67 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arbitration_holdoff_internal~24 JB1L67 = !JB1L69 & !JB1_d1_reasons_to_wait & (JB1_cpu_0_data_master_qualified_request_sdram_0_s1 # JB1L18); --JB1L26 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|last_cycle_cpu_0_instruction_master_granted_slave_sdram_0_s1~18 JB1L26 = JB1L19 & (JB1L65 # JB1_last_cycle_cpu_0_instruction_master_granted_slave_sdram_0_s1 & !JB1L67); --JB1L54 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_addend[1]~730 JB1L54 = GE1L93 & (HB1L263 & JB1L7 # !HB1L263 & (JB1L65)) # !GE1L93 & (JB1L65); --JB1L55 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_addend[1]~731 JB1L55 = JB1L3 & JB1_sdram_0_s1_arb_addend[1] # !JB1L3 & (JB1L54); --JB1_sdram_0_s1_saved_chosen_master_vector[1] is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_saved_chosen_master_vector[1] JB1_sdram_0_s1_saved_chosen_master_vector[1] = DFFEAS(JB1L7, F1__clk1, N1_data_out, , JB1L66, , , , ); --JB1L23 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|last_cycle_cpu_0_data_master_granted_slave_sdram_0_s1~63 JB1L23 = JB1L69 & JB1_sdram_0_s1_saved_chosen_master_vector[1] # !JB1L69 & (JB1L7 # JB1_sdram_0_s1_saved_chosen_master_vector[1] & !JB1L16); --JB1L24 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|last_cycle_cpu_0_data_master_granted_slave_sdram_0_s1~64 JB1L24 = JB1_cpu_0_data_master_requests_sdram_0_s1 & (JB1L23 # JB1_last_cycle_cpu_0_data_master_granted_slave_sdram_0_s1 & !JB1L67); --JB1L51 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_addend[0]~732 JB1L51 = GE1L93 & (HB1L263 & JB1L16 # !HB1L263 & (!JB1L65)) # !GE1L93 & (!JB1L65); --JB1L52 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_addend[0]~733 JB1L52 = JB1L3 & (JB1_sdram_0_s1_arb_addend[0]) # !JB1L3 & !JB1L51; --MB1L15 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_counter_load_value[1]~224 MB1L15 = MB1L19 # MB1L20 # MB1L28 & MB1L6; --MB1L14 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_counter_load_value[0]~225 MB1L14 = MB1L28 & MB1L4 & (!MB1L145 # !MB1L144); --HB1_rd_valid[2] is system_0:u0|sdram_0:the_sdram_0|rd_valid[2] HB1_rd_valid[2] = DFFEAS(HB1_rd_valid[1], F1__clk1, N1_data_out, , , , , , ); --HE1_stage_1 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|stage_1 HE1_stage_1 = DFFEAS(HE1L30, F1__clk1, , , HE1L19, , , , ); --JE1_full_1 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_1 JE1_full_1 = DFFEAS(HE1L29, F1__clk1, N1_data_out, , HE1L14, , , , ); --HE1L28 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|p0_stage_0~10 HE1L28 = JE1_full_1 & HE1_stage_1 # !JE1_full_1 & (JB1L7); --JE1_full_0 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_0 JE1_full_0 = DFFEAS(HE1L27, F1__clk1, N1_data_out, , HE1L14, , , , ); --HE1L20 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|always12~3 HE1L20 = HB1_za_valid # JB1L5 & !JE1_full_0; --LB1L60 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_counter_load_value[0]~205 LB1L60 = !LB1_sram_0_avalonS_wait_counter[0] & !AB1L356 & (!LB1L66 # !LB1L58); --Z1_M_alu_result[22] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[22] Z1_M_alu_result[22] = AMPP_FUNCTION(F1__clk1, Z1L1459, N1_data_out, Z1_A_stall); --Z1_A_shift_rot_stall is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_stall Z1_A_shift_rot_stall = AMPP_FUNCTION(F1__clk1, Z1L714, N1_data_out); --Z1_A_mul_stall is system_0:u0|cpu_0:the_cpu_0|A_mul_stall Z1_A_mul_stall = AMPP_FUNCTION(F1__clk1, Z1L521, N1_data_out); --Z1_A_stall is system_0:u0|cpu_0:the_cpu_0|A_stall Z1_A_stall = AMPP_FUNCTION(Z1L953, Z1L522, Z1_A_shift_rot_stall, Z1_A_mul_stall); --GC1_q_a[11] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_prq1:auto_generated|q_a[11] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 15, Port B Logical Depth: 512, Port B Logical Width: 15 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered GC1_q_a[11] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3236, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224); --Z1_M_alu_result[10] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[10] Z1_M_alu_result[10] = AMPP_FUNCTION(F1__clk1, Z1L1422, N1_data_out, Z1_A_stall); --Z1_M_alu_result[8] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[8] Z1_M_alu_result[8] = AMPP_FUNCTION(F1__clk1, Z1L1418, N1_data_out, Z1_A_stall); --Z1L2100 is system_0:u0|cpu_0:the_cpu_0|M_A_dc_latest_line_match~62 Z1L2100 = AMPP_FUNCTION(Z1_A_mem_baddr[8], Z1_A_mem_baddr[10], Z1_M_alu_result[10], Z1_M_alu_result[8]); --Z1_M_alu_result[3] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[3] Z1_M_alu_result[3] = AMPP_FUNCTION(F1__clk1, Z1L1408, N1_data_out, Z1_A_stall); --Z1_M_alu_result[2] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[2] Z1_M_alu_result[2] = AMPP_FUNCTION(F1__clk1, Z1L1406, N1_data_out, Z1_A_stall); --Z1L2101 is system_0:u0|cpu_0:the_cpu_0|M_A_dc_latest_line_match~63 Z1L2101 = AMPP_FUNCTION(Z1_A_mem_baddr[2], Z1_A_mem_baddr[3], Z1_M_alu_result[3], Z1_M_alu_result[2]); --Z1_M_alu_result[6] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[6] Z1_M_alu_result[6] = AMPP_FUNCTION(F1__clk1, Z1L1414, N1_data_out, Z1_A_stall); --Z1_M_alu_result[4] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[4] Z1_M_alu_result[4] = AMPP_FUNCTION(F1__clk1, Z1L1410, N1_data_out, Z1_A_stall); --Z1L2102 is system_0:u0|cpu_0:the_cpu_0|M_A_dc_latest_line_match~64 Z1L2102 = AMPP_FUNCTION(Z1_A_mem_baddr[4], Z1_A_mem_baddr[6], Z1_M_alu_result[6], Z1_M_alu_result[4]); --Z1_M_alu_result[7] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[7] Z1_M_alu_result[7] = AMPP_FUNCTION(F1__clk1, Z1L1416, N1_data_out, Z1_A_stall); --Z1_M_alu_result[5] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[5] Z1_M_alu_result[5] = AMPP_FUNCTION(F1__clk1, Z1L1412, N1_data_out, Z1_A_stall); --Z1L2103 is system_0:u0|cpu_0:the_cpu_0|M_A_dc_latest_line_match~65 Z1L2103 = AMPP_FUNCTION(Z1_A_mem_baddr[5], Z1_A_mem_baddr[7], Z1_M_alu_result[7], Z1_M_alu_result[5]); --Z1L2104 is system_0:u0|cpu_0:the_cpu_0|M_A_dc_latest_line_match~66 Z1L2104 = AMPP_FUNCTION(Z1L2100, Z1L2101, Z1L2102, Z1L2103); --Z1_A_dc_latest_data_valid is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_valid Z1_A_dc_latest_data_valid = AMPP_FUNCTION(F1__clk1, Z1L74, N1_data_out); --Z1_M_alu_result[9] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[9] Z1_M_alu_result[9] = AMPP_FUNCTION(F1__clk1, Z1L1420, N1_data_out, Z1_A_stall); --Z1_M_A_dc_latest_line_match is system_0:u0|cpu_0:the_cpu_0|M_A_dc_latest_line_match Z1_M_A_dc_latest_line_match = AMPP_FUNCTION(Z1L2104, Z1_A_dc_latest_data_valid, Z1_A_mem_baddr[9], Z1_M_alu_result[9]); --Z1L2266 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_tag[11]~741 Z1L2266 = AMPP_FUNCTION(Z1_A_mem_baddr[22], GC1_q_a[11], Z1_M_A_dc_latest_line_match); --Z1_M_ctrl_ld_st_bypass is system_0:u0|cpu_0:the_cpu_0|M_ctrl_ld_st_bypass Z1_M_ctrl_ld_st_bypass = AMPP_FUNCTION(F1__clk1, Z1L1537, N1_data_out, Z1_A_stall); --Z1_M_valid_from_E is system_0:u0|cpu_0:the_cpu_0|M_valid_from_E Z1_M_valid_from_E = AMPP_FUNCTION(F1__clk1, Z1L1891, N1_data_out, Z1_A_stall); --Z1_M_sel_data_master is system_0:u0|cpu_0:the_cpu_0|M_sel_data_master Z1_M_sel_data_master = AMPP_FUNCTION(F1__clk1, GND, N1_data_out, Z1_A_stall); --Z1L2200 is system_0:u0|cpu_0:the_cpu_0|M_dc_av_rd_req~29 Z1L2200 = AMPP_FUNCTION(Z1_M_valid_from_E, Z1_M_sel_data_master); --Z1_M_ctrl_ld_bypass is system_0:u0|cpu_0:the_cpu_0|M_ctrl_ld_bypass Z1_M_ctrl_ld_bypass = AMPP_FUNCTION(F1__clk1, Z1L1530, N1_data_out, Z1_A_stall); --Z1_M_ctrl_ld_st_non_bypass_non_st32 is system_0:u0|cpu_0:the_cpu_0|M_ctrl_ld_st_non_bypass_non_st32 Z1_M_ctrl_ld_st_non_bypass_non_st32 = AMPP_FUNCTION(F1__clk1, Z1L1539, N1_data_out, Z1_A_stall); --Z1_M_alu_result[11] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[11] Z1_M_alu_result[11] = AMPP_FUNCTION(F1__clk1, Z1L1426, N1_data_out, Z1_A_stall); --Z1_M_alu_result[23] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[23] Z1_M_alu_result[23] = AMPP_FUNCTION(F1__clk1, Z1L1462, N1_data_out, Z1_A_stall); --Z1L2205 is system_0:u0|cpu_0:the_cpu_0|M_dc_hit~230 Z1L2205 = AMPP_FUNCTION(Z1_A_mem_baddr[23], Z1_A_mem_baddr[11], Z1_M_alu_result[11], Z1_M_alu_result[23]); --Z1_M_alu_result[18] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[18] Z1_M_alu_result[18] = AMPP_FUNCTION(F1__clk1, Z1L1447, N1_data_out, Z1_A_stall); --Z1_M_alu_result[19] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[19] Z1_M_alu_result[19] = AMPP_FUNCTION(F1__clk1, Z1L1450, N1_data_out, Z1_A_stall); --Z1L2206 is system_0:u0|cpu_0:the_cpu_0|M_dc_hit~231 Z1L2206 = AMPP_FUNCTION(Z1_A_mem_baddr[19], Z1_A_mem_baddr[18], Z1_M_alu_result[18], Z1_M_alu_result[19]); --Z1_M_alu_result[17] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[17] Z1_M_alu_result[17] = AMPP_FUNCTION(F1__clk1, Z1L1444, N1_data_out, Z1_A_stall); --Z1_M_alu_result[16] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[16] Z1_M_alu_result[16] = AMPP_FUNCTION(F1__clk1, Z1L1441, N1_data_out, Z1_A_stall); --Z1L2207 is system_0:u0|cpu_0:the_cpu_0|M_dc_hit~232 Z1L2207 = AMPP_FUNCTION(Z1_A_mem_baddr[16], Z1_A_mem_baddr[17], Z1_M_alu_result[17], Z1_M_alu_result[16]); --Z1_M_alu_result[13] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[13] Z1_M_alu_result[13] = AMPP_FUNCTION(F1__clk1, Z1L1432, N1_data_out, Z1_A_stall); --Z1_M_alu_result[20] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[20] Z1_M_alu_result[20] = AMPP_FUNCTION(F1__clk1, Z1L1453, N1_data_out, Z1_A_stall); --Z1L2208 is system_0:u0|cpu_0:the_cpu_0|M_dc_hit~233 Z1L2208 = AMPP_FUNCTION(Z1_A_mem_baddr[20], Z1_A_mem_baddr[13], Z1_M_alu_result[13], Z1_M_alu_result[20]); --Z1L2209 is system_0:u0|cpu_0:the_cpu_0|M_dc_hit~234 Z1L2209 = AMPP_FUNCTION(Z1L2205, Z1L2206, Z1L2207, Z1L2208); --Z1_M_alu_result[21] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[21] Z1_M_alu_result[21] = AMPP_FUNCTION(F1__clk1, Z1L1456, N1_data_out, Z1_A_stall); --Z1L2210 is system_0:u0|cpu_0:the_cpu_0|M_dc_hit~235 Z1L2210 = AMPP_FUNCTION(Z1_A_mem_baddr[22], Z1_A_mem_baddr[21], Z1_M_alu_result[21], Z1_M_alu_result[22]); --Z1_M_alu_result[14] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[14] Z1_M_alu_result[14] = AMPP_FUNCTION(F1__clk1, Z1L1435, N1_data_out, Z1_A_stall); --Z1_M_alu_result[12] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[12] Z1_M_alu_result[12] = AMPP_FUNCTION(F1__clk1, Z1L1429, N1_data_out, Z1_A_stall); --Z1L2211 is system_0:u0|cpu_0:the_cpu_0|M_dc_hit~236 Z1L2211 = AMPP_FUNCTION(Z1_A_mem_baddr[12], Z1_A_mem_baddr[14], Z1_M_alu_result[14], Z1_M_alu_result[12]); --Z1_M_alu_result[15] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[15] Z1_M_alu_result[15] = AMPP_FUNCTION(F1__clk1, Z1L1438, N1_data_out, Z1_A_stall); --Z1_M_ctrl_ld is system_0:u0|cpu_0:the_cpu_0|M_ctrl_ld Z1_M_ctrl_ld = AMPP_FUNCTION(F1__clk1, Z1L1542, N1_data_out, Z1_A_stall); --Z1_A_ctrl_initd_flushd_flushda is system_0:u0|cpu_0:the_cpu_0|A_ctrl_initd_flushd_flushda Z1_A_ctrl_initd_flushd_flushda = AMPP_FUNCTION(F1__clk1, Z1_M_ctrl_initd_flushd_flushda, N1_data_out, Z1_A_stall); --Z1L2212 is system_0:u0|cpu_0:the_cpu_0|M_dc_hit~237 Z1L2212 = AMPP_FUNCTION(Z1_A_mem_baddr[15], Z1_M_alu_result[15], Z1_M_ctrl_ld, Z1_A_ctrl_initd_flushd_flushda); --Z1L2213 is system_0:u0|cpu_0:the_cpu_0|M_dc_hit~238 Z1L2213 = AMPP_FUNCTION(Z1L2209, Z1L2210, Z1L2211, Z1L2212); --GC1_q_a[1] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_prq1:auto_generated|q_a[1] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 15, Port B Logical Depth: 512, Port B Logical Width: 15 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered GC1_q_a[1] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3226, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224); --GC1_q_a[5] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_prq1:auto_generated|q_a[5] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 15, Port B Logical Depth: 512, Port B Logical Width: 15 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered GC1_q_a[5] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3230, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224); --Z1L2214 is system_0:u0|cpu_0:the_cpu_0|M_dc_hit~239 Z1L2214 = AMPP_FUNCTION(GC1_q_a[1], GC1_q_a[5], Z1_M_alu_result[16], Z1_M_alu_result[12]); --GC1_q_a[4] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_prq1:auto_generated|q_a[4] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 15, Port B Logical Depth: 512, Port B Logical Width: 15 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered GC1_q_a[4] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3229, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224); --Z1L2215 is system_0:u0|cpu_0:the_cpu_0|M_dc_hit~240 Z1L2215 = AMPP_FUNCTION(GC1_q_a[4], GC1_q_a[11], Z1_M_alu_result[22], Z1_M_alu_result[15]); --GC1_q_a[7] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_prq1:auto_generated|q_a[7] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 15, Port B Logical Depth: 512, Port B Logical Width: 15 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered GC1_q_a[7] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3232, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224); --GC1_q_a[6] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_prq1:auto_generated|q_a[6] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 15, Port B Logical Depth: 512, Port B Logical Width: 15 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered GC1_q_a[6] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3231, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224); --Z1L2216 is system_0:u0|cpu_0:the_cpu_0|M_dc_hit~241 Z1L2216 = AMPP_FUNCTION(GC1_q_a[7], GC1_q_a[6], Z1_M_alu_result[17], Z1_M_alu_result[18]); --GC1_q_a[9] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_prq1:auto_generated|q_a[9] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 15, Port B Logical Depth: 512, Port B Logical Width: 15 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered GC1_q_a[9] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3234, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224); --GC1_q_a[3] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_prq1:auto_generated|q_a[3] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 15, Port B Logical Depth: 512, Port B Logical Width: 15 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered GC1_q_a[3] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3228, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224); --Z1L2217 is system_0:u0|cpu_0:the_cpu_0|M_dc_hit~242 Z1L2217 = AMPP_FUNCTION(GC1_q_a[9], GC1_q_a[3], Z1_M_alu_result[14], Z1_M_alu_result[20]); --Z1L2218 is system_0:u0|cpu_0:the_cpu_0|M_dc_hit~243 Z1L2218 = AMPP_FUNCTION(Z1L2214, Z1L2215, Z1L2216, Z1L2217); --GC1_q_a[13] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_prq1:auto_generated|q_a[13] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 15, Port B Logical Depth: 512, Port B Logical Width: 15 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered GC1_q_a[13] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3238, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224); --GC1_q_a[0] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_prq1:auto_generated|q_a[0] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 15, Port B Logical Depth: 512, Port B Logical Width: 15 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered GC1_q_a[0] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3225, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224); --GC1_q_a[10] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_prq1:auto_generated|q_a[10] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 15, Port B Logical Depth: 512, Port B Logical Width: 15 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered GC1_q_a[10] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3235, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224); --Z1L2219 is system_0:u0|cpu_0:the_cpu_0|M_dc_hit~244 Z1L2219 = AMPP_FUNCTION(GC1_q_a[0], GC1_q_a[10], Z1_M_alu_result[21], Z1_M_alu_result[11]); --GC1_q_a[12] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_prq1:auto_generated|q_a[12] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 15, Port B Logical Depth: 512, Port B Logical Width: 15 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered GC1_q_a[12] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3237, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224); --GC1_q_a[8] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_prq1:auto_generated|q_a[8] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 15, Port B Logical Depth: 512, Port B Logical Width: 15 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered GC1_q_a[8] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3233, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224); --Z1L2220 is system_0:u0|cpu_0:the_cpu_0|M_dc_hit~245 Z1L2220 = AMPP_FUNCTION(GC1_q_a[12], GC1_q_a[8], Z1_M_alu_result[19], Z1_M_alu_result[23]); --GC1_q_a[2] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_prq1:auto_generated|q_a[2] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 15, Port B Logical Depth: 512, Port B Logical Width: 15 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered GC1_q_a[2] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3227, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224); --Z1L2105 is system_0:u0|cpu_0:the_cpu_0|M_M_dc_tag_match~42 Z1L2105 = AMPP_FUNCTION(GC1_q_a[2], Z1_M_alu_result[13]); --Z1L2221 is system_0:u0|cpu_0:the_cpu_0|M_dc_hit~246 Z1L2221 = AMPP_FUNCTION(GC1_q_a[13], Z1L2219, Z1L2220, Z1L2105); --Z1L2222 is system_0:u0|cpu_0:the_cpu_0|M_dc_hit~247 Z1L2222 = AMPP_FUNCTION(Z1L2213, Z1L2218, Z1L2221, Z1_M_A_dc_latest_line_match); --Z1L2201 is system_0:u0|cpu_0:the_cpu_0|M_dc_av_rd_req~30 Z1L2201 = AMPP_FUNCTION(Z1L2200, Z1_M_ctrl_ld_bypass, Z1_M_ctrl_ld_st_non_bypass_non_st32, Z1L2222); --Z1_M_ctrl_flushd_flushda is system_0:u0|cpu_0:the_cpu_0|M_ctrl_flushd_flushda Z1_M_ctrl_flushd_flushda = AMPP_FUNCTION(F1__clk1, Z1L1521, N1_data_out, Z1_A_stall); --Z1_M_ctrl_ld_st_non_bypass is system_0:u0|cpu_0:the_cpu_0|M_ctrl_ld_st_non_bypass Z1_M_ctrl_ld_st_non_bypass = AMPP_FUNCTION(F1__clk1, Z1L1540, N1_data_out, Z1_A_stall); --Z1L2202 is system_0:u0|cpu_0:the_cpu_0|M_dc_av_wr_req~223 Z1L2202 = AMPP_FUNCTION(Z1_M_ctrl_flushd_flushda, Z1_M_sel_data_master, Z1_M_ctrl_ld_st_non_bypass, Z1L2222); --Z1_A_ctrl_st is system_0:u0|cpu_0:the_cpu_0|A_ctrl_st Z1_A_ctrl_st = AMPP_FUNCTION(F1__clk1, Z1_M_ctrl_st, N1_data_out, Z1_A_stall); --GC1_q_a[14] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_prq1:auto_generated|q_a[14] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 15, Port B Logical Depth: 512, Port B Logical Width: 15 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered GC1_q_a[14] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3239, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224); --Z1L2203 is system_0:u0|cpu_0:the_cpu_0|M_dc_av_wr_req~224 Z1L2203 = AMPP_FUNCTION(Z1L2202, Z1_A_ctrl_st, GC1_q_a[14], Z1_M_A_dc_latest_line_match); --Z1_M_ctrl_st_bypass is system_0:u0|cpu_0:the_cpu_0|M_ctrl_st_bypass Z1_M_ctrl_st_bypass = AMPP_FUNCTION(F1__clk1, Z1L1550, N1_data_out, Z1_A_stall); --Z1L2204 is system_0:u0|cpu_0:the_cpu_0|M_dc_av_wr_req~225 Z1L2204 = AMPP_FUNCTION(Z1_M_valid_from_E, Z1L2203, Z1_M_sel_data_master, Z1_M_ctrl_st_bypass); --Z1L3026 is system_0:u0|cpu_0:the_cpu_0|av_wr_done_nxt~0 Z1L3026 = AMPP_FUNCTION(Z1_av_wr_done, Z1_d_write, AB1_cpu_0_data_master_waitrequest); --Z1_av_rd_data_transfer is system_0:u0|cpu_0:the_cpu_0|av_rd_data_transfer Z1_av_rd_data_transfer = AMPP_FUNCTION(Z1_d_read, AB1_cpu_0_data_master_waitrequest); --Z1L2267 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_tag[12]~742 Z1L2267 = AMPP_FUNCTION(Z1_A_mem_baddr[23], GC1_q_a[12], Z1_M_A_dc_latest_line_match); --Z1L2265 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_tag[10]~743 Z1L2265 = AMPP_FUNCTION(Z1_A_mem_baddr[21], GC1_q_a[10], Z1_M_A_dc_latest_line_match); --Z1L2264 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_tag[9]~744 Z1L2264 = AMPP_FUNCTION(Z1_A_mem_baddr[20], GC1_q_a[9], Z1_M_A_dc_latest_line_match); --Z1L2263 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_tag[8]~745 Z1L2263 = AMPP_FUNCTION(Z1_A_mem_baddr[19], GC1_q_a[8], Z1_M_A_dc_latest_line_match); --LB1L55 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_arb_share_counter_next_value[2]~138 LB1L55 = LB1L52 & (LB1L4 $ (LB1L3 # LB1L2)); --LB1L47 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_arb_counter_enable~22 LB1L47 = !LB1L67 & (LB1L59 # !LB1L8 & !LB1L14); --LB1L53 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_arb_share_counter_next_value[0]~139 LB1L53 = LB1L52 & (LB1L69 & (!LB1_sram_0_avalonS_arb_share_counter[0]) # !LB1L69 & LB1L59); --LB1L54 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_arb_share_counter_next_value[1]~140 LB1L54 = LB1L52 & (LB1L3 $ !LB1L2); --LB1L57 is system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_arb_winner~0 LB1L57 = LB1L59 & !LB1L69; --Z1_F_pc[20] is system_0:u0|cpu_0:the_cpu_0|F_pc[20] Z1_F_pc[20] = AMPP_FUNCTION(F1__clk1, Z1L2064, Z1_M_pipe_flush_waddr[20], N1_data_out, !Z1_M_pipe_flush, Z1_F_stall); --Z1_E_ctrl_late_result is system_0:u0|cpu_0:the_cpu_0|E_ctrl_late_result Z1_E_ctrl_late_result = AMPP_FUNCTION(F1__clk1, Z1L1054, N1_data_out, Z1_A_stall); --Z1_E_regnum_a_cmp_D is system_0:u0|cpu_0:the_cpu_0|E_regnum_a_cmp_D Z1_E_regnum_a_cmp_D = AMPP_FUNCTION(F1__clk1, Z1L1201, N1_data_out, !Z1_F_stall, Z1_A_stall); --Z1_D_ctrl_a_not_src is system_0:u0|cpu_0:the_cpu_0|D_ctrl_a_not_src Z1_D_ctrl_a_not_src = AMPP_FUNCTION(F1__clk1, Z1L1929, N1_data_out, Z1_F_stall); --Z1_D_src1_hazard_E is system_0:u0|cpu_0:the_cpu_0|D_src1_hazard_E Z1_D_src1_hazard_E = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src); --Z1_E_regnum_b_cmp_D is system_0:u0|cpu_0:the_cpu_0|E_regnum_b_cmp_D Z1_E_regnum_b_cmp_D = AMPP_FUNCTION(F1__clk1, Z1L1204, N1_data_out, !Z1_F_stall, Z1_A_stall); --Z1_D_ctrl_b_not_src is system_0:u0|cpu_0:the_cpu_0|D_ctrl_b_not_src Z1_D_ctrl_b_not_src = AMPP_FUNCTION(F1__clk1, Z1L1931, N1_data_out, Z1_F_stall); --Z1L1066 is system_0:u0|cpu_0:the_cpu_0|D_data_depend~76 Z1L1066 = AMPP_FUNCTION(Z1_E_ctrl_late_result, Z1_D_src1_hazard_E, Z1_E_regnum_b_cmp_D, Z1_D_ctrl_b_not_src); --Z1_M_ctrl_late_result is system_0:u0|cpu_0:the_cpu_0|M_ctrl_late_result Z1_M_ctrl_late_result = AMPP_FUNCTION(F1__clk1, Z1_E_ctrl_late_result, N1_data_out, Z1_A_stall); --Z1_M_regnum_a_cmp_D is system_0:u0|cpu_0:the_cpu_0|M_regnum_a_cmp_D Z1_M_regnum_a_cmp_D = AMPP_FUNCTION(F1__clk1, Z1_E_regnum_a_cmp_F, Z1_E_regnum_a_cmp_D, N1_data_out, !Z1_F_stall, Z1_A_stall); --Z1_M_regnum_b_cmp_D is system_0:u0|cpu_0:the_cpu_0|M_regnum_b_cmp_D Z1_M_regnum_b_cmp_D = AMPP_FUNCTION(F1__clk1, Z1_E_regnum_b_cmp_F, Z1_E_regnum_b_cmp_D, N1_data_out, !Z1_F_stall, Z1_A_stall); --Z1L1067 is system_0:u0|cpu_0:the_cpu_0|D_data_depend~77 Z1L1067 = AMPP_FUNCTION(Z1_M_regnum_a_cmp_D, Z1_M_regnum_b_cmp_D, Z1_D_ctrl_a_not_src, Z1_D_ctrl_b_not_src); --Z1L1068 is system_0:u0|cpu_0:the_cpu_0|D_data_depend~78 Z1L1068 = AMPP_FUNCTION(Z1L1066, Z1_M_ctrl_late_result, Z1L1067); --Z1_D_issue is system_0:u0|cpu_0:the_cpu_0|D_issue Z1_D_issue = AMPP_FUNCTION(F1__clk1, Z1_F_issue, N1_data_out, Z1_F_stall); --Z1_F_stall is system_0:u0|cpu_0:the_cpu_0|F_stall Z1_F_stall = AMPP_FUNCTION(Z1_A_stall, Z1_M_pipe_flush, Z1L1068, Z1_D_issue); --Z1L1101 is system_0:u0|cpu_0:the_cpu_0|D_inst_ram_hit~21 Z1L1101 = AMPP_FUNCTION(Z1_D_kill, Z1_D_inst_ram_hit); --Z1_E_valid_jmp_indirect is system_0:u0|cpu_0:the_cpu_0|E_valid_jmp_indirect Z1_E_valid_jmp_indirect = AMPP_FUNCTION(F1__clk1, Z1L1889, N1_data_out, Z1_A_stall); --Z1L2035 is system_0:u0|cpu_0:the_cpu_0|F_kill~282 Z1L2035 = AMPP_FUNCTION(Z1_E_valid_jmp_indirect, Z1_M_pipe_flush); --Z1_D_iw[4] is system_0:u0|cpu_0:the_cpu_0|D_iw[4] Z1_D_iw[4] = AMPP_FUNCTION(F1__clk1, Z1L1997, N1_data_out, Z1_F_stall); --Z1_D_iw[5] is system_0:u0|cpu_0:the_cpu_0|D_iw[5] Z1_D_iw[5] = AMPP_FUNCTION(F1__clk1, Z1L1998, N1_data_out, Z1_F_stall); --Z1L1047 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_implicit_dst_retaddr~44 Z1L1047 = AMPP_FUNCTION(Z1_D_iw[4], Z1_D_iw[5]); --Z1_D_iw[1] is system_0:u0|cpu_0:the_cpu_0|D_iw[1] Z1_D_iw[1] = AMPP_FUNCTION(F1__clk1, Z1L1993, N1_data_out, Z1_F_stall); --Z1_D_iw[2] is system_0:u0|cpu_0:the_cpu_0|D_iw[2] Z1_D_iw[2] = AMPP_FUNCTION(F1__clk1, Z1L1995, N1_data_out, Z1_F_stall); --Z1_D_iw[3] is system_0:u0|cpu_0:the_cpu_0|D_iw[3] Z1_D_iw[3] = AMPP_FUNCTION(F1__clk1, Z1L1996, N1_data_out, Z1_F_stall); --Z1L1048 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_implicit_dst_retaddr~45 Z1L1048 = AMPP_FUNCTION(Z1L1047, Z1_D_iw[1], Z1_D_iw[2], Z1_D_iw[3]); --Z1_D_ctrl_br is system_0:u0|cpu_0:the_cpu_0|D_ctrl_br Z1_D_ctrl_br = AMPP_FUNCTION(F1__clk1, Z1L1934, N1_data_out, Z1_F_stall); --Z1_D_ctrl_br_uncond is system_0:u0|cpu_0:the_cpu_0|D_ctrl_br_uncond Z1_D_ctrl_br_uncond = AMPP_FUNCTION(F1__clk1, Z1L1933, N1_data_out, Z1_F_stall); --Z1_D_bht_data[1] is system_0:u0|cpu_0:the_cpu_0|D_bht_data[1] Z1_D_bht_data[1] = AMPP_FUNCTION(F1__clk1, EC1_q_a[1], N1_data_out, Z1_F_stall); --Z1L966 is system_0:u0|cpu_0:the_cpu_0|D_br_pred_taken~28 Z1L966 = AMPP_FUNCTION(Z1_D_ctrl_br, Z1_D_ctrl_br_uncond, Z1_D_bht_data[1]); --Z1_D_iw[11] is system_0:u0|cpu_0:the_cpu_0|D_iw[11] Z1_D_iw[11] = AMPP_FUNCTION(F1__clk1, Z1L2004, N1_data_out, Z1_F_stall); --Z1_D_iw[15] is system_0:u0|cpu_0:the_cpu_0|D_iw[15] Z1_D_iw[15] = AMPP_FUNCTION(F1__clk1, Z1L2008, N1_data_out, Z1_F_stall); --Z1_D_iw[13] is system_0:u0|cpu_0:the_cpu_0|D_iw[13] Z1_D_iw[13] = AMPP_FUNCTION(F1__clk1, Z1L2006, N1_data_out, Z1_F_stall); --Z1_D_iw[14] is system_0:u0|cpu_0:the_cpu_0|D_iw[14] Z1_D_iw[14] = AMPP_FUNCTION(F1__clk1, Z1L2007, N1_data_out, Z1_F_stall); --Z1L1894 is system_0:u0|cpu_0:the_cpu_0|Equal~6215 Z1L1894 = AMPP_FUNCTION(Z1_D_iw[15], Z1_D_iw[14]); --Z1_D_iw[0] is system_0:u0|cpu_0:the_cpu_0|D_iw[0] Z1_D_iw[0] = AMPP_FUNCTION(F1__clk1, Z1L1992, N1_data_out, Z1_F_stall); --Z1L1141 is system_0:u0|cpu_0:the_cpu_0|D_op_call~823 Z1L1141 = AMPP_FUNCTION(Z1_D_iw[0], Z1_D_iw[1], Z1_D_iw[2], Z1_D_iw[3]); --Z1L1142 is system_0:u0|cpu_0:the_cpu_0|D_op_call~824 Z1L1142 = AMPP_FUNCTION(Z1_D_iw[4], Z1_D_iw[5], Z1L1141); --Z1_D_iw[16] is system_0:u0|cpu_0:the_cpu_0|D_iw[16] Z1_D_iw[16] = AMPP_FUNCTION(F1__clk1, Z1L2009, N1_data_out, Z1_F_stall); --Z1_D_iw[12] is system_0:u0|cpu_0:the_cpu_0|D_iw[12] Z1_D_iw[12] = AMPP_FUNCTION(F1__clk1, Z1L2005, N1_data_out, Z1_F_stall); --Z1L2036 is system_0:u0|cpu_0:the_cpu_0|F_kill~283 Z1L2036 = AMPP_FUNCTION(Z1L1142, Z1_D_iw[16], Z1_D_iw[12]); --Z1L2037 is system_0:u0|cpu_0:the_cpu_0|F_kill~284 Z1L2037 = AMPP_FUNCTION(Z1L1048, Z1L966, Z1_D_iw[11], Z1L2036); --Z1L2038 is system_0:u0|cpu_0:the_cpu_0|F_kill~285 Z1L2038 = AMPP_FUNCTION(Z1L1101, Z1L2035, Z1_D_issue, Z1L2037); --KC1_q_b[12] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[12] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[12] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1_ic_fill_tag[4], Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --KC1_q_b[8] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[8] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[8] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1_ic_fill_tag[0], Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --Z1_F_pc[10] is system_0:u0|cpu_0:the_cpu_0|F_pc[10] Z1_F_pc[10] = AMPP_FUNCTION(F1__clk1, Z1L2067, Z1_M_pipe_flush_waddr[10], N1_data_out, !Z1_M_pipe_flush, Z1_F_stall); --Z1_F_pc[14] is system_0:u0|cpu_0:the_cpu_0|F_pc[14] Z1_F_pc[14] = AMPP_FUNCTION(F1__clk1, Z1L2070, Z1_M_pipe_flush_waddr[14], N1_data_out, !Z1_M_pipe_flush, Z1_F_stall); --Z1L1949 is system_0:u0|cpu_0:the_cpu_0|F_ic_hit~95 Z1L1949 = AMPP_FUNCTION(KC1_q_b[12], KC1_q_b[8], Z1_F_pc[10], Z1_F_pc[14]); --KC1_q_b[14] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[14] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[14] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1_ic_fill_tag[6], Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --KC1_q_b[10] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[10] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[10] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1_ic_fill_tag[2], Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --Z1_F_pc[12] is system_0:u0|cpu_0:the_cpu_0|F_pc[12] Z1_F_pc[12] = AMPP_FUNCTION(F1__clk1, Z1L2073, Z1_M_pipe_flush_waddr[12], N1_data_out, !Z1_M_pipe_flush, Z1_F_stall); --Z1_F_pc[16] is system_0:u0|cpu_0:the_cpu_0|F_pc[16] Z1_F_pc[16] = AMPP_FUNCTION(F1__clk1, Z1L2076, Z1_M_pipe_flush_waddr[16], N1_data_out, !Z1_M_pipe_flush, Z1_F_stall); --Z1L1950 is system_0:u0|cpu_0:the_cpu_0|F_ic_hit~96 Z1L1950 = AMPP_FUNCTION(KC1_q_b[14], KC1_q_b[10], Z1_F_pc[12], Z1_F_pc[16]); --KC1_q_b[19] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[19] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[19] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1_ic_fill_tag[11], Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --KC1_q_b[18] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[18] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[18] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1_ic_fill_tag[10], Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --Z1_F_pc[21] is system_0:u0|cpu_0:the_cpu_0|F_pc[21] Z1_F_pc[21] = AMPP_FUNCTION(F1__clk1, Z1L2079, Z1_M_pipe_flush_waddr[21], N1_data_out, !Z1_M_pipe_flush, Z1_F_stall); --Z1L1951 is system_0:u0|cpu_0:the_cpu_0|F_ic_hit~97 Z1L1951 = AMPP_FUNCTION(KC1_q_b[19], KC1_q_b[18], Z1_F_pc[20], Z1_F_pc[21]); --KC1_q_b[13] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[13] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[13] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1_ic_fill_tag[5], Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --KC1_q_b[9] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[9] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[9] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1_ic_fill_tag[1], Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --Z1_F_pc[11] is system_0:u0|cpu_0:the_cpu_0|F_pc[11] Z1_F_pc[11] = AMPP_FUNCTION(F1__clk1, Z1L2082, Z1_M_pipe_flush_waddr[11], N1_data_out, !Z1_M_pipe_flush, Z1_F_stall); --Z1_F_pc[15] is system_0:u0|cpu_0:the_cpu_0|F_pc[15] Z1_F_pc[15] = AMPP_FUNCTION(F1__clk1, Z1L2085, Z1_M_pipe_flush_waddr[15], N1_data_out, !Z1_M_pipe_flush, Z1_F_stall); --Z1L1952 is system_0:u0|cpu_0:the_cpu_0|F_ic_hit~98 Z1L1952 = AMPP_FUNCTION(KC1_q_b[13], KC1_q_b[9], Z1_F_pc[11], Z1_F_pc[15]); --Z1L1953 is system_0:u0|cpu_0:the_cpu_0|F_ic_hit~99 Z1L1953 = AMPP_FUNCTION(Z1L1949, Z1L1950, Z1L1951, Z1L1952); --KC1_q_b[17] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[17] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[17] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1_ic_fill_tag[9], Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --KC1_q_b[11] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[11] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[11] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1_ic_fill_tag[3], Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --Z1_F_pc[13] is system_0:u0|cpu_0:the_cpu_0|F_pc[13] Z1_F_pc[13] = AMPP_FUNCTION(F1__clk1, Z1L2088, Z1_M_pipe_flush_waddr[13], N1_data_out, !Z1_M_pipe_flush, Z1_F_stall); --Z1_F_pc[19] is system_0:u0|cpu_0:the_cpu_0|F_pc[19] Z1_F_pc[19] = AMPP_FUNCTION(F1__clk1, Z1L2091, Z1_M_pipe_flush_waddr[19], N1_data_out, !Z1_M_pipe_flush, Z1_F_stall); --Z1L1954 is system_0:u0|cpu_0:the_cpu_0|F_ic_hit~100 Z1L1954 = AMPP_FUNCTION(KC1_q_b[17], KC1_q_b[11], Z1_F_pc[13], Z1_F_pc[19]); --KC1_q_b[5] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[5] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[5] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1L3372, Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --Z1_F_pc[0] is system_0:u0|cpu_0:the_cpu_0|F_pc[0] Z1_F_pc[0] = AMPP_FUNCTION(F1__clk1, Z1L1939, N1_data_out, Z1_F_stall); --KC1_q_b[6] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[6] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[6] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1L3373, Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --Z1_F_pc[1] is system_0:u0|cpu_0:the_cpu_0|F_pc[1] Z1_F_pc[1] = AMPP_FUNCTION(F1__clk1, Z1L1943, N1_data_out, Z1_F_stall); --KC1_q_b[4] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[4] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[4] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1L3371, Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --Z1L1986 is system_0:u0|cpu_0:the_cpu_0|F_ic_valid~29 Z1L1986 = AMPP_FUNCTION(Z1_F_pc[0], KC1_q_b[6], Z1_F_pc[1], KC1_q_b[4]); --KC1_q_b[7] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[7] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[7] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1L3374, Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --Z1L1987 is system_0:u0|cpu_0:the_cpu_0|F_ic_valid~30 Z1L1987 = AMPP_FUNCTION(KC1_q_b[5], Z1_F_pc[0], Z1L1986, KC1_q_b[7]); --KC1_q_b[2] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[2] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[2] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1L3369, Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --KC1_q_b[1] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[1] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[1] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1L3368, Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --KC1_q_b[0] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[0] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[0] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1L3367, Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --Z1L1988 is system_0:u0|cpu_0:the_cpu_0|F_ic_valid~31 Z1L1988 = AMPP_FUNCTION(Z1_F_pc[1], KC1_q_b[1], Z1_F_pc[0], KC1_q_b[0]); --KC1_q_b[3] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[3] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[3] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1L3370, Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --Z1L1989 is system_0:u0|cpu_0:the_cpu_0|F_ic_valid~32 Z1L1989 = AMPP_FUNCTION(KC1_q_b[2], Z1_F_pc[1], Z1L1988, KC1_q_b[3]); --Z1_F_pc[2] is system_0:u0|cpu_0:the_cpu_0|F_pc[2] Z1_F_pc[2] = AMPP_FUNCTION(F1__clk1, Z1L1947, N1_data_out, Z1_F_stall); --Z1L1990 is system_0:u0|cpu_0:the_cpu_0|F_ic_valid~33 Z1L1990 = AMPP_FUNCTION(Z1L1987, Z1L1989, Z1_F_pc[2]); --KC1_q_b[16] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[16] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[16] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1_ic_fill_tag[8], Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --KC1_q_b[15] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_n071:auto_generated|q_b[15] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 20, Port B Logical Depth: 128, Port B Logical Width: 20 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered KC1_q_b[15] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, Z1_ic_tag_wren, Z1_F_stall, Z1_ic_fill_tag[7], Z1L3360, Z1L3361, Z1L3362, Z1L3363, Z1L3364, Z1L3365, Z1L3366, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985); --Z1_F_pc[17] is system_0:u0|cpu_0:the_cpu_0|F_pc[17] Z1_F_pc[17] = AMPP_FUNCTION(F1__clk1, Z1L2094, Z1_M_pipe_flush_waddr[17], N1_data_out, !Z1_M_pipe_flush, Z1_F_stall); --Z1_F_pc[18] is system_0:u0|cpu_0:the_cpu_0|F_pc[18] Z1_F_pc[18] = AMPP_FUNCTION(F1__clk1, Z1L2097, Z1_M_pipe_flush_waddr[18], N1_data_out, !Z1_M_pipe_flush, Z1_F_stall); --Z1L1955 is system_0:u0|cpu_0:the_cpu_0|F_ic_hit~101 Z1L1955 = AMPP_FUNCTION(KC1_q_b[16], KC1_q_b[15], Z1_F_pc[17], Z1_F_pc[18]); --Z1_F_ic_hit is system_0:u0|cpu_0:the_cpu_0|F_ic_hit Z1_F_ic_hit = AMPP_FUNCTION(Z1L1953, Z1L1954, Z1L1990, Z1L1955); --Z1_ic_fill_initial_offset[2] is system_0:u0|cpu_0:the_cpu_0|ic_fill_initial_offset[2] Z1_ic_fill_initial_offset[2] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[2], N1_data_out, Z1L1099); --Z1_ic_fill_dp_offset[2] is system_0:u0|cpu_0:the_cpu_0|ic_fill_dp_offset[2] Z1_ic_fill_dp_offset[2] = AMPP_FUNCTION(F1__clk1, Z1L3306, N1_data_out, Z1L3342); --Z1_ic_fill_dp_offset[0] is system_0:u0|cpu_0:the_cpu_0|ic_fill_dp_offset[0] Z1_ic_fill_dp_offset[0] = AMPP_FUNCTION(F1__clk1, Z1L3304, N1_data_out, Z1L3342); --Z1_ic_fill_dp_offset[1] is system_0:u0|cpu_0:the_cpu_0|ic_fill_dp_offset[1] Z1_ic_fill_dp_offset[1] = AMPP_FUNCTION(F1__clk1, Z1L3305, N1_data_out, Z1L3342); --Z1L2805 is system_0:u0|cpu_0:the_cpu_0|add~2942 Z1L2805 = AMPP_FUNCTION(Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1]); --Z1L3306 is system_0:u0|cpu_0:the_cpu_0|ic_fill_dp_offset_nxt[2]~312 Z1L3306 = AMPP_FUNCTION(Z1_D_pc[2], Z1L1099, Z1_ic_fill_dp_offset[2], Z1L2805); --Z1_ic_fill_initial_offset[0] is system_0:u0|cpu_0:the_cpu_0|ic_fill_initial_offset[0] Z1_ic_fill_initial_offset[0] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[0], N1_data_out, Z1L1099); --Z1L3304 is system_0:u0|cpu_0:the_cpu_0|ic_fill_dp_offset_nxt[0]~313 Z1L3304 = AMPP_FUNCTION(Z1_D_pc[0], Z1L1099, Z1_ic_fill_dp_offset[0]); --Z1L3280 is system_0:u0|cpu_0:the_cpu_0|ic_fill_active_nxt~85 Z1L3280 = AMPP_FUNCTION(Z1_ic_fill_initial_offset[2], Z1L3306, Z1_ic_fill_initial_offset[0], Z1L3304); --Z1_ic_fill_initial_offset[1] is system_0:u0|cpu_0:the_cpu_0|ic_fill_initial_offset[1] Z1_ic_fill_initial_offset[1] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[1], N1_data_out, Z1L1099); --Z1L3305 is system_0:u0|cpu_0:the_cpu_0|ic_fill_dp_offset_nxt[1]~314 Z1L3305 = AMPP_FUNCTION(Z1_D_pc[1], Z1L1099, Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1]); --Z1_i_readdatavalid_d1 is system_0:u0|cpu_0:the_cpu_0|i_readdatavalid_d1 Z1_i_readdatavalid_d1 = AMPP_FUNCTION(F1__clk1, BB1L143, N1_data_out); --Z1L3281 is system_0:u0|cpu_0:the_cpu_0|ic_fill_active_nxt~86 Z1L3281 = AMPP_FUNCTION(Z1_ic_fill_initial_offset[1], Z1L3305, Z1_i_readdatavalid_d1); --Z1L3282 is system_0:u0|cpu_0:the_cpu_0|ic_fill_active_nxt~87 Z1L3282 = AMPP_FUNCTION(Z1_ic_fill_active, Z1L3280, Z1L3281, Z1L1099); --Z1_E_valid_from_D is system_0:u0|cpu_0:the_cpu_0|E_valid_from_D Z1_E_valid_from_D = AMPP_FUNCTION(F1__clk1, Z1_D_valid, N1_data_out, Z1_A_stall); --Z1L1890 is system_0:u0|cpu_0:the_cpu_0|E_valid~31 Z1L1890 = AMPP_FUNCTION(Z1_M_pipe_flush, Z1_E_valid_from_D); --Z1_E_ctrl_br_cond is system_0:u0|cpu_0:the_cpu_0|E_ctrl_br_cond Z1_E_ctrl_br_cond = AMPP_FUNCTION(F1__clk1, Z1L1024, N1_data_out, Z1_A_stall); --Z1_E_bht_data[1] is system_0:u0|cpu_0:the_cpu_0|E_bht_data[1] Z1_E_bht_data[1] = AMPP_FUNCTION(F1__clk1, Z1_D_bht_data[1], N1_data_out, Z1_A_stall); --Z1_E_compare_op[1] is system_0:u0|cpu_0:the_cpu_0|E_compare_op[1] Z1_E_compare_op[1] = AMPP_FUNCTION(F1__clk1, Z1L1140, N1_data_out, Z1_A_stall); --Z1_E_src2[31] is system_0:u0|cpu_0:the_cpu_0|E_src2[31] Z1_E_src2[31] = AMPP_FUNCTION(F1__clk1, Z1L1836, Z1L1332, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_ctrl_alu_signed_cmp is system_0:u0|cpu_0:the_cpu_0|E_ctrl_alu_signed_cmp Z1_E_ctrl_alu_signed_cmp = AMPP_FUNCTION(F1__clk1, Z1L1016, N1_data_out, Z1_A_stall); --Z1_E_arith_src2[31] is system_0:u0|cpu_0:the_cpu_0|E_arith_src2[31] Z1_E_arith_src2[31] = AMPP_FUNCTION(Z1_E_src2[31], Z1_E_ctrl_alu_signed_cmp); --Z1_E_src1[31] is system_0:u0|cpu_0:the_cpu_0|E_src1[31] Z1_E_src1[31] = AMPP_FUNCTION(F1__clk1, Z1L1300, N1_data_out, Z1_A_stall); --Z1_E_arith_src1[31] is system_0:u0|cpu_0:the_cpu_0|E_arith_src1[31] Z1_E_arith_src1[31] = AMPP_FUNCTION(Z1_E_src1[31], Z1_E_ctrl_alu_signed_cmp); --Z1_E_src2[30] is system_0:u0|cpu_0:the_cpu_0|E_src2[30] Z1_E_src2[30] = AMPP_FUNCTION(F1__clk1, Z1L1833, Z1L1331, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[30] is system_0:u0|cpu_0:the_cpu_0|E_src1[30] Z1_E_src1[30] = AMPP_FUNCTION(F1__clk1, Z1L1297, N1_data_out, Z1_A_stall); --Z1_E_src2[29] is system_0:u0|cpu_0:the_cpu_0|E_src2[29] Z1_E_src2[29] = AMPP_FUNCTION(F1__clk1, Z1L1830, Z1L1330, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[29] is system_0:u0|cpu_0:the_cpu_0|E_src1[29] Z1_E_src1[29] = AMPP_FUNCTION(F1__clk1, Z1L1294, N1_data_out, Z1_A_stall); --Z1_E_src2[28] is system_0:u0|cpu_0:the_cpu_0|E_src2[28] Z1_E_src2[28] = AMPP_FUNCTION(F1__clk1, Z1L1827, Z1L1329, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[28] is system_0:u0|cpu_0:the_cpu_0|E_src1[28] Z1_E_src1[28] = AMPP_FUNCTION(F1__clk1, Z1L1291, N1_data_out, Z1_A_stall); --Z1_E_src2[27] is system_0:u0|cpu_0:the_cpu_0|E_src2[27] Z1_E_src2[27] = AMPP_FUNCTION(F1__clk1, Z1L1824, Z1L1328, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[27] is system_0:u0|cpu_0:the_cpu_0|E_src1[27] Z1_E_src1[27] = AMPP_FUNCTION(F1__clk1, Z1L1288, N1_data_out, Z1_A_stall); --Z1_E_src2[26] is system_0:u0|cpu_0:the_cpu_0|E_src2[26] Z1_E_src2[26] = AMPP_FUNCTION(F1__clk1, Z1L1821, Z1L1327, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[26] is system_0:u0|cpu_0:the_cpu_0|E_src1[26] Z1_E_src1[26] = AMPP_FUNCTION(F1__clk1, Z1L1285, N1_data_out, Z1_A_stall); --Z1_E_src2[25] is system_0:u0|cpu_0:the_cpu_0|E_src2[25] Z1_E_src2[25] = AMPP_FUNCTION(F1__clk1, Z1L1818, Z1L1326, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[25] is system_0:u0|cpu_0:the_cpu_0|E_src1[25] Z1_E_src1[25] = AMPP_FUNCTION(F1__clk1, Z1L1282, N1_data_out, Z1_A_stall); --Z1_E_src2[24] is system_0:u0|cpu_0:the_cpu_0|E_src2[24] Z1_E_src2[24] = AMPP_FUNCTION(F1__clk1, Z1L1815, Z1L1325, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[24] is system_0:u0|cpu_0:the_cpu_0|E_src1[24] Z1_E_src1[24] = AMPP_FUNCTION(F1__clk1, Z1L1279, N1_data_out, Z1_A_stall); --Z1_E_src2[23] is system_0:u0|cpu_0:the_cpu_0|E_src2[23] Z1_E_src2[23] = AMPP_FUNCTION(F1__clk1, Z1L1812, Z1L1324, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[23] is system_0:u0|cpu_0:the_cpu_0|E_src1[23] Z1_E_src1[23] = AMPP_FUNCTION(F1__clk1, Z1L1276, N1_data_out, Z1_A_stall); --Z1_E_src2[22] is system_0:u0|cpu_0:the_cpu_0|E_src2[22] Z1_E_src2[22] = AMPP_FUNCTION(F1__clk1, Z1L1809, Z1L1323, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[22] is system_0:u0|cpu_0:the_cpu_0|E_src1[22] Z1_E_src1[22] = AMPP_FUNCTION(F1__clk1, Z1L1273, N1_data_out, Z1_A_stall); --Z1_E_src2[21] is system_0:u0|cpu_0:the_cpu_0|E_src2[21] Z1_E_src2[21] = AMPP_FUNCTION(F1__clk1, Z1L1806, Z1L1322, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[21] is system_0:u0|cpu_0:the_cpu_0|E_src1[21] Z1_E_src1[21] = AMPP_FUNCTION(F1__clk1, Z1L1270, N1_data_out, Z1_A_stall); --Z1_E_src2[20] is system_0:u0|cpu_0:the_cpu_0|E_src2[20] Z1_E_src2[20] = AMPP_FUNCTION(F1__clk1, Z1L1803, Z1L1321, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[20] is system_0:u0|cpu_0:the_cpu_0|E_src1[20] Z1_E_src1[20] = AMPP_FUNCTION(F1__clk1, Z1L1267, N1_data_out, Z1_A_stall); --Z1_E_src2[19] is system_0:u0|cpu_0:the_cpu_0|E_src2[19] Z1_E_src2[19] = AMPP_FUNCTION(F1__clk1, Z1L1800, Z1L1320, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[19] is system_0:u0|cpu_0:the_cpu_0|E_src1[19] Z1_E_src1[19] = AMPP_FUNCTION(F1__clk1, Z1L1264, N1_data_out, Z1_A_stall); --Z1_E_src2[18] is system_0:u0|cpu_0:the_cpu_0|E_src2[18] Z1_E_src2[18] = AMPP_FUNCTION(F1__clk1, Z1L1797, Z1L1319, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[18] is system_0:u0|cpu_0:the_cpu_0|E_src1[18] Z1_E_src1[18] = AMPP_FUNCTION(F1__clk1, Z1L1261, N1_data_out, Z1_A_stall); --Z1_E_src2[17] is system_0:u0|cpu_0:the_cpu_0|E_src2[17] Z1_E_src2[17] = AMPP_FUNCTION(F1__clk1, Z1L1794, Z1L1318, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[17] is system_0:u0|cpu_0:the_cpu_0|E_src1[17] Z1_E_src1[17] = AMPP_FUNCTION(F1__clk1, Z1L1258, N1_data_out, Z1_A_stall); --Z1_E_src2[16] is system_0:u0|cpu_0:the_cpu_0|E_src2[16] Z1_E_src2[16] = AMPP_FUNCTION(F1__clk1, Z1L1791, Z1L1317, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[16] is system_0:u0|cpu_0:the_cpu_0|E_src1[16] Z1_E_src1[16] = AMPP_FUNCTION(F1__clk1, Z1L1255, N1_data_out, Z1_A_stall); --Z1_E_src2[15] is system_0:u0|cpu_0:the_cpu_0|E_src2[15] Z1_E_src2[15] = AMPP_FUNCTION(F1__clk1, Z1L1788, Z1L1316, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[15] is system_0:u0|cpu_0:the_cpu_0|E_src1[15] Z1_E_src1[15] = AMPP_FUNCTION(F1__clk1, Z1L1252, N1_data_out, Z1_A_stall); --Z1_E_src2[14] is system_0:u0|cpu_0:the_cpu_0|E_src2[14] Z1_E_src2[14] = AMPP_FUNCTION(F1__clk1, Z1L1785, Z1L1315, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[14] is system_0:u0|cpu_0:the_cpu_0|E_src1[14] Z1_E_src1[14] = AMPP_FUNCTION(F1__clk1, Z1L1249, N1_data_out, Z1_A_stall); --Z1_E_src2[13] is system_0:u0|cpu_0:the_cpu_0|E_src2[13] Z1_E_src2[13] = AMPP_FUNCTION(F1__clk1, Z1L1782, Z1L1314, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[13] is system_0:u0|cpu_0:the_cpu_0|E_src1[13] Z1_E_src1[13] = AMPP_FUNCTION(F1__clk1, Z1L1246, N1_data_out, Z1_A_stall); --Z1_E_src2[12] is system_0:u0|cpu_0:the_cpu_0|E_src2[12] Z1_E_src2[12] = AMPP_FUNCTION(F1__clk1, Z1L1779, Z1L1313, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[12] is system_0:u0|cpu_0:the_cpu_0|E_src1[12] Z1_E_src1[12] = AMPP_FUNCTION(F1__clk1, Z1L1243, N1_data_out, Z1_A_stall); --Z1_E_src2[11] is system_0:u0|cpu_0:the_cpu_0|E_src2[11] Z1_E_src2[11] = AMPP_FUNCTION(F1__clk1, Z1L1776, Z1L1312, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[11] is system_0:u0|cpu_0:the_cpu_0|E_src1[11] Z1_E_src1[11] = AMPP_FUNCTION(F1__clk1, Z1L1240, N1_data_out, Z1_A_stall); --Z1_E_src2[10] is system_0:u0|cpu_0:the_cpu_0|E_src2[10] Z1_E_src2[10] = AMPP_FUNCTION(F1__clk1, Z1L1773, Z1L1311, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[10] is system_0:u0|cpu_0:the_cpu_0|E_src1[10] Z1_E_src1[10] = AMPP_FUNCTION(F1__clk1, Z1L1237, N1_data_out, Z1_A_stall); --Z1_E_src2[9] is system_0:u0|cpu_0:the_cpu_0|E_src2[9] Z1_E_src2[9] = AMPP_FUNCTION(F1__clk1, Z1L1770, Z1L1310, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[9] is system_0:u0|cpu_0:the_cpu_0|E_src1[9] Z1_E_src1[9] = AMPP_FUNCTION(F1__clk1, Z1L1234, N1_data_out, Z1_A_stall); --Z1_E_src2[8] is system_0:u0|cpu_0:the_cpu_0|E_src2[8] Z1_E_src2[8] = AMPP_FUNCTION(F1__clk1, Z1L1767, Z1L1309, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[8] is system_0:u0|cpu_0:the_cpu_0|E_src1[8] Z1_E_src1[8] = AMPP_FUNCTION(F1__clk1, Z1L1231, N1_data_out, Z1_A_stall); --Z1_E_src2[7] is system_0:u0|cpu_0:the_cpu_0|E_src2[7] Z1_E_src2[7] = AMPP_FUNCTION(F1__clk1, Z1L1764, Z1L1308, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[7] is system_0:u0|cpu_0:the_cpu_0|E_src1[7] Z1_E_src1[7] = AMPP_FUNCTION(F1__clk1, Z1L1228, N1_data_out, Z1_A_stall); --Z1_E_src2[6] is system_0:u0|cpu_0:the_cpu_0|E_src2[6] Z1_E_src2[6] = AMPP_FUNCTION(F1__clk1, Z1L1761, Z1L1307, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[6] is system_0:u0|cpu_0:the_cpu_0|E_src1[6] Z1_E_src1[6] = AMPP_FUNCTION(F1__clk1, Z1L1225, N1_data_out, Z1_A_stall); --Z1_E_src2[5] is system_0:u0|cpu_0:the_cpu_0|E_src2[5] Z1_E_src2[5] = AMPP_FUNCTION(F1__clk1, Z1L1758, Z1L1306, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[5] is system_0:u0|cpu_0:the_cpu_0|E_src1[5] Z1_E_src1[5] = AMPP_FUNCTION(F1__clk1, Z1L1222, N1_data_out, Z1_A_stall); --Z1_E_src2[4] is system_0:u0|cpu_0:the_cpu_0|E_src2[4] Z1_E_src2[4] = AMPP_FUNCTION(F1__clk1, Z1L1755, Z1L1305, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[4] is system_0:u0|cpu_0:the_cpu_0|E_src1[4] Z1_E_src1[4] = AMPP_FUNCTION(F1__clk1, Z1L1219, N1_data_out, Z1_A_stall); --Z1_E_src2[3] is system_0:u0|cpu_0:the_cpu_0|E_src2[3] Z1_E_src2[3] = AMPP_FUNCTION(F1__clk1, Z1L1752, Z1L1304, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[3] is system_0:u0|cpu_0:the_cpu_0|E_src1[3] Z1_E_src1[3] = AMPP_FUNCTION(F1__clk1, Z1L1216, N1_data_out, Z1_A_stall); --Z1_E_src2[2] is system_0:u0|cpu_0:the_cpu_0|E_src2[2] Z1_E_src2[2] = AMPP_FUNCTION(F1__clk1, Z1L1749, Z1L1303, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[2] is system_0:u0|cpu_0:the_cpu_0|E_src1[2] Z1_E_src1[2] = AMPP_FUNCTION(F1__clk1, Z1L1213, N1_data_out, Z1_A_stall); --Z1_E_src2[1] is system_0:u0|cpu_0:the_cpu_0|E_src2[1] Z1_E_src2[1] = AMPP_FUNCTION(F1__clk1, Z1L1746, Z1L1302, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[1] is system_0:u0|cpu_0:the_cpu_0|E_src1[1] Z1_E_src1[1] = AMPP_FUNCTION(F1__clk1, Z1L1210, N1_data_out, Z1_A_stall); --Z1_E_src2[0] is system_0:u0|cpu_0:the_cpu_0|E_src2[0] Z1_E_src2[0] = AMPP_FUNCTION(F1__clk1, Z1L1743, Z1L1301, N1_data_out, Z1L1063, Z1_A_stall); --Z1_E_src1[0] is system_0:u0|cpu_0:the_cpu_0|E_src1[0] Z1_E_src1[0] = AMPP_FUNCTION(F1__clk1, Z1L1706, Z1L1207, N1_data_out, Z1_D_src1_hazard_E, Z1_A_stall); --Z1L2806 is system_0:u0|cpu_0:the_cpu_0|add~2943 Z1L2806 = AMPP_FUNCTION(Z1_E_src2[0], Z1_E_src1[0], GND); --Z1L2807 is system_0:u0|cpu_0:the_cpu_0|add~2944 Z1L2807 = AMPP_FUNCTION(Z1_E_src2[0], Z1_E_src1[0]); --Z1L2808 is system_0:u0|cpu_0:the_cpu_0|add~2945 Z1L2808 = AMPP_FUNCTION(Z1_E_src2[1], Z1_E_src1[1], GND, Z1L2807); --Z1L2809 is system_0:u0|cpu_0:the_cpu_0|add~2946 Z1L2809 = AMPP_FUNCTION(Z1_E_src2[1], Z1_E_src1[1], Z1L2807); --Z1L2810 is system_0:u0|cpu_0:the_cpu_0|add~2947 Z1L2810 = AMPP_FUNCTION(Z1_E_src2[2], Z1_E_src1[2], GND, Z1L2809); --Z1L2811 is system_0:u0|cpu_0:the_cpu_0|add~2948 Z1L2811 = AMPP_FUNCTION(Z1_E_src2[2], Z1_E_src1[2], Z1L2809); --Z1L2812 is system_0:u0|cpu_0:the_cpu_0|add~2949 Z1L2812 = AMPP_FUNCTION(Z1_E_src2[3], Z1_E_src1[3], GND, Z1L2811); --Z1L2813 is system_0:u0|cpu_0:the_cpu_0|add~2950 Z1L2813 = AMPP_FUNCTION(Z1_E_src2[3], Z1_E_src1[3], Z1L2811); --Z1L2814 is system_0:u0|cpu_0:the_cpu_0|add~2951 Z1L2814 = AMPP_FUNCTION(Z1_E_src2[4], Z1_E_src1[4], GND, Z1L2813); --Z1L2815 is system_0:u0|cpu_0:the_cpu_0|add~2952 Z1L2815 = AMPP_FUNCTION(Z1_E_src2[4], Z1_E_src1[4], Z1L2813); --Z1L2816 is system_0:u0|cpu_0:the_cpu_0|add~2953 Z1L2816 = AMPP_FUNCTION(Z1_E_src2[5], Z1_E_src1[5], GND, Z1L2815); --Z1L2817 is system_0:u0|cpu_0:the_cpu_0|add~2954 Z1L2817 = AMPP_FUNCTION(Z1_E_src2[5], Z1_E_src1[5], Z1L2815); --Z1L2818 is system_0:u0|cpu_0:the_cpu_0|add~2955 Z1L2818 = AMPP_FUNCTION(Z1_E_src2[6], Z1_E_src1[6], GND, Z1L2817); --Z1L2819 is system_0:u0|cpu_0:the_cpu_0|add~2956 Z1L2819 = AMPP_FUNCTION(Z1_E_src2[6], Z1_E_src1[6], Z1L2817); --Z1L2820 is system_0:u0|cpu_0:the_cpu_0|add~2957 Z1L2820 = AMPP_FUNCTION(Z1_E_src2[7], Z1_E_src1[7], GND, Z1L2819); --Z1L2821 is system_0:u0|cpu_0:the_cpu_0|add~2958 Z1L2821 = AMPP_FUNCTION(Z1_E_src2[7], Z1_E_src1[7], Z1L2819); --Z1L2822 is system_0:u0|cpu_0:the_cpu_0|add~2959 Z1L2822 = AMPP_FUNCTION(Z1_E_src2[8], Z1_E_src1[8], GND, Z1L2821); --Z1L2823 is system_0:u0|cpu_0:the_cpu_0|add~2960 Z1L2823 = AMPP_FUNCTION(Z1_E_src2[8], Z1_E_src1[8], Z1L2821); --Z1L2824 is system_0:u0|cpu_0:the_cpu_0|add~2961 Z1L2824 = AMPP_FUNCTION(Z1_E_src2[9], Z1_E_src1[9], GND, Z1L2823); --Z1L2825 is system_0:u0|cpu_0:the_cpu_0|add~2962 Z1L2825 = AMPP_FUNCTION(Z1_E_src2[9], Z1_E_src1[9], Z1L2823); --Z1L2826 is system_0:u0|cpu_0:the_cpu_0|add~2963 Z1L2826 = AMPP_FUNCTION(Z1_E_src2[10], Z1_E_src1[10], GND, Z1L2825); --Z1L2827 is system_0:u0|cpu_0:the_cpu_0|add~2964 Z1L2827 = AMPP_FUNCTION(Z1_E_src2[10], Z1_E_src1[10], Z1L2825); --Z1L2828 is system_0:u0|cpu_0:the_cpu_0|add~2965 Z1L2828 = AMPP_FUNCTION(Z1_E_src2[11], Z1_E_src1[11], GND, Z1L2827); --Z1L2829 is system_0:u0|cpu_0:the_cpu_0|add~2966 Z1L2829 = AMPP_FUNCTION(Z1_E_src2[11], Z1_E_src1[11], Z1L2827); --Z1L2830 is system_0:u0|cpu_0:the_cpu_0|add~2967 Z1L2830 = AMPP_FUNCTION(Z1_E_src2[12], Z1_E_src1[12], GND, Z1L2829); --Z1L2831 is system_0:u0|cpu_0:the_cpu_0|add~2968 Z1L2831 = AMPP_FUNCTION(Z1_E_src2[12], Z1_E_src1[12], Z1L2829); --Z1L2832 is system_0:u0|cpu_0:the_cpu_0|add~2969 Z1L2832 = AMPP_FUNCTION(Z1_E_src2[13], Z1_E_src1[13], GND, Z1L2831); --Z1L2833 is system_0:u0|cpu_0:the_cpu_0|add~2970 Z1L2833 = AMPP_FUNCTION(Z1_E_src2[13], Z1_E_src1[13], Z1L2831); --Z1L2834 is system_0:u0|cpu_0:the_cpu_0|add~2971 Z1L2834 = AMPP_FUNCTION(Z1_E_src2[14], Z1_E_src1[14], GND, Z1L2833); --Z1L2835 is system_0:u0|cpu_0:the_cpu_0|add~2972 Z1L2835 = AMPP_FUNCTION(Z1_E_src2[14], Z1_E_src1[14], Z1L2833); --Z1L2836 is system_0:u0|cpu_0:the_cpu_0|add~2973 Z1L2836 = AMPP_FUNCTION(Z1_E_src2[15], Z1_E_src1[15], GND, Z1L2835); --Z1L2837 is system_0:u0|cpu_0:the_cpu_0|add~2974 Z1L2837 = AMPP_FUNCTION(Z1_E_src2[15], Z1_E_src1[15], Z1L2835); --Z1L2838 is system_0:u0|cpu_0:the_cpu_0|add~2975 Z1L2838 = AMPP_FUNCTION(Z1_E_src2[16], Z1_E_src1[16], GND, Z1L2837); --Z1L2839 is system_0:u0|cpu_0:the_cpu_0|add~2976 Z1L2839 = AMPP_FUNCTION(Z1_E_src2[16], Z1_E_src1[16], Z1L2837); --Z1L2840 is system_0:u0|cpu_0:the_cpu_0|add~2977 Z1L2840 = AMPP_FUNCTION(Z1_E_src2[17], Z1_E_src1[17], GND, Z1L2839); --Z1L2841 is system_0:u0|cpu_0:the_cpu_0|add~2978 Z1L2841 = AMPP_FUNCTION(Z1_E_src2[17], Z1_E_src1[17], Z1L2839); --Z1L2842 is system_0:u0|cpu_0:the_cpu_0|add~2979 Z1L2842 = AMPP_FUNCTION(Z1_E_src2[18], Z1_E_src1[18], GND, Z1L2841); --Z1L2843 is system_0:u0|cpu_0:the_cpu_0|add~2980 Z1L2843 = AMPP_FUNCTION(Z1_E_src2[18], Z1_E_src1[18], Z1L2841); --Z1L2844 is system_0:u0|cpu_0:the_cpu_0|add~2981 Z1L2844 = AMPP_FUNCTION(Z1_E_src2[19], Z1_E_src1[19], GND, Z1L2843); --Z1L2845 is system_0:u0|cpu_0:the_cpu_0|add~2982 Z1L2845 = AMPP_FUNCTION(Z1_E_src2[19], Z1_E_src1[19], Z1L2843); --Z1L2846 is system_0:u0|cpu_0:the_cpu_0|add~2983 Z1L2846 = AMPP_FUNCTION(Z1_E_src2[20], Z1_E_src1[20], GND, Z1L2845); --Z1L2847 is system_0:u0|cpu_0:the_cpu_0|add~2984 Z1L2847 = AMPP_FUNCTION(Z1_E_src2[20], Z1_E_src1[20], Z1L2845); --Z1L2848 is system_0:u0|cpu_0:the_cpu_0|add~2985 Z1L2848 = AMPP_FUNCTION(Z1_E_src2[21], Z1_E_src1[21], GND, Z1L2847); --Z1L2849 is system_0:u0|cpu_0:the_cpu_0|add~2986 Z1L2849 = AMPP_FUNCTION(Z1_E_src2[21], Z1_E_src1[21], Z1L2847); --Z1L2850 is system_0:u0|cpu_0:the_cpu_0|add~2987 Z1L2850 = AMPP_FUNCTION(Z1_E_src2[22], Z1_E_src1[22], GND, Z1L2849); --Z1L2851 is system_0:u0|cpu_0:the_cpu_0|add~2988 Z1L2851 = AMPP_FUNCTION(Z1_E_src2[22], Z1_E_src1[22], Z1L2849); --Z1L2852 is system_0:u0|cpu_0:the_cpu_0|add~2989 Z1L2852 = AMPP_FUNCTION(Z1_E_src2[23], Z1_E_src1[23], GND, Z1L2851); --Z1L2853 is system_0:u0|cpu_0:the_cpu_0|add~2990 Z1L2853 = AMPP_FUNCTION(Z1_E_src2[23], Z1_E_src1[23], Z1L2851); --Z1L2854 is system_0:u0|cpu_0:the_cpu_0|add~2991 Z1L2854 = AMPP_FUNCTION(Z1_E_src2[24], Z1_E_src1[24], GND, Z1L2853); --Z1L2855 is system_0:u0|cpu_0:the_cpu_0|add~2992 Z1L2855 = AMPP_FUNCTION(Z1_E_src2[24], Z1_E_src1[24], Z1L2853); --Z1L2856 is system_0:u0|cpu_0:the_cpu_0|add~2993 Z1L2856 = AMPP_FUNCTION(Z1_E_src2[25], Z1_E_src1[25], GND, Z1L2855); --Z1L2857 is system_0:u0|cpu_0:the_cpu_0|add~2994 Z1L2857 = AMPP_FUNCTION(Z1_E_src2[25], Z1_E_src1[25], Z1L2855); --Z1L2858 is system_0:u0|cpu_0:the_cpu_0|add~2995 Z1L2858 = AMPP_FUNCTION(Z1_E_src2[26], Z1_E_src1[26], GND, Z1L2857); --Z1L2859 is system_0:u0|cpu_0:the_cpu_0|add~2996 Z1L2859 = AMPP_FUNCTION(Z1_E_src2[26], Z1_E_src1[26], Z1L2857); --Z1L2860 is system_0:u0|cpu_0:the_cpu_0|add~2997 Z1L2860 = AMPP_FUNCTION(Z1_E_src2[27], Z1_E_src1[27], GND, Z1L2859); --Z1L2861 is system_0:u0|cpu_0:the_cpu_0|add~2998 Z1L2861 = AMPP_FUNCTION(Z1_E_src2[27], Z1_E_src1[27], Z1L2859); --Z1L2862 is system_0:u0|cpu_0:the_cpu_0|add~2999 Z1L2862 = AMPP_FUNCTION(Z1_E_src2[28], Z1_E_src1[28], GND, Z1L2861); --Z1L2863 is system_0:u0|cpu_0:the_cpu_0|add~3000 Z1L2863 = AMPP_FUNCTION(Z1_E_src2[28], Z1_E_src1[28], Z1L2861); --Z1L2864 is system_0:u0|cpu_0:the_cpu_0|add~3001 Z1L2864 = AMPP_FUNCTION(Z1_E_src2[29], Z1_E_src1[29], GND, Z1L2863); --Z1L2865 is system_0:u0|cpu_0:the_cpu_0|add~3002 Z1L2865 = AMPP_FUNCTION(Z1_E_src2[29], Z1_E_src1[29], Z1L2863); --Z1L2866 is system_0:u0|cpu_0:the_cpu_0|add~3003 Z1L2866 = AMPP_FUNCTION(Z1_E_src2[30], Z1_E_src1[30], GND, Z1L2865); --Z1L2867 is system_0:u0|cpu_0:the_cpu_0|add~3004 Z1L2867 = AMPP_FUNCTION(Z1_E_src2[30], Z1_E_src1[30], Z1L2865); --Z1L2868 is system_0:u0|cpu_0:the_cpu_0|add~3005 Z1L2868 = AMPP_FUNCTION(Z1_E_arith_src2[31], Z1_E_arith_src1[31], GND, Z1L2867); --Z1L2869 is system_0:u0|cpu_0:the_cpu_0|add~3006 Z1L2869 = AMPP_FUNCTION(Z1_E_arith_src2[31], Z1_E_arith_src1[31], Z1L2867); --Z1L2870 is system_0:u0|cpu_0:the_cpu_0|add~3007 Z1L2870 = AMPP_FUNCTION(Z1L2869); --Z1L2872 is system_0:u0|cpu_0:the_cpu_0|add~3009 Z1L2872 = AMPP_FUNCTION(Z1_E_src2[0], Z1_E_src1[0], GND); --Z1L2873 is system_0:u0|cpu_0:the_cpu_0|add~3010 Z1L2873 = AMPP_FUNCTION(Z1_E_src2[0], Z1_E_src1[0]); --Z1L2874 is system_0:u0|cpu_0:the_cpu_0|add~3011 Z1L2874 = AMPP_FUNCTION(Z1_E_src2[1], Z1_E_src1[1], GND, Z1L2873); --Z1L2875 is system_0:u0|cpu_0:the_cpu_0|add~3012 Z1L2875 = AMPP_FUNCTION(Z1_E_src2[1], Z1_E_src1[1], Z1L2873); --Z1L2876 is system_0:u0|cpu_0:the_cpu_0|add~3013 Z1L2876 = AMPP_FUNCTION(Z1_E_src2[2], Z1_E_src1[2], GND, Z1L2875); --Z1L2877 is system_0:u0|cpu_0:the_cpu_0|add~3014 Z1L2877 = AMPP_FUNCTION(Z1_E_src2[2], Z1_E_src1[2], Z1L2875); --Z1L2878 is system_0:u0|cpu_0:the_cpu_0|add~3015 Z1L2878 = AMPP_FUNCTION(Z1_E_src2[3], Z1_E_src1[3], GND, Z1L2877); --Z1L2879 is system_0:u0|cpu_0:the_cpu_0|add~3016 Z1L2879 = AMPP_FUNCTION(Z1_E_src2[3], Z1_E_src1[3], Z1L2877); --Z1L2880 is system_0:u0|cpu_0:the_cpu_0|add~3017 Z1L2880 = AMPP_FUNCTION(Z1_E_src2[4], Z1_E_src1[4], GND, Z1L2879); --Z1L2881 is system_0:u0|cpu_0:the_cpu_0|add~3018 Z1L2881 = AMPP_FUNCTION(Z1_E_src2[4], Z1_E_src1[4], Z1L2879); --Z1L2882 is system_0:u0|cpu_0:the_cpu_0|add~3019 Z1L2882 = AMPP_FUNCTION(Z1_E_src2[5], Z1_E_src1[5], GND, Z1L2881); --Z1L2883 is system_0:u0|cpu_0:the_cpu_0|add~3020 Z1L2883 = AMPP_FUNCTION(Z1_E_src2[5], Z1_E_src1[5], Z1L2881); --Z1L2884 is system_0:u0|cpu_0:the_cpu_0|add~3021 Z1L2884 = AMPP_FUNCTION(Z1_E_src2[6], Z1_E_src1[6], GND, Z1L2883); --Z1L2885 is system_0:u0|cpu_0:the_cpu_0|add~3022 Z1L2885 = AMPP_FUNCTION(Z1_E_src2[6], Z1_E_src1[6], Z1L2883); --Z1L2886 is system_0:u0|cpu_0:the_cpu_0|add~3023 Z1L2886 = AMPP_FUNCTION(Z1_E_src2[7], Z1_E_src1[7], GND, Z1L2885); --Z1L2887 is system_0:u0|cpu_0:the_cpu_0|add~3024 Z1L2887 = AMPP_FUNCTION(Z1_E_src2[7], Z1_E_src1[7], Z1L2885); --Z1L2888 is system_0:u0|cpu_0:the_cpu_0|add~3025 Z1L2888 = AMPP_FUNCTION(Z1_E_src2[8], Z1_E_src1[8], GND, Z1L2887); --Z1L2889 is system_0:u0|cpu_0:the_cpu_0|add~3026 Z1L2889 = AMPP_FUNCTION(Z1_E_src2[8], Z1_E_src1[8], Z1L2887); --Z1L2890 is system_0:u0|cpu_0:the_cpu_0|add~3027 Z1L2890 = AMPP_FUNCTION(Z1_E_src2[9], Z1_E_src1[9], GND, Z1L2889); --Z1L2891 is system_0:u0|cpu_0:the_cpu_0|add~3028 Z1L2891 = AMPP_FUNCTION(Z1_E_src2[9], Z1_E_src1[9], Z1L2889); --Z1L2892 is system_0:u0|cpu_0:the_cpu_0|add~3029 Z1L2892 = AMPP_FUNCTION(Z1_E_src2[10], Z1_E_src1[10], GND, Z1L2891); --Z1L2893 is system_0:u0|cpu_0:the_cpu_0|add~3030 Z1L2893 = AMPP_FUNCTION(Z1_E_src2[10], Z1_E_src1[10], Z1L2891); --Z1L2894 is system_0:u0|cpu_0:the_cpu_0|add~3031 Z1L2894 = AMPP_FUNCTION(Z1_E_src2[11], Z1_E_src1[11], GND, Z1L2893); --Z1L2895 is system_0:u0|cpu_0:the_cpu_0|add~3032 Z1L2895 = AMPP_FUNCTION(Z1_E_src2[11], Z1_E_src1[11], Z1L2893); --Z1L2896 is system_0:u0|cpu_0:the_cpu_0|add~3033 Z1L2896 = AMPP_FUNCTION(Z1_E_src2[12], Z1_E_src1[12], GND, Z1L2895); --Z1L2897 is system_0:u0|cpu_0:the_cpu_0|add~3034 Z1L2897 = AMPP_FUNCTION(Z1_E_src2[12], Z1_E_src1[12], Z1L2895); --Z1L2898 is system_0:u0|cpu_0:the_cpu_0|add~3035 Z1L2898 = AMPP_FUNCTION(Z1_E_src2[13], Z1_E_src1[13], GND, Z1L2897); --Z1L2899 is system_0:u0|cpu_0:the_cpu_0|add~3036 Z1L2899 = AMPP_FUNCTION(Z1_E_src2[13], Z1_E_src1[13], Z1L2897); --Z1L2900 is system_0:u0|cpu_0:the_cpu_0|add~3037 Z1L2900 = AMPP_FUNCTION(Z1_E_src2[14], Z1_E_src1[14], GND, Z1L2899); --Z1L2901 is system_0:u0|cpu_0:the_cpu_0|add~3038 Z1L2901 = AMPP_FUNCTION(Z1_E_src2[14], Z1_E_src1[14], Z1L2899); --Z1L2902 is system_0:u0|cpu_0:the_cpu_0|add~3039 Z1L2902 = AMPP_FUNCTION(Z1_E_src2[15], Z1_E_src1[15], GND, Z1L2901); --Z1L2903 is system_0:u0|cpu_0:the_cpu_0|add~3040 Z1L2903 = AMPP_FUNCTION(Z1_E_src2[15], Z1_E_src1[15], Z1L2901); --Z1L2904 is system_0:u0|cpu_0:the_cpu_0|add~3041 Z1L2904 = AMPP_FUNCTION(Z1_E_src2[16], Z1_E_src1[16], GND, Z1L2903); --Z1L2905 is system_0:u0|cpu_0:the_cpu_0|add~3042 Z1L2905 = AMPP_FUNCTION(Z1_E_src2[16], Z1_E_src1[16], Z1L2903); --Z1L2906 is system_0:u0|cpu_0:the_cpu_0|add~3043 Z1L2906 = AMPP_FUNCTION(Z1_E_src2[17], Z1_E_src1[17], GND, Z1L2905); --Z1L2907 is system_0:u0|cpu_0:the_cpu_0|add~3044 Z1L2907 = AMPP_FUNCTION(Z1_E_src2[17], Z1_E_src1[17], Z1L2905); --Z1L2908 is system_0:u0|cpu_0:the_cpu_0|add~3045 Z1L2908 = AMPP_FUNCTION(Z1_E_src2[18], Z1_E_src1[18], GND, Z1L2907); --Z1L2909 is system_0:u0|cpu_0:the_cpu_0|add~3046 Z1L2909 = AMPP_FUNCTION(Z1_E_src2[18], Z1_E_src1[18], Z1L2907); --Z1L2910 is system_0:u0|cpu_0:the_cpu_0|add~3047 Z1L2910 = AMPP_FUNCTION(Z1_E_src2[19], Z1_E_src1[19], GND, Z1L2909); --Z1L2911 is system_0:u0|cpu_0:the_cpu_0|add~3048 Z1L2911 = AMPP_FUNCTION(Z1_E_src2[19], Z1_E_src1[19], Z1L2909); --Z1L2912 is system_0:u0|cpu_0:the_cpu_0|add~3049 Z1L2912 = AMPP_FUNCTION(Z1_E_src2[20], Z1_E_src1[20], GND, Z1L2911); --Z1L2913 is system_0:u0|cpu_0:the_cpu_0|add~3050 Z1L2913 = AMPP_FUNCTION(Z1_E_src2[20], Z1_E_src1[20], Z1L2911); --Z1L2914 is system_0:u0|cpu_0:the_cpu_0|add~3051 Z1L2914 = AMPP_FUNCTION(Z1_E_src2[21], Z1_E_src1[21], GND, Z1L2913); --Z1L2915 is system_0:u0|cpu_0:the_cpu_0|add~3052 Z1L2915 = AMPP_FUNCTION(Z1_E_src2[21], Z1_E_src1[21], Z1L2913); --Z1L2916 is system_0:u0|cpu_0:the_cpu_0|add~3053 Z1L2916 = AMPP_FUNCTION(Z1_E_src2[22], Z1_E_src1[22], GND, Z1L2915); --Z1L2917 is system_0:u0|cpu_0:the_cpu_0|add~3054 Z1L2917 = AMPP_FUNCTION(Z1_E_src2[22], Z1_E_src1[22], Z1L2915); --Z1L2918 is system_0:u0|cpu_0:the_cpu_0|add~3055 Z1L2918 = AMPP_FUNCTION(Z1_E_src2[23], Z1_E_src1[23], GND, Z1L2917); --Z1L2919 is system_0:u0|cpu_0:the_cpu_0|add~3056 Z1L2919 = AMPP_FUNCTION(Z1_E_src2[23], Z1_E_src1[23], Z1L2917); --Z1L2920 is system_0:u0|cpu_0:the_cpu_0|add~3057 Z1L2920 = AMPP_FUNCTION(Z1_E_src2[24], Z1_E_src1[24], GND, Z1L2919); --Z1L2921 is system_0:u0|cpu_0:the_cpu_0|add~3058 Z1L2921 = AMPP_FUNCTION(Z1_E_src2[24], Z1_E_src1[24], Z1L2919); --Z1L2922 is system_0:u0|cpu_0:the_cpu_0|add~3059 Z1L2922 = AMPP_FUNCTION(Z1_E_src2[25], Z1_E_src1[25], GND, Z1L2921); --Z1L2923 is system_0:u0|cpu_0:the_cpu_0|add~3060 Z1L2923 = AMPP_FUNCTION(Z1_E_src2[25], Z1_E_src1[25], Z1L2921); --Z1L2924 is system_0:u0|cpu_0:the_cpu_0|add~3061 Z1L2924 = AMPP_FUNCTION(Z1_E_src2[26], Z1_E_src1[26], GND, Z1L2923); --Z1L2925 is system_0:u0|cpu_0:the_cpu_0|add~3062 Z1L2925 = AMPP_FUNCTION(Z1_E_src2[26], Z1_E_src1[26], Z1L2923); --Z1L2926 is system_0:u0|cpu_0:the_cpu_0|add~3063 Z1L2926 = AMPP_FUNCTION(Z1_E_src2[27], Z1_E_src1[27], GND, Z1L2925); --Z1L2927 is system_0:u0|cpu_0:the_cpu_0|add~3064 Z1L2927 = AMPP_FUNCTION(Z1_E_src2[27], Z1_E_src1[27], Z1L2925); --Z1L2928 is system_0:u0|cpu_0:the_cpu_0|add~3065 Z1L2928 = AMPP_FUNCTION(Z1_E_src2[28], Z1_E_src1[28], GND, Z1L2927); --Z1L2929 is system_0:u0|cpu_0:the_cpu_0|add~3066 Z1L2929 = AMPP_FUNCTION(Z1_E_src2[28], Z1_E_src1[28], Z1L2927); --Z1L2930 is system_0:u0|cpu_0:the_cpu_0|add~3067 Z1L2930 = AMPP_FUNCTION(Z1_E_src2[29], Z1_E_src1[29], GND, Z1L2929); --Z1L2931 is system_0:u0|cpu_0:the_cpu_0|add~3068 Z1L2931 = AMPP_FUNCTION(Z1_E_src2[29], Z1_E_src1[29], Z1L2929); --Z1L2932 is system_0:u0|cpu_0:the_cpu_0|add~3069 Z1L2932 = AMPP_FUNCTION(Z1_E_src2[30], Z1_E_src1[30], GND, Z1L2931); --Z1L2933 is system_0:u0|cpu_0:the_cpu_0|add~3070 Z1L2933 = AMPP_FUNCTION(Z1_E_src2[30], Z1_E_src1[30], Z1L2931); --Z1L2934 is system_0:u0|cpu_0:the_cpu_0|add~3071 Z1L2934 = AMPP_FUNCTION(Z1_E_arith_src2[31], Z1_E_arith_src1[31], GND, Z1L2933); --Z1L2935 is system_0:u0|cpu_0:the_cpu_0|add~3072 Z1L2935 = AMPP_FUNCTION(Z1_E_arith_src2[31], Z1_E_arith_src1[31], Z1L2933); --Z1L2936 is system_0:u0|cpu_0:the_cpu_0|add~3073 Z1L2936 = AMPP_FUNCTION(Z1L2935); --Z1_E_ctrl_alu_subtract is system_0:u0|cpu_0:the_cpu_0|E_ctrl_alu_subtract Z1_E_ctrl_alu_subtract = AMPP_FUNCTION(F1__clk1, Z1L1020, N1_data_out, Z1_A_stall); --Z1L1484 is system_0:u0|cpu_0:the_cpu_0|E_arith_result[32]~66 Z1L1484 = AMPP_FUNCTION(Z1L2870, Z1L2936, Z1_E_ctrl_alu_subtract); --Z1_E_logic_op[1] is system_0:u0|cpu_0:the_cpu_0|E_logic_op[1] Z1_E_logic_op[1] = AMPP_FUNCTION(F1__clk1, Z1L1138, N1_data_out, Z1_A_stall); --Z1_E_logic_op[0] is system_0:u0|cpu_0:the_cpu_0|E_logic_op[0] Z1_E_logic_op[0] = AMPP_FUNCTION(F1__clk1, Z1L1137, N1_data_out, Z1_A_stall); --Z1L1630 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[17]~8407 Z1L1630 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[17], Z1_E_src1[17], Z1_E_logic_op[0]); --Z1L1629 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[16]~8408 Z1L1629 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[16], Z1_E_src1[16], Z1_E_logic_op[0]); --Z1L1614 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[1]~8409 Z1L1614 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[1], Z1_E_src1[1], Z1_E_logic_op[0]); --Z1L1634 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[21]~8410 Z1L1634 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[21], Z1_E_src1[21], Z1_E_logic_op[0]); --BC1L1 is system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|E_src1_eq_src2~849 BC1L1 = AMPP_FUNCTION(Z1L1630, Z1L1629, Z1L1614, Z1L1634); --Z1L1633 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[20]~8411 Z1L1633 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[20], Z1_E_src1[20], Z1_E_logic_op[0]); --Z1L1622 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[9]~8412 Z1L1622 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[9], Z1_E_src1[9], Z1_E_logic_op[0]); --Z1L1623 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[10]~8413 Z1L1623 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[10], Z1_E_src1[10], Z1_E_logic_op[0]); --Z1L1617 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[4]~8414 Z1L1617 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[4], Z1_E_src1[4], Z1_E_logic_op[0]); --BC1L2 is system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|E_src1_eq_src2~850 BC1L2 = AMPP_FUNCTION(Z1L1633, Z1L1622, Z1L1623, Z1L1617); --Z1L1636 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[23]~8415 Z1L1636 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[23], Z1_E_src1[23], Z1_E_logic_op[0]); --Z1L1635 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[22]~8416 Z1L1635 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[22], Z1_E_src1[22], Z1_E_logic_op[0]); --Z1L1626 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[13]~8417 Z1L1626 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[13], Z1_E_src1[13], Z1_E_logic_op[0]); --Z1L1640 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[27]~8418 Z1L1640 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[27], Z1_E_src1[27], Z1_E_logic_op[0]); --BC1L3 is system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|E_src1_eq_src2~851 BC1L3 = AMPP_FUNCTION(Z1L1636, Z1L1635, Z1L1626, Z1L1640); --Z1L1637 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[24]~8419 Z1L1637 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[24], Z1_E_src1[24], Z1_E_logic_op[0]); --Z1L1624 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[11]~8420 Z1L1624 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[11], Z1_E_src1[11], Z1_E_logic_op[0]); --Z1L1639 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[26]~8421 Z1L1639 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[26], Z1_E_src1[26], Z1_E_logic_op[0]); --Z1L1625 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[12]~8422 Z1L1625 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[12], Z1_E_src1[12], Z1_E_logic_op[0]); --BC1L4 is system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|E_src1_eq_src2~852 BC1L4 = AMPP_FUNCTION(Z1L1637, Z1L1624, Z1L1639, Z1L1625); --BC1L5 is system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|E_src1_eq_src2~853 BC1L5 = AMPP_FUNCTION(BC1L1, BC1L2, BC1L3, BC1L4); --Z1L1618 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[5]~8423 Z1L1618 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[5], Z1_E_src1[5], Z1_E_logic_op[0]); --Z1L1638 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[25]~8424 Z1L1638 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[25], Z1_E_src1[25], Z1_E_logic_op[0]); --BC1L6 is system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|E_src1_eq_src2~854 BC1L6 = AMPP_FUNCTION(Z1L1618, Z1L1638); --Z1L1632 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[19]~8425 Z1L1632 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[19], Z1_E_src1[19], Z1_E_logic_op[0]); --Z1L1631 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[18]~8426 Z1L1631 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[18], Z1_E_src1[18], Z1_E_logic_op[0]); --Z1L1621 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[8]~8427 Z1L1621 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[8], Z1_E_src1[8], Z1_E_logic_op[0]); --Z1L1616 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[3]~8428 Z1L1616 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[3], Z1_E_src1[3], Z1_E_logic_op[0]); --BC1L7 is system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|E_src1_eq_src2~855 BC1L7 = AMPP_FUNCTION(Z1L1632, Z1L1631, Z1L1621, Z1L1616); --Z1L1628 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[15]~8429 Z1L1628 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[15], Z1_E_src1[15], Z1_E_logic_op[0]); --Z1L1641 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[28]~8430 Z1L1641 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[28], Z1_E_src1[28], Z1_E_logic_op[0]); --BC1L8 is system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|E_src1_eq_src2~856 BC1L8 = AMPP_FUNCTION(BC1L6, BC1L7, Z1L1628, Z1L1641); --Z1L1620 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[7]~8431 Z1L1620 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[7], Z1_E_src1[7], Z1_E_logic_op[0]); --Z1L1644 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[31]~8432 Z1L1644 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[31], Z1_E_src1[31], Z1_E_logic_op[0]); --Z1L1619 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[6]~8433 Z1L1619 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[6], Z1_E_src1[6], Z1_E_logic_op[0]); --Z1L1615 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[2]~8434 Z1L1615 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[2], Z1_E_src1[2], Z1_E_logic_op[0]); --BC1L9 is system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|E_src1_eq_src2~857 BC1L9 = AMPP_FUNCTION(Z1L1620, Z1L1644, Z1L1619, Z1L1615); --Z1L1612 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[0]~8435 Z1L1612 = AMPP_FUNCTION(Z1_E_src2[0], Z1_E_src1[0], Z1_E_logic_op[0]); --Z1L1613 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[0]~8436 Z1L1613 = AMPP_FUNCTION(Z1L2872, Z1_E_logic_op[1], Z1_E_logic_op[0], Z1L1612); --Z1L1642 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[29]~8437 Z1L1642 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[29], Z1_E_src1[29], Z1_E_logic_op[0]); --Z1L1643 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[30]~8438 Z1L1643 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[30], Z1_E_src1[30], Z1_E_logic_op[0]); --Z1L1627 is system_0:u0|cpu_0:the_cpu_0|E_logic_result[14]~8439 Z1L1627 = AMPP_FUNCTION(Z1_E_logic_op[1], Z1_E_src2[14], Z1_E_src1[14], Z1_E_logic_op[0]); --BC1L10 is system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|E_src1_eq_src2~858 BC1L10 = AMPP_FUNCTION(Z1L1613, Z1L1642, Z1L1643, Z1L1627); --BC1L11 is system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|E_src1_eq_src2~859 BC1L11 = AMPP_FUNCTION(BC1L5, BC1L8, BC1L9, BC1L10); --Z1_E_compare_op[0] is system_0:u0|cpu_0:the_cpu_0|E_compare_op[0] Z1_E_compare_op[0] = AMPP_FUNCTION(F1__clk1, Z1L1139, N1_data_out, Z1_A_stall); --Z1L1501 is system_0:u0|cpu_0:the_cpu_0|E_br_actually_taken~265 Z1L1501 = AMPP_FUNCTION(Z1_E_compare_op[1], Z1L1484, BC1L11, Z1_E_compare_op[0]); --Z1_E_br_mispredict is system_0:u0|cpu_0:the_cpu_0|E_br_mispredict Z1_E_br_mispredict = AMPP_FUNCTION(Z1_E_ctrl_br_cond, Z1_E_bht_data[1], Z1L1501); --Z1_E_ctrl_flush_pipe_always is system_0:u0|cpu_0:the_cpu_0|E_ctrl_flush_pipe_always Z1_E_ctrl_flush_pipe_always = AMPP_FUNCTION(F1__clk1, Z1L1038, N1_data_out, Z1_A_stall); --Z1_latched_oci_tb_hbreak_req is system_0:u0|cpu_0:the_cpu_0|latched_oci_tb_hbreak_req Z1_latched_oci_tb_hbreak_req = AMPP_FUNCTION(F1__clk1, Z1L3378, N1_data_out); --XC1_jtag_break is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|jtag_break XC1_jtag_break = AMPP_FUNCTION(F1__clk1, XC1L2, XC1L4, D1_CLRN_SIGNAL, FD1L196); --Z1_hbreak_enabled is system_0:u0|cpu_0:the_cpu_0|hbreak_enabled Z1_hbreak_enabled = AMPP_FUNCTION(F1__clk1, Z1L3241, N1_data_out, Z1L3020); --Z1_wait_for_one_post_bret_inst is system_0:u0|cpu_0:the_cpu_0|wait_for_one_post_bret_inst Z1_wait_for_one_post_bret_inst = AMPP_FUNCTION(F1__clk1, Z1L3381, N1_data_out); --Z1L3242 is system_0:u0|cpu_0:the_cpu_0|hbreak_req~30 Z1L3242 = AMPP_FUNCTION(Z1_latched_oci_tb_hbreak_req, XC1_jtag_break, Z1_hbreak_enabled, Z1_wait_for_one_post_bret_inst); --Z1_E_iw[12] is system_0:u0|cpu_0:the_cpu_0|E_iw[12] Z1_E_iw[12] = AMPP_FUNCTION(F1__clk1, Z1_D_iw[12], N1_data_out, Z1_A_stall); --Z1_E_iw[5] is system_0:u0|cpu_0:the_cpu_0|E_iw[5] Z1_E_iw[5] = AMPP_FUNCTION(F1__clk1, Z1_D_iw[5], N1_data_out, Z1_A_stall); --Z1_E_iw[4] is system_0:u0|cpu_0:the_cpu_0|E_iw[4] Z1_E_iw[4] = AMPP_FUNCTION(F1__clk1, Z1_D_iw[4], N1_data_out, Z1_A_stall); --Z1_E_iw[1] is system_0:u0|cpu_0:the_cpu_0|E_iw[1] Z1_E_iw[1] = AMPP_FUNCTION(F1__clk1, Z1_D_iw[1], N1_data_out, Z1_A_stall); --Z1_E_iw[2] is system_0:u0|cpu_0:the_cpu_0|E_iw[2] Z1_E_iw[2] = AMPP_FUNCTION(F1__clk1, Z1_D_iw[2], N1_data_out, Z1_A_stall); --Z1L1649 is system_0:u0|cpu_0:the_cpu_0|E_op_opx~104 Z1L1649 = AMPP_FUNCTION(Z1_E_iw[4], Z1_E_iw[1], Z1_E_iw[2]); --Z1_E_iw[3] is system_0:u0|cpu_0:the_cpu_0|E_iw[3] Z1_E_iw[3] = AMPP_FUNCTION(F1__clk1, Z1_D_iw[3], N1_data_out, Z1_A_stall); --Z1_E_iw[0] is system_0:u0|cpu_0:the_cpu_0|E_iw[0] Z1_E_iw[0] = AMPP_FUNCTION(F1__clk1, Z1_D_iw[0], N1_data_out, Z1_A_stall); --Z1L1650 is system_0:u0|cpu_0:the_cpu_0|E_op_opx~105 Z1L1650 = AMPP_FUNCTION(Z1_E_iw[5], Z1L1649, Z1_E_iw[3], Z1_E_iw[0]); --Z1_E_iw[16] is system_0:u0|cpu_0:the_cpu_0|E_iw[16] Z1_E_iw[16] = AMPP_FUNCTION(F1__clk1, Z1_D_iw[16], N1_data_out, Z1_A_stall); --Z1_E_iw[13] is system_0:u0|cpu_0:the_cpu_0|E_iw[13] Z1_E_iw[13] = AMPP_FUNCTION(F1__clk1, Z1_D_iw[13], N1_data_out, Z1_A_stall); --Z1L1591 is system_0:u0|cpu_0:the_cpu_0|E_hbreak_req~50 Z1L1591 = AMPP_FUNCTION(Z1L1650, Z1_E_iw[16], Z1_E_iw[13]); --Z1_E_iw[15] is system_0:u0|cpu_0:the_cpu_0|E_iw[15] Z1_E_iw[15] = AMPP_FUNCTION(F1__clk1, Z1_D_iw[15], N1_data_out, Z1_A_stall); --Z1_E_iw[14] is system_0:u0|cpu_0:the_cpu_0|E_iw[14] Z1_E_iw[14] = AMPP_FUNCTION(F1__clk1, Z1_D_iw[14], N1_data_out, Z1_A_stall); --Z1L1592 is system_0:u0|cpu_0:the_cpu_0|E_hbreak_req~51 Z1L1592 = AMPP_FUNCTION(Z1L1890, Z1L1591, Z1_E_iw[15], Z1_E_iw[14]); --Z1_E_iw[11] is system_0:u0|cpu_0:the_cpu_0|E_iw[11] Z1_E_iw[11] = AMPP_FUNCTION(F1__clk1, Z1_D_iw[11], N1_data_out, Z1_A_stall); --Z1L2334 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_nxt~55 Z1L2334 = AMPP_FUNCTION(Z1L3242, Z1_E_iw[12], Z1L1592, Z1_E_iw[11]); --Z1L2335 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_nxt~56 Z1L2335 = AMPP_FUNCTION(Z1L1890, Z1_E_br_mispredict, Z1_E_ctrl_flush_pipe_always, Z1L2334); --Z1_ic_fill_ap_cnt[2] is system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_cnt[2] Z1_ic_fill_ap_cnt[2] = AMPP_FUNCTION(F1__clk1, Z1L3290, N1_data_out, Z1L3296); --Z1_ic_fill_ap_cnt[1] is system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_cnt[1] Z1_ic_fill_ap_cnt[1] = AMPP_FUNCTION(F1__clk1, Z1L3289, N1_data_out, Z1L3296); --Z1_ic_fill_ap_cnt[0] is system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_cnt[0] Z1_ic_fill_ap_cnt[0] = AMPP_FUNCTION(F1__clk1, Z1L3288, N1_data_out, Z1L3296); --Z1L2938 is system_0:u0|cpu_0:the_cpu_0|add~3075 Z1L2938 = AMPP_FUNCTION(Z1_ic_fill_ap_cnt[1], Z1_ic_fill_ap_cnt[0]); --Z1L3291 is system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_cnt_nxt[3]~39 Z1L3291 = AMPP_FUNCTION(BB1L250, Z1_ic_fill_ap_cnt[3], Z1_ic_fill_ap_cnt[2], Z1L2938); --EB1L26 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_grant_vector[1]~30 EB1L26 = EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port & (EB1_epcs_controller_epcs_control_port_arb_addend[1] # !EB1L29 & !EB1_epcs_controller_epcs_control_port_arb_addend[0]); --EB1L7 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_0_instruction_master_granted_epcs_controller_epcs_control_port~84 EB1L7 = EB1L29 & (EB1_epcs_controller_epcs_control_port_arb_addend[1] & !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port # !EB1_epcs_controller_epcs_control_port_arb_addend[0]); --EB1_epcs_controller_epcs_control_port_saved_chosen_master_vector[0] is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_saved_chosen_master_vector[0] EB1_epcs_controller_epcs_control_port_saved_chosen_master_vector[0] = DFFEAS(EB1L23, F1__clk1, N1_data_out, , , , , , ); --EB1L23 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_winner[0]~16 EB1L23 = EB1L7 # EB1_epcs_controller_epcs_control_port_saved_chosen_master_vector[0] & !EB1L26; --EB1_epcs_controller_epcs_control_port_in_a_read_cycle is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_in_a_read_cycle EB1_epcs_controller_epcs_control_port_in_a_read_cycle = EB1L7 # Z1_d_read & EB1L26; --EB1L25 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_end_xfer~19 EB1L25 = EB1L24 & (EB1_epcs_controller_epcs_control_port_in_a_read_cycle # Z1_d_write & EB1L26); --EB1L21 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_addend[1]~734 EB1L21 = EB1L7 & EB1L22 # !EB1L7 & (EB1L26 & EB1L22 # !EB1L26 & (EB1_epcs_controller_epcs_control_port_arb_addend[1])); --EB1L18 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_addend[0]~735 EB1L18 = EB1L7 & !EB1L19 # !EB1L7 & (EB1L26 & !EB1L19 # !EB1L26 & (EB1_epcs_controller_epcs_control_port_arb_addend[0])); --CB1L5 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_instruction_master_granted_cpu_0_jtag_debug_module~83 CB1L5 = CB1L28 & (CB1_cpu_0_jtag_debug_module_arb_addend[1] & !CB1_cpu_0_data_master_requests_cpu_0_jtag_debug_module # !CB1_cpu_0_jtag_debug_module_arb_addend[0]); --CB1L30 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_grant_vector[1]~55 CB1L30 = CB1_cpu_0_data_master_requests_cpu_0_jtag_debug_module & (CB1_cpu_0_jtag_debug_module_arb_addend[1] # !CB1L28 & !CB1_cpu_0_jtag_debug_module_arb_addend[0]); --CB1L29 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_end_xfer~42 CB1L29 = CB1L23 & (CB1L5 # LB1L10 & CB1L30); --CB1L20 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[1]~738 CB1L20 = CB1L5 & (!CB1L29) # !CB1L5 & CB1_cpu_0_jtag_debug_module_arb_addend[1] & !CB1L30; --CB1_cpu_0_jtag_debug_module_saved_chosen_master_vector[0] is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_saved_chosen_master_vector[0] CB1_cpu_0_jtag_debug_module_saved_chosen_master_vector[0] = DFFEAS(CB1L22, F1__clk1, N1_data_out, , , , , , ); --CB1L22 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_winner[0]~24 CB1L22 = CB1L5 # CB1_cpu_0_jtag_debug_module_saved_chosen_master_vector[0] & !CB1L30; --CB1L21 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[1]~739 CB1L21 = CB1L20 # CB1L30 & (CB1L29 # CB1L22); --CB1L17 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[0]~740 CB1L17 = CB1L5 & CB1L29 # !CB1L5 & (!CB1_cpu_0_jtag_debug_module_arb_addend[0] & !CB1L30); --CB1L18 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[0]~741 CB1L18 = !CB1L17 & (CB1L29 # CB1L22 # !CB1L30); --Z1_M_mem_byte_en[1] is system_0:u0|cpu_0:the_cpu_0|M_mem_byte_en[1] Z1_M_mem_byte_en[1] = AMPP_FUNCTION(F1__clk1, Z1L1645, N1_data_out, Z1_A_stall); --Z1_M_mem_byte_en[3] is system_0:u0|cpu_0:the_cpu_0|M_mem_byte_en[3] Z1_M_mem_byte_en[3] = AMPP_FUNCTION(F1__clk1, Z1L1647, N1_data_out, Z1_A_stall); --Z1_M_mem_byte_en[2] is system_0:u0|cpu_0:the_cpu_0|M_mem_byte_en[2] Z1_M_mem_byte_en[2] = AMPP_FUNCTION(F1__clk1, Z1L1646, N1_data_out, Z1_A_stall); --Z1_M_mem_byte_en[0] is system_0:u0|cpu_0:the_cpu_0|M_mem_byte_en[0] Z1_M_mem_byte_en[0] = AMPP_FUNCTION(F1__clk1, Z1L1648, N1_data_out, Z1_A_stall); --JE1_stage_1 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|stage_1 JE1_stage_1 = DFFEAS(JE1L28, F1__clk1, , , HE1L19, , , , ); --JE1L27 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|p0_stage_0~10 JE1L27 = JE1_full_1 & JE1_stage_1 # !JE1_full_1 & (JB1L16); --Z1_F_pc[3] is system_0:u0|cpu_0:the_cpu_0|F_pc[3] Z1_F_pc[3] = AMPP_FUNCTION(F1__clk1, Z1L1959, N1_data_out, Z1_F_stall); --Z1_F_pc[4] is system_0:u0|cpu_0:the_cpu_0|F_pc[4] Z1_F_pc[4] = AMPP_FUNCTION(F1__clk1, Z1L1963, N1_data_out, Z1_F_stall); --Z1_F_pc[5] is system_0:u0|cpu_0:the_cpu_0|F_pc[5] Z1_F_pc[5] = AMPP_FUNCTION(F1__clk1, Z1L1967, N1_data_out, Z1_F_stall); --Z1_F_pc[6] is system_0:u0|cpu_0:the_cpu_0|F_pc[6] Z1_F_pc[6] = AMPP_FUNCTION(F1__clk1, Z1L1971, N1_data_out, Z1_F_stall); --Z1_F_pc[7] is system_0:u0|cpu_0:the_cpu_0|F_pc[7] Z1_F_pc[7] = AMPP_FUNCTION(F1__clk1, Z1L1976, N1_data_out, Z1_F_stall); --Z1_F_pc[8] is system_0:u0|cpu_0:the_cpu_0|F_pc[8] Z1_F_pc[8] = AMPP_FUNCTION(F1__clk1, Z1L1981, N1_data_out, Z1_F_stall); --Z1L2255 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_tag[0]~746 Z1L2255 = AMPP_FUNCTION(Z1_A_mem_baddr[11], GC1_q_a[0], Z1_M_A_dc_latest_line_match); --Z1_F_pc[9] is system_0:u0|cpu_0:the_cpu_0|F_pc[9] Z1_F_pc[9] = AMPP_FUNCTION(F1__clk1, Z1L1985, N1_data_out, Z1_F_stall); --Z1L2256 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_tag[1]~747 Z1L2256 = AMPP_FUNCTION(Z1_A_mem_baddr[12], GC1_q_a[1], Z1_M_A_dc_latest_line_match); --Z1L2257 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_tag[2]~748 Z1L2257 = AMPP_FUNCTION(Z1_A_mem_baddr[13], GC1_q_a[2], Z1_M_A_dc_latest_line_match); --Z1L2258 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_tag[3]~749 Z1L2258 = AMPP_FUNCTION(Z1_A_mem_baddr[14], GC1_q_a[3], Z1_M_A_dc_latest_line_match); --Z1L2259 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_tag[4]~750 Z1L2259 = AMPP_FUNCTION(Z1_A_mem_baddr[15], GC1_q_a[4], Z1_M_A_dc_latest_line_match); --Z1L2260 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_tag[5]~751 Z1L2260 = AMPP_FUNCTION(Z1_A_mem_baddr[16], GC1_q_a[5], Z1_M_A_dc_latest_line_match); --Z1L2261 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_tag[6]~752 Z1L2261 = AMPP_FUNCTION(Z1_A_mem_baddr[17], GC1_q_a[6], Z1_M_A_dc_latest_line_match); --Z1L2262 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_tag[7]~753 Z1L2262 = AMPP_FUNCTION(Z1_A_mem_baddr[18], GC1_q_a[7], Z1_M_A_dc_latest_line_match); --G3_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0] G3_Q[0] = AMPP_FUNCTION(A1L333, G3L4, G3_Q[1], D1_CLRN_SIGNAL, L1_state[4], G3L5); --G9_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] G9_Q[0] = AMPP_FUNCTION(A1L333, D1L7, D1L28); --H1_WORD_SR[0] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] H1_WORD_SR[0] = AMPP_FUNCTION(A1L333, H1L29, H1L26); --D1_HUB_BYPASS_REG is sld_hub:sld_hub_inst|HUB_BYPASS_REG D1_HUB_BYPASS_REG = AMPP_FUNCTION(A1L333, D1L17); --M1_dffe1a[0] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|dffe1a[0] M1_dffe1a[0] = AMPP_FUNCTION(A1L333, M1_w_anode1w[3], D1_CLRN_SIGNAL, D1L6); --D1L19 is sld_hub:sld_hub_inst|hub_tdo~531 D1L19 = AMPP_FUNCTION(G9_Q[0], H1_WORD_SR[0], D1_HUB_BYPASS_REG, M1_dffe1a[0]); --G8_Q[1] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1] G8_Q[1] = AMPP_FUNCTION(A1L333, D1L8, D1_CLRN_SIGNAL, D1L28); --G8_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] G8_Q[0] = AMPP_FUNCTION(A1L333, D1L9, D1_CLRN_SIGNAL, D1L28); --FD1_sr[0] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[0] FD1_sr[0] = AMPP_FUNCTION(A1L333, FD1L106, D1_CLRN_SIGNAL, FD1L118); --VD1_td_shift[0] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[0] VD1_td_shift[0] = AMPP_FUNCTION(A1L333, VD1L83, D1_CLRN_SIGNAL, !L1_state[4], VD1L57); --D1L20 is sld_hub:sld_hub_inst|hub_tdo~532 D1L20 = AMPP_FUNCTION(G8_Q[1], G8_Q[0], FD1_sr[0], VD1_td_shift[0]); --D1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1 D1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L333, D1L12, L1_state[0], L1_state[12]); --D1L21 is sld_hub:sld_hub_inst|hub_tdo~533 D1L21 = AMPP_FUNCTION(G3_Q[0], D1L19, D1L20, D1_jtag_debug_mode_usr1); --L1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] L1_state[3] = AMPP_FUNCTION(A1L333, L1L19); --L1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] L1_state[4] = AMPP_FUNCTION(A1L333, L1L20, A1L335); --D1L22 is sld_hub:sld_hub_inst|hub_tdo~534 D1L22 = AMPP_FUNCTION(D1L21, L1_state[3], L1_state[4], D1_hub_tdo); --L1_state[8] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8] L1_state[8] = AMPP_FUNCTION(A1L333, L1L24, !A1L335); --HB1_m_data[0] is system_0:u0|sdram_0:the_sdram_0|m_data[0] HB1_m_data[0] = DFFEAS(HB1L114, F1__clk1, N1_data_out, , , , , , ); --HB1_oe is system_0:u0|sdram_0:the_sdram_0|oe HB1_oe = DFFEAS(HB1L262, F1__clk1, N1_data_out, , , , , !HB1_m_state.000010000, ); --HB1_m_data[1] is system_0:u0|sdram_0:the_sdram_0|m_data[1] HB1_m_data[1] = DFFEAS(HB1L117, F1__clk1, N1_data_out, , , , , , ); --HB1_m_data[2] is system_0:u0|sdram_0:the_sdram_0|m_data[2] HB1_m_data[2] = DFFEAS(HB1L120, F1__clk1, N1_data_out, , , , , , ); --HB1_m_data[3] is system_0:u0|sdram_0:the_sdram_0|m_data[3] HB1_m_data[3] = DFFEAS(HB1L123, F1__clk1, N1_data_out, , , , , , ); --HB1_m_data[4] is system_0:u0|sdram_0:the_sdram_0|m_data[4] HB1_m_data[4] = DFFEAS(HB1L126, F1__clk1, N1_data_out, , , , , , ); --HB1_m_data[5] is system_0:u0|sdram_0:the_sdram_0|m_data[5] HB1_m_data[5] = DFFEAS(HB1L129, F1__clk1, N1_data_out, , , , , , ); --HB1_m_data[6] is system_0:u0|sdram_0:the_sdram_0|m_data[6] HB1_m_data[6] = DFFEAS(HB1L132, F1__clk1, N1_data_out, , , , , , ); --HB1_m_data[7] is system_0:u0|sdram_0:the_sdram_0|m_data[7] HB1_m_data[7] = DFFEAS(HB1L135, F1__clk1, N1_data_out, , , , , , ); --HB1_m_data[8] is system_0:u0|sdram_0:the_sdram_0|m_data[8] HB1_m_data[8] = DFFEAS(HB1L138, F1__clk1, N1_data_out, , , , , , ); --HB1_m_data[9] is system_0:u0|sdram_0:the_sdram_0|m_data[9] HB1_m_data[9] = DFFEAS(HB1L141, F1__clk1, N1_data_out, , , , , , ); --HB1_m_data[10] is system_0:u0|sdram_0:the_sdram_0|m_data[10] HB1_m_data[10] = DFFEAS(HB1L144, F1__clk1, N1_data_out, , , , , , ); --HB1_m_data[11] is system_0:u0|sdram_0:the_sdram_0|m_data[11] HB1_m_data[11] = DFFEAS(HB1L147, F1__clk1, N1_data_out, , , , , , ); --HB1_m_data[12] is system_0:u0|sdram_0:the_sdram_0|m_data[12] HB1_m_data[12] = DFFEAS(HB1L150, F1__clk1, N1_data_out, , , , , , ); --HB1_m_data[13] is system_0:u0|sdram_0:the_sdram_0|m_data[13] HB1_m_data[13] = DFFEAS(HB1L153, F1__clk1, N1_data_out, , , , , , ); --HB1_m_data[14] is system_0:u0|sdram_0:the_sdram_0|m_data[14] HB1_m_data[14] = DFFEAS(HB1L156, F1__clk1, N1_data_out, , , , , , ); --HB1_m_data[15] is system_0:u0|sdram_0:the_sdram_0|m_data[15] HB1_m_data[15] = DFFEAS(HB1L159, F1__clk1, N1_data_out, , , , , , ); --MB1_d1_outgoing_tri_state_bridge_0_data[0] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[0] MB1_d1_outgoing_tri_state_bridge_0_data[0] = DFFEAS(AB1L13, F1__clk1, N1_data_out, , , , , , ); --MB1_d1_in_a_write_cycle is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle MB1_d1_in_a_write_cycle = DFFEAS(MB1_in_a_write_cycle, F1__clk1, N1_data_out, , , , , , ); --MB1_d1_outgoing_tri_state_bridge_0_data[1] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[1] MB1_d1_outgoing_tri_state_bridge_0_data[1] = DFFEAS(AB1L15, F1__clk1, N1_data_out, , , , , , ); --MB1_d1_outgoing_tri_state_bridge_0_data[2] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[2] MB1_d1_outgoing_tri_state_bridge_0_data[2] = DFFEAS(AB1L17, F1__clk1, N1_data_out, , , , , , ); --MB1_d1_outgoing_tri_state_bridge_0_data[3] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[3] MB1_d1_outgoing_tri_state_bridge_0_data[3] = DFFEAS(AB1L19, F1__clk1, N1_data_out, , , , , , ); --MB1_d1_outgoing_tri_state_bridge_0_data[4] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[4] MB1_d1_outgoing_tri_state_bridge_0_data[4] = DFFEAS(AB1L21, F1__clk1, N1_data_out, , , , , , ); --MB1_d1_outgoing_tri_state_bridge_0_data[5] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[5] MB1_d1_outgoing_tri_state_bridge_0_data[5] = DFFEAS(AB1L23, F1__clk1, N1_data_out, , , , , , ); --MB1_d1_outgoing_tri_state_bridge_0_data[6] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[6] MB1_d1_outgoing_tri_state_bridge_0_data[6] = DFFEAS(AB1L25, F1__clk1, N1_data_out, , , , , , ); --MB1_d1_outgoing_tri_state_bridge_0_data[7] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7] MB1_d1_outgoing_tri_state_bridge_0_data[7] = DFFEAS(AB1L27, F1__clk1, N1_data_out, , , , , , ); --Z1_d_writedata[16] is system_0:u0|cpu_0:the_cpu_0|d_writedata[16] Z1_d_writedata[16] = AMPP_FUNCTION(F1__clk1, Z1L3145, N1_data_out, Z1_A_en_d1); --AB1L28 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[0]~192 AB1L28 = AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[16] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[0]); --Z1_d_writedata[17] is system_0:u0|cpu_0:the_cpu_0|d_writedata[17] Z1_d_writedata[17] = AMPP_FUNCTION(F1__clk1, Z1L3146, N1_data_out, Z1_A_en_d1); --AB1L29 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[1]~193 AB1L29 = AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[17] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[1]); --Z1_d_writedata[18] is system_0:u0|cpu_0:the_cpu_0|d_writedata[18] Z1_d_writedata[18] = AMPP_FUNCTION(F1__clk1, Z1L3147, N1_data_out, Z1_A_en_d1); --AB1L30 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[2]~194 AB1L30 = AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[18] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[2]); --Z1_d_writedata[19] is system_0:u0|cpu_0:the_cpu_0|d_writedata[19] Z1_d_writedata[19] = AMPP_FUNCTION(F1__clk1, Z1L3148, N1_data_out, Z1_A_en_d1); --AB1L31 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[3]~195 AB1L31 = AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[19] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[3]); --Z1_d_writedata[20] is system_0:u0|cpu_0:the_cpu_0|d_writedata[20] Z1_d_writedata[20] = AMPP_FUNCTION(F1__clk1, Z1L3149, N1_data_out, Z1_A_en_d1); --AB1L32 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[4]~196 AB1L32 = AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[20] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[4]); --Z1_d_writedata[21] is system_0:u0|cpu_0:the_cpu_0|d_writedata[21] Z1_d_writedata[21] = AMPP_FUNCTION(F1__clk1, Z1L3150, N1_data_out, Z1_A_en_d1); --AB1L33 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[5]~197 AB1L33 = AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[21] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[5]); --Z1_d_writedata[22] is system_0:u0|cpu_0:the_cpu_0|d_writedata[22] Z1_d_writedata[22] = AMPP_FUNCTION(F1__clk1, Z1L3151, N1_data_out, Z1_A_en_d1); --AB1L34 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[6]~198 AB1L34 = AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[22] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[6]); --Z1_d_writedata[23] is system_0:u0|cpu_0:the_cpu_0|d_writedata[23] Z1_d_writedata[23] = AMPP_FUNCTION(F1__clk1, Z1L3152, N1_data_out, Z1_A_en_d1); --AB1L35 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[7]~199 AB1L35 = AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[23] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[7]); --Z1_d_writedata[24] is system_0:u0|cpu_0:the_cpu_0|d_writedata[24] Z1_d_writedata[24] = AMPP_FUNCTION(F1__clk1, Z1L3153, N1_data_out, Z1_A_en_d1); --AB1L36 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[8]~200 AB1L36 = AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[24] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[8]); --Z1_d_writedata[25] is system_0:u0|cpu_0:the_cpu_0|d_writedata[25] Z1_d_writedata[25] = AMPP_FUNCTION(F1__clk1, Z1L3154, N1_data_out, Z1_A_en_d1); --AB1L37 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[9]~201 AB1L37 = AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[25] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[9]); --Z1_d_writedata[26] is system_0:u0|cpu_0:the_cpu_0|d_writedata[26] Z1_d_writedata[26] = AMPP_FUNCTION(F1__clk1, Z1L3155, N1_data_out, Z1_A_en_d1); --AB1L38 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[10]~202 AB1L38 = AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[26] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[10]); --Z1_d_writedata[27] is system_0:u0|cpu_0:the_cpu_0|d_writedata[27] Z1_d_writedata[27] = AMPP_FUNCTION(F1__clk1, Z1L3156, N1_data_out, Z1_A_en_d1); --AB1L39 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[11]~203 AB1L39 = AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[27] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[11]); --Z1_d_writedata[28] is system_0:u0|cpu_0:the_cpu_0|d_writedata[28] Z1_d_writedata[28] = AMPP_FUNCTION(F1__clk1, Z1L3157, N1_data_out, Z1_A_en_d1); --AB1L40 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[12]~204 AB1L40 = AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[28] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[12]); --Z1_d_writedata[29] is system_0:u0|cpu_0:the_cpu_0|d_writedata[29] Z1_d_writedata[29] = AMPP_FUNCTION(F1__clk1, Z1L3158, N1_data_out, Z1_A_en_d1); --AB1L41 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[13]~205 AB1L41 = AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[29] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[13]); --Z1_d_writedata[30] is system_0:u0|cpu_0:the_cpu_0|d_writedata[30] Z1_d_writedata[30] = AMPP_FUNCTION(F1__clk1, Z1L3159, N1_data_out, Z1_A_en_d1); --AB1L42 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[14]~206 AB1L42 = AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[30] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[14]); --Z1_d_writedata[31] is system_0:u0|cpu_0:the_cpu_0|d_writedata[31] Z1_d_writedata[31] = AMPP_FUNCTION(F1__clk1, Z1L3160, N1_data_out, Z1_A_en_d1); --AB1L43 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[15]~207 AB1L43 = AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[31] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[15]); --Z1_M_st_data[0] is system_0:u0|cpu_0:the_cpu_0|M_st_data[0] Z1_M_st_data[0] = AMPP_FUNCTION(F1__clk1, Z1_E_src2_reg[0], N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_0[0] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_0[0] Z1_A_dc_latest_data_byte_0[0] = AMPP_FUNCTION(F1__clk1, Z1L3165, N1_data_out, Z1_dc_data_wr_byte_0); --FC1_q_a[0] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[0] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[0] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3165, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3161); --Z1_A_dc_latest_data_valid_byte_0 is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_valid_byte_0 Z1_A_dc_latest_data_valid_byte_0 = AMPP_FUNCTION(F1__clk1, Z1L67, N1_data_out); --Z1L2223 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_0[0]~480 Z1L2223 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_0[0], FC1_q_a[0], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_0); --FD1L41Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[22]~reg0 FD1L41Q = AMPP_FUNCTION(A1L336, FD1_sr[22], FD1L104); --D1_CLRN_SIGNAL is sld_hub:sld_hub_inst|CLRN_SIGNAL D1_CLRN_SIGNAL = AMPP_FUNCTION(A1L333, D1L4); --FD1L53Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[34]~reg0 FD1L53Q = AMPP_FUNCTION(A1L336, FD1_sr[34], FD1L104); --FD1_jxdr is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jxdr FD1_jxdr = AMPP_FUNCTION(F1__clk1, FD1L58); --FD1_ir[1] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|ir[1] FD1_ir[1] = AMPP_FUNCTION(A1L333, G5_Q[1], FD1L16); --FD1_ir[0] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|ir[0] FD1_ir[0] = AMPP_FUNCTION(A1L333, G5_Q[0], FD1L16); --FD1L102 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4752 FD1L102 = AMPP_FUNCTION(FD1_ir[1], FD1_ir[0]); --FD1L54Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[35]~reg0 FD1L54Q = AMPP_FUNCTION(A1L336, FD1_sr[35], FD1L104); --FD1L196 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|take_action_ocimem_a~45 FD1L196 = AMPP_FUNCTION(FD1L53Q, FD1_jxdr, FD1L102, FD1L54Q); --C1_Cont[0] is Reset_Delay:delay1|Cont[0] C1_Cont[0] = DFFEAS(C1L3, CLOCK_50, , , C1L81, , , , ); --C1_Cont[1] is Reset_Delay:delay1|Cont[1] C1_Cont[1] = DFFEAS(C1L6, CLOCK_50, , , C1L81, , , , ); --C1_Cont[2] is Reset_Delay:delay1|Cont[2] C1_Cont[2] = DFFEAS(C1L9, CLOCK_50, , , C1L81, , , , ); --C1_Cont[3] is Reset_Delay:delay1|Cont[3] C1_Cont[3] = DFFEAS(C1L12, CLOCK_50, , , C1L81, , , , ); --C1L74 is Reset_Delay:delay1|Equal~241 C1L74 = C1_Cont[0] & C1_Cont[1] & C1_Cont[2] & C1_Cont[3]; --C1_Cont[4] is Reset_Delay:delay1|Cont[4] C1_Cont[4] = DFFEAS(C1L15, CLOCK_50, , , C1L81, , , , ); --C1_Cont[5] is Reset_Delay:delay1|Cont[5] C1_Cont[5] = DFFEAS(C1L18, CLOCK_50, , , C1L81, , , , ); --C1_Cont[6] is Reset_Delay:delay1|Cont[6] C1_Cont[6] = DFFEAS(C1L21, CLOCK_50, , , C1L81, , , , ); --C1_Cont[7] is Reset_Delay:delay1|Cont[7] C1_Cont[7] = DFFEAS(C1L24, CLOCK_50, , , C1L81, , , , ); --C1L75 is Reset_Delay:delay1|Equal~242 C1L75 = C1_Cont[4] & C1_Cont[5] & C1_Cont[6] & C1_Cont[7]; --C1_Cont[8] is Reset_Delay:delay1|Cont[8] C1_Cont[8] = DFFEAS(C1L27, CLOCK_50, , , C1L81, , , , ); --C1_Cont[9] is Reset_Delay:delay1|Cont[9] C1_Cont[9] = DFFEAS(C1L30, CLOCK_50, , , C1L81, , , , ); --C1_Cont[10] is Reset_Delay:delay1|Cont[10] C1_Cont[10] = DFFEAS(C1L33, CLOCK_50, , , C1L81, , , , ); --C1_Cont[11] is Reset_Delay:delay1|Cont[11] C1_Cont[11] = DFFEAS(C1L36, CLOCK_50, , , C1L81, , , , ); --C1L76 is Reset_Delay:delay1|Equal~243 C1L76 = C1_Cont[8] & C1_Cont[9] & C1_Cont[10] & C1_Cont[11]; --C1_Cont[12] is Reset_Delay:delay1|Cont[12] C1_Cont[12] = DFFEAS(C1L39, CLOCK_50, , , C1L81, , , , ); --C1_Cont[13] is Reset_Delay:delay1|Cont[13] C1_Cont[13] = DFFEAS(C1L42, CLOCK_50, , , C1L81, , , , ); --C1_Cont[14] is Reset_Delay:delay1|Cont[14] C1_Cont[14] = DFFEAS(C1L45, CLOCK_50, , , C1L81, , , , ); --C1_Cont[15] is Reset_Delay:delay1|Cont[15] C1_Cont[15] = DFFEAS(C1L48, CLOCK_50, , , C1L81, , , , ); --C1L77 is Reset_Delay:delay1|Equal~244 C1L77 = C1_Cont[12] & C1_Cont[13] & C1_Cont[14] & C1_Cont[15]; --C1L78 is Reset_Delay:delay1|Equal~245 C1L78 = C1L74 & C1L75 & C1L76 & C1L77; --C1_Cont[16] is Reset_Delay:delay1|Cont[16] C1_Cont[16] = DFFEAS(C1L51, CLOCK_50, , , C1L81, , , , ); --C1_Cont[17] is Reset_Delay:delay1|Cont[17] C1_Cont[17] = DFFEAS(C1L54, CLOCK_50, , , C1L81, , , , ); --C1_Cont[18] is Reset_Delay:delay1|Cont[18] C1_Cont[18] = DFFEAS(C1L57, CLOCK_50, , , C1L81, , , , ); --C1_Cont[19] is Reset_Delay:delay1|Cont[19] C1_Cont[19] = DFFEAS(C1L60, CLOCK_50, , , C1L81, , , , ); --C1L79 is Reset_Delay:delay1|Equal~246 C1L79 = C1_Cont[16] & C1_Cont[17] & C1_Cont[18] & C1_Cont[19]; --C1_Cont[20] is Reset_Delay:delay1|Cont[20] C1_Cont[20] = DFFEAS(C1L63, CLOCK_50, , , C1L81, , , , ); --C1_Cont[21] is Reset_Delay:delay1|Cont[21] C1_Cont[21] = DFFEAS(C1L66, CLOCK_50, , , C1L81, , , , ); --C1_Cont[22] is Reset_Delay:delay1|Cont[22] C1_Cont[22] = DFFEAS(C1L69, CLOCK_50, , , C1L81, , , , ); --C1_Cont[23] is Reset_Delay:delay1|Cont[23] C1_Cont[23] = DFFEAS(C1L72, CLOCK_50, , , C1L81, , , , ); --C1L80 is Reset_Delay:delay1|Equal~247 C1L80 = C1_Cont[20] & C1_Cont[21] & C1_Cont[22] & C1_Cont[23]; --C1L81 is Reset_Delay:delay1|Equal~248 C1L81 = !C1L80 # !C1L79 # !C1L78; --Z1_M_st_data[1] is system_0:u0|cpu_0:the_cpu_0|M_st_data[1] Z1_M_st_data[1] = AMPP_FUNCTION(F1__clk1, Z1_E_src2_reg[1], N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_0[1] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_0[1] Z1_A_dc_latest_data_byte_0[1] = AMPP_FUNCTION(F1__clk1, Z1L3166, N1_data_out, Z1_dc_data_wr_byte_0); --FC1_q_a[1] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[1] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[1] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3166, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3161); --Z1L2224 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_0[1]~481 Z1L2224 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_0[1], FC1_q_a[1], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_0); --Z1_M_st_data[2] is system_0:u0|cpu_0:the_cpu_0|M_st_data[2] Z1_M_st_data[2] = AMPP_FUNCTION(F1__clk1, Z1_E_src2_reg[2], N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_0[2] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_0[2] Z1_A_dc_latest_data_byte_0[2] = AMPP_FUNCTION(F1__clk1, Z1L3167, N1_data_out, Z1_dc_data_wr_byte_0); --FC1_q_a[2] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[2] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[2] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3167, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3161); --Z1L2225 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_0[2]~482 Z1L2225 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_0[2], FC1_q_a[2], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_0); --Z1_M_st_data[3] is system_0:u0|cpu_0:the_cpu_0|M_st_data[3] Z1_M_st_data[3] = AMPP_FUNCTION(F1__clk1, Z1_E_src2_reg[3], N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_0[3] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_0[3] Z1_A_dc_latest_data_byte_0[3] = AMPP_FUNCTION(F1__clk1, Z1L3168, N1_data_out, Z1_dc_data_wr_byte_0); --FC1_q_a[3] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[3] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[3] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3168, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3161); --Z1L2226 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_0[3]~483 Z1L2226 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_0[3], FC1_q_a[3], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_0); --Z1_M_st_data[4] is system_0:u0|cpu_0:the_cpu_0|M_st_data[4] Z1_M_st_data[4] = AMPP_FUNCTION(F1__clk1, Z1_E_src2_reg[4], N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_0[4] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_0[4] Z1_A_dc_latest_data_byte_0[4] = AMPP_FUNCTION(F1__clk1, Z1L3169, N1_data_out, Z1_dc_data_wr_byte_0); --FC1_q_a[4] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[4] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[4] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3169, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3161); --Z1L2227 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_0[4]~484 Z1L2227 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_0[4], FC1_q_a[4], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_0); --Z1_M_st_data[5] is system_0:u0|cpu_0:the_cpu_0|M_st_data[5] Z1_M_st_data[5] = AMPP_FUNCTION(F1__clk1, Z1_E_src2_reg[5], N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_0[5] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_0[5] Z1_A_dc_latest_data_byte_0[5] = AMPP_FUNCTION(F1__clk1, Z1L3170, N1_data_out, Z1_dc_data_wr_byte_0); --FC1_q_a[5] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[5] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[5] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3170, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3161); --Z1L2228 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_0[5]~485 Z1L2228 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_0[5], FC1_q_a[5], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_0); --Z1_M_st_data[6] is system_0:u0|cpu_0:the_cpu_0|M_st_data[6] Z1_M_st_data[6] = AMPP_FUNCTION(F1__clk1, Z1_E_src2_reg[6], N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_0[6] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_0[6] Z1_A_dc_latest_data_byte_0[6] = AMPP_FUNCTION(F1__clk1, Z1L3171, N1_data_out, Z1_dc_data_wr_byte_0); --FC1_q_a[6] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[6] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[6] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3171, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3161); --Z1L2229 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_0[6]~486 Z1L2229 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_0[6], FC1_q_a[6], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_0); --Z1_M_st_data[7] is system_0:u0|cpu_0:the_cpu_0|M_st_data[7] Z1_M_st_data[7] = AMPP_FUNCTION(F1__clk1, Z1_E_src2_reg[7], N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_0[7] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_0[7] Z1_A_dc_latest_data_byte_0[7] = AMPP_FUNCTION(F1__clk1, Z1L3172, N1_data_out, Z1_dc_data_wr_byte_0); --FC1_q_a[7] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[7] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[7] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3172, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3161); --Z1L2230 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_0[7]~487 Z1L2230 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_0[7], FC1_q_a[7], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_0); --Z1_M_st_data[8] is system_0:u0|cpu_0:the_cpu_0|M_st_data[8] Z1_M_st_data[8] = AMPP_FUNCTION(F1__clk1, Z1L1871, N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_1[0] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_1[0] Z1_A_dc_latest_data_byte_1[0] = AMPP_FUNCTION(F1__clk1, Z1L3173, N1_data_out, Z1_dc_data_wr_byte_1); --FC1_q_a[8] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[8] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[8] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3173, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3162); --Z1_A_dc_latest_data_valid_byte_1 is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_valid_byte_1 Z1_A_dc_latest_data_valid_byte_1 = AMPP_FUNCTION(F1__clk1, Z1L69, N1_data_out); --Z1L2231 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_1[0]~480 Z1L2231 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_1[0], FC1_q_a[8], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_1); --Z1_M_st_data[9] is system_0:u0|cpu_0:the_cpu_0|M_st_data[9] Z1_M_st_data[9] = AMPP_FUNCTION(F1__clk1, Z1L1872, N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_1[1] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_1[1] Z1_A_dc_latest_data_byte_1[1] = AMPP_FUNCTION(F1__clk1, Z1L3174, N1_data_out, Z1_dc_data_wr_byte_1); --FC1_q_a[9] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[9] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[9] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3174, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3162); --Z1L2232 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_1[1]~481 Z1L2232 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_1[1], FC1_q_a[9], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_1); --Z1_M_st_data[10] is system_0:u0|cpu_0:the_cpu_0|M_st_data[10] Z1_M_st_data[10] = AMPP_FUNCTION(F1__clk1, Z1L1873, N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_1[2] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_1[2] Z1_A_dc_latest_data_byte_1[2] = AMPP_FUNCTION(F1__clk1, Z1L3175, N1_data_out, Z1_dc_data_wr_byte_1); --FC1_q_a[10] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[10] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[10] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3175, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3162); --Z1L2233 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_1[2]~482 Z1L2233 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_1[2], FC1_q_a[10], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_1); --Z1_M_st_data[11] is system_0:u0|cpu_0:the_cpu_0|M_st_data[11] Z1_M_st_data[11] = AMPP_FUNCTION(F1__clk1, Z1L1874, N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_1[3] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_1[3] Z1_A_dc_latest_data_byte_1[3] = AMPP_FUNCTION(F1__clk1, Z1L3176, N1_data_out, Z1_dc_data_wr_byte_1); --FC1_q_a[11] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[11] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[11] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3176, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3162); --Z1L2234 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_1[3]~483 Z1L2234 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_1[3], FC1_q_a[11], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_1); --Z1_M_st_data[12] is system_0:u0|cpu_0:the_cpu_0|M_st_data[12] Z1_M_st_data[12] = AMPP_FUNCTION(F1__clk1, Z1L1875, N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_1[4] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_1[4] Z1_A_dc_latest_data_byte_1[4] = AMPP_FUNCTION(F1__clk1, Z1L3177, N1_data_out, Z1_dc_data_wr_byte_1); --FC1_q_a[12] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[12] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[12] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3177, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3162); --Z1L2235 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_1[4]~484 Z1L2235 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_1[4], FC1_q_a[12], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_1); --Z1_M_st_data[13] is system_0:u0|cpu_0:the_cpu_0|M_st_data[13] Z1_M_st_data[13] = AMPP_FUNCTION(F1__clk1, Z1L1876, N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_1[5] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_1[5] Z1_A_dc_latest_data_byte_1[5] = AMPP_FUNCTION(F1__clk1, Z1L3178, N1_data_out, Z1_dc_data_wr_byte_1); --FC1_q_a[13] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[13] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[13] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3178, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3162); --Z1L2236 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_1[5]~485 Z1L2236 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_1[5], FC1_q_a[13], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_1); --Z1_M_st_data[14] is system_0:u0|cpu_0:the_cpu_0|M_st_data[14] Z1_M_st_data[14] = AMPP_FUNCTION(F1__clk1, Z1L1877, N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_1[6] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_1[6] Z1_A_dc_latest_data_byte_1[6] = AMPP_FUNCTION(F1__clk1, Z1L3179, N1_data_out, Z1_dc_data_wr_byte_1); --FC1_q_a[14] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[14] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[14] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3179, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3162); --Z1L2237 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_1[6]~486 Z1L2237 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_1[6], FC1_q_a[14], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_1); --Z1_M_st_data[15] is system_0:u0|cpu_0:the_cpu_0|M_st_data[15] Z1_M_st_data[15] = AMPP_FUNCTION(F1__clk1, Z1L1878, N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_1[7] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_1[7] Z1_A_dc_latest_data_byte_1[7] = AMPP_FUNCTION(F1__clk1, Z1L3180, N1_data_out, Z1_dc_data_wr_byte_1); --FC1_q_a[15] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[15] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[15] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3180, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3162); --Z1L2238 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_1[7]~487 Z1L2238 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_1[7], FC1_q_a[15], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_1); --NE1_do_load_shifter is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|do_load_shifter NE1_do_load_shifter = DFFEAS(NE1L38, F1__clk1, N1_data_out, , , , , , ); --NE1L73 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9]~1472 NE1L73 = NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] & !NE1_do_load_shifter; --NE1_baud_clk_en is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_clk_en NE1_baud_clk_en = DFFEAS(NE1L36, F1__clk1, N1_data_out, , , , , , ); --NE1L74 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9]~1473 NE1L74 = NE1_do_load_shifter # NE1_baud_clk_en & (NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] # !NE1L42); --LE1_tx_data[7] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|tx_data[7] LE1_tx_data[7] = DFFEAS(Z1_d_writedata[7], F1__clk1, N1_data_out, , NE1L50, , , , ); --NE1L61 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[8]~82 NE1L61 = NE1_do_load_shifter & LE1_tx_data[7] # !NE1_do_load_shifter & (NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9]); --LE1_tx_data[6] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|tx_data[6] LE1_tx_data[6] = DFFEAS(Z1_d_writedata[6], F1__clk1, N1_data_out, , NE1L50, , , , ); --NE1L60 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[7]~83 NE1L60 = NE1_do_load_shifter & LE1_tx_data[6] # !NE1_do_load_shifter & (NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8]); --LE1_tx_data[5] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|tx_data[5] LE1_tx_data[5] = DFFEAS(Z1_d_writedata[5], F1__clk1, N1_data_out, , NE1L50, , , , ); --NE1L59 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[6]~84 NE1L59 = NE1_do_load_shifter & LE1_tx_data[5] # !NE1_do_load_shifter & (NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7]); --LE1_tx_data[4] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|tx_data[4] LE1_tx_data[4] = DFFEAS(Z1_d_writedata[4], F1__clk1, N1_data_out, , NE1L50, , , , ); --NE1L58 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[5]~85 NE1L58 = NE1_do_load_shifter & LE1_tx_data[4] # !NE1_do_load_shifter & (NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6]); --LE1_tx_data[3] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|tx_data[3] LE1_tx_data[3] = DFFEAS(Z1_d_writedata[3], F1__clk1, N1_data_out, , NE1L50, , , , ); --NE1L57 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[4]~86 NE1L57 = NE1_do_load_shifter & LE1_tx_data[3] # !NE1_do_load_shifter & (NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5]); --LE1_tx_data[2] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|tx_data[2] LE1_tx_data[2] = DFFEAS(Z1_d_writedata[2], F1__clk1, N1_data_out, , NE1L50, , , , ); --NE1L56 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[3]~87 NE1L56 = NE1_do_load_shifter & LE1_tx_data[2] # !NE1_do_load_shifter & (NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4]); --LE1_tx_data[1] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|tx_data[1] LE1_tx_data[1] = DFFEAS(Z1_d_writedata[1], F1__clk1, N1_data_out, , NE1L50, , , , ); --NE1L55 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[2]~88 NE1L55 = NE1_do_load_shifter & LE1_tx_data[1] # !NE1_do_load_shifter & (NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]); --LE1_tx_data[0] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|tx_data[0] LE1_tx_data[0] = DFFEAS(Z1_d_writedata[0], F1__clk1, N1_data_out, , NE1L50, , , , ); --NE1L54 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[1]~89 NE1L54 = NE1_do_load_shifter & LE1_tx_data[0] # !NE1_do_load_shifter & (NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2]); --HB1L93 is system_0:u0|sdram_0:the_sdram_0|Select~8197 HB1L93 = HB1_m_state.100000000 & (HB1_refresh_request # GE1L1 & !HB1L385); --HB1L348 is system_0:u0|sdram_0:the_sdram_0|m_next.000001000~207 HB1L348 = HB1_active_rnw & !HB1_m_state.010000000 & !HB1L93; --HB1L349 is system_0:u0|sdram_0:the_sdram_0|m_next.000001000~208 HB1L349 = HB1_refresh_request # !HB1_init_done; --HB1L350 is system_0:u0|sdram_0:the_sdram_0|m_next.000001000~209 HB1L350 = !HB1_m_state.010000000 & (!HB1L356 # !HB1_m_state.100000000); --HB1L351 is system_0:u0|sdram_0:the_sdram_0|m_next.000001000~210 HB1L351 = HB1L350 & (HB1L358 # !HB1_refresh_request # !HB1L22); --HB1L352 is system_0:u0|sdram_0:the_sdram_0|m_next.000001000~211 HB1L352 = HB1_m_state.000000010 # HB1L349 & !HB1_m_state.000000001 # !HB1L351; --HB1L94 is system_0:u0|sdram_0:the_sdram_0|Select~8198 HB1L94 = !HB1_m_state.000000001 & (!HB1_refresh_request # !HB1_init_done); --HB1_m_count[0] is system_0:u0|sdram_0:the_sdram_0|m_count[0] HB1_m_count[0] = DFFEAS(HB1L162, F1__clk1, N1_data_out, , , , , , ); --HB1L95 is system_0:u0|sdram_0:the_sdram_0|Select~8199 HB1L95 = HB1L94 # !HB1L89 & (HB1_m_count[1] # HB1_m_count[0]); --HB1L96 is system_0:u0|sdram_0:the_sdram_0|Select~8200 HB1L96 = HB1_m_state.010000000 # HB1_m_count[2] & (HB1L95 # !HB1L91); --HB1L97 is system_0:u0|sdram_0:the_sdram_0|Select~8201 HB1L97 = HB1L89 # HB1_m_count[2] & !HB1_m_count[1] & !HB1_m_count[0]; --HB1L98 is system_0:u0|sdram_0:the_sdram_0|Select~8202 HB1L98 = HB1_m_state.000000001 & !HB1_m_state.001000000 & !HB1_m_state.100000000 & !HB1L90; --HB1L99 is system_0:u0|sdram_0:the_sdram_0|Select~8203 HB1L99 = HB1_m_count[1] & !HB1L70 & (HB1L89 # HB1_m_count[0]); --HB1L100 is system_0:u0|sdram_0:the_sdram_0|Select~8204 HB1L100 = HB1L97 & (HB1L98 # HB1L99 & !HB1L93) # !HB1L97 & (HB1L99 & !HB1L93); --HB1L353 is system_0:u0|sdram_0:the_sdram_0|m_next.000001000~212 HB1L353 = !HB1_active_rnw & !HB1_m_state.010000000 & !HB1L93; --HB1_i_next.111 is system_0:u0|sdram_0:the_sdram_0|i_next.111 HB1_i_next.111 = DFFEAS(HB1L164, F1__clk1, N1_data_out, , , , , , ); --HB1_i_count[2] is system_0:u0|sdram_0:the_sdram_0|i_count[2] HB1_i_count[2] = DFFEAS(HB1L166, F1__clk1, N1_data_out, , , , , , ); --HB1_i_count[1] is system_0:u0|sdram_0:the_sdram_0|i_count[1] HB1_i_count[1] = DFFEAS(HB1L168, F1__clk1, N1_data_out, , , , , , ); --HB1L101 is system_0:u0|sdram_0:the_sdram_0|Select~8205 HB1L101 = HB1_i_state.011 & HB1_i_next.111 & !HB1_i_count[2] & !HB1_i_count[1]; --HB1L102 is system_0:u0|sdram_0:the_sdram_0|Select~8206 HB1L102 = HB1_i_state.011 & !HB1_i_count[2] & !HB1_i_count[1]; --HB1_i_next.101 is system_0:u0|sdram_0:the_sdram_0|i_next.101 HB1_i_next.101 = DFFEAS(HB1L169, F1__clk1, N1_data_out, , , , , , ); --HB1L293 is system_0:u0|sdram_0:the_sdram_0|i_state.101~43 HB1L293 = HB1_i_state.101 # HB1L102 & HB1_i_next.101; --HB1L103 is system_0:u0|sdram_0:the_sdram_0|Select~8207 HB1L103 = HB1_m_state.000001000 # HB1_m_state.000010000 # !HB1_m_state.000000001 & !HB1_refresh_request; --HB1L104 is system_0:u0|sdram_0:the_sdram_0|Select~8208 HB1L104 = !HB1_m_next.000000001 & (HB1_m_state.001000000 # HB1L103 # !HB1L301); --HB1L105 is system_0:u0|sdram_0:the_sdram_0|Select~8209 HB1L105 = !HB1L104 & HB1L351 & (HB1_m_state.000000001 # HB1_init_done); --HB1L7 is system_0:u0|sdram_0:the_sdram_0|LessThan~82 HB1L7 = HB1_i_count[2] # HB1_i_count[1]; --HB1L106 is system_0:u0|sdram_0:the_sdram_0|Select~8210 HB1L106 = !HB1_i_state.111 & !HB1_i_state.010; --HB1L107 is system_0:u0|sdram_0:the_sdram_0|Select~8211 HB1L107 = HB1_i_state.001 # HB1_i_state.011 & HB1L7 # !HB1L106; --HB1_i_next.000 is system_0:u0|sdram_0:the_sdram_0|i_next.000 HB1_i_next.000 = DFFEAS(HB1L280, F1__clk1, N1_data_out, , , , , , ); --HB1L108 is system_0:u0|sdram_0:the_sdram_0|Select~8212 HB1L108 = HB1L102 & HB1_i_next.000 & (HB1_i_state.000 # HB1L5) # !HB1L102 & (HB1_i_state.000 # HB1L5); --HB1_i_next.010 is system_0:u0|sdram_0:the_sdram_0|i_next.010 HB1_i_next.010 = DFFEAS(HB1L171, F1__clk1, N1_data_out, , , , , , ); --HB1L109 is system_0:u0|sdram_0:the_sdram_0|Select~8213 HB1L109 = HB1_i_state.011 & HB1_i_next.010 & !HB1_i_count[2] & !HB1_i_count[1]; --HB1L110 is system_0:u0|sdram_0:the_sdram_0|Select~8214 HB1L110 = HB1L5 & !HB1_i_state.000; --HB1L233 is system_0:u0|sdram_0:the_sdram_0|add~392 HB1L233 = HB1_refresh_counter[0] $ VCC; --HB1L234 is system_0:u0|sdram_0:the_sdram_0|add~393 HB1L234 = CARRY(HB1_refresh_counter[0]); --HB1L235 is system_0:u0|sdram_0:the_sdram_0|add~394 HB1L235 = HB1_refresh_counter[1] & HB1L234 & VCC # !HB1_refresh_counter[1] & !HB1L234; --HB1L236 is system_0:u0|sdram_0:the_sdram_0|add~395 HB1L236 = CARRY(!HB1_refresh_counter[1] & !HB1L234); --HB1L237 is system_0:u0|sdram_0:the_sdram_0|add~396 HB1L237 = HB1_refresh_counter[2] & (GND # !HB1L236) # !HB1_refresh_counter[2] & (HB1L236 $ GND); --HB1L238 is system_0:u0|sdram_0:the_sdram_0|add~397 HB1L238 = CARRY(HB1_refresh_counter[2] # !HB1L236); --HB1L239 is system_0:u0|sdram_0:the_sdram_0|add~398 HB1L239 = HB1_refresh_counter[3] & HB1L238 & VCC # !HB1_refresh_counter[3] & !HB1L238; --HB1L240 is system_0:u0|sdram_0:the_sdram_0|add~399 HB1L240 = CARRY(!HB1_refresh_counter[3] & !HB1L238); --HB1L241 is system_0:u0|sdram_0:the_sdram_0|add~400 HB1L241 = HB1_refresh_counter[4] & (HB1L240 $ GND) # !HB1_refresh_counter[4] & (GND # !HB1L240); --HB1L242 is system_0:u0|sdram_0:the_sdram_0|add~401 HB1L242 = CARRY(!HB1L240 # !HB1_refresh_counter[4]); --HB1L243 is system_0:u0|sdram_0:the_sdram_0|add~402 HB1L243 = HB1_refresh_counter[5] & HB1L242 & VCC # !HB1_refresh_counter[5] & !HB1L242; --HB1L244 is system_0:u0|sdram_0:the_sdram_0|add~403 HB1L244 = CARRY(!HB1_refresh_counter[5] & !HB1L242); --HB1L245 is system_0:u0|sdram_0:the_sdram_0|add~404 HB1L245 = HB1_refresh_counter[6] & (GND # !HB1L244) # !HB1_refresh_counter[6] & (HB1L244 $ GND); --HB1L246 is system_0:u0|sdram_0:the_sdram_0|add~405 HB1L246 = CARRY(HB1_refresh_counter[6] # !HB1L244); --HB1L247 is system_0:u0|sdram_0:the_sdram_0|add~406 HB1L247 = HB1_refresh_counter[7] & HB1L246 & VCC # !HB1_refresh_counter[7] & !HB1L246; --HB1L248 is system_0:u0|sdram_0:the_sdram_0|add~407 HB1L248 = CARRY(!HB1_refresh_counter[7] & !HB1L246); --HB1L249 is system_0:u0|sdram_0:the_sdram_0|add~408 HB1L249 = HB1_refresh_counter[8] & (HB1L248 $ GND) # !HB1_refresh_counter[8] & (GND # !HB1L248); --HB1L250 is system_0:u0|sdram_0:the_sdram_0|add~409 HB1L250 = CARRY(!HB1L248 # !HB1_refresh_counter[8]); --HB1L251 is system_0:u0|sdram_0:the_sdram_0|add~410 HB1L251 = HB1_refresh_counter[9] & !HB1L250 # !HB1_refresh_counter[9] & HB1L250 & VCC; --HB1L252 is system_0:u0|sdram_0:the_sdram_0|add~411 HB1L252 = CARRY(HB1_refresh_counter[9] & !HB1L250); --HB1L253 is system_0:u0|sdram_0:the_sdram_0|add~412 HB1L253 = HB1_refresh_counter[10] & (HB1L252 $ GND) # !HB1_refresh_counter[10] & (GND # !HB1L252); --HB1L254 is system_0:u0|sdram_0:the_sdram_0|add~413 HB1L254 = CARRY(!HB1L252 # !HB1_refresh_counter[10]); --HB1L255 is system_0:u0|sdram_0:the_sdram_0|add~414 HB1L255 = HB1_refresh_counter[11] & HB1L254 & VCC # !HB1_refresh_counter[11] & !HB1L254; --HB1L256 is system_0:u0|sdram_0:the_sdram_0|add~415 HB1L256 = CARRY(!HB1_refresh_counter[11] & !HB1L254); --HB1L257 is system_0:u0|sdram_0:the_sdram_0|add~416 HB1L257 = HB1_refresh_counter[12] & (GND # !HB1L256) # !HB1_refresh_counter[12] & (HB1L256 $ GND); --HB1L258 is system_0:u0|sdram_0:the_sdram_0|add~417 HB1L258 = CARRY(HB1_refresh_counter[12] # !HB1L256); --HB1L259 is system_0:u0|sdram_0:the_sdram_0|add~418 HB1L259 = HB1_refresh_counter[13] $ HB1L258; --HB1L412 is system_0:u0|sdram_0:the_sdram_0|refresh_counter~486 HB1L412 = HB1L5 # !HB1L259; --HB1L413 is system_0:u0|sdram_0:the_sdram_0|refresh_counter~487 HB1L413 = HB1L257 & !HB1L5; --HB1L414 is system_0:u0|sdram_0:the_sdram_0|refresh_counter~488 HB1L414 = HB1L255 & !HB1L5; --HB1L415 is system_0:u0|sdram_0:the_sdram_0|refresh_counter~489 HB1L415 = HB1L5 # !HB1L249; --HB1L416 is system_0:u0|sdram_0:the_sdram_0|refresh_counter~490 HB1L416 = HB1L247 & !HB1L5; --HB1L417 is system_0:u0|sdram_0:the_sdram_0|refresh_counter~491 HB1L417 = HB1L245 & !HB1L5; --HB1L418 is system_0:u0|sdram_0:the_sdram_0|refresh_counter~492 HB1L418 = HB1L243 & !HB1L5; --HB1L419 is system_0:u0|sdram_0:the_sdram_0|refresh_counter~493 HB1L419 = HB1L237 & !HB1L5; --HB1L420 is system_0:u0|sdram_0:the_sdram_0|refresh_counter~494 HB1L420 = HB1L233 & !HB1L5; --HB1L111 is system_0:u0|sdram_0:the_sdram_0|Select~8215 HB1L111 = HB1_m_state.000000001 & (HB1_ack_refresh_request # HB1_m_state.010000000) # !HB1_m_state.000000001 & HB1_ack_refresh_request & (!HB1_init_done); --MB1L133 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_counter_enable~22 MB1L133 = !MB1L146 & (MB1L76 # !MB1L33 & !MB1L43); --MB1L138 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter_next_value[0]~224 MB1L138 = MB1L140 & (MB1L148 & (!MB1_tri_state_bridge_0_avalon_slave_arb_share_counter[0]) # !MB1L148 & MB1L76); --MB1L143 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_winner~0 MB1L143 = MB1L76 & !MB1L148; --JB1L56 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_counter_enable~22 JB1L56 = !JB1L68 & (!JB1_cpu_0_data_master_qualified_request_sdram_0_s1 & !JB1L18 # !JB1L3); --JB1L62 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_share_counter_next_value[0]~175 JB1L62 = JB1L61 & (JB1L69 & (!JB1_sdram_0_s1_arb_share_counter[0]) # !JB1L69 & !JB1L3); --JB1L63 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_share_counter_next_value[1]~176 JB1L63 = JB1L61 & (JB1L4 $ (!JB1L2 & !JB1L66)); --HB1_rd_valid[1] is system_0:u0|sdram_0:the_sdram_0|rd_valid[1] HB1_rd_valid[1] = DFFEAS(HB1_rd_valid[0], F1__clk1, N1_data_out, , , , , , ); --HE1_stage_2 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|stage_2 HE1_stage_2 = DFFEAS(HE1L32, F1__clk1, , , HE1L18, , , , ); --JE1_full_2 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_2 JE1_full_2 = DFFEAS(HE1L31, F1__clk1, N1_data_out, , HE1L14, , , , ); --HE1L30 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|p1_stage_1~10 HE1L30 = JE1_full_2 & HE1_stage_2 # !JE1_full_2 & (JB1L7); --HE1L19 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|always10~1 HE1L19 = HB1_za_valid # JB1L5 & !JE1_full_1; --HE1L29 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|p1_full_1~9 HE1L29 = HB1_za_valid & (JB1L5 & JE1_full_0 # !JB1L5 & (JE1_full_2)) # !HB1_za_valid & JE1_full_0; --HE1L14 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|always1~3 HE1L14 = HB1_za_valid & (!JE1_full_0 # !JB1L5) # !HB1_za_valid & JB1L5; --HE1L27 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|p0_full_0~1 HE1L27 = JB1L5 # JE1_full_1 # !HB1_za_valid; --Z1_E_ctrl_dst_data_sel_logic_result is system_0:u0|cpu_0:the_cpu_0|E_ctrl_dst_data_sel_logic_result Z1_E_ctrl_dst_data_sel_logic_result = AMPP_FUNCTION(F1__clk1, Z1_D_ctrl_dst_data_sel_logic_result, N1_data_out, Z1_A_stall); --Z1_E_ctrl_dst_data_sel_pc_plus_one is system_0:u0|cpu_0:the_cpu_0|E_ctrl_dst_data_sel_pc_plus_one Z1_E_ctrl_dst_data_sel_pc_plus_one = AMPP_FUNCTION(F1__clk1, Z1L1033, N1_data_out, Z1_A_stall); --Z1L1423 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[11]~6718 Z1L1423 = AMPP_FUNCTION(Z1_E_ctrl_dst_data_sel_logic_result, Z1_E_ctrl_alu_subtract, Z1_E_ctrl_dst_data_sel_pc_plus_one); --Z1_E_extra_pc[20] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[20] Z1_E_extra_pc[20] = AMPP_FUNCTION(F1__clk1, Z1L1097, N1_data_out, Z1_A_stall); --Z1L1479 is system_0:u0|cpu_0:the_cpu_0|E_alu_result~6719 Z1L1479 = AMPP_FUNCTION(Z1_E_ctrl_dst_data_sel_pc_plus_one, Z1_E_ctrl_dst_data_sel_logic_result); --Z1L1457 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[22]~6720 Z1L1457 = AMPP_FUNCTION(Z1L1423, Z1_E_extra_pc[20], Z1L1479, Z1L2916); --Z1L1458 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[22]~6721 Z1L1458 = AMPP_FUNCTION(Z1L2850, Z1L1423, Z1L1457, Z1L1635); --Z1_E_ctrl_dst_data_sel_cmp is system_0:u0|cpu_0:the_cpu_0|E_ctrl_dst_data_sel_cmp Z1_E_ctrl_dst_data_sel_cmp = AMPP_FUNCTION(F1__clk1, Z1L1029, N1_data_out, Z1_A_stall); --Z1L1459 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[22]~6722 Z1L1459 = AMPP_FUNCTION(Z1L1458, Z1_E_ctrl_dst_data_sel_cmp); --Z1L3020 is system_0:u0|cpu_0:the_cpu_0|always95~36 Z1L3020 = AMPP_FUNCTION(Z1_M_valid_from_E, Z1_A_stall); --Z1_M_ctrl_shift_rot is system_0:u0|cpu_0:the_cpu_0|M_ctrl_shift_rot Z1_M_ctrl_shift_rot = AMPP_FUNCTION(F1__clk1, Z1_E_ctrl_shift_rot, N1_data_out, Z1_A_stall); --Z1_A_shift_rot_cnt is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_cnt Z1_A_shift_rot_cnt = AMPP_FUNCTION(F1__clk1, Z1L615, N1_data_out); --Z1L714 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_stall_nxt~69 Z1L714 = AMPP_FUNCTION(Z1L3020, Z1_M_ctrl_shift_rot, Z1_A_shift_rot_stall, Z1_A_shift_rot_cnt); --Z1_A_mul_cnt[1] is system_0:u0|cpu_0:the_cpu_0|A_mul_cnt[1] Z1_A_mul_cnt[1] = AMPP_FUNCTION(F1__clk1, Z1L222, N1_data_out); --Z1_A_mul_cnt[2] is system_0:u0|cpu_0:the_cpu_0|A_mul_cnt[2] Z1_A_mul_cnt[2] = AMPP_FUNCTION(F1__clk1, Z1L223, N1_data_out); --Z1_A_mul_cnt[0] is system_0:u0|cpu_0:the_cpu_0|A_mul_cnt[0] Z1_A_mul_cnt[0] = AMPP_FUNCTION(F1__clk1, Z1L221, N1_data_out); --Z1L520 is system_0:u0|cpu_0:the_cpu_0|A_mul_stall_nxt~147 Z1L520 = AMPP_FUNCTION(Z1_A_mul_cnt[1], Z1_A_mul_cnt[2], Z1_A_mul_cnt[0]); --Z1_M_ctrl_mul_lsw is system_0:u0|cpu_0:the_cpu_0|M_ctrl_mul_lsw Z1_M_ctrl_mul_lsw = AMPP_FUNCTION(F1__clk1, Z1_E_ctrl_mul_lsw, N1_data_out, Z1_A_stall); --Z1L521 is system_0:u0|cpu_0:the_cpu_0|A_mul_stall_nxt~148 Z1L521 = AMPP_FUNCTION(Z1L520, Z1L3020, Z1_M_ctrl_mul_lsw, Z1_A_mul_stall); --Z1_A_ctrl_ld_bypass is system_0:u0|cpu_0:the_cpu_0|A_ctrl_ld_bypass Z1_A_ctrl_ld_bypass = AMPP_FUNCTION(F1__clk1, Z1_M_ctrl_ld_bypass, N1_data_out, Z1_A_stall); --Z1_A_dc_fill_wr_en is system_0:u0|cpu_0:the_cpu_0|A_dc_fill_wr_en Z1_A_dc_fill_wr_en = AMPP_FUNCTION(Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_M_ctrl_initd_flushd_flushda is system_0:u0|cpu_0:the_cpu_0|M_ctrl_initd_flushd_flushda Z1_M_ctrl_initd_flushd_flushda = AMPP_FUNCTION(F1__clk1, Z1L1522, N1_data_out, Z1_A_stall); --Z1_M_ctrl_st_non_bypass is system_0:u0|cpu_0:the_cpu_0|M_ctrl_st_non_bypass Z1_M_ctrl_st_non_bypass = AMPP_FUNCTION(F1__clk1, Z1L1551, N1_data_out, Z1_A_stall); --Z1L3197 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_en~173 Z1L3197 = AMPP_FUNCTION(Z1_M_ctrl_initd_flushd_flushda, Z1_M_sel_data_master, Z1_M_ctrl_st_non_bypass); --Z1L3198 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_en~174 Z1L3198 = AMPP_FUNCTION(Z1_A_dc_fill_wr_en, Z1_M_valid_from_E, Z1L3197, Z1_A_stall); --Z1L1553 is system_0:u0|cpu_0:the_cpu_0|E_dc_line[0]~81 Z1L1553 = AMPP_FUNCTION(Z1L2810, Z1L2876, Z1_E_ctrl_alu_subtract); --Z1L1554 is system_0:u0|cpu_0:the_cpu_0|E_dc_line[1]~82 Z1L1554 = AMPP_FUNCTION(Z1L2812, Z1L2878, Z1_E_ctrl_alu_subtract); --Z1L1555 is system_0:u0|cpu_0:the_cpu_0|E_dc_line[2]~83 Z1L1555 = AMPP_FUNCTION(Z1L2814, Z1L2880, Z1_E_ctrl_alu_subtract); --Z1L1556 is system_0:u0|cpu_0:the_cpu_0|E_dc_line[3]~84 Z1L1556 = AMPP_FUNCTION(Z1L2816, Z1L2882, Z1_E_ctrl_alu_subtract); --Z1L1557 is system_0:u0|cpu_0:the_cpu_0|E_dc_line[4]~85 Z1L1557 = AMPP_FUNCTION(Z1L2818, Z1L2884, Z1_E_ctrl_alu_subtract); --Z1L1558 is system_0:u0|cpu_0:the_cpu_0|E_dc_line[5]~86 Z1L1558 = AMPP_FUNCTION(Z1L2820, Z1L2886, Z1_E_ctrl_alu_subtract); --Z1L1559 is system_0:u0|cpu_0:the_cpu_0|E_dc_line[6]~87 Z1L1559 = AMPP_FUNCTION(Z1L2822, Z1L2888, Z1_E_ctrl_alu_subtract); --Z1L1560 is system_0:u0|cpu_0:the_cpu_0|E_dc_line[7]~88 Z1L1560 = AMPP_FUNCTION(Z1L2824, Z1L2890, Z1_E_ctrl_alu_subtract); --Z1L1561 is system_0:u0|cpu_0:the_cpu_0|E_dc_line[8]~89 Z1L1561 = AMPP_FUNCTION(Z1L2826, Z1L2892, Z1_E_ctrl_alu_subtract); --Z1L3236 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_data[11]~593 Z1L3236 = AMPP_FUNCTION(Z1_M_alu_result[22], Z1_A_mem_baddr[22], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3216 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_addr[0]~378 Z1L3216 = AMPP_FUNCTION(Z1_M_alu_result[2], Z1_A_mem_baddr[2], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3217 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_addr[1]~379 Z1L3217 = AMPP_FUNCTION(Z1_M_alu_result[3], Z1_A_mem_baddr[3], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3218 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_addr[2]~380 Z1L3218 = AMPP_FUNCTION(Z1_M_alu_result[4], Z1_A_mem_baddr[4], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3219 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_addr[3]~381 Z1L3219 = AMPP_FUNCTION(Z1_M_alu_result[5], Z1_A_mem_baddr[5], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3220 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_addr[4]~382 Z1L3220 = AMPP_FUNCTION(Z1_M_alu_result[6], Z1_A_mem_baddr[6], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3221 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_addr[5]~383 Z1L3221 = AMPP_FUNCTION(Z1_M_alu_result[7], Z1_A_mem_baddr[7], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3222 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_addr[6]~384 Z1L3222 = AMPP_FUNCTION(Z1_M_alu_result[8], Z1_A_mem_baddr[8], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3223 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_addr[7]~385 Z1L3223 = AMPP_FUNCTION(Z1_M_alu_result[9], Z1_A_mem_baddr[9], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3224 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_addr[8]~386 Z1L3224 = AMPP_FUNCTION(Z1_M_alu_result[10], Z1_A_mem_baddr[10], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_E_extra_pc[8] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[8] Z1_E_extra_pc[8] = AMPP_FUNCTION(F1__clk1, Z1L1085, N1_data_out, Z1_A_stall); --Z1L1421 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[10]~6723 Z1L1421 = AMPP_FUNCTION(Z1_E_extra_pc[8], Z1L1561, Z1_E_ctrl_dst_data_sel_pc_plus_one); --Z1L1422 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[10]~6724 Z1L1422 = AMPP_FUNCTION(Z1L1623, Z1L1421, Z1_E_ctrl_dst_data_sel_logic_result, Z1_E_ctrl_dst_data_sel_cmp); --Z1_E_extra_pc[6] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[6] Z1_E_extra_pc[6] = AMPP_FUNCTION(F1__clk1, Z1L1083, N1_data_out, Z1_A_stall); --Z1L1417 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[8]~6725 Z1L1417 = AMPP_FUNCTION(Z1_E_extra_pc[6], Z1L1559, Z1_E_ctrl_dst_data_sel_pc_plus_one); --Z1L1418 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[8]~6726 Z1L1418 = AMPP_FUNCTION(Z1L1621, Z1L1417, Z1_E_ctrl_dst_data_sel_logic_result, Z1_E_ctrl_dst_data_sel_cmp); --Z1_E_extra_pc[1] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[1] Z1_E_extra_pc[1] = AMPP_FUNCTION(F1__clk1, Z1L1078, N1_data_out, Z1_A_stall); --Z1L1407 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[3]~6727 Z1L1407 = AMPP_FUNCTION(Z1_E_extra_pc[1], Z1L1554, Z1_E_ctrl_dst_data_sel_pc_plus_one); --Z1L1408 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[3]~6728 Z1L1408 = AMPP_FUNCTION(Z1L1616, Z1L1407, Z1_E_ctrl_dst_data_sel_logic_result, Z1_E_ctrl_dst_data_sel_cmp); --Z1_E_extra_pc[0] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[0] Z1_E_extra_pc[0] = AMPP_FUNCTION(F1__clk1, Z1L1077, N1_data_out, Z1_A_stall); --Z1L1405 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[2]~6729 Z1L1405 = AMPP_FUNCTION(Z1_E_extra_pc[0], Z1L1553, Z1_E_ctrl_dst_data_sel_pc_plus_one); --Z1L1406 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[2]~6730 Z1L1406 = AMPP_FUNCTION(Z1L1615, Z1L1405, Z1_E_ctrl_dst_data_sel_logic_result, Z1_E_ctrl_dst_data_sel_cmp); --Z1_E_extra_pc[4] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[4] Z1_E_extra_pc[4] = AMPP_FUNCTION(F1__clk1, Z1L1081, N1_data_out, Z1_A_stall); --Z1L1413 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[6]~6731 Z1L1413 = AMPP_FUNCTION(Z1_E_extra_pc[4], Z1L1557, Z1_E_ctrl_dst_data_sel_pc_plus_one); --Z1L1414 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[6]~6732 Z1L1414 = AMPP_FUNCTION(Z1L1619, Z1L1413, Z1_E_ctrl_dst_data_sel_logic_result, Z1_E_ctrl_dst_data_sel_cmp); --Z1_E_extra_pc[2] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[2] Z1_E_extra_pc[2] = AMPP_FUNCTION(F1__clk1, Z1L1079, N1_data_out, Z1_A_stall); --Z1L1409 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[4]~6733 Z1L1409 = AMPP_FUNCTION(Z1_E_extra_pc[2], Z1L1555, Z1_E_ctrl_dst_data_sel_pc_plus_one); --Z1L1410 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[4]~6734 Z1L1410 = AMPP_FUNCTION(Z1L1617, Z1L1409, Z1_E_ctrl_dst_data_sel_logic_result, Z1_E_ctrl_dst_data_sel_cmp); --Z1_E_extra_pc[5] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[5] Z1_E_extra_pc[5] = AMPP_FUNCTION(F1__clk1, Z1L1082, N1_data_out, Z1_A_stall); --Z1L1415 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[7]~6735 Z1L1415 = AMPP_FUNCTION(Z1_E_extra_pc[5], Z1L1558, Z1_E_ctrl_dst_data_sel_pc_plus_one); --Z1L1416 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[7]~6736 Z1L1416 = AMPP_FUNCTION(Z1L1620, Z1L1415, Z1_E_ctrl_dst_data_sel_logic_result, Z1_E_ctrl_dst_data_sel_cmp); --Z1_E_extra_pc[3] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[3] Z1_E_extra_pc[3] = AMPP_FUNCTION(F1__clk1, Z1L1080, N1_data_out, Z1_A_stall); --Z1L1411 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[5]~6737 Z1L1411 = AMPP_FUNCTION(Z1_E_extra_pc[3], Z1L1556, Z1_E_ctrl_dst_data_sel_pc_plus_one); --Z1L1412 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[5]~6738 Z1L1412 = AMPP_FUNCTION(Z1L1618, Z1L1411, Z1_E_ctrl_dst_data_sel_logic_result, Z1_E_ctrl_dst_data_sel_cmp); --Z1L74 is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_valid~78 Z1L74 = AMPP_FUNCTION(Z1L3198, Z1_A_stall, Z1_A_dc_latest_data_valid); --Z1_E_extra_pc[7] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[7] Z1_E_extra_pc[7] = AMPP_FUNCTION(F1__clk1, Z1L1084, N1_data_out, Z1_A_stall); --Z1L1419 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[9]~6739 Z1L1419 = AMPP_FUNCTION(Z1_E_extra_pc[7], Z1L1560, Z1_E_ctrl_dst_data_sel_pc_plus_one); --Z1L1420 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[9]~6740 Z1L1420 = AMPP_FUNCTION(Z1L1622, Z1L1419, Z1_E_ctrl_dst_data_sel_logic_result, Z1_E_ctrl_dst_data_sel_cmp); --Z1L1483 is system_0:u0|cpu_0:the_cpu_0|E_arith_result[31]~67 Z1L1483 = AMPP_FUNCTION(Z1L2868, Z1L2934, Z1_E_ctrl_alu_subtract); --Z1L1534 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_ld_non_io~38 Z1L1534 = AMPP_FUNCTION(Z1_E_iw[1], Z1_E_iw[0], Z1_E_iw[3], Z1_E_iw[4]); --Z1L1541 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_ld_st_non_io~33 Z1L1541 = AMPP_FUNCTION(Z1L1534, Z1_E_iw[0], Z1_E_iw[1], Z1_E_iw[5]); --Z1L1532 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_ld_io~92 Z1L1532 = AMPP_FUNCTION(Z1_E_iw[5], Z1_E_iw[4], Z1_E_iw[3], Z1_E_iw[2]); --Z1L1536 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_ld_st_bypass~128 Z1L1536 = AMPP_FUNCTION(Z1L1532, Z1_E_iw[5], Z1_E_iw[1]); --Z1L1537 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_ld_st_bypass~129 Z1L1537 = AMPP_FUNCTION(Z1_E_iw[0], Z1L1483, Z1L1541, Z1L1536); --Z1L1533 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_ld_io~93 Z1L1533 = AMPP_FUNCTION(Z1_E_iw[1], Z1_E_iw[0], Z1L1532); --Z1L1530 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_ld_bypass~1 Z1L1530 = AMPP_FUNCTION(Z1L1533, Z1L1483, Z1L1534, Z1_E_iw[5]); --Z1L1538 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_ld_st_non_bypass_non_st32~56 Z1L1538 = AMPP_FUNCTION(Z1_E_iw[2], Z1_E_iw[0], Z1_E_iw[4], Z1_E_iw[1]); --Z1L1539 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_ld_st_non_bypass_non_st32~57 Z1L1539 = AMPP_FUNCTION(Z1L1534, Z1L1538, Z1_E_iw[5], Z1L1483); --Z1_E_extra_pc[9] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[9] Z1_E_extra_pc[9] = AMPP_FUNCTION(F1__clk1, Z1L1086, N1_data_out, Z1_A_stall); --Z1L1424 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[11]~6741 Z1L1424 = AMPP_FUNCTION(Z1L1479, Z1L2828, Z1L1423, Z1L2894); --Z1L1425 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[11]~6742 Z1L1425 = AMPP_FUNCTION(Z1_E_extra_pc[9], Z1L1479, Z1L1424, Z1L1624); --Z1L1426 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[11]~6743 Z1L1426 = AMPP_FUNCTION(Z1L1425, Z1_E_ctrl_dst_data_sel_cmp); --Z1_E_extra_pc[21] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[21] Z1_E_extra_pc[21] = AMPP_FUNCTION(F1__clk1, Z1L1098, N1_data_out, Z1_A_stall); --Z1L1460 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[23]~6744 Z1L1460 = AMPP_FUNCTION(Z1L1479, Z1L2852, Z1L1423, Z1L2918); --Z1L1461 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[23]~6745 Z1L1461 = AMPP_FUNCTION(Z1_E_extra_pc[21], Z1L1479, Z1L1460, Z1L1636); --Z1L1462 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[23]~6746 Z1L1462 = AMPP_FUNCTION(Z1L1461, Z1_E_ctrl_dst_data_sel_cmp); --Z1_E_extra_pc[16] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[16] Z1_E_extra_pc[16] = AMPP_FUNCTION(F1__clk1, Z1L1093, N1_data_out, Z1_A_stall); --Z1L1445 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[18]~6747 Z1L1445 = AMPP_FUNCTION(Z1L1423, Z1_E_extra_pc[16], Z1L1479, Z1L2908); --Z1L1446 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[18]~6748 Z1L1446 = AMPP_FUNCTION(Z1L2842, Z1L1423, Z1L1445, Z1L1631); --Z1L1447 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[18]~6749 Z1L1447 = AMPP_FUNCTION(Z1L1446, Z1_E_ctrl_dst_data_sel_cmp); --Z1_E_extra_pc[17] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[17] Z1_E_extra_pc[17] = AMPP_FUNCTION(F1__clk1, Z1L1094, N1_data_out, Z1_A_stall); --Z1L1448 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[19]~6750 Z1L1448 = AMPP_FUNCTION(Z1L1479, Z1L2844, Z1L1423, Z1L2910); --Z1L1449 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[19]~6751 Z1L1449 = AMPP_FUNCTION(Z1_E_extra_pc[17], Z1L1479, Z1L1448, Z1L1632); --Z1L1450 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[19]~6752 Z1L1450 = AMPP_FUNCTION(Z1L1449, Z1_E_ctrl_dst_data_sel_cmp); --Z1_E_extra_pc[15] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[15] Z1_E_extra_pc[15] = AMPP_FUNCTION(F1__clk1, Z1L1092, N1_data_out, Z1_A_stall); --Z1L1442 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[17]~6753 Z1L1442 = AMPP_FUNCTION(Z1L1479, Z1L2840, Z1L1423, Z1L2906); --Z1L1443 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[17]~6754 Z1L1443 = AMPP_FUNCTION(Z1_E_extra_pc[15], Z1L1479, Z1L1442, Z1L1630); --Z1L1444 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[17]~6755 Z1L1444 = AMPP_FUNCTION(Z1L1443, Z1_E_ctrl_dst_data_sel_cmp); --Z1_E_extra_pc[14] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[14] Z1_E_extra_pc[14] = AMPP_FUNCTION(F1__clk1, Z1L1091, N1_data_out, Z1_A_stall); --Z1L1439 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[16]~6756 Z1L1439 = AMPP_FUNCTION(Z1L1423, Z1_E_extra_pc[14], Z1L1479, Z1L2904); --Z1L1440 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[16]~6757 Z1L1440 = AMPP_FUNCTION(Z1L2838, Z1L1423, Z1L1439, Z1L1629); --Z1L1441 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[16]~6758 Z1L1441 = AMPP_FUNCTION(Z1L1440, Z1_E_ctrl_dst_data_sel_cmp); --Z1_E_extra_pc[11] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[11] Z1_E_extra_pc[11] = AMPP_FUNCTION(F1__clk1, Z1L1088, N1_data_out, Z1_A_stall); --Z1L1430 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[13]~6759 Z1L1430 = AMPP_FUNCTION(Z1L1479, Z1L2832, Z1L1423, Z1L2898); --Z1L1431 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[13]~6760 Z1L1431 = AMPP_FUNCTION(Z1_E_extra_pc[11], Z1L1479, Z1L1430, Z1L1626); --Z1L1432 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[13]~6761 Z1L1432 = AMPP_FUNCTION(Z1L1431, Z1_E_ctrl_dst_data_sel_cmp); --Z1_E_extra_pc[18] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[18] Z1_E_extra_pc[18] = AMPP_FUNCTION(F1__clk1, Z1L1095, N1_data_out, Z1_A_stall); --Z1L1451 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[20]~6762 Z1L1451 = AMPP_FUNCTION(Z1L1423, Z1_E_extra_pc[18], Z1L1479, Z1L2912); --Z1L1452 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[20]~6763 Z1L1452 = AMPP_FUNCTION(Z1L2846, Z1L1423, Z1L1451, Z1L1633); --Z1L1453 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[20]~6764 Z1L1453 = AMPP_FUNCTION(Z1L1452, Z1_E_ctrl_dst_data_sel_cmp); --Z1_E_extra_pc[19] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[19] Z1_E_extra_pc[19] = AMPP_FUNCTION(F1__clk1, Z1L1096, N1_data_out, Z1_A_stall); --Z1L1454 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[21]~6765 Z1L1454 = AMPP_FUNCTION(Z1L1479, Z1L2848, Z1L1423, Z1L2914); --Z1L1455 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[21]~6766 Z1L1455 = AMPP_FUNCTION(Z1_E_extra_pc[19], Z1L1479, Z1L1454, Z1L1634); --Z1L1456 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[21]~6767 Z1L1456 = AMPP_FUNCTION(Z1L1455, Z1_E_ctrl_dst_data_sel_cmp); --Z1_E_extra_pc[12] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[12] Z1_E_extra_pc[12] = AMPP_FUNCTION(F1__clk1, Z1L1089, N1_data_out, Z1_A_stall); --Z1L1433 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[14]~6768 Z1L1433 = AMPP_FUNCTION(Z1L1423, Z1_E_extra_pc[12], Z1L1479, Z1L2900); --Z1L1434 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[14]~6769 Z1L1434 = AMPP_FUNCTION(Z1L2834, Z1L1423, Z1L1433, Z1L1627); --Z1L1435 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[14]~6770 Z1L1435 = AMPP_FUNCTION(Z1L1434, Z1_E_ctrl_dst_data_sel_cmp); --Z1_E_extra_pc[10] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[10] Z1_E_extra_pc[10] = AMPP_FUNCTION(F1__clk1, Z1L1087, N1_data_out, Z1_A_stall); --Z1L1427 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[12]~6771 Z1L1427 = AMPP_FUNCTION(Z1L1423, Z1_E_extra_pc[10], Z1L1479, Z1L2896); --Z1L1428 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[12]~6772 Z1L1428 = AMPP_FUNCTION(Z1L2830, Z1L1423, Z1L1427, Z1L1625); --Z1L1429 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[12]~6773 Z1L1429 = AMPP_FUNCTION(Z1L1428, Z1_E_ctrl_dst_data_sel_cmp); --Z1_E_extra_pc[13] is system_0:u0|cpu_0:the_cpu_0|E_extra_pc[13] Z1_E_extra_pc[13] = AMPP_FUNCTION(F1__clk1, Z1L1090, N1_data_out, Z1_A_stall); --Z1L1436 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[15]~6774 Z1L1436 = AMPP_FUNCTION(Z1L1479, Z1L2836, Z1L1423, Z1L2902); --Z1L1437 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[15]~6775 Z1L1437 = AMPP_FUNCTION(Z1_E_extra_pc[13], Z1L1479, Z1L1436, Z1L1628); --Z1L1438 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[15]~6776 Z1L1438 = AMPP_FUNCTION(Z1L1437, Z1_E_ctrl_dst_data_sel_cmp); --Z1L1542 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_ld~28 Z1L1542 = AMPP_FUNCTION(Z1_E_iw[2], Z1_E_iw[1], Z1_E_iw[0], Z1_E_iw[4]); --Z1L3226 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_data[1]~594 Z1L3226 = AMPP_FUNCTION(Z1_M_alu_result[12], Z1_A_mem_baddr[12], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3230 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_data[5]~595 Z1L3230 = AMPP_FUNCTION(Z1_M_alu_result[16], Z1_A_mem_baddr[16], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3229 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_data[4]~596 Z1L3229 = AMPP_FUNCTION(Z1_M_alu_result[15], Z1_A_mem_baddr[15], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3232 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_data[7]~597 Z1L3232 = AMPP_FUNCTION(Z1_M_alu_result[18], Z1_A_mem_baddr[18], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3231 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_data[6]~598 Z1L3231 = AMPP_FUNCTION(Z1_M_alu_result[17], Z1_A_mem_baddr[17], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3234 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_data[9]~599 Z1L3234 = AMPP_FUNCTION(Z1_M_alu_result[20], Z1_A_mem_baddr[20], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3228 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_data[3]~600 Z1L3228 = AMPP_FUNCTION(Z1_M_alu_result[14], Z1_A_mem_baddr[14], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_M_ctrl_st is system_0:u0|cpu_0:the_cpu_0|M_ctrl_st Z1_M_ctrl_st = AMPP_FUNCTION(F1__clk1, Z1L1552, N1_data_out, Z1_A_stall); --Z1L3238 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_data[13]~601 Z1L3238 = AMPP_FUNCTION(Z1_M_ctrl_st, Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3225 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_data[0]~602 Z1L3225 = AMPP_FUNCTION(Z1_M_alu_result[11], Z1_A_mem_baddr[11], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3235 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_data[10]~603 Z1L3235 = AMPP_FUNCTION(Z1_M_alu_result[21], Z1_A_mem_baddr[21], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3237 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_data[12]~604 Z1L3237 = AMPP_FUNCTION(Z1_M_alu_result[23], Z1_A_mem_baddr[23], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3233 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_data[8]~605 Z1L3233 = AMPP_FUNCTION(Z1_M_alu_result[19], Z1_A_mem_baddr[19], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3227 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_data[2]~606 Z1L3227 = AMPP_FUNCTION(Z1_M_alu_result[13], Z1_A_mem_baddr[13], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L1521 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_flushd_flushda~35 Z1L1521 = AMPP_FUNCTION(Z1_E_iw[4], Z1_E_iw[3], Z1_E_iw[0]); --Z1L3239 is system_0:u0|cpu_0:the_cpu_0|dc_tag_portb_data[14]~607 Z1L3239 = AMPP_FUNCTION(Z1_M_ctrl_st, Z1_A_ctrl_st, Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L1552 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_st_non_io~22 Z1L1552 = AMPP_FUNCTION(Z1_E_iw[0], Z1_E_iw[1]); --Z1L1972 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[4]~1062 Z1L1972 = AMPP_FUNCTION(Z1L1101, Z1_D_ctrl_a_not_src, Z1_D_issue, Z1L966); --Z1L2939 is system_0:u0|cpu_0:the_cpu_0|add~3076 Z1L2939 = AMPP_FUNCTION(Z1_F_pc[0], GND); --Z1L2940 is system_0:u0|cpu_0:the_cpu_0|add~3077 Z1L2940 = AMPP_FUNCTION(Z1_F_pc[0]); --Z1L2941 is system_0:u0|cpu_0:the_cpu_0|add~3078 Z1L2941 = AMPP_FUNCTION(Z1_F_pc[1], GND, Z1L2940); --Z1L2942 is system_0:u0|cpu_0:the_cpu_0|add~3079 Z1L2942 = AMPP_FUNCTION(Z1_F_pc[1], Z1L2940); --Z1L2943 is system_0:u0|cpu_0:the_cpu_0|add~3080 Z1L2943 = AMPP_FUNCTION(Z1_F_pc[2], GND, Z1L2942); --Z1L2944 is system_0:u0|cpu_0:the_cpu_0|add~3081 Z1L2944 = AMPP_FUNCTION(Z1_F_pc[2], Z1L2942); --Z1L2945 is system_0:u0|cpu_0:the_cpu_0|add~3082 Z1L2945 = AMPP_FUNCTION(Z1_F_pc[3], GND, Z1L2944); --Z1L2946 is system_0:u0|cpu_0:the_cpu_0|add~3083 Z1L2946 = AMPP_FUNCTION(Z1_F_pc[3], Z1L2944); --Z1L2947 is system_0:u0|cpu_0:the_cpu_0|add~3084 Z1L2947 = AMPP_FUNCTION(Z1_F_pc[4], GND, Z1L2946); --Z1L2948 is system_0:u0|cpu_0:the_cpu_0|add~3085 Z1L2948 = AMPP_FUNCTION(Z1_F_pc[4], Z1L2946); --Z1L2949 is system_0:u0|cpu_0:the_cpu_0|add~3086 Z1L2949 = AMPP_FUNCTION(Z1_F_pc[5], GND, Z1L2948); --Z1L2950 is system_0:u0|cpu_0:the_cpu_0|add~3087 Z1L2950 = AMPP_FUNCTION(Z1_F_pc[5], Z1L2948); --Z1L2951 is system_0:u0|cpu_0:the_cpu_0|add~3088 Z1L2951 = AMPP_FUNCTION(Z1_F_pc[6], GND, Z1L2950); --Z1L2952 is system_0:u0|cpu_0:the_cpu_0|add~3089 Z1L2952 = AMPP_FUNCTION(Z1_F_pc[6], Z1L2950); --Z1L2953 is system_0:u0|cpu_0:the_cpu_0|add~3090 Z1L2953 = AMPP_FUNCTION(Z1_F_pc[7], GND, Z1L2952); --Z1L2954 is system_0:u0|cpu_0:the_cpu_0|add~3091 Z1L2954 = AMPP_FUNCTION(Z1_F_pc[7], Z1L2952); --Z1L2955 is system_0:u0|cpu_0:the_cpu_0|add~3092 Z1L2955 = AMPP_FUNCTION(Z1_F_pc[8], GND, Z1L2954); --Z1L2956 is system_0:u0|cpu_0:the_cpu_0|add~3093 Z1L2956 = AMPP_FUNCTION(Z1_F_pc[8], Z1L2954); --Z1L2957 is system_0:u0|cpu_0:the_cpu_0|add~3094 Z1L2957 = AMPP_FUNCTION(Z1_F_pc[9], GND, Z1L2956); --Z1L2958 is system_0:u0|cpu_0:the_cpu_0|add~3095 Z1L2958 = AMPP_FUNCTION(Z1_F_pc[9], Z1L2956); --Z1L2959 is system_0:u0|cpu_0:the_cpu_0|add~3096 Z1L2959 = AMPP_FUNCTION(Z1_F_pc[10], GND, Z1L2958); --Z1L2960 is system_0:u0|cpu_0:the_cpu_0|add~3097 Z1L2960 = AMPP_FUNCTION(Z1_F_pc[10], Z1L2958); --Z1L2961 is system_0:u0|cpu_0:the_cpu_0|add~3098 Z1L2961 = AMPP_FUNCTION(Z1_F_pc[11], GND, Z1L2960); --Z1L2962 is system_0:u0|cpu_0:the_cpu_0|add~3099 Z1L2962 = AMPP_FUNCTION(Z1_F_pc[11], Z1L2960); --Z1L2963 is system_0:u0|cpu_0:the_cpu_0|add~3100 Z1L2963 = AMPP_FUNCTION(Z1_F_pc[12], GND, Z1L2962); --Z1L2964 is system_0:u0|cpu_0:the_cpu_0|add~3101 Z1L2964 = AMPP_FUNCTION(Z1_F_pc[12], Z1L2962); --Z1L2965 is system_0:u0|cpu_0:the_cpu_0|add~3102 Z1L2965 = AMPP_FUNCTION(Z1_F_pc[13], GND, Z1L2964); --Z1L2966 is system_0:u0|cpu_0:the_cpu_0|add~3103 Z1L2966 = AMPP_FUNCTION(Z1_F_pc[13], Z1L2964); --Z1L2967 is system_0:u0|cpu_0:the_cpu_0|add~3104 Z1L2967 = AMPP_FUNCTION(Z1_F_pc[14], GND, Z1L2966); --Z1L2968 is system_0:u0|cpu_0:the_cpu_0|add~3105 Z1L2968 = AMPP_FUNCTION(Z1_F_pc[14], Z1L2966); --Z1L2969 is system_0:u0|cpu_0:the_cpu_0|add~3106 Z1L2969 = AMPP_FUNCTION(Z1_F_pc[15], GND, Z1L2968); --Z1L2970 is system_0:u0|cpu_0:the_cpu_0|add~3107 Z1L2970 = AMPP_FUNCTION(Z1_F_pc[15], Z1L2968); --Z1L2971 is system_0:u0|cpu_0:the_cpu_0|add~3108 Z1L2971 = AMPP_FUNCTION(Z1_F_pc[16], GND, Z1L2970); --Z1L2972 is system_0:u0|cpu_0:the_cpu_0|add~3109 Z1L2972 = AMPP_FUNCTION(Z1_F_pc[16], Z1L2970); --Z1L2973 is system_0:u0|cpu_0:the_cpu_0|add~3110 Z1L2973 = AMPP_FUNCTION(Z1_F_pc[17], GND, Z1L2972); --Z1L2974 is system_0:u0|cpu_0:the_cpu_0|add~3111 Z1L2974 = AMPP_FUNCTION(Z1_F_pc[17], Z1L2972); --Z1L2975 is system_0:u0|cpu_0:the_cpu_0|add~3112 Z1L2975 = AMPP_FUNCTION(Z1_F_pc[18], GND, Z1L2974); --Z1L2976 is system_0:u0|cpu_0:the_cpu_0|add~3113 Z1L2976 = AMPP_FUNCTION(Z1_F_pc[18], Z1L2974); --Z1L2977 is system_0:u0|cpu_0:the_cpu_0|add~3114 Z1L2977 = AMPP_FUNCTION(Z1_F_pc[19], GND, Z1L2976); --Z1L2978 is system_0:u0|cpu_0:the_cpu_0|add~3115 Z1L2978 = AMPP_FUNCTION(Z1_F_pc[19], Z1L2976); --Z1L2979 is system_0:u0|cpu_0:the_cpu_0|add~3116 Z1L2979 = AMPP_FUNCTION(Z1_F_pc[20], GND, Z1L2978); --Z1L2980 is system_0:u0|cpu_0:the_cpu_0|add~3117 Z1L2980 = AMPP_FUNCTION(Z1_F_pc[20], Z1L2978); --Z1_D_pc_plus_one[20] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[20] Z1_D_pc_plus_one[20] = AMPP_FUNCTION(F1__clk1, Z1L2979, N1_data_out, Z1_F_stall); --Z1_D_iw[21] is system_0:u0|cpu_0:the_cpu_0|D_iw[21] Z1_D_iw[21] = AMPP_FUNCTION(F1__clk1, Z1L2014, N1_data_out, Z1_F_stall); --Z1_D_pc_plus_one[19] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[19] Z1_D_pc_plus_one[19] = AMPP_FUNCTION(F1__clk1, Z1L2977, N1_data_out, Z1_F_stall); --Z1_D_pc_plus_one[18] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[18] Z1_D_pc_plus_one[18] = AMPP_FUNCTION(F1__clk1, Z1L2975, N1_data_out, Z1_F_stall); --Z1_D_pc_plus_one[17] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[17] Z1_D_pc_plus_one[17] = AMPP_FUNCTION(F1__clk1, Z1L2973, N1_data_out, Z1_F_stall); --Z1_D_pc_plus_one[16] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[16] Z1_D_pc_plus_one[16] = AMPP_FUNCTION(F1__clk1, Z1L2971, N1_data_out, Z1_F_stall); --Z1_D_pc_plus_one[15] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[15] Z1_D_pc_plus_one[15] = AMPP_FUNCTION(F1__clk1, Z1L2969, N1_data_out, Z1_F_stall); --Z1_D_pc_plus_one[14] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[14] Z1_D_pc_plus_one[14] = AMPP_FUNCTION(F1__clk1, Z1L2967, N1_data_out, Z1_F_stall); --Z1_D_pc_plus_one[13] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[13] Z1_D_pc_plus_one[13] = AMPP_FUNCTION(F1__clk1, Z1L2965, N1_data_out, Z1_F_stall); --Z1_D_pc_plus_one[12] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[12] Z1_D_pc_plus_one[12] = AMPP_FUNCTION(F1__clk1, Z1L2963, N1_data_out, Z1_F_stall); --Z1_D_iw[20] is system_0:u0|cpu_0:the_cpu_0|D_iw[20] Z1_D_iw[20] = AMPP_FUNCTION(F1__clk1, Z1L2013, N1_data_out, Z1_F_stall); --Z1_D_pc_plus_one[11] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[11] Z1_D_pc_plus_one[11] = AMPP_FUNCTION(F1__clk1, Z1L2961, N1_data_out, Z1_F_stall); --Z1_D_iw[19] is system_0:u0|cpu_0:the_cpu_0|D_iw[19] Z1_D_iw[19] = AMPP_FUNCTION(F1__clk1, Z1L2012, N1_data_out, Z1_F_stall); --Z1_D_pc_plus_one[10] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[10] Z1_D_pc_plus_one[10] = AMPP_FUNCTION(F1__clk1, Z1L2959, N1_data_out, Z1_F_stall); --Z1_D_iw[18] is system_0:u0|cpu_0:the_cpu_0|D_iw[18] Z1_D_iw[18] = AMPP_FUNCTION(F1__clk1, Z1L2011, N1_data_out, Z1_F_stall); --Z1_D_br_taken_waddr_partial[10] is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[10] Z1_D_br_taken_waddr_partial[10] = AMPP_FUNCTION(F1__clk1, Z1L999, N1_data_out, Z1_F_stall); --Z1L2982 is system_0:u0|cpu_0:the_cpu_0|add~3119 Z1L2982 = AMPP_FUNCTION(Z1_D_br_taken_waddr_partial[10]); --Z1L2983 is system_0:u0|cpu_0:the_cpu_0|add~3120 Z1L2983 = AMPP_FUNCTION(Z1_D_pc_plus_one[10], Z1_D_iw[18], GND, Z1L2982); --Z1L2984 is system_0:u0|cpu_0:the_cpu_0|add~3121 Z1L2984 = AMPP_FUNCTION(Z1_D_pc_plus_one[10], Z1_D_iw[18], Z1L2982); --Z1L2985 is system_0:u0|cpu_0:the_cpu_0|add~3122 Z1L2985 = AMPP_FUNCTION(Z1_D_pc_plus_one[11], Z1_D_iw[19], GND, Z1L2984); --Z1L2986 is system_0:u0|cpu_0:the_cpu_0|add~3123 Z1L2986 = AMPP_FUNCTION(Z1_D_pc_plus_one[11], Z1_D_iw[19], Z1L2984); --Z1L2987 is system_0:u0|cpu_0:the_cpu_0|add~3124 Z1L2987 = AMPP_FUNCTION(Z1_D_pc_plus_one[12], Z1_D_iw[20], GND, Z1L2986); --Z1L2988 is system_0:u0|cpu_0:the_cpu_0|add~3125 Z1L2988 = AMPP_FUNCTION(Z1_D_pc_plus_one[12], Z1_D_iw[20], Z1L2986); --Z1L2989 is system_0:u0|cpu_0:the_cpu_0|add~3126 Z1L2989 = AMPP_FUNCTION(Z1_D_pc_plus_one[13], Z1_D_iw[21], GND, Z1L2988); --Z1L2990 is system_0:u0|cpu_0:the_cpu_0|add~3127 Z1L2990 = AMPP_FUNCTION(Z1_D_pc_plus_one[13], Z1_D_iw[21], Z1L2988); --Z1L2991 is system_0:u0|cpu_0:the_cpu_0|add~3128 Z1L2991 = AMPP_FUNCTION(Z1_D_pc_plus_one[14], Z1_D_iw[21], GND, Z1L2990); --Z1L2992 is system_0:u0|cpu_0:the_cpu_0|add~3129 Z1L2992 = AMPP_FUNCTION(Z1_D_pc_plus_one[14], Z1_D_iw[21], Z1L2990); --Z1L2993 is system_0:u0|cpu_0:the_cpu_0|add~3130 Z1L2993 = AMPP_FUNCTION(Z1_D_pc_plus_one[15], Z1_D_iw[21], GND, Z1L2992); --Z1L2994 is system_0:u0|cpu_0:the_cpu_0|add~3131 Z1L2994 = AMPP_FUNCTION(Z1_D_pc_plus_one[15], Z1_D_iw[21], Z1L2992); --Z1L2995 is system_0:u0|cpu_0:the_cpu_0|add~3132 Z1L2995 = AMPP_FUNCTION(Z1_D_pc_plus_one[16], Z1_D_iw[21], GND, Z1L2994); --Z1L2996 is system_0:u0|cpu_0:the_cpu_0|add~3133 Z1L2996 = AMPP_FUNCTION(Z1_D_pc_plus_one[16], Z1_D_iw[21], Z1L2994); --Z1L2997 is system_0:u0|cpu_0:the_cpu_0|add~3134 Z1L2997 = AMPP_FUNCTION(Z1_D_pc_plus_one[17], Z1_D_iw[21], GND, Z1L2996); --Z1L2998 is system_0:u0|cpu_0:the_cpu_0|add~3135 Z1L2998 = AMPP_FUNCTION(Z1_D_pc_plus_one[17], Z1_D_iw[21], Z1L2996); --Z1L2999 is system_0:u0|cpu_0:the_cpu_0|add~3136 Z1L2999 = AMPP_FUNCTION(Z1_D_pc_plus_one[18], Z1_D_iw[21], GND, Z1L2998); --Z1L3000 is system_0:u0|cpu_0:the_cpu_0|add~3137 Z1L3000 = AMPP_FUNCTION(Z1_D_pc_plus_one[18], Z1_D_iw[21], Z1L2998); --Z1L3001 is system_0:u0|cpu_0:the_cpu_0|add~3138 Z1L3001 = AMPP_FUNCTION(Z1_D_pc_plus_one[19], Z1_D_iw[21], GND, Z1L3000); --Z1L3002 is system_0:u0|cpu_0:the_cpu_0|add~3139 Z1L3002 = AMPP_FUNCTION(Z1_D_pc_plus_one[19], Z1_D_iw[21], Z1L3000); --Z1L3003 is system_0:u0|cpu_0:the_cpu_0|add~3140 Z1L3003 = AMPP_FUNCTION(Z1_D_pc_plus_one[20], Z1_D_iw[21], GND, Z1L3002); --Z1L3004 is system_0:u0|cpu_0:the_cpu_0|add~3141 Z1L3004 = AMPP_FUNCTION(Z1_D_pc_plus_one[20], Z1_D_iw[21], Z1L3002); --Z1L2062 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~344 Z1L2062 = AMPP_FUNCTION(Z1L1972, Z1L2979, Z1L1977, Z1L3003); --Z1_D_iw[26] is system_0:u0|cpu_0:the_cpu_0|D_iw[26] Z1_D_iw[26] = AMPP_FUNCTION(F1__clk1, Z1L2019, N1_data_out, Z1_F_stall); --Z1L2063 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~345 Z1L2063 = AMPP_FUNCTION(Z1_D_pc[20], Z1L1972, Z1L2062, Z1_D_iw[26]); --Z1L2064 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~346 Z1L2064 = AMPP_FUNCTION(Z1_E_src1[22], Z1L2063, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[20] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[20] Z1_M_pipe_flush_waddr[20] = AMPP_FUNCTION(F1__clk1, Z1L2398, Z1_E_pc[20], N1_data_out, Z1L2334, Z1_A_stall); --Z1L1143 is system_0:u0|cpu_0:the_cpu_0|D_op_call~825 Z1L1143 = AMPP_FUNCTION(Z1_D_iw[0], Z1_D_iw[1], Z1_D_iw[2], Z1_D_iw[3]); --Z1L1144 is system_0:u0|cpu_0:the_cpu_0|D_op_call~826 Z1L1144 = AMPP_FUNCTION(Z1_D_iw[5], Z1L1143); --Z1L1145 is system_0:u0|cpu_0:the_cpu_0|D_op_call~827 Z1L1145 = AMPP_FUNCTION(Z1_D_iw[0], Z1_D_iw[1], Z1_D_iw[2], Z1_D_iw[3]); --Z1L1146 is system_0:u0|cpu_0:the_cpu_0|D_op_call~828 Z1L1146 = AMPP_FUNCTION(Z1_D_iw[0], Z1_D_iw[1], Z1_D_iw[2], Z1_D_iw[3]); --Z1L1051 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_late_result~350 Z1L1051 = AMPP_FUNCTION(Z1L1144, Z1L1145, Z1L1146, Z1_D_iw[4]); --Z1L1052 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_late_result~351 Z1L1052 = AMPP_FUNCTION(Z1_D_iw[12], Z1_D_iw[4], Z1_D_iw[5], Z1L1141); --Z1L1895 is system_0:u0|cpu_0:the_cpu_0|Equal~6216 Z1L1895 = AMPP_FUNCTION(Z1_D_iw[16], Z1_D_iw[15], Z1_D_iw[14]); --Z1L1053 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_late_result~352 Z1L1053 = AMPP_FUNCTION(Z1_D_iw[11], Z1L1895, Z1_D_iw[13], Z1_D_iw[16]); --Z1L1896 is system_0:u0|cpu_0:the_cpu_0|Equal~6217 Z1L1896 = AMPP_FUNCTION(Z1_D_iw[12], Z1L1142, Z1_D_iw[11], Z1_D_iw[13]); --Z1L1061 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_src2_is_imm~128 Z1L1061 = AMPP_FUNCTION(Z1_D_iw[0], Z1_D_iw[1], Z1_D_iw[2], Z1L1896); --Z1L1054 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_late_result~353 Z1L1054 = AMPP_FUNCTION(Z1L1051, Z1L1052, Z1L1053, Z1L1061); --Z1_D_ctrl_ignore_dst is system_0:u0|cpu_0:the_cpu_0|D_ctrl_ignore_dst Z1_D_ctrl_ignore_dst = AMPP_FUNCTION(F1__clk1, Z1L1935, N1_data_out, Z1_F_stall); --Z1L1402 is system_0:u0|cpu_0:the_cpu_0|D_wr_dst_reg~19 Z1L1402 = AMPP_FUNCTION(Z1_M_pipe_flush, Z1_D_issue, Z1L1068, Z1_D_ctrl_ignore_dst); --Z1L1044 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_implicit_dst_eretaddr~106 Z1L1044 = AMPP_FUNCTION(Z1_D_iw[11], Z1_D_iw[12]); --Z1L1045 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_implicit_dst_eretaddr~107 Z1L1045 = AMPP_FUNCTION(Z1_D_iw[16], Z1_D_iw[15], Z1_D_iw[14], Z1_D_iw[12]); --Z1L1046 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_implicit_dst_eretaddr~108 Z1L1046 = AMPP_FUNCTION(Z1_D_iw[11], Z1L1045); --Z1L1026 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_break~27 Z1L1026 = AMPP_FUNCTION(Z1_D_iw[13], Z1_D_iw[4], Z1_D_iw[5], Z1L1141); --Z1L1073 is system_0:u0|cpu_0:the_cpu_0|D_dst_regnum[3]~490 Z1L1073 = AMPP_FUNCTION(Z1L1895, Z1L1044, Z1L1046, Z1L1026); --Z1L1074 is system_0:u0|cpu_0:the_cpu_0|D_dst_regnum[3]~491 Z1L1074 = AMPP_FUNCTION(Z1L1073, Z1L1048); --Z1L1076 is system_0:u0|cpu_0:the_cpu_0|D_dst_regnum[4]~492 Z1L1076 = AMPP_FUNCTION(Z1_D_iw[26], Z1_D_iw[21], Z1_D_ctrl_b_not_src, Z1L1074); --Z1_D_iw[24] is system_0:u0|cpu_0:the_cpu_0|D_iw[24] Z1_D_iw[24] = AMPP_FUNCTION(F1__clk1, Z1L2017, N1_data_out, Z1_F_stall); --Z1L1072 is system_0:u0|cpu_0:the_cpu_0|D_dst_regnum[2]~493 Z1L1072 = AMPP_FUNCTION(Z1_D_iw[24], Z1_D_iw[19], Z1_D_ctrl_b_not_src, Z1L1074); --Z1_D_iw[22] is system_0:u0|cpu_0:the_cpu_0|D_iw[22] Z1_D_iw[22] = AMPP_FUNCTION(F1__clk1, Z1L2015, N1_data_out, Z1_F_stall); --Z1_D_iw[17] is system_0:u0|cpu_0:the_cpu_0|D_iw[17] Z1_D_iw[17] = AMPP_FUNCTION(F1__clk1, Z1L2010, N1_data_out, Z1_F_stall); --Z1L1069 is system_0:u0|cpu_0:the_cpu_0|D_dst_regnum[0]~494 Z1L1069 = AMPP_FUNCTION(Z1_D_iw[22], Z1_D_iw[17], Z1_D_ctrl_b_not_src, Z1L1074); --Z1_D_iw[25] is system_0:u0|cpu_0:the_cpu_0|D_iw[25] Z1_D_iw[25] = AMPP_FUNCTION(F1__clk1, Z1L2018, N1_data_out, Z1_F_stall); --Z1L1075 is system_0:u0|cpu_0:the_cpu_0|D_dst_regnum[3]~495 Z1L1075 = AMPP_FUNCTION(Z1_D_iw[25], Z1_D_iw[20], Z1_D_ctrl_b_not_src, Z1L1074); --Z1_D_iw[23] is system_0:u0|cpu_0:the_cpu_0|D_iw[23] Z1_D_iw[23] = AMPP_FUNCTION(F1__clk1, Z1L2016, N1_data_out, Z1_F_stall); --Z1L1070 is system_0:u0|cpu_0:the_cpu_0|D_dst_regnum[1]~496 Z1L1070 = AMPP_FUNCTION(Z1L1073, Z1_D_iw[23], Z1_D_iw[18], Z1_D_ctrl_b_not_src); --Z1L1147 is system_0:u0|cpu_0:the_cpu_0|D_op_call~829 Z1L1147 = AMPP_FUNCTION(Z1_D_iw[0], Z1_D_iw[1], Z1_D_iw[2], Z1_D_iw[3]); --Z1L1148 is system_0:u0|cpu_0:the_cpu_0|D_op_call~830 Z1L1148 = AMPP_FUNCTION(Z1_D_iw[0], Z1_D_iw[1], Z1_D_iw[2], Z1_D_iw[3]); --Z1L1071 is system_0:u0|cpu_0:the_cpu_0|D_dst_regnum[1]~497 Z1L1071 = AMPP_FUNCTION(Z1L1070, Z1L1047, Z1L1147, Z1L1148); --Z1L1897 is system_0:u0|cpu_0:the_cpu_0|Equal~6218 Z1L1897 = AMPP_FUNCTION(Z1L1069, Z1L1075, Z1L1071); --Z1_D_wr_dst_reg is system_0:u0|cpu_0:the_cpu_0|D_wr_dst_reg Z1_D_wr_dst_reg = AMPP_FUNCTION(Z1L1402, Z1L1076, Z1L1072, Z1L1897); --JC1_q_a[27] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[27] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[27] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[27], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --JC1_q_a[31] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[31] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[31] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[31], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L1199 is system_0:u0|cpu_0:the_cpu_0|D_regnum_a_cmp_F~54 Z1L1199 = AMPP_FUNCTION(JC1_q_a[27], JC1_q_a[31], Z1L1076, Z1L1069); --JC1_q_a[28] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[28] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[28] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[28], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --JC1_q_a[30] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[30] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[30] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[30], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L1200 is system_0:u0|cpu_0:the_cpu_0|D_regnum_a_cmp_F~55 Z1L1200 = AMPP_FUNCTION(JC1_q_a[28], JC1_q_a[30], Z1L1075, Z1L1071); --JC1_q_a[29] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[29] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[29] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[29], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L1898 is system_0:u0|cpu_0:the_cpu_0|Equal~6219 Z1L1898 = AMPP_FUNCTION(JC1_q_a[29], Z1L1072); --Z1L1201 is system_0:u0|cpu_0:the_cpu_0|D_regnum_a_cmp_F~56 Z1L1201 = AMPP_FUNCTION(Z1_D_wr_dst_reg, Z1L1199, Z1L1200, Z1L1898); --JC1_q_a[2] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[2] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[2] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[2], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1_A_ipending_reg[3] is system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[3] Z1_A_ipending_reg[3] = AMPP_FUNCTION(F1__clk1, Z1L184, N1_data_out); --Z1_A_ipending_reg[2] is system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[2] Z1_A_ipending_reg[2] = AMPP_FUNCTION(F1__clk1, Z1L181, N1_data_out); --Z1_A_ipending_reg[1] is system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[1] Z1_A_ipending_reg[1] = AMPP_FUNCTION(F1__clk1, Z1L180, N1_data_out); --Z1_A_ipending_reg[0] is system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[0] Z1_A_ipending_reg[0] = AMPP_FUNCTION(F1__clk1, Z1L179, N1_data_out); --Z1L1899 is system_0:u0|cpu_0:the_cpu_0|Equal~6220 Z1L1899 = AMPP_FUNCTION(Z1_A_ipending_reg[3], Z1_A_ipending_reg[2], Z1_A_ipending_reg[1], Z1_A_ipending_reg[0]); --Z1_A_valid_wrctl_ienable is system_0:u0|cpu_0:the_cpu_0|A_valid_wrctl_ienable Z1_A_valid_wrctl_ienable = AMPP_FUNCTION(F1__clk1, Z1L139, N1_data_out, Z1_A_stall); --Z1_A_status_reg_pie is system_0:u0|cpu_0:the_cpu_0|A_status_reg_pie Z1_A_status_reg_pie = AMPP_FUNCTION(F1__clk1, Z1L840, N1_data_out, Z1L3020); --Z1L3379 is system_0:u0|cpu_0:the_cpu_0|latched_oci_tb_hbreak_req~24 Z1L3379 = AMPP_FUNCTION(Z1_latched_oci_tb_hbreak_req, Z1_hbreak_enabled); --Z1L1994 is system_0:u0|cpu_0:the_cpu_0|F_iw[2]~1578 Z1L1994 = AMPP_FUNCTION(Z1L1899, Z1_A_valid_wrctl_ienable, Z1_A_status_reg_pie, Z1L3379); --Z1L1995 is system_0:u0|cpu_0:the_cpu_0|F_iw[2]~1579 Z1L1995 = AMPP_FUNCTION(JC1_q_a[2], Z1L1994); --JC1_q_a[1] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[1] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[1] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[1], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L1993 is system_0:u0|cpu_0:the_cpu_0|F_iw[1]~1580 Z1L1993 = AMPP_FUNCTION(JC1_q_a[1], Z1L1994); --JC1_q_a[4] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[4] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[4] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[4], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --JC1_q_a[3] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[3] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[3] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[3], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --JC1_q_a[5] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[5] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[5] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[5], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L1932 is system_0:u0|cpu_0:the_cpu_0|F_ctrl_br_uncond~75 Z1L1932 = AMPP_FUNCTION(Z1L1994, JC1_q_a[4], JC1_q_a[3], JC1_q_a[5]); --JC1_q_a[22] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[22] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[22] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[22], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --JC1_q_a[26] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[26] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[26] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[26], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L1202 is system_0:u0|cpu_0:the_cpu_0|D_regnum_b_cmp_F~54 Z1L1202 = AMPP_FUNCTION(JC1_q_a[22], JC1_q_a[26], Z1L1076, Z1L1069); --JC1_q_a[23] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[23] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[23] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[23], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --JC1_q_a[25] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[25] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[25] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[25], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L1203 is system_0:u0|cpu_0:the_cpu_0|D_regnum_b_cmp_F~55 Z1L1203 = AMPP_FUNCTION(JC1_q_a[23], JC1_q_a[25], Z1L1075, Z1L1071); --JC1_q_a[24] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[24] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[24] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[24], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L1900 is system_0:u0|cpu_0:the_cpu_0|Equal~6221 Z1L1900 = AMPP_FUNCTION(JC1_q_a[24], Z1L1072); --Z1L1204 is system_0:u0|cpu_0:the_cpu_0|D_regnum_b_cmp_F~56 Z1L1204 = AMPP_FUNCTION(Z1_D_wr_dst_reg, Z1L1202, Z1L1203, Z1L1900); --Z1L1997 is system_0:u0|cpu_0:the_cpu_0|F_iw[4]~1581 Z1L1997 = AMPP_FUNCTION(Z1L1994, JC1_q_a[4]); --Z1L1998 is system_0:u0|cpu_0:the_cpu_0|F_iw[5]~1582 Z1L1998 = AMPP_FUNCTION(JC1_q_a[5], Z1L1994); --JC1_q_a[0] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[0] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[0] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[0], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L1992 is system_0:u0|cpu_0:the_cpu_0|F_iw[0]~1583 Z1L1992 = AMPP_FUNCTION(JC1_q_a[0], Z1L1994); --Z1L1930 is system_0:u0|cpu_0:the_cpu_0|F_ctrl_b_not_src~256 Z1L1930 = AMPP_FUNCTION(Z1L1995, Z1L1997, Z1L1998, Z1L1992); --Z1L1996 is system_0:u0|cpu_0:the_cpu_0|F_iw[3]~1584 Z1L1996 = AMPP_FUNCTION(Z1L1994, JC1_q_a[3]); --Z1L1931 is system_0:u0|cpu_0:the_cpu_0|F_ctrl_b_not_src~257 Z1L1931 = AMPP_FUNCTION(Z1L1930, Z1L1993, Z1L1992, Z1L1996); --Z1_E_wr_dst_reg_from_D is system_0:u0|cpu_0:the_cpu_0|E_wr_dst_reg_from_D Z1_E_wr_dst_reg_from_D = AMPP_FUNCTION(F1__clk1, Z1_D_wr_dst_reg, N1_data_out, Z1_A_stall); --Z1L1893 is system_0:u0|cpu_0:the_cpu_0|E_wr_dst_reg~35 Z1L1893 = AMPP_FUNCTION(Z1_M_pipe_flush, Z1_E_wr_dst_reg_from_D, Z1L2334); --Z1_E_dst_regnum[4] is system_0:u0|cpu_0:the_cpu_0|E_dst_regnum[4] Z1_E_dst_regnum[4] = AMPP_FUNCTION(F1__clk1, Z1L1076, N1_data_out, Z1_A_stall); --Z1_E_dst_regnum[0] is system_0:u0|cpu_0:the_cpu_0|E_dst_regnum[0] Z1_E_dst_regnum[0] = AMPP_FUNCTION(F1__clk1, Z1L1069, N1_data_out, Z1_A_stall); --Z1L1679 is system_0:u0|cpu_0:the_cpu_0|E_regnum_a_cmp_F~29 Z1L1679 = AMPP_FUNCTION(JC1_q_a[27], JC1_q_a[31], Z1_E_dst_regnum[4], Z1_E_dst_regnum[0]); --Z1_E_dst_regnum[3] is system_0:u0|cpu_0:the_cpu_0|E_dst_regnum[3] Z1_E_dst_regnum[3] = AMPP_FUNCTION(F1__clk1, Z1L1075, N1_data_out, Z1_A_stall); --Z1_E_dst_regnum[1] is system_0:u0|cpu_0:the_cpu_0|E_dst_regnum[1] Z1_E_dst_regnum[1] = AMPP_FUNCTION(F1__clk1, Z1L1071, N1_data_out, Z1_A_stall); --Z1L1680 is system_0:u0|cpu_0:the_cpu_0|E_regnum_a_cmp_F~30 Z1L1680 = AMPP_FUNCTION(JC1_q_a[28], JC1_q_a[30], Z1_E_dst_regnum[3], Z1_E_dst_regnum[1]); --Z1_E_dst_regnum[2] is system_0:u0|cpu_0:the_cpu_0|E_dst_regnum[2] Z1_E_dst_regnum[2] = AMPP_FUNCTION(F1__clk1, Z1L1072, N1_data_out, Z1_A_stall); --Z1L1901 is system_0:u0|cpu_0:the_cpu_0|Equal~6222 Z1L1901 = AMPP_FUNCTION(JC1_q_a[29], Z1_E_dst_regnum[2]); --Z1_E_regnum_a_cmp_F is system_0:u0|cpu_0:the_cpu_0|E_regnum_a_cmp_F Z1_E_regnum_a_cmp_F = AMPP_FUNCTION(Z1L1893, Z1L1679, Z1L1680, Z1L1901); --Z1L1683 is system_0:u0|cpu_0:the_cpu_0|E_regnum_b_cmp_F~29 Z1L1683 = AMPP_FUNCTION(JC1_q_a[22], JC1_q_a[26], Z1_E_dst_regnum[4], Z1_E_dst_regnum[0]); --Z1L1684 is system_0:u0|cpu_0:the_cpu_0|E_regnum_b_cmp_F~30 Z1L1684 = AMPP_FUNCTION(JC1_q_a[23], JC1_q_a[25], Z1_E_dst_regnum[3], Z1_E_dst_regnum[1]); --Z1L1902 is system_0:u0|cpu_0:the_cpu_0|Equal~6223 Z1L1902 = AMPP_FUNCTION(JC1_q_a[24], Z1_E_dst_regnum[2]); --Z1_E_regnum_b_cmp_F is system_0:u0|cpu_0:the_cpu_0|E_regnum_b_cmp_F Z1_E_regnum_b_cmp_F = AMPP_FUNCTION(Z1L1893, Z1L1683, Z1L1684, Z1L1902); --Z1_F_issue is system_0:u0|cpu_0:the_cpu_0|F_issue Z1_F_issue = AMPP_FUNCTION(Z1_F_ic_hit, Z1L2038); --Z1L1049 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_jmp_indirect~36 Z1L1049 = AMPP_FUNCTION(Z1_D_iw[4], Z1_D_iw[5], Z1L1141, Z1_D_iw[12]); --Z1L1889 is system_0:u0|cpu_0:the_cpu_0|E_valid_jmp_indirect~0 Z1L1889 = AMPP_FUNCTION(Z1_M_pipe_flush, Z1_D_issue, Z1L1050, Z1L1068); --Z1L1934 is system_0:u0|cpu_0:the_cpu_0|F_ctrl_br~43 Z1L1934 = AMPP_FUNCTION(JC1_q_a[2], JC1_q_a[1], Z1L1994, JC1_q_a[0]); --EC1_q_a[1] is system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_kk61:auto_generated|altsyncram_u5e1:altsyncram1|q_a[1] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 2, Port B Logical Depth: 256, Port B Logical Width: 2 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered EC1_q_a[1] = AMPP_FUNCTION(VCC, Z1_M_bht_wr_en, F1__clk1, F1__clk1, Z1_F_stall, Z1_M_bht_wr_en, GND, Z1_F_bht_ptr_nxt[0], Z1_F_bht_ptr_nxt[1], Z1_F_bht_ptr_nxt[2], Z1_F_bht_ptr_nxt[3], Z1_F_bht_ptr_nxt[4], Z1_F_bht_ptr_nxt[5], Z1_F_bht_ptr_nxt[6], Z1_F_bht_ptr_nxt[7], Z1L2151, Z1_M_bht_ptr[0], Z1_M_bht_ptr[1], Z1_M_bht_ptr[2], Z1_M_bht_ptr[3], Z1_M_bht_ptr[4], Z1_M_bht_ptr[5], Z1_M_bht_ptr[6], Z1_M_bht_ptr[7]); --JC1_q_a[11] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[11] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[11] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[11], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L2004 is system_0:u0|cpu_0:the_cpu_0|F_iw[11]~1585 Z1L2004 = AMPP_FUNCTION(JC1_q_a[11], Z1L1994); --JC1_q_a[15] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[15] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[15] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[15], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L2008 is system_0:u0|cpu_0:the_cpu_0|F_iw[15]~1586 Z1L2008 = AMPP_FUNCTION(JC1_q_a[15], Z1L1994); --JC1_q_a[13] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[13] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[13] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[13], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L2006 is system_0:u0|cpu_0:the_cpu_0|F_iw[13]~1587 Z1L2006 = AMPP_FUNCTION(JC1_q_a[13], Z1L1994); --JC1_q_a[14] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[14] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[14] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[14], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --JC1_q_a[16] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[16] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[16] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[16], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L2009 is system_0:u0|cpu_0:the_cpu_0|F_iw[16]~1588 Z1L2009 = AMPP_FUNCTION(JC1_q_a[16], Z1L1994); --JC1_q_a[12] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[12] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[12] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[12], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L2005 is system_0:u0|cpu_0:the_cpu_0|F_iw[12]~1589 Z1L2005 = AMPP_FUNCTION(JC1_q_a[12], Z1L1994); --Z1_M_ctrl_invalidate_i is system_0:u0|cpu_0:the_cpu_0|M_ctrl_invalidate_i Z1_M_ctrl_invalidate_i = AMPP_FUNCTION(F1__clk1, Z1L1524, N1_data_out, Z1_A_stall); --Z1_ic_tag_wren is system_0:u0|cpu_0:the_cpu_0|ic_tag_wren Z1_ic_tag_wren = AMPP_FUNCTION(Z1_i_readdatavalid_d1, Z1_M_valid_from_E, Z1_M_ctrl_invalidate_i, N1_data_out); --Z1L3359 is system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[0]~945 Z1L3359 = AMPP_FUNCTION(Z1_M_alu_result[5], Z1_ic_fill_line[0], Z1_M_valid_from_E, Z1_M_ctrl_invalidate_i); --Z1L3360 is system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[0]~946 Z1L3360 = AMPP_FUNCTION(Z1L3359, Z1L3242, N1_data_out); --Z1L3376 is system_0:u0|cpu_0:the_cpu_0|ic_tag_wren~1 Z1L3376 = AMPP_FUNCTION(Z1_M_valid_from_E, Z1_M_ctrl_invalidate_i); --Z1L3361 is system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[1]~947 Z1L3361 = AMPP_FUNCTION(N1_data_out, Z1_M_alu_result[6], Z1_ic_fill_line[1], Z1L3376); --Z1L3362 is system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[2]~948 Z1L3362 = AMPP_FUNCTION(N1_data_out, Z1_M_alu_result[7], Z1_ic_fill_line[2], Z1L3376); --Z1L3363 is system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[3]~949 Z1L3363 = AMPP_FUNCTION(N1_data_out, Z1_M_alu_result[8], Z1_ic_fill_line[3], Z1L3376); --Z1L3364 is system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[4]~950 Z1L3364 = AMPP_FUNCTION(N1_data_out, Z1_M_alu_result[9], Z1_ic_fill_line[4], Z1L3376); --Z1L3365 is system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[5]~951 Z1L3365 = AMPP_FUNCTION(N1_data_out, Z1_M_alu_result[10], Z1_ic_fill_line[5], Z1L3376); --Z1L3366 is system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[6]~952 Z1L3366 = AMPP_FUNCTION(N1_data_out, Z1_M_alu_result[11], Z1_ic_fill_line[6], Z1L3376); --Z1_D_br_taken_waddr_partial[3] is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[3] Z1_D_br_taken_waddr_partial[3] = AMPP_FUNCTION(F1__clk1, Z1L978, N1_data_out, Z1_F_stall); --Z1L1956 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[0]~1063 Z1L1956 = AMPP_FUNCTION(Z1L1972, Z1L2945, Z1L1977, Z1_D_br_taken_waddr_partial[3]); --Z1_D_iw[9] is system_0:u0|cpu_0:the_cpu_0|D_iw[9] Z1_D_iw[9] = AMPP_FUNCTION(F1__clk1, Z1L2002, N1_data_out, Z1_F_stall); --Z1L1957 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[0]~1064 Z1L1957 = AMPP_FUNCTION(Z1_D_pc[3], Z1L1972, Z1L1956, Z1_D_iw[9]); --Z1L1958 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[0]~1065 Z1L1958 = AMPP_FUNCTION(Z1_E_src1[5], Z1L1957, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[3] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[3] Z1_M_pipe_flush_waddr[3] = AMPP_FUNCTION(F1__clk1, Z1L2347, Z1_E_pc[3], N1_data_out, Z1L2334, Z1_A_stall); --Z1L1959 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[0]~1066 Z1L1959 = AMPP_FUNCTION(Z1L1958, Z1_M_pipe_flush_waddr[3], Z1_M_pipe_flush); --Z1_D_br_taken_waddr_partial[4] is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[4] Z1_D_br_taken_waddr_partial[4] = AMPP_FUNCTION(F1__clk1, Z1L981, N1_data_out, Z1_F_stall); --Z1L1960 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[1]~1067 Z1L1960 = AMPP_FUNCTION(Z1L1977, Z1_D_pc[4], Z1L1972, Z1_D_br_taken_waddr_partial[4]); --Z1_D_iw[10] is system_0:u0|cpu_0:the_cpu_0|D_iw[10] Z1_D_iw[10] = AMPP_FUNCTION(F1__clk1, Z1L2003, N1_data_out, Z1_F_stall); --Z1L1961 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[1]~1068 Z1L1961 = AMPP_FUNCTION(Z1L2947, Z1L1977, Z1L1960, Z1_D_iw[10]); --Z1L1962 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[1]~1069 Z1L1962 = AMPP_FUNCTION(Z1_E_src1[6], Z1L1961, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[4] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[4] Z1_M_pipe_flush_waddr[4] = AMPP_FUNCTION(F1__clk1, Z1L2350, Z1_E_pc[4], N1_data_out, Z1L2334, Z1_A_stall); --Z1L1963 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[1]~1070 Z1L1963 = AMPP_FUNCTION(Z1L1962, Z1_M_pipe_flush_waddr[4], Z1_M_pipe_flush); --Z1_D_br_taken_waddr_partial[5] is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[5] Z1_D_br_taken_waddr_partial[5] = AMPP_FUNCTION(F1__clk1, Z1L984, N1_data_out, Z1_F_stall); --Z1L1964 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[2]~1071 Z1L1964 = AMPP_FUNCTION(Z1L1972, Z1L2949, Z1L1977, Z1_D_br_taken_waddr_partial[5]); --Z1L1965 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[2]~1072 Z1L1965 = AMPP_FUNCTION(Z1_D_pc[5], Z1L1972, Z1L1964, Z1_D_iw[11]); --Z1L1966 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[2]~1073 Z1L1966 = AMPP_FUNCTION(Z1_E_src1[7], Z1L1965, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[5] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[5] Z1_M_pipe_flush_waddr[5] = AMPP_FUNCTION(F1__clk1, Z1L2353, Z1_E_pc[5], N1_data_out, Z1L2334, Z1_A_stall); --Z1L1967 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[2]~1074 Z1L1967 = AMPP_FUNCTION(Z1L1966, Z1_M_pipe_flush_waddr[5], Z1_M_pipe_flush); --Z1_D_br_taken_waddr_partial[6] is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[6] Z1_D_br_taken_waddr_partial[6] = AMPP_FUNCTION(F1__clk1, Z1L987, N1_data_out, Z1_F_stall); --Z1L1968 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[3]~1075 Z1L1968 = AMPP_FUNCTION(Z1L1977, Z1_D_pc[6], Z1L1972, Z1_D_br_taken_waddr_partial[6]); --Z1L1969 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[3]~1076 Z1L1969 = AMPP_FUNCTION(Z1L2951, Z1L1977, Z1L1968, Z1_D_iw[12]); --Z1L1970 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[3]~1077 Z1L1970 = AMPP_FUNCTION(Z1_E_src1[8], Z1L1969, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[6] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[6] Z1_M_pipe_flush_waddr[6] = AMPP_FUNCTION(F1__clk1, Z1L2356, Z1_E_pc[6], N1_data_out, Z1L2334, Z1_A_stall); --Z1L1971 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[3]~1078 Z1L1971 = AMPP_FUNCTION(Z1L1970, Z1_M_pipe_flush_waddr[6], Z1_M_pipe_flush); --Z1_D_br_taken_waddr_partial[7] is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[7] Z1_D_br_taken_waddr_partial[7] = AMPP_FUNCTION(F1__clk1, Z1L990, N1_data_out, Z1_F_stall); --Z1L1973 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[4]~1079 Z1L1973 = AMPP_FUNCTION(Z1L1972, Z1L2953, Z1L1977, Z1_D_br_taken_waddr_partial[7]); --Z1L1974 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[4]~1080 Z1L1974 = AMPP_FUNCTION(Z1_D_pc[7], Z1L1972, Z1L1973, Z1_D_iw[13]); --Z1L1975 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[4]~1081 Z1L1975 = AMPP_FUNCTION(Z1_E_src1[9], Z1L1974, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[7] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[7] Z1_M_pipe_flush_waddr[7] = AMPP_FUNCTION(F1__clk1, Z1L2359, Z1_E_pc[7], N1_data_out, Z1L2334, Z1_A_stall); --Z1L1976 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[4]~1082 Z1L1976 = AMPP_FUNCTION(Z1L1975, Z1_M_pipe_flush_waddr[7], Z1_M_pipe_flush); --Z1_D_br_taken_waddr_partial[8] is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[8] Z1_D_br_taken_waddr_partial[8] = AMPP_FUNCTION(F1__clk1, Z1L993, N1_data_out, Z1_F_stall); --Z1L1978 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[5]~1083 Z1L1978 = AMPP_FUNCTION(Z1L1977, Z1_D_pc[8], Z1L1972, Z1_D_br_taken_waddr_partial[8]); --Z1L1979 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[5]~1084 Z1L1979 = AMPP_FUNCTION(Z1L2955, Z1L1977, Z1L1978, Z1_D_iw[14]); --Z1L1980 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[5]~1085 Z1L1980 = AMPP_FUNCTION(Z1_E_src1[10], Z1L1979, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[8] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[8] Z1_M_pipe_flush_waddr[8] = AMPP_FUNCTION(F1__clk1, Z1L2362, Z1_E_pc[8], N1_data_out, Z1L2334, Z1_A_stall); --Z1L1981 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[5]~1086 Z1L1981 = AMPP_FUNCTION(Z1L1980, Z1_M_pipe_flush_waddr[8], Z1_M_pipe_flush); --Z1_D_br_taken_waddr_partial[9] is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[9] Z1_D_br_taken_waddr_partial[9] = AMPP_FUNCTION(F1__clk1, Z1L996, N1_data_out, Z1_F_stall); --Z1L1982 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[6]~1087 Z1L1982 = AMPP_FUNCTION(Z1L1972, Z1L2957, Z1L1977, Z1_D_br_taken_waddr_partial[9]); --Z1L1983 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[6]~1088 Z1L1983 = AMPP_FUNCTION(Z1_D_pc[9], Z1L1972, Z1L1982, Z1_D_iw[15]); --Z1L1984 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[6]~1089 Z1L1984 = AMPP_FUNCTION(Z1_E_src1[11], Z1L1983, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[9] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[9] Z1_M_pipe_flush_waddr[9] = AMPP_FUNCTION(F1__clk1, Z1L2365, Z1_E_pc[9], N1_data_out, Z1L2334, Z1_A_stall); --Z1L1985 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[6]~1090 Z1L1985 = AMPP_FUNCTION(Z1L1984, Z1_M_pipe_flush_waddr[9], Z1_M_pipe_flush); --Z1L2065 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~347 Z1L2065 = AMPP_FUNCTION(Z1L1972, Z1L2959, Z1L1977, Z1L2983); --Z1L2066 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~348 Z1L2066 = AMPP_FUNCTION(Z1_D_pc[10], Z1L1972, Z1L2065, Z1_D_iw[16]); --Z1L2067 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~349 Z1L2067 = AMPP_FUNCTION(Z1_E_src1[12], Z1L2066, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[10] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[10] Z1_M_pipe_flush_waddr[10] = AMPP_FUNCTION(F1__clk1, Z1L2368, Z1_E_pc[10], N1_data_out, Z1L2334, Z1_A_stall); --Z1L2068 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~350 Z1L2068 = AMPP_FUNCTION(Z1L1972, Z1L2967, Z1L1977, Z1L2991); --Z1L2069 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~351 Z1L2069 = AMPP_FUNCTION(Z1_D_pc[14], Z1L1972, Z1L2068, Z1_D_iw[20]); --Z1L2070 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~352 Z1L2070 = AMPP_FUNCTION(Z1_E_src1[16], Z1L2069, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[14] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[14] Z1_M_pipe_flush_waddr[14] = AMPP_FUNCTION(F1__clk1, Z1L2380, Z1_E_pc[14], N1_data_out, Z1L2334, Z1_A_stall); --Z1L2071 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~353 Z1L2071 = AMPP_FUNCTION(Z1L1972, Z1L2963, Z1L1977, Z1L2987); --Z1L2072 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~354 Z1L2072 = AMPP_FUNCTION(Z1_D_pc[12], Z1L1972, Z1L2071, Z1_D_iw[18]); --Z1L2073 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~355 Z1L2073 = AMPP_FUNCTION(Z1_E_src1[14], Z1L2072, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[12] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[12] Z1_M_pipe_flush_waddr[12] = AMPP_FUNCTION(F1__clk1, Z1L2374, Z1_E_pc[12], N1_data_out, Z1L2334, Z1_A_stall); --Z1L2074 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~356 Z1L2074 = AMPP_FUNCTION(Z1L1972, Z1L2971, Z1L1977, Z1L2995); --Z1L2075 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~357 Z1L2075 = AMPP_FUNCTION(Z1_D_pc[16], Z1L1972, Z1L2074, Z1_D_iw[22]); --Z1L2076 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~358 Z1L2076 = AMPP_FUNCTION(Z1_E_src1[18], Z1L2075, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[16] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[16] Z1_M_pipe_flush_waddr[16] = AMPP_FUNCTION(F1__clk1, Z1L2386, Z1_E_pc[16], N1_data_out, Z1L2334, Z1_A_stall); --Z1L3005 is system_0:u0|cpu_0:the_cpu_0|add~3142 Z1L3005 = AMPP_FUNCTION(Z1_F_pc[21], Z1L2980); --Z1_D_pc_plus_one[21] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[21] Z1_D_pc_plus_one[21] = AMPP_FUNCTION(F1__clk1, Z1L3005, N1_data_out, Z1_F_stall); --Z1L3007 is system_0:u0|cpu_0:the_cpu_0|add~3144 Z1L3007 = AMPP_FUNCTION(Z1_D_pc_plus_one[21], Z1_D_iw[21], Z1L3004); --Z1L2077 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~359 Z1L2077 = AMPP_FUNCTION(Z1L1977, Z1_D_pc[21], Z1L1972, Z1L3007); --Z1_D_iw[27] is system_0:u0|cpu_0:the_cpu_0|D_iw[27] Z1_D_iw[27] = AMPP_FUNCTION(F1__clk1, Z1L2020, N1_data_out, Z1_F_stall); --Z1L2078 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~360 Z1L2078 = AMPP_FUNCTION(Z1L3005, Z1L1977, Z1L2077, Z1_D_iw[27]); --Z1L2079 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~361 Z1L2079 = AMPP_FUNCTION(Z1_E_src1[23], Z1L2078, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[21] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[21] Z1_M_pipe_flush_waddr[21] = AMPP_FUNCTION(F1__clk1, Z1L2401, Z1_E_pc[21], N1_data_out, Z1L2334, Z1_A_stall); --Z1L2080 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~362 Z1L2080 = AMPP_FUNCTION(Z1L1977, Z1_D_pc[11], Z1L1972, Z1L2985); --Z1L2081 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~363 Z1L2081 = AMPP_FUNCTION(Z1L2961, Z1L1977, Z1L2080, Z1_D_iw[17]); --Z1L2082 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~364 Z1L2082 = AMPP_FUNCTION(Z1_E_src1[13], Z1L2081, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[11] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[11] Z1_M_pipe_flush_waddr[11] = AMPP_FUNCTION(F1__clk1, Z1L2371, Z1_E_pc[11], N1_data_out, Z1L2334, Z1_A_stall); --Z1L2083 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~365 Z1L2083 = AMPP_FUNCTION(Z1L1977, Z1_D_pc[15], Z1L1972, Z1L2993); --Z1L2084 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~366 Z1L2084 = AMPP_FUNCTION(Z1L2969, Z1L1977, Z1L2083, Z1_D_iw[21]); --Z1L2085 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~367 Z1L2085 = AMPP_FUNCTION(Z1_E_src1[17], Z1L2084, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[15] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[15] Z1_M_pipe_flush_waddr[15] = AMPP_FUNCTION(F1__clk1, Z1L2383, Z1_E_pc[15], N1_data_out, Z1L2334, Z1_A_stall); --Z1L2086 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~368 Z1L2086 = AMPP_FUNCTION(Z1L1977, Z1_D_pc[13], Z1L1972, Z1L2989); --Z1L2087 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~369 Z1L2087 = AMPP_FUNCTION(Z1L2965, Z1L1977, Z1L2086, Z1_D_iw[19]); --Z1L2088 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~370 Z1L2088 = AMPP_FUNCTION(Z1_E_src1[15], Z1L2087, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[13] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[13] Z1_M_pipe_flush_waddr[13] = AMPP_FUNCTION(F1__clk1, Z1L2377, Z1_E_pc[13], N1_data_out, Z1L2334, Z1_A_stall); --Z1L2089 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~371 Z1L2089 = AMPP_FUNCTION(Z1L1977, Z1_D_pc[19], Z1L1972, Z1L3001); --Z1L2090 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~372 Z1L2090 = AMPP_FUNCTION(Z1L2977, Z1L1977, Z1L2089, Z1_D_iw[25]); --Z1L2091 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~373 Z1L2091 = AMPP_FUNCTION(Z1_E_src1[21], Z1L2090, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[19] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[19] Z1_M_pipe_flush_waddr[19] = AMPP_FUNCTION(F1__clk1, Z1L2395, Z1_E_pc[19], N1_data_out, Z1L2334, Z1_A_stall); --Z1_ic_fill_valid_bits[5] is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits[5] Z1_ic_fill_valid_bits[5] = AMPP_FUNCTION(F1__clk1, Z1L3354, N1_data_out, Z1_ic_fill_valid_bits_en); --Z1L3372 is system_0:u0|cpu_0:the_cpu_0|ic_tag_wrdata[5]~192 Z1L3372 = AMPP_FUNCTION(N1_data_out, Z1_ic_fill_valid_bits[5], Z1_M_valid_from_E, Z1_M_ctrl_invalidate_i); --Z1_D_br_taken_waddr_partial[0] is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[0] Z1_D_br_taken_waddr_partial[0] = AMPP_FUNCTION(F1__clk1, Z1L969, N1_data_out, Z1_F_stall); --Z1L1936 is system_0:u0|cpu_0:the_cpu_0|F_ic_data_rd_addr_nxt[0]~390 Z1L1936 = AMPP_FUNCTION(Z1L1977, Z1_D_pc[0], Z1L1972, Z1_D_br_taken_waddr_partial[0]); --Z1_D_iw[6] is system_0:u0|cpu_0:the_cpu_0|D_iw[6] Z1_D_iw[6] = AMPP_FUNCTION(F1__clk1, Z1L1999, N1_data_out, Z1_F_stall); --Z1L1937 is system_0:u0|cpu_0:the_cpu_0|F_ic_data_rd_addr_nxt[0]~391 Z1L1937 = AMPP_FUNCTION(Z1L2939, Z1L1977, Z1L1936, Z1_D_iw[6]); --Z1L1938 is system_0:u0|cpu_0:the_cpu_0|F_ic_data_rd_addr_nxt[0]~392 Z1L1938 = AMPP_FUNCTION(Z1_E_src1[2], Z1L1937, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[0] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[0] Z1_M_pipe_flush_waddr[0] = AMPP_FUNCTION(F1__clk1, Z1L2338, Z1_E_pc[0], N1_data_out, Z1L2334, Z1_A_stall); --Z1L1939 is system_0:u0|cpu_0:the_cpu_0|F_ic_data_rd_addr_nxt[0]~393 Z1L1939 = AMPP_FUNCTION(Z1L1938, Z1_M_pipe_flush_waddr[0], Z1_M_pipe_flush); --Z1_ic_fill_valid_bits[6] is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits[6] Z1_ic_fill_valid_bits[6] = AMPP_FUNCTION(F1__clk1, Z1L3356, N1_data_out, Z1_ic_fill_valid_bits_en); --Z1L3373 is system_0:u0|cpu_0:the_cpu_0|ic_tag_wrdata[6]~193 Z1L3373 = AMPP_FUNCTION(N1_data_out, Z1_ic_fill_valid_bits[6], Z1_M_valid_from_E, Z1_M_ctrl_invalidate_i); --Z1_D_br_taken_waddr_partial[1] is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[1] Z1_D_br_taken_waddr_partial[1] = AMPP_FUNCTION(F1__clk1, Z1L972, N1_data_out, Z1_F_stall); --Z1L1940 is system_0:u0|cpu_0:the_cpu_0|F_ic_data_rd_addr_nxt[1]~394 Z1L1940 = AMPP_FUNCTION(Z1L1972, Z1L2941, Z1L1977, Z1_D_br_taken_waddr_partial[1]); --Z1_D_iw[7] is system_0:u0|cpu_0:the_cpu_0|D_iw[7] Z1_D_iw[7] = AMPP_FUNCTION(F1__clk1, Z1L2000, N1_data_out, Z1_F_stall); --Z1L1941 is system_0:u0|cpu_0:the_cpu_0|F_ic_data_rd_addr_nxt[1]~395 Z1L1941 = AMPP_FUNCTION(Z1_D_pc[1], Z1L1972, Z1L1940, Z1_D_iw[7]); --Z1L1942 is system_0:u0|cpu_0:the_cpu_0|F_ic_data_rd_addr_nxt[1]~396 Z1L1942 = AMPP_FUNCTION(Z1_E_src1[3], Z1L1941, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[1] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[1] Z1_M_pipe_flush_waddr[1] = AMPP_FUNCTION(F1__clk1, Z1L2341, Z1_E_pc[1], N1_data_out, Z1L2334, Z1_A_stall); --Z1L1943 is system_0:u0|cpu_0:the_cpu_0|F_ic_data_rd_addr_nxt[1]~397 Z1L1943 = AMPP_FUNCTION(Z1L1942, Z1_M_pipe_flush_waddr[1], Z1_M_pipe_flush); --Z1_ic_fill_valid_bits[4] is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits[4] Z1_ic_fill_valid_bits[4] = AMPP_FUNCTION(F1__clk1, Z1L3352, N1_data_out, Z1_ic_fill_valid_bits_en); --Z1L3371 is system_0:u0|cpu_0:the_cpu_0|ic_tag_wrdata[4]~194 Z1L3371 = AMPP_FUNCTION(N1_data_out, Z1_ic_fill_valid_bits[4], Z1_M_valid_from_E, Z1_M_ctrl_invalidate_i); --Z1_ic_fill_valid_bits[7] is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits[7] Z1_ic_fill_valid_bits[7] = AMPP_FUNCTION(F1__clk1, Z1L3358, N1_data_out, Z1_ic_fill_valid_bits_en); --Z1L3374 is system_0:u0|cpu_0:the_cpu_0|ic_tag_wrdata[7]~195 Z1L3374 = AMPP_FUNCTION(N1_data_out, Z1_ic_fill_valid_bits[7], Z1_M_valid_from_E, Z1_M_ctrl_invalidate_i); --Z1_ic_fill_valid_bits[2] is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits[2] Z1_ic_fill_valid_bits[2] = AMPP_FUNCTION(F1__clk1, Z1L3348, N1_data_out, Z1_ic_fill_valid_bits_en); --Z1L3369 is system_0:u0|cpu_0:the_cpu_0|ic_tag_wrdata[2]~196 Z1L3369 = AMPP_FUNCTION(N1_data_out, Z1_ic_fill_valid_bits[2], Z1_M_valid_from_E, Z1_M_ctrl_invalidate_i); --Z1_ic_fill_valid_bits[1] is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits[1] Z1_ic_fill_valid_bits[1] = AMPP_FUNCTION(F1__clk1, Z1L3346, N1_data_out, Z1_ic_fill_valid_bits_en); --Z1L3368 is system_0:u0|cpu_0:the_cpu_0|ic_tag_wrdata[1]~197 Z1L3368 = AMPP_FUNCTION(N1_data_out, Z1_ic_fill_valid_bits[1], Z1_M_valid_from_E, Z1_M_ctrl_invalidate_i); --Z1_ic_fill_valid_bits[0] is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits[0] Z1_ic_fill_valid_bits[0] = AMPP_FUNCTION(F1__clk1, Z1L3344, N1_data_out, Z1_ic_fill_valid_bits_en); --Z1L3367 is system_0:u0|cpu_0:the_cpu_0|ic_tag_wrdata[0]~198 Z1L3367 = AMPP_FUNCTION(N1_data_out, Z1_ic_fill_valid_bits[0], Z1_M_valid_from_E, Z1_M_ctrl_invalidate_i); --Z1_ic_fill_valid_bits[3] is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits[3] Z1_ic_fill_valid_bits[3] = AMPP_FUNCTION(F1__clk1, Z1L3350, N1_data_out, Z1_ic_fill_valid_bits_en); --Z1L3370 is system_0:u0|cpu_0:the_cpu_0|ic_tag_wrdata[3]~199 Z1L3370 = AMPP_FUNCTION(N1_data_out, Z1_ic_fill_valid_bits[3], Z1_M_valid_from_E, Z1_M_ctrl_invalidate_i); --Z1_D_br_taken_waddr_partial[2] is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[2] Z1_D_br_taken_waddr_partial[2] = AMPP_FUNCTION(F1__clk1, Z1L975, N1_data_out, Z1_F_stall); --Z1L1944 is system_0:u0|cpu_0:the_cpu_0|F_ic_data_rd_addr_nxt[2]~398 Z1L1944 = AMPP_FUNCTION(Z1L1977, Z1_D_pc[2], Z1L1972, Z1_D_br_taken_waddr_partial[2]); --Z1_D_iw[8] is system_0:u0|cpu_0:the_cpu_0|D_iw[8] Z1_D_iw[8] = AMPP_FUNCTION(F1__clk1, Z1L2001, N1_data_out, Z1_F_stall); --Z1L1945 is system_0:u0|cpu_0:the_cpu_0|F_ic_data_rd_addr_nxt[2]~399 Z1L1945 = AMPP_FUNCTION(Z1L2943, Z1L1977, Z1L1944, Z1_D_iw[8]); --Z1L1946 is system_0:u0|cpu_0:the_cpu_0|F_ic_data_rd_addr_nxt[2]~400 Z1L1946 = AMPP_FUNCTION(Z1_E_src1[4], Z1L1945, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[2] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[2] Z1_M_pipe_flush_waddr[2] = AMPP_FUNCTION(F1__clk1, Z1L2344, Z1_E_pc[2], N1_data_out, Z1L2334, Z1_A_stall); --Z1L1947 is system_0:u0|cpu_0:the_cpu_0|F_ic_data_rd_addr_nxt[2]~401 Z1L1947 = AMPP_FUNCTION(Z1L1946, Z1_M_pipe_flush_waddr[2], Z1_M_pipe_flush); --Z1L2092 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~374 Z1L2092 = AMPP_FUNCTION(Z1L1977, Z1_D_pc[17], Z1L1972, Z1L2997); --Z1L2093 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~375 Z1L2093 = AMPP_FUNCTION(Z1L2973, Z1L1977, Z1L2092, Z1_D_iw[23]); --Z1L2094 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~376 Z1L2094 = AMPP_FUNCTION(Z1_E_src1[19], Z1L2093, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[17] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[17] Z1_M_pipe_flush_waddr[17] = AMPP_FUNCTION(F1__clk1, Z1L2389, Z1_E_pc[17], N1_data_out, Z1L2334, Z1_A_stall); --Z1L2095 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~377 Z1L2095 = AMPP_FUNCTION(Z1L1972, Z1L2975, Z1L1977, Z1L2999); --Z1L2096 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~378 Z1L2096 = AMPP_FUNCTION(Z1_D_pc[18], Z1L1972, Z1L2095, Z1_D_iw[24]); --Z1L2097 is system_0:u0|cpu_0:the_cpu_0|F_pc_nxt~379 Z1L2097 = AMPP_FUNCTION(Z1_E_src1[20], Z1L2096, Z1_E_valid_jmp_indirect); --Z1_M_pipe_flush_waddr[18] is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[18] Z1_M_pipe_flush_waddr[18] = AMPP_FUNCTION(F1__clk1, Z1L2392, Z1_E_pc[18], N1_data_out, Z1L2334, Z1_A_stall); --Z1L3342 is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits_en~6 Z1L3342 = AMPP_FUNCTION(Z1L1099, Z1_i_readdatavalid_d1); --BB1L139 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdatavalid~98 BB1L139 = BB1_cpu_0_instruction_master_dbs_address[1] & LB1L12 & BB1L138 & BB1L1; --BB1_cpu_0_instruction_master_read_but_no_slave_selected is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_read_but_no_slave_selected BB1_cpu_0_instruction_master_read_but_no_slave_selected = DFFEAS(BB1L24, F1__clk1, N1_data_out, , , , , , ); --BB1_cpu_0_instruction_master_dbs_rdv_counter[1] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_dbs_rdv_counter[1] BB1_cpu_0_instruction_master_dbs_rdv_counter[1] = DFFEAS(BB1L2, F1__clk1, N1_data_out, , BB1_dbs_rdv_count_enable, , , , ); --MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] = DFFEAS(MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0], F1__clk1, N1_data_out, , , , , , ); --BB1_dbs_rdv_count_enable is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_rdv_count_enable BB1_dbs_rdv_count_enable = MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] # JE1_fifo_contains_ones_n & HB1_za_valid & JE1_stage_0; --JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_instruction_master_read_data_valid_sdram_0_s1 JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1 = JE1_fifo_contains_ones_n & HB1_za_valid & JE1_stage_0; --BB1_cpu_0_instruction_master_dbs_rdv_counter[0] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_dbs_rdv_counter[0] BB1_cpu_0_instruction_master_dbs_rdv_counter[0] = DFFEAS(BB1L3, F1__clk1, N1_data_out, , BB1_dbs_rdv_count_enable, , , , ); --BB1L2 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|add~278 BB1L2 = BB1_cpu_0_instruction_master_dbs_rdv_counter[1] $ (JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1 # BB1_cpu_0_instruction_master_dbs_rdv_counter[0]); --BB1L140 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdatavalid~99 BB1L140 = BB1_cpu_0_instruction_master_read_but_no_slave_selected # BB1_cpu_0_instruction_master_dbs_rdv_counter[1] & BB1_dbs_rdv_count_enable & !BB1L2; --BB1L141 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdatavalid~100 BB1L141 = CB1L1 & CB1_cpu_0_instruction_master_granted_cpu_0_jtag_debug_module & !CB1L23; --BB1L142 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdatavalid~101 BB1L142 = BB1L141 # EB1L3 & EB1_cpu_0_instruction_master_granted_epcs_controller_epcs_control_port & !EB1L24; --BB1L143 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdatavalid~102 BB1L143 = BB1L139 # BB1L140 # EB1L28 & BB1L142; --Z1_D_valid is system_0:u0|cpu_0:the_cpu_0|D_valid Z1_D_valid = AMPP_FUNCTION(Z1_M_pipe_flush, Z1_D_issue, Z1L1068); --Z1L1023 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_br_cond~105 Z1L1023 = AMPP_FUNCTION(Z1_D_iw[5], Z1_D_iw[4], Z1_D_iw[3], Z1_D_iw[2]); --Z1L1024 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_br_cond~106 Z1L1024 = AMPP_FUNCTION(Z1_D_iw[1], Z1L1023, Z1_D_iw[0]); --Z1L1140 is system_0:u0|cpu_0:the_cpu_0|D_logic_op_raw[1]~94 Z1L1140 = AMPP_FUNCTION(Z1_D_iw[4], Z1_D_iw[15], Z1_D_iw[5], Z1L1141); --MC1_q_b[31] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[31] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[31] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L950, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_regnum_b_cmp_D is system_0:u0|cpu_0:the_cpu_0|A_regnum_b_cmp_D Z1_A_regnum_b_cmp_D = AMPP_FUNCTION(F1__clk1, Z1L2432, Z1_M_regnum_b_cmp_D, N1_data_out, !Z1_F_stall, Z1_A_stall); --Z1L1336 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[1]~589 Z1L1336 = AMPP_FUNCTION(Z1_D_ctrl_b_not_src, Z1_M_regnum_b_cmp_D, Z1_A_regnum_b_cmp_D); --Z1_M_alu_result[31] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[31] Z1_M_alu_result[31] = AMPP_FUNCTION(F1__clk1, Z1L1478, N1_data_out, Z1_A_stall); --Z1_W_regnum_b_cmp_D is system_0:u0|cpu_0:the_cpu_0|W_regnum_b_cmp_D Z1_W_regnum_b_cmp_D = AMPP_FUNCTION(F1__clk1, Z1L530, Z1_A_regnum_b_cmp_D, N1_data_out, !Z1_F_stall); --Z1L1337 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[1]~590 Z1L1337 = AMPP_FUNCTION(Z1_M_regnum_b_cmp_D, Z1_W_regnum_b_cmp_D, Z1_A_regnum_b_cmp_D, Z1_D_ctrl_b_not_src); --Z1_A_mul_result[31] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[31] Z1_A_mul_result[31] = AMPP_FUNCTION(F1__clk1, Z1L384, Z1_A_mul_partial_prod[31], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_data_ram_ld_align_fill_bit is system_0:u0|cpu_0:the_cpu_0|A_data_ram_ld_align_fill_bit Z1_A_data_ram_ld_align_fill_bit = AMPP_FUNCTION(F1__clk1, Z1_M_data_ram_ld_align_fill_bit, N1_data_out, Z1_A_stall); --Z1_A_ctrl_shift_rot is system_0:u0|cpu_0:the_cpu_0|A_ctrl_shift_rot Z1_A_ctrl_shift_rot = AMPP_FUNCTION(F1__clk1, Z1_M_ctrl_shift_rot, N1_data_out, Z1_A_stall); --Z1_A_ctrl_ld8_ld16 is system_0:u0|cpu_0:the_cpu_0|A_ctrl_ld8_ld16 Z1_A_ctrl_ld8_ld16 = AMPP_FUNCTION(F1__clk1, Z1_M_ctrl_ld8_ld16, N1_data_out, Z1_A_stall); --Z1_A_slow_inst_sel is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_sel Z1_A_slow_inst_sel = AMPP_FUNCTION(F1__clk1, Z1L781, N1_data_out); --Z1L931 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[26]~1677 Z1L931 = AMPP_FUNCTION(Z1_A_ctrl_shift_rot, Z1_A_ctrl_ld8_ld16, Z1_A_slow_inst_sel); --Z1_A_slow_inst_result[31] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[31] Z1_A_slow_inst_result[31] = AMPP_FUNCTION(F1__clk1, Z1L797, N1_data_out, Z1_A_ctrl_ld); --Z1L932 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[26]~1678 Z1L932 = AMPP_FUNCTION(Z1_A_ctrl_shift_rot, Z1_A_slow_inst_sel); --Z1_A_inst_result[31] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[31] Z1_A_inst_result[31] = AMPP_FUNCTION(F1__clk1, Z1L2305, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L948 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[31]~1679 Z1L948 = AMPP_FUNCTION(Z1L931, Z1_A_slow_inst_result[31], Z1L932, Z1_A_inst_result[31]); --Z1_A_shift_rot_result[31] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[31] Z1_A_shift_rot_result[31] = AMPP_FUNCTION(F1__clk1, Z1L650, N1_data_out); --Z1L949 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[31]~1680 Z1L949 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L931, Z1L948, Z1_A_shift_rot_result[31]); --Z1_A_ctrl_mul_lsw is system_0:u0|cpu_0:the_cpu_0|A_ctrl_mul_lsw Z1_A_ctrl_mul_lsw = AMPP_FUNCTION(F1__clk1, Z1_M_ctrl_mul_lsw, N1_data_out, Z1_A_stall); --Z1L950 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[31]~1681 Z1L950 = AMPP_FUNCTION(Z1_A_mul_result[31], Z1L949, Z1_A_ctrl_mul_lsw); --Z1L1398 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[31]~591 Z1L1398 = AMPP_FUNCTION(Z1L1336, Z1_M_alu_result[31], Z1L1337, Z1L950); --Z1_W_wr_data[31] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[31] Z1_W_wr_data[31] = AMPP_FUNCTION(F1__clk1, Z1L950, N1_data_out); --Z1L1399 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[31]~592 Z1L1399 = AMPP_FUNCTION(MC1_q_b[31], Z1L1336, Z1L1398, Z1_W_wr_data[31]); --Z1L1477 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[31]~6777 Z1L1477 = AMPP_FUNCTION(Z1L1644, Z1_E_ctrl_dst_data_sel_logic_result); --Z1L1478 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[31]~6778 Z1L1478 = AMPP_FUNCTION(Z1L1477, Z1L1479, Z1L1483, Z1_E_ctrl_dst_data_sel_cmp); --Z1_D_src2_hazard_E is system_0:u0|cpu_0:the_cpu_0|D_src2_hazard_E Z1_D_src2_hazard_E = AMPP_FUNCTION(Z1_E_regnum_b_cmp_D, Z1_D_ctrl_b_not_src); --Z1L1836 is system_0:u0|cpu_0:the_cpu_0|E_src2[31]~145 Z1L1836 = AMPP_FUNCTION(Z1L1399, Z1L1478, Z1_D_src2_hazard_E); --Z1L1149 is system_0:u0|cpu_0:the_cpu_0|D_op_call~831 Z1L1149 = AMPP_FUNCTION(Z1_D_iw[0], Z1_D_iw[1], Z1_D_iw[2], Z1_D_iw[3]); --Z1L1064 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_unsigned_lo_imm~198 Z1L1064 = AMPP_FUNCTION(Z1L1147, Z1L1149, Z1_D_iw[4]); --Z1L1150 is system_0:u0|cpu_0:the_cpu_0|D_op_call~832 Z1L1150 = AMPP_FUNCTION(Z1_D_iw[0], Z1_D_iw[1], Z1_D_iw[2], Z1_D_iw[3]); --Z1L1031 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_dst_data_sel_logic_result~50 Z1L1031 = AMPP_FUNCTION(Z1_D_iw[4], Z1L1143, Z1L1150); --Z1L1065 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_unsigned_lo_imm~199 Z1L1065 = AMPP_FUNCTION(Z1L1064, Z1_D_iw[5], Z1L1031, Z1L1896); --Z1L1332 is system_0:u0|cpu_0:the_cpu_0|D_src2[31]~1936 Z1L1332 = AMPP_FUNCTION(Z1_D_iw[21], Z1L1065); --Z1L1062 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_src2_is_imm~129 Z1L1062 = AMPP_FUNCTION(Z1L1146, Z1_D_iw[5], Z1_D_iw[4]); --Z1L1063 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_src2_is_imm~130 Z1L1063 = AMPP_FUNCTION(Z1L1145, Z1L1062, Z1_D_iw[1], Z1L1061); --Z1L1903 is system_0:u0|cpu_0:the_cpu_0|Equal~6224 Z1L1903 = AMPP_FUNCTION(Z1_D_iw[11], Z1_D_iw[13]); --Z1L1015 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_alu_signed_cmp~274 Z1L1015 = AMPP_FUNCTION(Z1_D_iw[15], Z1_D_iw[14], Z1L2036, Z1L1903); --LC1_q_b[31] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[31] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[31] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L950, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1_A_regnum_a_cmp_D is system_0:u0|cpu_0:the_cpu_0|A_regnum_a_cmp_D Z1_A_regnum_a_cmp_D = AMPP_FUNCTION(F1__clk1, Z1L2428, Z1_M_regnum_a_cmp_D, N1_data_out, !Z1_F_stall, Z1_A_stall); --Z1L1730 is system_0:u0|cpu_0:the_cpu_0|E_src1[22]~494 Z1L1730 = AMPP_FUNCTION(Z1_D_ctrl_a_not_src, Z1_M_regnum_a_cmp_D, Z1_A_regnum_a_cmp_D); --Z1_W_regnum_a_cmp_D is system_0:u0|cpu_0:the_cpu_0|W_regnum_a_cmp_D Z1_W_regnum_a_cmp_D = AMPP_FUNCTION(F1__clk1, Z1L526, Z1_A_regnum_a_cmp_D, N1_data_out, !Z1_F_stall); --Z1L1731 is system_0:u0|cpu_0:the_cpu_0|E_src1[22]~495 Z1L1731 = AMPP_FUNCTION(Z1_M_regnum_a_cmp_D, Z1_W_regnum_a_cmp_D, Z1_A_regnum_a_cmp_D, Z1_D_ctrl_a_not_src); --Z1L1298 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[31]~3645 Z1L1298 = AMPP_FUNCTION(Z1L1730, Z1_M_alu_result[31], Z1L1731, Z1L950); --Z1L1299 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[31]~3646 Z1L1299 = AMPP_FUNCTION(LC1_q_b[31], Z1L1730, Z1L1298, Z1_W_wr_data[31]); --Z1_M_alu_result[30] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[30] Z1_M_alu_result[30] = AMPP_FUNCTION(F1__clk1, Z1L1476, N1_data_out, Z1_A_stall); --MC1_q_b[30] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[30] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[30] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L947, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[30] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[30] Z1_A_mul_result[30] = AMPP_FUNCTION(F1__clk1, Z1L381, Z1_A_mul_partial_prod[30], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[30] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[30] Z1_A_slow_inst_result[30] = AMPP_FUNCTION(F1__clk1, Z1L796, N1_data_out, Z1_A_ctrl_ld); --Z1_A_inst_result[30] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[30] Z1_A_inst_result[30] = AMPP_FUNCTION(F1__clk1, Z1L2304, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L945 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[30]~1682 Z1L945 = AMPP_FUNCTION(Z1L931, Z1_A_slow_inst_result[30], Z1L932, Z1_A_inst_result[30]); --Z1_A_shift_rot_result[30] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[30] Z1_A_shift_rot_result[30] = AMPP_FUNCTION(F1__clk1, Z1L652, N1_data_out); --Z1L946 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[30]~1683 Z1L946 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L931, Z1L945, Z1_A_shift_rot_result[30]); --Z1L947 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[30]~1684 Z1L947 = AMPP_FUNCTION(Z1_A_mul_result[30], Z1L946, Z1_A_ctrl_mul_lsw); --Z1L1396 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[30]~593 Z1L1396 = AMPP_FUNCTION(Z1L1337, MC1_q_b[30], Z1L1336, Z1L947); --Z1_W_wr_data[30] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[30] Z1_W_wr_data[30] = AMPP_FUNCTION(F1__clk1, Z1L947, N1_data_out); --Z1L1397 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[30]~594 Z1L1397 = AMPP_FUNCTION(Z1_M_alu_result[30], Z1L1337, Z1L1396, Z1_W_wr_data[30]); --Z1L1475 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[30]~6779 Z1L1475 = AMPP_FUNCTION(Z1L1479, Z1L2866, Z1L2932, Z1_E_ctrl_alu_subtract); --Z1L1476 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[30]~6780 Z1L1476 = AMPP_FUNCTION(Z1L1475, Z1L1643, Z1_E_ctrl_dst_data_sel_logic_result, Z1_E_ctrl_dst_data_sel_cmp); --Z1L1833 is system_0:u0|cpu_0:the_cpu_0|E_src2[30]~144 Z1L1833 = AMPP_FUNCTION(Z1L1397, Z1L1476, Z1_D_src2_hazard_E); --Z1L1041 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_hi_imm~98 Z1L1041 = AMPP_FUNCTION(Z1_D_iw[0], Z1_D_iw[1], Z1_D_iw[4], Z1_D_iw[3]); --Z1L1042 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_hi_imm~99 Z1L1042 = AMPP_FUNCTION(Z1_D_iw[5], Z1_D_iw[2], Z1L1041); --Z1L1331 is system_0:u0|cpu_0:the_cpu_0|D_src2[30]~1937 Z1L1331 = AMPP_FUNCTION(Z1_D_iw[20], Z1_D_iw[21], Z1L1042, Z1L1065); --LC1_q_b[30] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[30] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[30] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L947, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1295 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[30]~3647 Z1L1295 = AMPP_FUNCTION(Z1L1731, LC1_q_b[30], Z1L1730, Z1L947); --Z1L1296 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[30]~3648 Z1L1296 = AMPP_FUNCTION(Z1_M_alu_result[30], Z1L1731, Z1L1295, Z1_W_wr_data[30]); --MC1_q_b[29] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[29] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[29] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L944, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_M_alu_result[29] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[29] Z1_M_alu_result[29] = AMPP_FUNCTION(F1__clk1, Z1L1474, N1_data_out, Z1_A_stall); --Z1_A_mul_result[29] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[29] Z1_A_mul_result[29] = AMPP_FUNCTION(F1__clk1, Z1L378, Z1_A_mul_partial_prod[29], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[29] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[29] Z1_A_slow_inst_result[29] = AMPP_FUNCTION(F1__clk1, Z1L795, N1_data_out, Z1_A_ctrl_ld); --Z1_A_inst_result[29] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[29] Z1_A_inst_result[29] = AMPP_FUNCTION(F1__clk1, Z1L2303, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L942 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[29]~1685 Z1L942 = AMPP_FUNCTION(Z1L931, Z1_A_slow_inst_result[29], Z1L932, Z1_A_inst_result[29]); --Z1_A_shift_rot_result[29] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[29] Z1_A_shift_rot_result[29] = AMPP_FUNCTION(F1__clk1, Z1L654, N1_data_out); --Z1L943 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[29]~1686 Z1L943 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L931, Z1L942, Z1_A_shift_rot_result[29]); --Z1L944 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[29]~1687 Z1L944 = AMPP_FUNCTION(Z1_A_mul_result[29], Z1L943, Z1_A_ctrl_mul_lsw); --Z1L1394 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[29]~595 Z1L1394 = AMPP_FUNCTION(Z1L1336, Z1_M_alu_result[29], Z1L1337, Z1L944); --Z1_W_wr_data[29] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[29] Z1_W_wr_data[29] = AMPP_FUNCTION(F1__clk1, Z1L944, N1_data_out); --Z1L1395 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[29]~596 Z1L1395 = AMPP_FUNCTION(MC1_q_b[29], Z1L1336, Z1L1394, Z1_W_wr_data[29]); --Z1L1473 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[29]~6781 Z1L1473 = AMPP_FUNCTION(Z1L1479, Z1L2864, Z1L2930, Z1_E_ctrl_alu_subtract); --Z1L1474 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[29]~6782 Z1L1474 = AMPP_FUNCTION(Z1L1473, Z1L1642, Z1_E_ctrl_dst_data_sel_logic_result, Z1_E_ctrl_dst_data_sel_cmp); --Z1L1830 is system_0:u0|cpu_0:the_cpu_0|E_src2[29]~143 Z1L1830 = AMPP_FUNCTION(Z1L1395, Z1L1474, Z1_D_src2_hazard_E); --Z1L1330 is system_0:u0|cpu_0:the_cpu_0|D_src2[29]~1938 Z1L1330 = AMPP_FUNCTION(Z1_D_iw[19], Z1_D_iw[21], Z1L1042, Z1L1065); --LC1_q_b[29] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[29] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[29] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L944, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1292 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[29]~3649 Z1L1292 = AMPP_FUNCTION(Z1L1730, Z1_M_alu_result[29], Z1L1731, Z1L944); --Z1L1293 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[29]~3650 Z1L1293 = AMPP_FUNCTION(LC1_q_b[29], Z1L1730, Z1L1292, Z1_W_wr_data[29]); --Z1_M_alu_result[28] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[28] Z1_M_alu_result[28] = AMPP_FUNCTION(F1__clk1, Z1L1472, N1_data_out, Z1_A_stall); --MC1_q_b[28] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[28] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[28] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L941, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[28] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[28] Z1_A_mul_result[28] = AMPP_FUNCTION(F1__clk1, Z1L375, Z1_A_mul_partial_prod[28], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[28] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[28] Z1_A_slow_inst_result[28] = AMPP_FUNCTION(F1__clk1, Z1L794, N1_data_out, Z1_A_ctrl_ld); --Z1_A_inst_result[28] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[28] Z1_A_inst_result[28] = AMPP_FUNCTION(F1__clk1, Z1L2302, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L939 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[28]~1688 Z1L939 = AMPP_FUNCTION(Z1L931, Z1_A_slow_inst_result[28], Z1L932, Z1_A_inst_result[28]); --Z1_A_shift_rot_result[28] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[28] Z1_A_shift_rot_result[28] = AMPP_FUNCTION(F1__clk1, Z1L656, N1_data_out); --Z1L940 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[28]~1689 Z1L940 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L931, Z1L939, Z1_A_shift_rot_result[28]); --Z1L941 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[28]~1690 Z1L941 = AMPP_FUNCTION(Z1_A_mul_result[28], Z1L940, Z1_A_ctrl_mul_lsw); --Z1L1392 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[28]~597 Z1L1392 = AMPP_FUNCTION(Z1L1337, MC1_q_b[28], Z1L1336, Z1L941); --Z1_W_wr_data[28] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[28] Z1_W_wr_data[28] = AMPP_FUNCTION(F1__clk1, Z1L941, N1_data_out); --Z1L1393 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[28]~598 Z1L1393 = AMPP_FUNCTION(Z1_M_alu_result[28], Z1L1337, Z1L1392, Z1_W_wr_data[28]); --Z1L1471 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[28]~6783 Z1L1471 = AMPP_FUNCTION(Z1L1479, Z1L2862, Z1L2928, Z1_E_ctrl_alu_subtract); --Z1L1472 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[28]~6784 Z1L1472 = AMPP_FUNCTION(Z1L1471, Z1L1641, Z1_E_ctrl_dst_data_sel_logic_result, Z1_E_ctrl_dst_data_sel_cmp); --Z1L1827 is system_0:u0|cpu_0:the_cpu_0|E_src2[28]~142 Z1L1827 = AMPP_FUNCTION(Z1L1393, Z1L1472, Z1_D_src2_hazard_E); --Z1L1329 is system_0:u0|cpu_0:the_cpu_0|D_src2[28]~1939 Z1L1329 = AMPP_FUNCTION(Z1_D_iw[18], Z1_D_iw[21], Z1L1042, Z1L1065); --LC1_q_b[28] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[28] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[28] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L941, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1289 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[28]~3651 Z1L1289 = AMPP_FUNCTION(Z1L1731, LC1_q_b[28], Z1L1730, Z1L941); --Z1L1290 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[28]~3652 Z1L1290 = AMPP_FUNCTION(Z1_M_alu_result[28], Z1L1731, Z1L1289, Z1_W_wr_data[28]); --MC1_q_b[27] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[27] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[27] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L938, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_M_alu_result[27] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[27] Z1_M_alu_result[27] = AMPP_FUNCTION(F1__clk1, Z1L1470, N1_data_out, Z1_A_stall); --Z1_A_mul_result[27] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[27] Z1_A_mul_result[27] = AMPP_FUNCTION(F1__clk1, Z1L372, Z1_A_mul_partial_prod[27], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[27] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[27] Z1_A_slow_inst_result[27] = AMPP_FUNCTION(F1__clk1, Z1L793, N1_data_out, Z1_A_ctrl_ld); --Z1_A_inst_result[27] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[27] Z1_A_inst_result[27] = AMPP_FUNCTION(F1__clk1, Z1L2301, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L936 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[27]~1691 Z1L936 = AMPP_FUNCTION(Z1L931, Z1_A_slow_inst_result[27], Z1L932, Z1_A_inst_result[27]); --Z1_A_shift_rot_result[27] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[27] Z1_A_shift_rot_result[27] = AMPP_FUNCTION(F1__clk1, Z1L658, N1_data_out); --Z1L937 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[27]~1692 Z1L937 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L931, Z1L936, Z1_A_shift_rot_result[27]); --Z1L938 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[27]~1693 Z1L938 = AMPP_FUNCTION(Z1_A_mul_result[27], Z1L937, Z1_A_ctrl_mul_lsw); --Z1L1390 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[27]~599 Z1L1390 = AMPP_FUNCTION(Z1L1336, Z1_M_alu_result[27], Z1L1337, Z1L938); --Z1_W_wr_data[27] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[27] Z1_W_wr_data[27] = AMPP_FUNCTION(F1__clk1, Z1L938, N1_data_out); --Z1L1391 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[27]~600 Z1L1391 = AMPP_FUNCTION(MC1_q_b[27], Z1L1336, Z1L1390, Z1_W_wr_data[27]); --Z1L1469 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[27]~6785 Z1L1469 = AMPP_FUNCTION(Z1L1479, Z1L2860, Z1L2926, Z1_E_ctrl_alu_subtract); --Z1L1470 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[27]~6786 Z1L1470 = AMPP_FUNCTION(Z1L1469, Z1L1640, Z1_E_ctrl_dst_data_sel_logic_result, Z1_E_ctrl_dst_data_sel_cmp); --Z1L1824 is system_0:u0|cpu_0:the_cpu_0|E_src2[27]~141 Z1L1824 = AMPP_FUNCTION(Z1L1391, Z1L1470, Z1_D_src2_hazard_E); --Z1L1328 is system_0:u0|cpu_0:the_cpu_0|D_src2[27]~1940 Z1L1328 = AMPP_FUNCTION(Z1_D_iw[17], Z1_D_iw[21], Z1L1042, Z1L1065); --LC1_q_b[27] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[27] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[27] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L938, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1286 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[27]~3653 Z1L1286 = AMPP_FUNCTION(Z1L1730, Z1_M_alu_result[27], Z1L1731, Z1L938); --Z1L1287 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[27]~3654 Z1L1287 = AMPP_FUNCTION(LC1_q_b[27], Z1L1730, Z1L1286, Z1_W_wr_data[27]); --Z1_M_alu_result[26] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[26] Z1_M_alu_result[26] = AMPP_FUNCTION(F1__clk1, Z1L1468, N1_data_out, Z1_A_stall); --MC1_q_b[26] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[26] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[26] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L935, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[26] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[26] Z1_A_mul_result[26] = AMPP_FUNCTION(F1__clk1, Z1L369, Z1_A_mul_partial_prod[26], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[26] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[26] Z1_A_slow_inst_result[26] = AMPP_FUNCTION(F1__clk1, Z1L792, N1_data_out, Z1_A_ctrl_ld); --Z1_A_inst_result[26] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[26] Z1_A_inst_result[26] = AMPP_FUNCTION(F1__clk1, Z1L2300, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L933 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[26]~1694 Z1L933 = AMPP_FUNCTION(Z1L931, Z1_A_slow_inst_result[26], Z1L932, Z1_A_inst_result[26]); --Z1_A_shift_rot_result[26] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[26] Z1_A_shift_rot_result[26] = AMPP_FUNCTION(F1__clk1, Z1L660, N1_data_out); --Z1L934 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[26]~1695 Z1L934 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L931, Z1L933, Z1_A_shift_rot_result[26]); --Z1L935 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[26]~1696 Z1L935 = AMPP_FUNCTION(Z1_A_mul_result[26], Z1L934, Z1_A_ctrl_mul_lsw); --Z1L1388 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[26]~601 Z1L1388 = AMPP_FUNCTION(Z1L1337, MC1_q_b[26], Z1L1336, Z1L935); --Z1_W_wr_data[26] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[26] Z1_W_wr_data[26] = AMPP_FUNCTION(F1__clk1, Z1L935, N1_data_out); --Z1L1389 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[26]~602 Z1L1389 = AMPP_FUNCTION(Z1_M_alu_result[26], Z1L1337, Z1L1388, Z1_W_wr_data[26]); --Z1L1467 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[26]~6787 Z1L1467 = AMPP_FUNCTION(Z1L1479, Z1L2858, Z1L2924, Z1_E_ctrl_alu_subtract); --Z1L1468 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[26]~6788 Z1L1468 = AMPP_FUNCTION(Z1L1467, Z1L1639, Z1_E_ctrl_dst_data_sel_logic_result, Z1_E_ctrl_dst_data_sel_cmp); --Z1L1821 is system_0:u0|cpu_0:the_cpu_0|E_src2[26]~140 Z1L1821 = AMPP_FUNCTION(Z1L1389, Z1L1468, Z1_D_src2_hazard_E); --Z1L1327 is system_0:u0|cpu_0:the_cpu_0|D_src2[26]~1941 Z1L1327 = AMPP_FUNCTION(Z1_D_iw[16], Z1_D_iw[21], Z1L1042, Z1L1065); --LC1_q_b[26] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[26] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[26] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L935, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1283 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[26]~3655 Z1L1283 = AMPP_FUNCTION(Z1L1731, LC1_q_b[26], Z1L1730, Z1L935); --Z1L1284 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[26]~3656 Z1L1284 = AMPP_FUNCTION(Z1_M_alu_result[26], Z1L1731, Z1L1283, Z1_W_wr_data[26]); --MC1_q_b[25] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[25] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[25] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L930, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_M_alu_result[25] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[25] Z1_M_alu_result[25] = AMPP_FUNCTION(F1__clk1, Z1L1466, N1_data_out, Z1_A_stall); --Z1_A_mul_result[25] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[25] Z1_A_mul_result[25] = AMPP_FUNCTION(F1__clk1, Z1L366, Z1_A_mul_partial_prod[25], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[25] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[25] Z1_A_slow_inst_result[25] = AMPP_FUNCTION(F1__clk1, Z1L791, N1_data_out, Z1_A_ctrl_ld); --Z1_A_inst_result[25] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[25] Z1_A_inst_result[25] = AMPP_FUNCTION(F1__clk1, Z1L2299, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L928 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[25]~1697 Z1L928 = AMPP_FUNCTION(Z1L931, Z1_A_slow_inst_result[25], Z1L932, Z1_A_inst_result[25]); --Z1_A_shift_rot_result[25] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[25] Z1_A_shift_rot_result[25] = AMPP_FUNCTION(F1__clk1, Z1L662, N1_data_out); --Z1L929 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[25]~1698 Z1L929 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L931, Z1L928, Z1_A_shift_rot_result[25]); --Z1L930 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[25]~1699 Z1L930 = AMPP_FUNCTION(Z1_A_mul_result[25], Z1L929, Z1_A_ctrl_mul_lsw); --Z1L1386 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[25]~603 Z1L1386 = AMPP_FUNCTION(Z1L1336, Z1_M_alu_result[25], Z1L1337, Z1L930); --Z1_W_wr_data[25] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[25] Z1_W_wr_data[25] = AMPP_FUNCTION(F1__clk1, Z1L930, N1_data_out); --Z1L1387 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[25]~604 Z1L1387 = AMPP_FUNCTION(MC1_q_b[25], Z1L1336, Z1L1386, Z1_W_wr_data[25]); --Z1L1465 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[25]~6789 Z1L1465 = AMPP_FUNCTION(Z1L1479, Z1L2856, Z1L2922, Z1_E_ctrl_alu_subtract); --Z1L1466 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[25]~6790 Z1L1466 = AMPP_FUNCTION(Z1L1465, Z1L1638, Z1_E_ctrl_dst_data_sel_logic_result, Z1_E_ctrl_dst_data_sel_cmp); --Z1L1818 is system_0:u0|cpu_0:the_cpu_0|E_src2[25]~139 Z1L1818 = AMPP_FUNCTION(Z1L1387, Z1L1466, Z1_D_src2_hazard_E); --Z1L1326 is system_0:u0|cpu_0:the_cpu_0|D_src2[25]~1942 Z1L1326 = AMPP_FUNCTION(Z1_D_iw[15], Z1_D_iw[21], Z1L1042, Z1L1065); --LC1_q_b[25] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[25] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[25] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L930, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1280 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[25]~3657 Z1L1280 = AMPP_FUNCTION(Z1L1730, Z1_M_alu_result[25], Z1L1731, Z1L930); --Z1L1281 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[25]~3658 Z1L1281 = AMPP_FUNCTION(LC1_q_b[25], Z1L1730, Z1L1280, Z1_W_wr_data[25]); --Z1_M_alu_result[24] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[24] Z1_M_alu_result[24] = AMPP_FUNCTION(F1__clk1, Z1L1464, N1_data_out, Z1_A_stall); --MC1_q_b[24] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[24] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[24] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L927, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[24] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[24] Z1_A_mul_result[24] = AMPP_FUNCTION(F1__clk1, Z1L363, Z1_A_mul_partial_prod[24], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[24] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[24] Z1_A_slow_inst_result[24] = AMPP_FUNCTION(F1__clk1, Z1L790, N1_data_out, Z1_A_ctrl_ld); --Z1_A_inst_result[24] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[24] Z1_A_inst_result[24] = AMPP_FUNCTION(F1__clk1, Z1L2298, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L925 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[24]~1700 Z1L925 = AMPP_FUNCTION(Z1L931, Z1_A_slow_inst_result[24], Z1L932, Z1_A_inst_result[24]); --Z1_A_shift_rot_result[24] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[24] Z1_A_shift_rot_result[24] = AMPP_FUNCTION(F1__clk1, Z1L664, N1_data_out); --Z1L926 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[24]~1701 Z1L926 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L931, Z1L925, Z1_A_shift_rot_result[24]); --Z1L927 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[24]~1702 Z1L927 = AMPP_FUNCTION(Z1_A_mul_result[24], Z1L926, Z1_A_ctrl_mul_lsw); --Z1L1384 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[24]~605 Z1L1384 = AMPP_FUNCTION(Z1L1337, MC1_q_b[24], Z1L1336, Z1L927); --Z1_W_wr_data[24] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[24] Z1_W_wr_data[24] = AMPP_FUNCTION(F1__clk1, Z1L927, N1_data_out); --Z1L1385 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[24]~606 Z1L1385 = AMPP_FUNCTION(Z1_M_alu_result[24], Z1L1337, Z1L1384, Z1_W_wr_data[24]); --Z1L1463 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[24]~6791 Z1L1463 = AMPP_FUNCTION(Z1L1479, Z1L2854, Z1L2920, Z1_E_ctrl_alu_subtract); --Z1L1464 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[24]~6792 Z1L1464 = AMPP_FUNCTION(Z1L1463, Z1L1637, Z1_E_ctrl_dst_data_sel_logic_result, Z1_E_ctrl_dst_data_sel_cmp); --Z1L1815 is system_0:u0|cpu_0:the_cpu_0|E_src2[24]~138 Z1L1815 = AMPP_FUNCTION(Z1L1385, Z1L1464, Z1_D_src2_hazard_E); --Z1L1325 is system_0:u0|cpu_0:the_cpu_0|D_src2[24]~1943 Z1L1325 = AMPP_FUNCTION(Z1_D_iw[14], Z1_D_iw[21], Z1L1042, Z1L1065); --LC1_q_b[24] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[24] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[24] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L927, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1277 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[24]~3659 Z1L1277 = AMPP_FUNCTION(Z1L1731, LC1_q_b[24], Z1L1730, Z1L927); --Z1L1278 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[24]~3660 Z1L1278 = AMPP_FUNCTION(Z1_M_alu_result[24], Z1L1731, Z1L1277, Z1_W_wr_data[24]); --MC1_q_b[23] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[23] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[23] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L924, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[23] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[23] Z1_A_mul_result[23] = AMPP_FUNCTION(F1__clk1, Z1L360, Z1_A_mul_partial_prod[23], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[23] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[23] Z1_A_slow_inst_result[23] = AMPP_FUNCTION(F1__clk1, Z1L789, N1_data_out, Z1_A_ctrl_ld); --Z1_A_inst_result[23] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[23] Z1_A_inst_result[23] = AMPP_FUNCTION(F1__clk1, Z1L2297, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L922 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[23]~1703 Z1L922 = AMPP_FUNCTION(Z1L932, Z1_A_data_ram_ld_align_fill_bit, Z1L931, Z1_A_inst_result[23]); --Z1_A_shift_rot_result[23] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[23] Z1_A_shift_rot_result[23] = AMPP_FUNCTION(F1__clk1, Z1L666, N1_data_out); --Z1L923 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[23]~1704 Z1L923 = AMPP_FUNCTION(Z1_A_slow_inst_result[23], Z1L932, Z1L922, Z1_A_shift_rot_result[23]); --Z1L924 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[23]~1705 Z1L924 = AMPP_FUNCTION(Z1_A_mul_result[23], Z1L923, Z1_A_ctrl_mul_lsw); --Z1L1382 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[23]~607 Z1L1382 = AMPP_FUNCTION(Z1L1336, Z1_M_alu_result[23], Z1L1337, Z1L924); --Z1_W_wr_data[23] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[23] Z1_W_wr_data[23] = AMPP_FUNCTION(F1__clk1, Z1L924, N1_data_out); --Z1L1383 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[23]~608 Z1L1383 = AMPP_FUNCTION(MC1_q_b[23], Z1L1336, Z1L1382, Z1_W_wr_data[23]); --Z1L1812 is system_0:u0|cpu_0:the_cpu_0|E_src2[23]~137 Z1L1812 = AMPP_FUNCTION(Z1L1383, Z1L1462, Z1_D_src2_hazard_E); --Z1L1324 is system_0:u0|cpu_0:the_cpu_0|D_src2[23]~1944 Z1L1324 = AMPP_FUNCTION(Z1_D_iw[13], Z1_D_iw[21], Z1L1042, Z1L1065); --LC1_q_b[23] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[23] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[23] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L924, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1274 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[23]~3661 Z1L1274 = AMPP_FUNCTION(Z1L1730, Z1_M_alu_result[23], Z1L1731, Z1L924); --Z1L1275 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[23]~3662 Z1L1275 = AMPP_FUNCTION(LC1_q_b[23], Z1L1730, Z1L1274, Z1_W_wr_data[23]); --Z1L1276 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[23]~3663 Z1L1276 = AMPP_FUNCTION(Z1L1275, Z1L1461, Z1_D_src1_hazard_E, Z1_E_ctrl_dst_data_sel_cmp); --MC1_q_b[22] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[22] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[22] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L921, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[22] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[22] Z1_A_mul_result[22] = AMPP_FUNCTION(F1__clk1, Z1L357, Z1_A_mul_partial_prod[22], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[22] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[22] Z1_A_slow_inst_result[22] = AMPP_FUNCTION(F1__clk1, Z1L788, N1_data_out, Z1_A_ctrl_ld); --Z1_A_inst_result[22] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[22] Z1_A_inst_result[22] = AMPP_FUNCTION(F1__clk1, Z1L2296, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L919 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[22]~1706 Z1L919 = AMPP_FUNCTION(Z1L931, Z1_A_slow_inst_result[22], Z1L932, Z1_A_inst_result[22]); --Z1_A_shift_rot_result[22] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[22] Z1_A_shift_rot_result[22] = AMPP_FUNCTION(F1__clk1, Z1L668, N1_data_out); --Z1L920 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[22]~1707 Z1L920 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L931, Z1L919, Z1_A_shift_rot_result[22]); --Z1L921 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[22]~1708 Z1L921 = AMPP_FUNCTION(Z1_A_mul_result[22], Z1L920, Z1_A_ctrl_mul_lsw); --Z1L1380 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[22]~609 Z1L1380 = AMPP_FUNCTION(Z1L1337, MC1_q_b[22], Z1L1336, Z1L921); --Z1_W_wr_data[22] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[22] Z1_W_wr_data[22] = AMPP_FUNCTION(F1__clk1, Z1L921, N1_data_out); --Z1L1381 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[22]~610 Z1L1381 = AMPP_FUNCTION(Z1_M_alu_result[22], Z1L1337, Z1L1380, Z1_W_wr_data[22]); --Z1L1809 is system_0:u0|cpu_0:the_cpu_0|E_src2[22]~136 Z1L1809 = AMPP_FUNCTION(Z1L1381, Z1L1459, Z1_D_src2_hazard_E); --Z1L1323 is system_0:u0|cpu_0:the_cpu_0|D_src2[22]~1945 Z1L1323 = AMPP_FUNCTION(Z1_D_iw[12], Z1_D_iw[21], Z1L1042, Z1L1065); --LC1_q_b[22] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[22] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[22] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L921, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1271 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[22]~3664 Z1L1271 = AMPP_FUNCTION(Z1L1731, LC1_q_b[22], Z1L1730, Z1L921); --Z1L1272 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[22]~3665 Z1L1272 = AMPP_FUNCTION(Z1_M_alu_result[22], Z1L1731, Z1L1271, Z1_W_wr_data[22]); --Z1L1273 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[22]~3666 Z1L1273 = AMPP_FUNCTION(Z1L1272, Z1L1458, Z1_D_src1_hazard_E, Z1_E_ctrl_dst_data_sel_cmp); --MC1_q_b[21] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[21] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[21] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L918, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[21] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[21] Z1_A_mul_result[21] = AMPP_FUNCTION(F1__clk1, Z1L354, Z1_A_mul_partial_prod[21], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[21] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[21] Z1_A_slow_inst_result[21] = AMPP_FUNCTION(F1__clk1, Z1L787, N1_data_out, Z1_A_ctrl_ld); --Z1_A_inst_result[21] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[21] Z1_A_inst_result[21] = AMPP_FUNCTION(F1__clk1, Z1L2295, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L916 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[21]~1709 Z1L916 = AMPP_FUNCTION(Z1L932, Z1_A_data_ram_ld_align_fill_bit, Z1L931, Z1_A_inst_result[21]); --Z1_A_shift_rot_result[21] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[21] Z1_A_shift_rot_result[21] = AMPP_FUNCTION(F1__clk1, Z1L670, N1_data_out); --Z1L917 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[21]~1710 Z1L917 = AMPP_FUNCTION(Z1_A_slow_inst_result[21], Z1L932, Z1L916, Z1_A_shift_rot_result[21]); --Z1L918 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[21]~1711 Z1L918 = AMPP_FUNCTION(Z1_A_mul_result[21], Z1L917, Z1_A_ctrl_mul_lsw); --Z1L1378 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[21]~611 Z1L1378 = AMPP_FUNCTION(Z1L1336, Z1_M_alu_result[21], Z1L1337, Z1L918); --Z1_W_wr_data[21] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[21] Z1_W_wr_data[21] = AMPP_FUNCTION(F1__clk1, Z1L918, N1_data_out); --Z1L1379 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[21]~612 Z1L1379 = AMPP_FUNCTION(MC1_q_b[21], Z1L1336, Z1L1378, Z1_W_wr_data[21]); --Z1L1806 is system_0:u0|cpu_0:the_cpu_0|E_src2[21]~135 Z1L1806 = AMPP_FUNCTION(Z1L1379, Z1L1456, Z1_D_src2_hazard_E); --Z1L1322 is system_0:u0|cpu_0:the_cpu_0|D_src2[21]~1946 Z1L1322 = AMPP_FUNCTION(Z1_D_iw[11], Z1_D_iw[21], Z1L1042, Z1L1065); --LC1_q_b[21] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[21] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[21] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L918, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1268 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[21]~3667 Z1L1268 = AMPP_FUNCTION(Z1L1730, Z1_M_alu_result[21], Z1L1731, Z1L918); --Z1L1269 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[21]~3668 Z1L1269 = AMPP_FUNCTION(LC1_q_b[21], Z1L1730, Z1L1268, Z1_W_wr_data[21]); --Z1L1270 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[21]~3669 Z1L1270 = AMPP_FUNCTION(Z1L1269, Z1L1455, Z1_D_src1_hazard_E, Z1_E_ctrl_dst_data_sel_cmp); --MC1_q_b[20] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[20] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[20] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L915, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[20] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[20] Z1_A_mul_result[20] = AMPP_FUNCTION(F1__clk1, Z1L351, Z1_A_mul_partial_prod[20], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[20] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[20] Z1_A_slow_inst_result[20] = AMPP_FUNCTION(F1__clk1, Z1L786, N1_data_out, Z1_A_ctrl_ld); --Z1_A_inst_result[20] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[20] Z1_A_inst_result[20] = AMPP_FUNCTION(F1__clk1, Z1L2294, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L913 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[20]~1712 Z1L913 = AMPP_FUNCTION(Z1L931, Z1_A_slow_inst_result[20], Z1L932, Z1_A_inst_result[20]); --Z1_A_shift_rot_result[20] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[20] Z1_A_shift_rot_result[20] = AMPP_FUNCTION(F1__clk1, Z1L672, N1_data_out); --Z1L914 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[20]~1713 Z1L914 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L931, Z1L913, Z1_A_shift_rot_result[20]); --Z1L915 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[20]~1714 Z1L915 = AMPP_FUNCTION(Z1_A_mul_result[20], Z1L914, Z1_A_ctrl_mul_lsw); --Z1L1376 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[20]~613 Z1L1376 = AMPP_FUNCTION(Z1L1337, MC1_q_b[20], Z1L1336, Z1L915); --Z1_W_wr_data[20] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[20] Z1_W_wr_data[20] = AMPP_FUNCTION(F1__clk1, Z1L915, N1_data_out); --Z1L1377 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[20]~614 Z1L1377 = AMPP_FUNCTION(Z1_M_alu_result[20], Z1L1337, Z1L1376, Z1_W_wr_data[20]); --Z1L1803 is system_0:u0|cpu_0:the_cpu_0|E_src2[20]~134 Z1L1803 = AMPP_FUNCTION(Z1L1377, Z1L1453, Z1_D_src2_hazard_E); --Z1L1321 is system_0:u0|cpu_0:the_cpu_0|D_src2[20]~1947 Z1L1321 = AMPP_FUNCTION(Z1_D_iw[10], Z1_D_iw[21], Z1L1042, Z1L1065); --LC1_q_b[20] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[20] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[20] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L915, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1265 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[20]~3670 Z1L1265 = AMPP_FUNCTION(Z1L1731, LC1_q_b[20], Z1L1730, Z1L915); --Z1L1266 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[20]~3671 Z1L1266 = AMPP_FUNCTION(Z1_M_alu_result[20], Z1L1731, Z1L1265, Z1_W_wr_data[20]); --Z1L1267 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[20]~3672 Z1L1267 = AMPP_FUNCTION(Z1L1266, Z1L1452, Z1_D_src1_hazard_E, Z1_E_ctrl_dst_data_sel_cmp); --MC1_q_b[19] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[19] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[19] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L912, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[19] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[19] Z1_A_mul_result[19] = AMPP_FUNCTION(F1__clk1, Z1L348, Z1_A_mul_partial_prod[19], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[19] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[19] Z1_A_slow_inst_result[19] = AMPP_FUNCTION(F1__clk1, Z1L785, N1_data_out, Z1_A_ctrl_ld); --Z1_A_inst_result[19] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[19] Z1_A_inst_result[19] = AMPP_FUNCTION(F1__clk1, Z1L2293, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L910 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[19]~1715 Z1L910 = AMPP_FUNCTION(Z1L932, Z1_A_data_ram_ld_align_fill_bit, Z1L931, Z1_A_inst_result[19]); --Z1_A_shift_rot_result[19] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[19] Z1_A_shift_rot_result[19] = AMPP_FUNCTION(F1__clk1, Z1L674, N1_data_out); --Z1L911 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[19]~1716 Z1L911 = AMPP_FUNCTION(Z1_A_slow_inst_result[19], Z1L932, Z1L910, Z1_A_shift_rot_result[19]); --Z1L912 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[19]~1717 Z1L912 = AMPP_FUNCTION(Z1_A_mul_result[19], Z1L911, Z1_A_ctrl_mul_lsw); --Z1L1374 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[19]~615 Z1L1374 = AMPP_FUNCTION(Z1L1336, Z1_M_alu_result[19], Z1L1337, Z1L912); --Z1_W_wr_data[19] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[19] Z1_W_wr_data[19] = AMPP_FUNCTION(F1__clk1, Z1L912, N1_data_out); --Z1L1375 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[19]~616 Z1L1375 = AMPP_FUNCTION(MC1_q_b[19], Z1L1336, Z1L1374, Z1_W_wr_data[19]); --Z1L1800 is system_0:u0|cpu_0:the_cpu_0|E_src2[19]~133 Z1L1800 = AMPP_FUNCTION(Z1L1375, Z1L1450, Z1_D_src2_hazard_E); --Z1L1320 is system_0:u0|cpu_0:the_cpu_0|D_src2[19]~1948 Z1L1320 = AMPP_FUNCTION(Z1_D_iw[9], Z1_D_iw[21], Z1L1042, Z1L1065); --LC1_q_b[19] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[19] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[19] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L912, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1262 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[19]~3673 Z1L1262 = AMPP_FUNCTION(Z1L1730, Z1_M_alu_result[19], Z1L1731, Z1L912); --Z1L1263 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[19]~3674 Z1L1263 = AMPP_FUNCTION(LC1_q_b[19], Z1L1730, Z1L1262, Z1_W_wr_data[19]); --Z1L1264 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[19]~3675 Z1L1264 = AMPP_FUNCTION(Z1L1263, Z1L1449, Z1_D_src1_hazard_E, Z1_E_ctrl_dst_data_sel_cmp); --MC1_q_b[18] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[18] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[18] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L909, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[18] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[18] Z1_A_mul_result[18] = AMPP_FUNCTION(F1__clk1, Z1L345, Z1_A_mul_partial_prod[18], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[18] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[18] Z1_A_slow_inst_result[18] = AMPP_FUNCTION(F1__clk1, Z1L784, N1_data_out, Z1_A_ctrl_ld); --Z1_A_inst_result[18] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[18] Z1_A_inst_result[18] = AMPP_FUNCTION(F1__clk1, Z1L2292, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L907 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[18]~1718 Z1L907 = AMPP_FUNCTION(Z1L931, Z1_A_slow_inst_result[18], Z1L932, Z1_A_inst_result[18]); --Z1_A_shift_rot_result[18] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[18] Z1_A_shift_rot_result[18] = AMPP_FUNCTION(F1__clk1, Z1L676, N1_data_out); --Z1L908 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[18]~1719 Z1L908 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L931, Z1L907, Z1_A_shift_rot_result[18]); --Z1L909 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[18]~1720 Z1L909 = AMPP_FUNCTION(Z1_A_mul_result[18], Z1L908, Z1_A_ctrl_mul_lsw); --Z1L1372 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[18]~617 Z1L1372 = AMPP_FUNCTION(Z1L1337, MC1_q_b[18], Z1L1336, Z1L909); --Z1_W_wr_data[18] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[18] Z1_W_wr_data[18] = AMPP_FUNCTION(F1__clk1, Z1L909, N1_data_out); --Z1L1373 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[18]~618 Z1L1373 = AMPP_FUNCTION(Z1_M_alu_result[18], Z1L1337, Z1L1372, Z1_W_wr_data[18]); --Z1L1797 is system_0:u0|cpu_0:the_cpu_0|E_src2[18]~132 Z1L1797 = AMPP_FUNCTION(Z1L1373, Z1L1447, Z1_D_src2_hazard_E); --Z1L1319 is system_0:u0|cpu_0:the_cpu_0|D_src2[18]~1949 Z1L1319 = AMPP_FUNCTION(Z1_D_iw[8], Z1_D_iw[21], Z1L1042, Z1L1065); --LC1_q_b[18] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[18] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[18] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L909, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1259 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[18]~3676 Z1L1259 = AMPP_FUNCTION(Z1L1731, LC1_q_b[18], Z1L1730, Z1L909); --Z1L1260 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[18]~3677 Z1L1260 = AMPP_FUNCTION(Z1_M_alu_result[18], Z1L1731, Z1L1259, Z1_W_wr_data[18]); --Z1L1261 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[18]~3678 Z1L1261 = AMPP_FUNCTION(Z1L1260, Z1L1446, Z1_D_src1_hazard_E, Z1_E_ctrl_dst_data_sel_cmp); --MC1_q_b[17] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[17] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[17] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L906, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[17] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[17] Z1_A_mul_result[17] = AMPP_FUNCTION(F1__clk1, Z1L342, Z1_A_mul_partial_prod[17], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[17] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[17] Z1_A_slow_inst_result[17] = AMPP_FUNCTION(F1__clk1, Z1L783, N1_data_out, Z1_A_ctrl_ld); --Z1_A_inst_result[17] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[17] Z1_A_inst_result[17] = AMPP_FUNCTION(F1__clk1, Z1L2291, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L904 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[17]~1721 Z1L904 = AMPP_FUNCTION(Z1L932, Z1_A_data_ram_ld_align_fill_bit, Z1L931, Z1_A_inst_result[17]); --Z1_A_shift_rot_result[17] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[17] Z1_A_shift_rot_result[17] = AMPP_FUNCTION(F1__clk1, Z1L678, N1_data_out); --Z1L905 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[17]~1722 Z1L905 = AMPP_FUNCTION(Z1_A_slow_inst_result[17], Z1L932, Z1L904, Z1_A_shift_rot_result[17]); --Z1L906 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[17]~1723 Z1L906 = AMPP_FUNCTION(Z1_A_mul_result[17], Z1L905, Z1_A_ctrl_mul_lsw); --Z1L1370 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[17]~619 Z1L1370 = AMPP_FUNCTION(Z1L1336, Z1_M_alu_result[17], Z1L1337, Z1L906); --Z1_W_wr_data[17] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[17] Z1_W_wr_data[17] = AMPP_FUNCTION(F1__clk1, Z1L906, N1_data_out); --Z1L1371 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[17]~620 Z1L1371 = AMPP_FUNCTION(MC1_q_b[17], Z1L1336, Z1L1370, Z1_W_wr_data[17]); --Z1L1794 is system_0:u0|cpu_0:the_cpu_0|E_src2[17]~131 Z1L1794 = AMPP_FUNCTION(Z1L1371, Z1L1444, Z1_D_src2_hazard_E); --Z1L1318 is system_0:u0|cpu_0:the_cpu_0|D_src2[17]~1950 Z1L1318 = AMPP_FUNCTION(Z1_D_iw[7], Z1_D_iw[21], Z1L1042, Z1L1065); --LC1_q_b[17] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[17] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[17] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L906, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1256 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[17]~3679 Z1L1256 = AMPP_FUNCTION(Z1L1730, Z1_M_alu_result[17], Z1L1731, Z1L906); --Z1L1257 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[17]~3680 Z1L1257 = AMPP_FUNCTION(LC1_q_b[17], Z1L1730, Z1L1256, Z1_W_wr_data[17]); --Z1L1258 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[17]~3681 Z1L1258 = AMPP_FUNCTION(Z1L1257, Z1L1443, Z1_D_src1_hazard_E, Z1_E_ctrl_dst_data_sel_cmp); --MC1_q_b[16] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[16] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[16] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L903, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[16] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[16] Z1_A_mul_result[16] = AMPP_FUNCTION(F1__clk1, Z1L339, Z1_A_mul_partial_prod[16], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[16] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[16] Z1_A_slow_inst_result[16] = AMPP_FUNCTION(F1__clk1, Z1L782, N1_data_out, Z1_A_ctrl_ld); --Z1_A_inst_result[16] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[16] Z1_A_inst_result[16] = AMPP_FUNCTION(F1__clk1, Z1L2290, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L901 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[16]~1724 Z1L901 = AMPP_FUNCTION(Z1L931, Z1_A_slow_inst_result[16], Z1L932, Z1_A_inst_result[16]); --Z1_A_shift_rot_result[16] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[16] Z1_A_shift_rot_result[16] = AMPP_FUNCTION(F1__clk1, Z1L680, N1_data_out); --Z1L902 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[16]~1725 Z1L902 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L931, Z1L901, Z1_A_shift_rot_result[16]); --Z1L903 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[16]~1726 Z1L903 = AMPP_FUNCTION(Z1_A_mul_result[16], Z1L902, Z1_A_ctrl_mul_lsw); --Z1L1368 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[16]~621 Z1L1368 = AMPP_FUNCTION(Z1L1337, MC1_q_b[16], Z1L1336, Z1L903); --Z1_W_wr_data[16] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[16] Z1_W_wr_data[16] = AMPP_FUNCTION(F1__clk1, Z1L903, N1_data_out); --Z1L1369 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[16]~622 Z1L1369 = AMPP_FUNCTION(Z1_M_alu_result[16], Z1L1337, Z1L1368, Z1_W_wr_data[16]); --Z1L1791 is system_0:u0|cpu_0:the_cpu_0|E_src2[16]~130 Z1L1791 = AMPP_FUNCTION(Z1L1369, Z1L1441, Z1_D_src2_hazard_E); --Z1L1317 is system_0:u0|cpu_0:the_cpu_0|D_src2[16]~1951 Z1L1317 = AMPP_FUNCTION(Z1_D_iw[6], Z1_D_iw[21], Z1L1042, Z1L1065); --LC1_q_b[16] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[16] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[16] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L903, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1253 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[16]~3682 Z1L1253 = AMPP_FUNCTION(Z1L1731, LC1_q_b[16], Z1L1730, Z1L903); --Z1L1254 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[16]~3683 Z1L1254 = AMPP_FUNCTION(Z1_M_alu_result[16], Z1L1731, Z1L1253, Z1_W_wr_data[16]); --Z1L1255 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[16]~3684 Z1L1255 = AMPP_FUNCTION(Z1L1254, Z1L1440, Z1_D_src1_hazard_E, Z1_E_ctrl_dst_data_sel_cmp); --MC1_q_b[15] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[15] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[15] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L900, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[15] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[15] Z1_A_mul_result[15] = AMPP_FUNCTION(F1__clk1, Z1L336, Z1_A_mul_partial_prod[15], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_ctrl_ld8 is system_0:u0|cpu_0:the_cpu_0|A_ctrl_ld8 Z1_A_ctrl_ld8 = AMPP_FUNCTION(F1__clk1, Z1_M_ctrl_ld8, N1_data_out, Z1_A_stall); --Z1L897 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[15]~1727 Z1L897 = AMPP_FUNCTION(Z1_A_ctrl_shift_rot, Z1_A_ctrl_ld8, Z1_A_slow_inst_sel); --Z1_A_slow_inst_result[15] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[15] Z1_A_slow_inst_result[15] = AMPP_FUNCTION(F1__clk1, Z1L762, Z1_A_slow_ld_data_fill_bit, N1_data_out, Z1_A_ctrl_ld8, Z1_A_ctrl_ld); --Z1_A_inst_result[15] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[15] Z1_A_inst_result[15] = AMPP_FUNCTION(F1__clk1, Z1L2289, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1_A_ld_align_sh16 is system_0:u0|cpu_0:the_cpu_0|A_ld_align_sh16 Z1_A_ld_align_sh16 = AMPP_FUNCTION(F1__clk1, Z1L2323, N1_data_out, Z1_A_stall); --Z1L24 is system_0:u0|cpu_0:the_cpu_0|A_data_ram_ld16_data[15]~72 Z1L24 = AMPP_FUNCTION(Z1_A_inst_result[31], Z1_A_inst_result[15], Z1_A_ld_align_sh16); --Z1L898 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[15]~1728 Z1L898 = AMPP_FUNCTION(Z1L897, Z1_A_slow_inst_result[15], Z1L932, Z1L24); --Z1_A_shift_rot_result[15] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[15] Z1_A_shift_rot_result[15] = AMPP_FUNCTION(F1__clk1, Z1L682, N1_data_out); --Z1L899 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[15]~1729 Z1L899 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L897, Z1L898, Z1_A_shift_rot_result[15]); --Z1L900 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[15]~1730 Z1L900 = AMPP_FUNCTION(Z1_A_mul_result[15], Z1L899, Z1_A_ctrl_mul_lsw); --Z1L1366 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[15]~623 Z1L1366 = AMPP_FUNCTION(Z1L1336, Z1_M_alu_result[15], Z1L1337, Z1L900); --Z1_W_wr_data[15] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[15] Z1_W_wr_data[15] = AMPP_FUNCTION(F1__clk1, Z1L900, N1_data_out); --Z1L1367 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[15]~624 Z1L1367 = AMPP_FUNCTION(MC1_q_b[15], Z1L1336, Z1L1366, Z1_W_wr_data[15]); --Z1L1788 is system_0:u0|cpu_0:the_cpu_0|E_src2[15]~129 Z1L1788 = AMPP_FUNCTION(Z1L1367, Z1L1438, Z1_D_src2_hazard_E); --Z1L1316 is system_0:u0|cpu_0:the_cpu_0|D_src2[15]~1952 Z1L1316 = AMPP_FUNCTION(Z1_D_iw[21], Z1_D_iw[5], Z1_D_iw[2], Z1L1041); --LC1_q_b[15] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[15] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[15] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L900, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1250 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[15]~3685 Z1L1250 = AMPP_FUNCTION(Z1L1730, Z1_M_alu_result[15], Z1L1731, Z1L900); --Z1L1251 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[15]~3686 Z1L1251 = AMPP_FUNCTION(LC1_q_b[15], Z1L1730, Z1L1250, Z1_W_wr_data[15]); --Z1L1252 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[15]~3687 Z1L1252 = AMPP_FUNCTION(Z1L1251, Z1L1437, Z1_D_src1_hazard_E, Z1_E_ctrl_dst_data_sel_cmp); --MC1_q_b[14] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[14] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[14] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L896, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[14] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[14] Z1_A_mul_result[14] = AMPP_FUNCTION(F1__clk1, Z1L333, Z1_A_mul_partial_prod[14], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[14] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[14] Z1_A_slow_inst_result[14] = AMPP_FUNCTION(F1__clk1, Z1L759, Z1_A_slow_ld_data_fill_bit, N1_data_out, Z1_A_ctrl_ld8, Z1_A_ctrl_ld); --Z1_A_inst_result[14] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[14] Z1_A_inst_result[14] = AMPP_FUNCTION(F1__clk1, Z1L2288, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L23 is system_0:u0|cpu_0:the_cpu_0|A_data_ram_ld16_data[14]~73 Z1L23 = AMPP_FUNCTION(Z1_A_inst_result[30], Z1_A_inst_result[14], Z1_A_ld_align_sh16); --Z1L894 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[14]~1731 Z1L894 = AMPP_FUNCTION(Z1L897, Z1_A_slow_inst_result[14], Z1L932, Z1L23); --Z1_A_shift_rot_result[14] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[14] Z1_A_shift_rot_result[14] = AMPP_FUNCTION(F1__clk1, Z1L684, N1_data_out); --Z1L895 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[14]~1732 Z1L895 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L897, Z1L894, Z1_A_shift_rot_result[14]); --Z1L896 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[14]~1733 Z1L896 = AMPP_FUNCTION(Z1_A_mul_result[14], Z1L895, Z1_A_ctrl_mul_lsw); --Z1L1364 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[14]~625 Z1L1364 = AMPP_FUNCTION(Z1L1337, MC1_q_b[14], Z1L1336, Z1L896); --Z1_W_wr_data[14] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[14] Z1_W_wr_data[14] = AMPP_FUNCTION(F1__clk1, Z1L896, N1_data_out); --Z1L1365 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[14]~626 Z1L1365 = AMPP_FUNCTION(Z1_M_alu_result[14], Z1L1337, Z1L1364, Z1_W_wr_data[14]); --Z1L1785 is system_0:u0|cpu_0:the_cpu_0|E_src2[14]~128 Z1L1785 = AMPP_FUNCTION(Z1L1365, Z1L1435, Z1_D_src2_hazard_E); --Z1L1315 is system_0:u0|cpu_0:the_cpu_0|D_src2[14]~1953 Z1L1315 = AMPP_FUNCTION(Z1_D_iw[20], Z1_D_iw[5], Z1_D_iw[2], Z1L1041); --LC1_q_b[14] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[14] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[14] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L896, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1247 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[14]~3688 Z1L1247 = AMPP_FUNCTION(Z1L1731, LC1_q_b[14], Z1L1730, Z1L896); --Z1L1248 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[14]~3689 Z1L1248 = AMPP_FUNCTION(Z1_M_alu_result[14], Z1L1731, Z1L1247, Z1_W_wr_data[14]); --Z1L1249 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[14]~3690 Z1L1249 = AMPP_FUNCTION(Z1L1248, Z1L1434, Z1_D_src1_hazard_E, Z1_E_ctrl_dst_data_sel_cmp); --MC1_q_b[13] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[13] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[13] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L893, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[13] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[13] Z1_A_mul_result[13] = AMPP_FUNCTION(F1__clk1, Z1L330, Z1_A_mul_partial_prod[13], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[13] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[13] Z1_A_slow_inst_result[13] = AMPP_FUNCTION(F1__clk1, Z1L756, Z1_A_slow_ld_data_fill_bit, N1_data_out, Z1_A_ctrl_ld8, Z1_A_ctrl_ld); --Z1_A_inst_result[13] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[13] Z1_A_inst_result[13] = AMPP_FUNCTION(F1__clk1, Z1L2287, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L22 is system_0:u0|cpu_0:the_cpu_0|A_data_ram_ld16_data[13]~74 Z1L22 = AMPP_FUNCTION(Z1_A_inst_result[29], Z1_A_inst_result[13], Z1_A_ld_align_sh16); --Z1L891 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[13]~1734 Z1L891 = AMPP_FUNCTION(Z1L897, Z1_A_slow_inst_result[13], Z1L932, Z1L22); --Z1_A_shift_rot_result[13] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[13] Z1_A_shift_rot_result[13] = AMPP_FUNCTION(F1__clk1, Z1L686, N1_data_out); --Z1L892 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[13]~1735 Z1L892 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L897, Z1L891, Z1_A_shift_rot_result[13]); --Z1L893 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[13]~1736 Z1L893 = AMPP_FUNCTION(Z1_A_mul_result[13], Z1L892, Z1_A_ctrl_mul_lsw); --Z1L1362 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[13]~627 Z1L1362 = AMPP_FUNCTION(Z1L1336, Z1_M_alu_result[13], Z1L1337, Z1L893); --Z1_W_wr_data[13] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[13] Z1_W_wr_data[13] = AMPP_FUNCTION(F1__clk1, Z1L893, N1_data_out); --Z1L1363 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[13]~628 Z1L1363 = AMPP_FUNCTION(MC1_q_b[13], Z1L1336, Z1L1362, Z1_W_wr_data[13]); --Z1L1782 is system_0:u0|cpu_0:the_cpu_0|E_src2[13]~127 Z1L1782 = AMPP_FUNCTION(Z1L1363, Z1L1432, Z1_D_src2_hazard_E); --Z1L1314 is system_0:u0|cpu_0:the_cpu_0|D_src2[13]~1954 Z1L1314 = AMPP_FUNCTION(Z1_D_iw[19], Z1_D_iw[5], Z1_D_iw[2], Z1L1041); --LC1_q_b[13] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[13] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[13] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L893, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1244 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[13]~3691 Z1L1244 = AMPP_FUNCTION(Z1L1730, Z1_M_alu_result[13], Z1L1731, Z1L893); --Z1L1245 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[13]~3692 Z1L1245 = AMPP_FUNCTION(LC1_q_b[13], Z1L1730, Z1L1244, Z1_W_wr_data[13]); --Z1L1246 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[13]~3693 Z1L1246 = AMPP_FUNCTION(Z1L1245, Z1L1431, Z1_D_src1_hazard_E, Z1_E_ctrl_dst_data_sel_cmp); --MC1_q_b[12] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[12] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[12] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L890, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[12] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[12] Z1_A_mul_result[12] = AMPP_FUNCTION(F1__clk1, Z1L327, Z1_A_mul_partial_prod[12], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[12] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[12] Z1_A_slow_inst_result[12] = AMPP_FUNCTION(F1__clk1, Z1L753, Z1_A_slow_ld_data_fill_bit, N1_data_out, Z1_A_ctrl_ld8, Z1_A_ctrl_ld); --Z1_A_inst_result[12] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[12] Z1_A_inst_result[12] = AMPP_FUNCTION(F1__clk1, Z1L2286, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L21 is system_0:u0|cpu_0:the_cpu_0|A_data_ram_ld16_data[12]~75 Z1L21 = AMPP_FUNCTION(Z1_A_inst_result[28], Z1_A_inst_result[12], Z1_A_ld_align_sh16); --Z1L888 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[12]~1737 Z1L888 = AMPP_FUNCTION(Z1L897, Z1_A_slow_inst_result[12], Z1L932, Z1L21); --Z1_A_shift_rot_result[12] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[12] Z1_A_shift_rot_result[12] = AMPP_FUNCTION(F1__clk1, Z1L688, N1_data_out); --Z1L889 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[12]~1738 Z1L889 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L897, Z1L888, Z1_A_shift_rot_result[12]); --Z1L890 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[12]~1739 Z1L890 = AMPP_FUNCTION(Z1_A_mul_result[12], Z1L889, Z1_A_ctrl_mul_lsw); --Z1L1360 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[12]~629 Z1L1360 = AMPP_FUNCTION(Z1L1337, MC1_q_b[12], Z1L1336, Z1L890); --Z1_W_wr_data[12] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[12] Z1_W_wr_data[12] = AMPP_FUNCTION(F1__clk1, Z1L890, N1_data_out); --Z1L1361 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[12]~630 Z1L1361 = AMPP_FUNCTION(Z1_M_alu_result[12], Z1L1337, Z1L1360, Z1_W_wr_data[12]); --Z1L1779 is system_0:u0|cpu_0:the_cpu_0|E_src2[12]~126 Z1L1779 = AMPP_FUNCTION(Z1L1361, Z1L1429, Z1_D_src2_hazard_E); --Z1L1313 is system_0:u0|cpu_0:the_cpu_0|D_src2[12]~1955 Z1L1313 = AMPP_FUNCTION(Z1_D_iw[18], Z1_D_iw[5], Z1_D_iw[2], Z1L1041); --LC1_q_b[12] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[12] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[12] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L890, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1241 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[12]~3694 Z1L1241 = AMPP_FUNCTION(Z1L1731, LC1_q_b[12], Z1L1730, Z1L890); --Z1L1242 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[12]~3695 Z1L1242 = AMPP_FUNCTION(Z1_M_alu_result[12], Z1L1731, Z1L1241, Z1_W_wr_data[12]); --Z1L1243 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[12]~3696 Z1L1243 = AMPP_FUNCTION(Z1L1242, Z1L1428, Z1_D_src1_hazard_E, Z1_E_ctrl_dst_data_sel_cmp); --MC1_q_b[11] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[11] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[11] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L887, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[11] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[11] Z1_A_mul_result[11] = AMPP_FUNCTION(F1__clk1, Z1L324, Z1_A_mul_partial_prod[11], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[11] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[11] Z1_A_slow_inst_result[11] = AMPP_FUNCTION(F1__clk1, Z1L750, Z1_A_slow_ld_data_fill_bit, N1_data_out, Z1_A_ctrl_ld8, Z1_A_ctrl_ld); --Z1_A_inst_result[11] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[11] Z1_A_inst_result[11] = AMPP_FUNCTION(F1__clk1, Z1L2285, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L20 is system_0:u0|cpu_0:the_cpu_0|A_data_ram_ld16_data[11]~76 Z1L20 = AMPP_FUNCTION(Z1_A_inst_result[27], Z1_A_inst_result[11], Z1_A_ld_align_sh16); --Z1L885 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[11]~1740 Z1L885 = AMPP_FUNCTION(Z1L897, Z1_A_slow_inst_result[11], Z1L932, Z1L20); --Z1_A_shift_rot_result[11] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[11] Z1_A_shift_rot_result[11] = AMPP_FUNCTION(F1__clk1, Z1L690, N1_data_out); --Z1L886 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[11]~1741 Z1L886 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L897, Z1L885, Z1_A_shift_rot_result[11]); --Z1L887 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[11]~1742 Z1L887 = AMPP_FUNCTION(Z1_A_mul_result[11], Z1L886, Z1_A_ctrl_mul_lsw); --Z1L1358 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[11]~631 Z1L1358 = AMPP_FUNCTION(Z1L1336, Z1_M_alu_result[11], Z1L1337, Z1L887); --Z1_W_wr_data[11] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[11] Z1_W_wr_data[11] = AMPP_FUNCTION(F1__clk1, Z1L887, N1_data_out); --Z1L1359 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[11]~632 Z1L1359 = AMPP_FUNCTION(MC1_q_b[11], Z1L1336, Z1L1358, Z1_W_wr_data[11]); --Z1L1776 is system_0:u0|cpu_0:the_cpu_0|E_src2[11]~125 Z1L1776 = AMPP_FUNCTION(Z1L1359, Z1L1426, Z1_D_src2_hazard_E); --Z1L1312 is system_0:u0|cpu_0:the_cpu_0|D_src2[11]~1956 Z1L1312 = AMPP_FUNCTION(Z1_D_iw[17], Z1_D_iw[5], Z1_D_iw[2], Z1L1041); --LC1_q_b[11] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[11] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[11] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L887, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1238 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[11]~3697 Z1L1238 = AMPP_FUNCTION(Z1L1730, Z1_M_alu_result[11], Z1L1731, Z1L887); --Z1L1239 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[11]~3698 Z1L1239 = AMPP_FUNCTION(LC1_q_b[11], Z1L1730, Z1L1238, Z1_W_wr_data[11]); --Z1L1240 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[11]~3699 Z1L1240 = AMPP_FUNCTION(Z1L1239, Z1L1425, Z1_D_src1_hazard_E, Z1_E_ctrl_dst_data_sel_cmp); --MC1_q_b[10] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[10] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[10] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L884, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[10] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[10] Z1_A_mul_result[10] = AMPP_FUNCTION(F1__clk1, Z1L321, Z1_A_mul_partial_prod[10], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[10] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[10] Z1_A_slow_inst_result[10] = AMPP_FUNCTION(F1__clk1, Z1L747, Z1_A_slow_ld_data_fill_bit, N1_data_out, Z1_A_ctrl_ld8, Z1_A_ctrl_ld); --Z1_A_inst_result[10] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[10] Z1_A_inst_result[10] = AMPP_FUNCTION(F1__clk1, Z1L2284, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L19 is system_0:u0|cpu_0:the_cpu_0|A_data_ram_ld16_data[10]~77 Z1L19 = AMPP_FUNCTION(Z1_A_inst_result[26], Z1_A_inst_result[10], Z1_A_ld_align_sh16); --Z1L882 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[10]~1743 Z1L882 = AMPP_FUNCTION(Z1L897, Z1_A_slow_inst_result[10], Z1L932, Z1L19); --Z1_A_shift_rot_result[10] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[10] Z1_A_shift_rot_result[10] = AMPP_FUNCTION(F1__clk1, Z1L692, N1_data_out); --Z1L883 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[10]~1744 Z1L883 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L897, Z1L882, Z1_A_shift_rot_result[10]); --Z1L884 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[10]~1745 Z1L884 = AMPP_FUNCTION(Z1_A_mul_result[10], Z1L883, Z1_A_ctrl_mul_lsw); --Z1L1356 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[10]~633 Z1L1356 = AMPP_FUNCTION(Z1L1337, MC1_q_b[10], Z1L1336, Z1L884); --Z1_W_wr_data[10] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[10] Z1_W_wr_data[10] = AMPP_FUNCTION(F1__clk1, Z1L884, N1_data_out); --Z1L1357 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[10]~634 Z1L1357 = AMPP_FUNCTION(Z1_M_alu_result[10], Z1L1337, Z1L1356, Z1_W_wr_data[10]); --Z1L1773 is system_0:u0|cpu_0:the_cpu_0|E_src2[10]~124 Z1L1773 = AMPP_FUNCTION(Z1L1357, Z1L1422, Z1_D_src2_hazard_E); --Z1L1311 is system_0:u0|cpu_0:the_cpu_0|D_src2[10]~1957 Z1L1311 = AMPP_FUNCTION(Z1_D_iw[16], Z1_D_iw[5], Z1_D_iw[2], Z1L1041); --LC1_q_b[10] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[10] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[10] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L884, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1235 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[10]~3700 Z1L1235 = AMPP_FUNCTION(Z1L1731, LC1_q_b[10], Z1L1730, Z1L884); --Z1L1236 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[10]~3701 Z1L1236 = AMPP_FUNCTION(Z1_M_alu_result[10], Z1L1731, Z1L1235, Z1_W_wr_data[10]); --MC1_q_b[9] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[9] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[9] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L881, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[9] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[9] Z1_A_mul_result[9] = AMPP_FUNCTION(F1__clk1, Z1L318, Z1_A_mul_partial_prod[9], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[9] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[9] Z1_A_slow_inst_result[9] = AMPP_FUNCTION(F1__clk1, Z1L744, Z1_A_slow_ld_data_fill_bit, N1_data_out, Z1_A_ctrl_ld8, Z1_A_ctrl_ld); --Z1_A_inst_result[9] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[9] Z1_A_inst_result[9] = AMPP_FUNCTION(F1__clk1, Z1L2283, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L18 is system_0:u0|cpu_0:the_cpu_0|A_data_ram_ld16_data[9]~78 Z1L18 = AMPP_FUNCTION(Z1_A_inst_result[25], Z1_A_inst_result[9], Z1_A_ld_align_sh16); --Z1L879 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[9]~1746 Z1L879 = AMPP_FUNCTION(Z1L897, Z1_A_slow_inst_result[9], Z1L932, Z1L18); --Z1_A_shift_rot_result[9] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[9] Z1_A_shift_rot_result[9] = AMPP_FUNCTION(F1__clk1, Z1L694, N1_data_out); --Z1L880 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[9]~1747 Z1L880 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L897, Z1L879, Z1_A_shift_rot_result[9]); --Z1L881 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[9]~1748 Z1L881 = AMPP_FUNCTION(Z1_A_mul_result[9], Z1L880, Z1_A_ctrl_mul_lsw); --Z1L1354 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[9]~635 Z1L1354 = AMPP_FUNCTION(Z1L1336, Z1_M_alu_result[9], Z1L1337, Z1L881); --Z1_W_wr_data[9] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[9] Z1_W_wr_data[9] = AMPP_FUNCTION(F1__clk1, Z1L881, N1_data_out); --Z1L1355 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[9]~636 Z1L1355 = AMPP_FUNCTION(MC1_q_b[9], Z1L1336, Z1L1354, Z1_W_wr_data[9]); --Z1L1770 is system_0:u0|cpu_0:the_cpu_0|E_src2[9]~123 Z1L1770 = AMPP_FUNCTION(Z1L1355, Z1L1420, Z1_D_src2_hazard_E); --Z1L1310 is system_0:u0|cpu_0:the_cpu_0|D_src2[9]~1958 Z1L1310 = AMPP_FUNCTION(Z1_D_iw[15], Z1_D_iw[5], Z1_D_iw[2], Z1L1041); --LC1_q_b[9] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[9] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[9] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L881, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1232 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[9]~3702 Z1L1232 = AMPP_FUNCTION(Z1L1730, Z1_M_alu_result[9], Z1L1731, Z1L881); --Z1L1233 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[9]~3703 Z1L1233 = AMPP_FUNCTION(LC1_q_b[9], Z1L1730, Z1L1232, Z1_W_wr_data[9]); --MC1_q_b[8] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[8] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[8] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L878, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[8] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[8] Z1_A_mul_result[8] = AMPP_FUNCTION(F1__clk1, Z1L315, Z1_A_mul_partial_prod[8], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_slow_inst_result[8] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[8] Z1_A_slow_inst_result[8] = AMPP_FUNCTION(F1__clk1, Z1L741, Z1_A_slow_ld_data_fill_bit, N1_data_out, Z1_A_ctrl_ld8, Z1_A_ctrl_ld); --Z1_A_inst_result[8] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[8] Z1_A_inst_result[8] = AMPP_FUNCTION(F1__clk1, Z1L2282, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L17 is system_0:u0|cpu_0:the_cpu_0|A_data_ram_ld16_data[8]~79 Z1L17 = AMPP_FUNCTION(Z1_A_inst_result[24], Z1_A_inst_result[8], Z1_A_ld_align_sh16); --Z1L876 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[8]~1749 Z1L876 = AMPP_FUNCTION(Z1L897, Z1_A_slow_inst_result[8], Z1L932, Z1L17); --Z1_A_shift_rot_result[8] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[8] Z1_A_shift_rot_result[8] = AMPP_FUNCTION(F1__clk1, Z1L696, N1_data_out); --Z1L877 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[8]~1750 Z1L877 = AMPP_FUNCTION(Z1_A_data_ram_ld_align_fill_bit, Z1L897, Z1L876, Z1_A_shift_rot_result[8]); --Z1L878 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[8]~1751 Z1L878 = AMPP_FUNCTION(Z1_A_mul_result[8], Z1L877, Z1_A_ctrl_mul_lsw); --Z1L1352 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[8]~637 Z1L1352 = AMPP_FUNCTION(Z1L1337, MC1_q_b[8], Z1L1336, Z1L878); --Z1_W_wr_data[8] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[8] Z1_W_wr_data[8] = AMPP_FUNCTION(F1__clk1, Z1L878, N1_data_out); --Z1L1353 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[8]~638 Z1L1353 = AMPP_FUNCTION(Z1_M_alu_result[8], Z1L1337, Z1L1352, Z1_W_wr_data[8]); --Z1L1767 is system_0:u0|cpu_0:the_cpu_0|E_src2[8]~122 Z1L1767 = AMPP_FUNCTION(Z1L1353, Z1L1418, Z1_D_src2_hazard_E); --Z1L1309 is system_0:u0|cpu_0:the_cpu_0|D_src2[8]~1959 Z1L1309 = AMPP_FUNCTION(Z1_D_iw[14], Z1_D_iw[5], Z1_D_iw[2], Z1L1041); --LC1_q_b[8] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[8] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[8] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L878, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1229 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[8]~3704 Z1L1229 = AMPP_FUNCTION(Z1L1731, LC1_q_b[8], Z1L1730, Z1L878); --Z1L1230 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[8]~3705 Z1L1230 = AMPP_FUNCTION(Z1_M_alu_result[8], Z1L1731, Z1L1229, Z1_W_wr_data[8]); --MC1_q_b[7] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[7] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[7] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L875, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[7] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[7] Z1_A_mul_result[7] = AMPP_FUNCTION(F1__clk1, Z1L312, Z1_A_mul_partial_prod[7], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_shift_rot_result[7] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[7] Z1_A_shift_rot_result[7] = AMPP_FUNCTION(F1__clk1, Z1L698, N1_data_out); --Z1_A_ld_align_sh8 is system_0:u0|cpu_0:the_cpu_0|A_ld_align_sh8 Z1_A_ld_align_sh8 = AMPP_FUNCTION(F1__clk1, Z1_M_ld_align_sh8, N1_data_out, Z1_A_stall); --Z1L842 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[0]~1752 Z1L842 = AMPP_FUNCTION(Z1_A_ld_align_sh16, Z1_A_ld_align_sh8, Z1_A_slow_inst_sel); --Z1_A_slow_inst_result[7] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[7] Z1_A_slow_inst_result[7] = AMPP_FUNCTION(F1__clk1, Z1L738, Z1L762, N1_data_out, Z1_A_ld_align_sh8, Z1_A_ctrl_ld); --Z1L843 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[0]~1753 Z1L843 = AMPP_FUNCTION(Z1_A_slow_inst_sel, Z1_A_ld_align_sh8); --Z1_A_inst_result[7] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[7] Z1_A_inst_result[7] = AMPP_FUNCTION(F1__clk1, Z1L2281, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L872 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[7]~1754 Z1L872 = AMPP_FUNCTION(Z1L842, Z1_A_slow_inst_result[7], Z1L843, Z1_A_inst_result[7]); --Z1L873 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[7]~1755 Z1L873 = AMPP_FUNCTION(Z1_A_inst_result[23], Z1L842, Z1L872, Z1L24); --Z1L874 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[7]~1756 Z1L874 = AMPP_FUNCTION(Z1_A_shift_rot_result[7], Z1L873, Z1_A_ctrl_shift_rot); --Z1L875 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[7]~1757 Z1L875 = AMPP_FUNCTION(Z1_A_mul_result[7], Z1L874, Z1_A_ctrl_mul_lsw); --Z1L1350 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[7]~639 Z1L1350 = AMPP_FUNCTION(Z1L1336, Z1_M_alu_result[7], Z1L1337, Z1L875); --Z1_W_wr_data[7] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[7] Z1_W_wr_data[7] = AMPP_FUNCTION(F1__clk1, Z1L875, N1_data_out); --Z1L1351 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[7]~640 Z1L1351 = AMPP_FUNCTION(MC1_q_b[7], Z1L1336, Z1L1350, Z1_W_wr_data[7]); --Z1L1764 is system_0:u0|cpu_0:the_cpu_0|E_src2[7]~121 Z1L1764 = AMPP_FUNCTION(Z1L1351, Z1L1416, Z1_D_src2_hazard_E); --Z1L1308 is system_0:u0|cpu_0:the_cpu_0|D_src2[7]~1960 Z1L1308 = AMPP_FUNCTION(Z1_D_iw[13], Z1_D_iw[5], Z1_D_iw[2], Z1L1041); --LC1_q_b[7] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[7] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[7] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L875, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1226 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[7]~3706 Z1L1226 = AMPP_FUNCTION(Z1L1730, Z1_M_alu_result[7], Z1L1731, Z1L875); --Z1L1227 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[7]~3707 Z1L1227 = AMPP_FUNCTION(LC1_q_b[7], Z1L1730, Z1L1226, Z1_W_wr_data[7]); --MC1_q_b[6] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[6] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[6] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L871, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[6] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[6] Z1_A_mul_result[6] = AMPP_FUNCTION(F1__clk1, Z1L309, Z1_A_mul_partial_prod[6], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_shift_rot_result[6] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[6] Z1_A_shift_rot_result[6] = AMPP_FUNCTION(F1__clk1, Z1L700, N1_data_out); --Z1_A_slow_inst_result[6] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[6] Z1_A_slow_inst_result[6] = AMPP_FUNCTION(F1__clk1, Z1L735, Z1L759, N1_data_out, Z1_A_ld_align_sh8, Z1_A_ctrl_ld); --Z1_A_inst_result[6] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[6] Z1_A_inst_result[6] = AMPP_FUNCTION(F1__clk1, Z1L2280, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L868 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[6]~1758 Z1L868 = AMPP_FUNCTION(Z1L843, Z1_A_inst_result[22], Z1L842, Z1_A_inst_result[6]); --Z1L869 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[6]~1759 Z1L869 = AMPP_FUNCTION(Z1_A_slow_inst_result[6], Z1L843, Z1L868, Z1L23); --Z1L870 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[6]~1760 Z1L870 = AMPP_FUNCTION(Z1_A_shift_rot_result[6], Z1L869, Z1_A_ctrl_shift_rot); --Z1L871 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[6]~1761 Z1L871 = AMPP_FUNCTION(Z1_A_mul_result[6], Z1L870, Z1_A_ctrl_mul_lsw); --Z1L1348 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[6]~641 Z1L1348 = AMPP_FUNCTION(Z1L1337, MC1_q_b[6], Z1L1336, Z1L871); --Z1_W_wr_data[6] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[6] Z1_W_wr_data[6] = AMPP_FUNCTION(F1__clk1, Z1L871, N1_data_out); --Z1L1349 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[6]~642 Z1L1349 = AMPP_FUNCTION(Z1_M_alu_result[6], Z1L1337, Z1L1348, Z1_W_wr_data[6]); --Z1L1761 is system_0:u0|cpu_0:the_cpu_0|E_src2[6]~120 Z1L1761 = AMPP_FUNCTION(Z1L1349, Z1L1414, Z1_D_src2_hazard_E); --Z1L1307 is system_0:u0|cpu_0:the_cpu_0|D_src2[6]~1961 Z1L1307 = AMPP_FUNCTION(Z1_D_iw[12], Z1_D_iw[5], Z1_D_iw[2], Z1L1041); --LC1_q_b[6] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[6] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[6] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L871, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1223 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[6]~3708 Z1L1223 = AMPP_FUNCTION(Z1L1731, LC1_q_b[6], Z1L1730, Z1L871); --Z1L1224 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[6]~3709 Z1L1224 = AMPP_FUNCTION(Z1_M_alu_result[6], Z1L1731, Z1L1223, Z1_W_wr_data[6]); --MC1_q_b[5] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[5] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[5] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L867, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[5] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[5] Z1_A_mul_result[5] = AMPP_FUNCTION(F1__clk1, Z1L306, Z1_A_mul_partial_prod[5], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_shift_rot_result[5] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[5] Z1_A_shift_rot_result[5] = AMPP_FUNCTION(F1__clk1, Z1L702, N1_data_out); --Z1_A_slow_inst_result[5] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[5] Z1_A_slow_inst_result[5] = AMPP_FUNCTION(F1__clk1, Z1L732, Z1L756, N1_data_out, Z1_A_ld_align_sh8, Z1_A_ctrl_ld); --Z1_A_inst_result[5] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[5] Z1_A_inst_result[5] = AMPP_FUNCTION(F1__clk1, Z1L2279, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L864 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[5]~1762 Z1L864 = AMPP_FUNCTION(Z1L842, Z1_A_slow_inst_result[5], Z1L843, Z1_A_inst_result[5]); --Z1L865 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[5]~1763 Z1L865 = AMPP_FUNCTION(Z1_A_inst_result[21], Z1L842, Z1L864, Z1L22); --Z1L866 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[5]~1764 Z1L866 = AMPP_FUNCTION(Z1_A_shift_rot_result[5], Z1L865, Z1_A_ctrl_shift_rot); --Z1L867 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[5]~1765 Z1L867 = AMPP_FUNCTION(Z1_A_mul_result[5], Z1L866, Z1_A_ctrl_mul_lsw); --Z1L1346 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[5]~643 Z1L1346 = AMPP_FUNCTION(Z1L1336, Z1_M_alu_result[5], Z1L1337, Z1L867); --Z1_W_wr_data[5] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[5] Z1_W_wr_data[5] = AMPP_FUNCTION(F1__clk1, Z1L867, N1_data_out); --Z1L1347 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[5]~644 Z1L1347 = AMPP_FUNCTION(MC1_q_b[5], Z1L1336, Z1L1346, Z1_W_wr_data[5]); --Z1L1758 is system_0:u0|cpu_0:the_cpu_0|E_src2[5]~119 Z1L1758 = AMPP_FUNCTION(Z1L1347, Z1L1412, Z1_D_src2_hazard_E); --Z1L1306 is system_0:u0|cpu_0:the_cpu_0|D_src2[5]~1962 Z1L1306 = AMPP_FUNCTION(Z1_D_iw[11], Z1_D_iw[5], Z1_D_iw[2], Z1L1041); --LC1_q_b[5] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[5] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[5] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L867, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1220 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[5]~3710 Z1L1220 = AMPP_FUNCTION(Z1L1730, Z1_M_alu_result[5], Z1L1731, Z1L867); --Z1L1221 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[5]~3711 Z1L1221 = AMPP_FUNCTION(LC1_q_b[5], Z1L1730, Z1L1220, Z1_W_wr_data[5]); --MC1_q_b[4] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[4] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[4] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L863, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[4] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[4] Z1_A_mul_result[4] = AMPP_FUNCTION(F1__clk1, Z1L303, Z1_A_mul_partial_prod[4], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_shift_rot_result[4] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[4] Z1_A_shift_rot_result[4] = AMPP_FUNCTION(F1__clk1, Z1L704, N1_data_out); --Z1_A_slow_inst_result[4] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[4] Z1_A_slow_inst_result[4] = AMPP_FUNCTION(F1__clk1, Z1L729, Z1L753, N1_data_out, Z1_A_ld_align_sh8, Z1_A_ctrl_ld); --Z1_A_inst_result[4] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[4] Z1_A_inst_result[4] = AMPP_FUNCTION(F1__clk1, Z1L2278, N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L860 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[4]~1766 Z1L860 = AMPP_FUNCTION(Z1L843, Z1_A_inst_result[20], Z1L842, Z1_A_inst_result[4]); --Z1L861 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[4]~1767 Z1L861 = AMPP_FUNCTION(Z1_A_slow_inst_result[4], Z1L843, Z1L860, Z1L21); --Z1L862 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[4]~1768 Z1L862 = AMPP_FUNCTION(Z1_A_shift_rot_result[4], Z1L861, Z1_A_ctrl_shift_rot); --Z1L863 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[4]~1769 Z1L863 = AMPP_FUNCTION(Z1_A_mul_result[4], Z1L862, Z1_A_ctrl_mul_lsw); --Z1L1344 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[4]~645 Z1L1344 = AMPP_FUNCTION(Z1L1337, MC1_q_b[4], Z1L1336, Z1L863); --Z1_W_wr_data[4] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[4] Z1_W_wr_data[4] = AMPP_FUNCTION(F1__clk1, Z1L863, N1_data_out); --Z1L1345 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[4]~646 Z1L1345 = AMPP_FUNCTION(Z1_M_alu_result[4], Z1L1337, Z1L1344, Z1_W_wr_data[4]); --Z1L1755 is system_0:u0|cpu_0:the_cpu_0|E_src2[4]~118 Z1L1755 = AMPP_FUNCTION(Z1L1345, Z1L1410, Z1_D_src2_hazard_E); --Z1L1305 is system_0:u0|cpu_0:the_cpu_0|D_src2[4]~1963 Z1L1305 = AMPP_FUNCTION(Z1_D_iw[10], Z1_D_iw[5], Z1_D_iw[2], Z1L1041); --LC1_q_b[4] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[4] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[4] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L863, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1217 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[4]~3712 Z1L1217 = AMPP_FUNCTION(Z1L1731, LC1_q_b[4], Z1L1730, Z1L863); --Z1L1218 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[4]~3713 Z1L1218 = AMPP_FUNCTION(Z1_M_alu_result[4], Z1L1731, Z1L1217, Z1_W_wr_data[4]); --MC1_q_b[3] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[3] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[3] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L859, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[3] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[3] Z1_A_mul_result[3] = AMPP_FUNCTION(F1__clk1, Z1L300, Z1_A_mul_partial_prod[3], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_shift_rot_result[3] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[3] Z1_A_shift_rot_result[3] = AMPP_FUNCTION(F1__clk1, Z1L706, N1_data_out); --Z1_A_slow_inst_result[3] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[3] Z1_A_slow_inst_result[3] = AMPP_FUNCTION(F1__clk1, Z1L726, Z1L750, N1_data_out, Z1_A_ld_align_sh8, Z1_A_ctrl_ld); --Z1_A_inst_result[3] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[3] Z1_A_inst_result[3] = AMPP_FUNCTION(F1__clk1, Z1L2277, Z1_M_control_rd_data[3], N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L856 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[3]~1770 Z1L856 = AMPP_FUNCTION(Z1L842, Z1_A_slow_inst_result[3], Z1L843, Z1_A_inst_result[3]); --Z1L857 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[3]~1771 Z1L857 = AMPP_FUNCTION(Z1_A_inst_result[19], Z1L842, Z1L856, Z1L20); --Z1L858 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[3]~1772 Z1L858 = AMPP_FUNCTION(Z1_A_shift_rot_result[3], Z1L857, Z1_A_ctrl_shift_rot); --Z1L859 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[3]~1773 Z1L859 = AMPP_FUNCTION(Z1_A_mul_result[3], Z1L858, Z1_A_ctrl_mul_lsw); --Z1L1342 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[3]~647 Z1L1342 = AMPP_FUNCTION(Z1L1336, Z1_M_alu_result[3], Z1L1337, Z1L859); --Z1_W_wr_data[3] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[3] Z1_W_wr_data[3] = AMPP_FUNCTION(F1__clk1, Z1L859, N1_data_out); --Z1L1343 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[3]~648 Z1L1343 = AMPP_FUNCTION(MC1_q_b[3], Z1L1336, Z1L1342, Z1_W_wr_data[3]); --Z1L1752 is system_0:u0|cpu_0:the_cpu_0|E_src2[3]~117 Z1L1752 = AMPP_FUNCTION(Z1L1343, Z1L1408, Z1_D_src2_hazard_E); --Z1L1304 is system_0:u0|cpu_0:the_cpu_0|D_src2[3]~1964 Z1L1304 = AMPP_FUNCTION(Z1_D_iw[9], Z1_D_iw[5], Z1_D_iw[2], Z1L1041); --LC1_q_b[3] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[3] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[3] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L859, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1214 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[3]~3714 Z1L1214 = AMPP_FUNCTION(Z1L1730, Z1_M_alu_result[3], Z1L1731, Z1L859); --Z1L1215 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[3]~3715 Z1L1215 = AMPP_FUNCTION(LC1_q_b[3], Z1L1730, Z1L1214, Z1_W_wr_data[3]); --MC1_q_b[2] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[2] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[2] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L855, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[2] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[2] Z1_A_mul_result[2] = AMPP_FUNCTION(F1__clk1, Z1L297, Z1_A_mul_partial_prod[2], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_shift_rot_result[2] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[2] Z1_A_shift_rot_result[2] = AMPP_FUNCTION(F1__clk1, Z1L708, N1_data_out); --Z1_A_slow_inst_result[2] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[2] Z1_A_slow_inst_result[2] = AMPP_FUNCTION(F1__clk1, Z1L723, Z1L747, N1_data_out, Z1_A_ld_align_sh8, Z1_A_ctrl_ld); --Z1_A_inst_result[2] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[2] Z1_A_inst_result[2] = AMPP_FUNCTION(F1__clk1, Z1L2276, Z1_M_control_rd_data[2], N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L852 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[2]~1774 Z1L852 = AMPP_FUNCTION(Z1L843, Z1_A_inst_result[18], Z1L842, Z1_A_inst_result[2]); --Z1L853 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[2]~1775 Z1L853 = AMPP_FUNCTION(Z1_A_slow_inst_result[2], Z1L843, Z1L852, Z1L19); --Z1L854 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[2]~1776 Z1L854 = AMPP_FUNCTION(Z1_A_shift_rot_result[2], Z1L853, Z1_A_ctrl_shift_rot); --Z1L855 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[2]~1777 Z1L855 = AMPP_FUNCTION(Z1_A_mul_result[2], Z1L854, Z1_A_ctrl_mul_lsw); --Z1L1340 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[2]~649 Z1L1340 = AMPP_FUNCTION(Z1L1337, MC1_q_b[2], Z1L1336, Z1L855); --Z1_W_wr_data[2] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[2] Z1_W_wr_data[2] = AMPP_FUNCTION(F1__clk1, Z1L855, N1_data_out); --Z1L1341 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[2]~650 Z1L1341 = AMPP_FUNCTION(Z1_M_alu_result[2], Z1L1337, Z1L1340, Z1_W_wr_data[2]); --Z1L1749 is system_0:u0|cpu_0:the_cpu_0|E_src2[2]~116 Z1L1749 = AMPP_FUNCTION(Z1L1341, Z1L1406, Z1_D_src2_hazard_E); --Z1L1303 is system_0:u0|cpu_0:the_cpu_0|D_src2[2]~1965 Z1L1303 = AMPP_FUNCTION(Z1_D_iw[8], Z1_D_iw[5], Z1_D_iw[2], Z1L1041); --LC1_q_b[2] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[2] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[2] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L855, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1211 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[2]~3716 Z1L1211 = AMPP_FUNCTION(Z1L1731, LC1_q_b[2], Z1L1730, Z1L855); --Z1L1212 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[2]~3717 Z1L1212 = AMPP_FUNCTION(Z1_M_alu_result[2], Z1L1731, Z1L1211, Z1_W_wr_data[2]); --MC1_q_b[1] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[1] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[1] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L851, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_M_alu_result[1] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[1] Z1_M_alu_result[1] = AMPP_FUNCTION(F1__clk1, Z1L1404, N1_data_out, Z1_A_stall); --Z1_A_mul_result[1] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[1] Z1_A_mul_result[1] = AMPP_FUNCTION(F1__clk1, Z1L294, Z1_A_mul_partial_prod[1], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_shift_rot_result[1] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[1] Z1_A_shift_rot_result[1] = AMPP_FUNCTION(F1__clk1, Z1L710, N1_data_out); --Z1_A_slow_inst_result[1] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[1] Z1_A_slow_inst_result[1] = AMPP_FUNCTION(F1__clk1, Z1L720, Z1L744, N1_data_out, Z1_A_ld_align_sh8, Z1_A_ctrl_ld); --Z1_A_inst_result[1] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[1] Z1_A_inst_result[1] = AMPP_FUNCTION(F1__clk1, Z1L2275, Z1_M_control_rd_data[1], N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L848 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[1]~1778 Z1L848 = AMPP_FUNCTION(Z1L842, Z1_A_slow_inst_result[1], Z1L843, Z1_A_inst_result[1]); --Z1L849 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[1]~1779 Z1L849 = AMPP_FUNCTION(Z1_A_inst_result[17], Z1L842, Z1L848, Z1L18); --Z1L850 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[1]~1780 Z1L850 = AMPP_FUNCTION(Z1_A_shift_rot_result[1], Z1L849, Z1_A_ctrl_shift_rot); --Z1L851 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[1]~1781 Z1L851 = AMPP_FUNCTION(Z1_A_mul_result[1], Z1L850, Z1_A_ctrl_mul_lsw); --Z1L1338 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[1]~651 Z1L1338 = AMPP_FUNCTION(Z1L1336, Z1_M_alu_result[1], Z1L1337, Z1L851); --Z1_W_wr_data[1] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[1] Z1_W_wr_data[1] = AMPP_FUNCTION(F1__clk1, Z1L851, N1_data_out); --Z1L1339 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[1]~652 Z1L1339 = AMPP_FUNCTION(MC1_q_b[1], Z1L1336, Z1L1338, Z1_W_wr_data[1]); --Z1L1403 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[1]~6793 Z1L1403 = AMPP_FUNCTION(Z1L1614, Z1_E_ctrl_dst_data_sel_logic_result); --Z1L1482 is system_0:u0|cpu_0:the_cpu_0|E_arith_result[1]~68 Z1L1482 = AMPP_FUNCTION(Z1L2808, Z1L2874, Z1_E_ctrl_alu_subtract); --Z1L1404 is system_0:u0|cpu_0:the_cpu_0|E_alu_result[1]~6794 Z1L1404 = AMPP_FUNCTION(Z1L1403, Z1L1479, Z1L1482, Z1_E_ctrl_dst_data_sel_cmp); --Z1L1746 is system_0:u0|cpu_0:the_cpu_0|E_src2[1]~115 Z1L1746 = AMPP_FUNCTION(Z1L1339, Z1L1404, Z1_D_src2_hazard_E); --Z1L1302 is system_0:u0|cpu_0:the_cpu_0|D_src2[1]~1966 Z1L1302 = AMPP_FUNCTION(Z1_D_iw[7], Z1_D_iw[5], Z1_D_iw[2], Z1L1041); --LC1_q_b[1] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[1] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[1] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L851, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1208 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[1]~3718 Z1L1208 = AMPP_FUNCTION(Z1L1730, Z1_M_alu_result[1], Z1L1731, Z1L851); --Z1L1209 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[1]~3719 Z1L1209 = AMPP_FUNCTION(LC1_q_b[1], Z1L1730, Z1L1208, Z1_W_wr_data[1]); --Z1_M_alu_result[0] is system_0:u0|cpu_0:the_cpu_0|M_alu_result[0] Z1_M_alu_result[0] = AMPP_FUNCTION(F1__clk1, Z1L1706, N1_data_out, Z1_A_stall); --MC1_q_b[0] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_vm61:auto_generated|q_b[0] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered MC1_q_b[0] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L847, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2030, Z1L2031, Z1L2032, Z1L2033, Z1L2034); --Z1_A_mul_result[0] is system_0:u0|cpu_0:the_cpu_0|A_mul_result[0] Z1_A_mul_result[0] = AMPP_FUNCTION(F1__clk1, Z1L291, Z1_A_mul_partial_prod[0], N1_data_out, !Z1_A_mul_stall_d3); --Z1_A_shift_rot_result[0] is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result[0] Z1_A_shift_rot_result[0] = AMPP_FUNCTION(F1__clk1, Z1L712, N1_data_out); --Z1_A_slow_inst_result[0] is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[0] Z1_A_slow_inst_result[0] = AMPP_FUNCTION(F1__clk1, Z1L717, Z1L741, N1_data_out, Z1_A_ld_align_sh8, Z1_A_ctrl_ld); --Z1_A_inst_result[0] is system_0:u0|cpu_0:the_cpu_0|A_inst_result[0] Z1_A_inst_result[0] = AMPP_FUNCTION(F1__clk1, Z1L2274, Z1_M_control_rd_data[0], N1_data_out, Z1_M_ctrl_rdctl_inst, Z1_A_stall); --Z1L844 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[0]~1782 Z1L844 = AMPP_FUNCTION(Z1L843, Z1_A_inst_result[16], Z1L842, Z1_A_inst_result[0]); --Z1L845 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[0]~1783 Z1L845 = AMPP_FUNCTION(Z1_A_slow_inst_result[0], Z1L843, Z1L844, Z1L17); --Z1L846 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[0]~1784 Z1L846 = AMPP_FUNCTION(Z1_A_shift_rot_result[0], Z1L845, Z1_A_ctrl_shift_rot); --Z1L847 is system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[0]~1785 Z1L847 = AMPP_FUNCTION(Z1_A_mul_result[0], Z1L846, Z1_A_ctrl_mul_lsw); --Z1L1334 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[0]~653 Z1L1334 = AMPP_FUNCTION(Z1L1337, MC1_q_b[0], Z1L1336, Z1L847); --Z1_W_wr_data[0] is system_0:u0|cpu_0:the_cpu_0|W_wr_data[0] Z1_W_wr_data[0] = AMPP_FUNCTION(F1__clk1, Z1L847, N1_data_out); --Z1L1335 is system_0:u0|cpu_0:the_cpu_0|D_src2_reg[0]~654 Z1L1335 = AMPP_FUNCTION(Z1_M_alu_result[0], Z1L1337, Z1L1334, Z1_W_wr_data[0]); --Z1L1481 is system_0:u0|cpu_0:the_cpu_0|E_arith_result[0]~69 Z1L1481 = AMPP_FUNCTION(Z1L2806, Z1L2872, Z1_E_ctrl_alu_subtract); --Z1L1480 is system_0:u0|cpu_0:the_cpu_0|E_alu_result~6795 Z1L1480 = AMPP_FUNCTION(Z1L1613, Z1_E_ctrl_dst_data_sel_logic_result, Z1L1481, Z1_E_ctrl_dst_data_sel_pc_plus_one); --Z1L1706 is system_0:u0|cpu_0:the_cpu_0|E_src1[0]~184 Z1L1706 = AMPP_FUNCTION(Z1L1501, Z1L1480, Z1_E_ctrl_dst_data_sel_cmp); --Z1L1743 is system_0:u0|cpu_0:the_cpu_0|E_src2[0]~114 Z1L1743 = AMPP_FUNCTION(Z1L1335, Z1L1706, Z1_D_src2_hazard_E); --Z1L1301 is system_0:u0|cpu_0:the_cpu_0|D_src2[0]~1967 Z1L1301 = AMPP_FUNCTION(Z1_D_iw[6], Z1_D_iw[5], Z1_D_iw[2], Z1L1041); --LC1_q_b[0] is system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_um61:auto_generated|q_b[0] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1 --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered LC1_q_b[0] = AMPP_FUNCTION(GND, GND, F1__clk1, F1__clk1, !Z1_A_wr_dst_reg_from_M, Z1L847, Z1_A_dst_regnum_from_M[0], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[2], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[4], Z1L2025, Z1L2026, Z1L2027, Z1L2028, Z1L2029); --Z1L1206 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[0]~3720 Z1L1206 = AMPP_FUNCTION(Z1L1731, LC1_q_b[0], Z1L1730, Z1L847); --Z1L1207 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[0]~3721 Z1L1207 = AMPP_FUNCTION(Z1_M_alu_result[0], Z1L1731, Z1L1206, Z1_W_wr_data[0]); --Z1L1018 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_alu_subtract~366 Z1L1018 = AMPP_FUNCTION(Z1_D_iw[15], Z1_D_iw[14], Z1_D_iw[11], Z1_D_iw[16]); --Z1L1009 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_alu_force_xor~278 Z1L1009 = AMPP_FUNCTION(Z1L1152, Z1L1149, Z1_D_iw[5]); --Z1L1010 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_alu_force_xor~279 Z1L1010 = AMPP_FUNCTION(Z1_D_iw[5], Z1L1141, Z1L1044, Z1_D_iw[13]); --Z1L1011 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_alu_force_xor~280 Z1L1011 = AMPP_FUNCTION(Z1L1010, Z1_D_iw[14], Z1_D_iw[16], Z1_D_iw[15]); --Z1L1012 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_alu_force_xor~281 Z1L1012 = AMPP_FUNCTION(Z1L1009, Z1L1011, Z1L1013, Z1_D_iw[4]); --Z1L1138 is system_0:u0|cpu_0:the_cpu_0|D_logic_op[1]~122 Z1L1138 = AMPP_FUNCTION(Z1L1012, Z1L1140); --Z1L1137 is system_0:u0|cpu_0:the_cpu_0|D_logic_op[0]~123 Z1L1137 = AMPP_FUNCTION(Z1L1012, Z1_D_iw[14], Z1_D_iw[3], Z1L1142); --Z1L1139 is system_0:u0|cpu_0:the_cpu_0|D_logic_op_raw[0]~95 Z1L1139 = AMPP_FUNCTION(Z1_D_iw[14], Z1_D_iw[3], Z1L1142); --Z1L1036 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_flush_pipe_always~321 Z1L1036 = AMPP_FUNCTION(Z1_D_iw[16], Z1_D_iw[15], Z1_D_iw[14], Z1_D_iw[11]); --Z1L1037 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_flush_pipe_always~322 Z1L1037 = AMPP_FUNCTION(Z1_D_iw[13], Z1L1036, Z1L1040, Z1_D_iw[12]); --Z1L3378 is system_0:u0|cpu_0:the_cpu_0|latched_oci_tb_hbreak_req_next~37 Z1L3378 = AMPP_FUNCTION(Z1L1890, Z1L3242, Z1_latched_oci_tb_hbreak_req, Z1_hbreak_enabled); --XC1_probepresent is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|probepresent XC1_probepresent = AMPP_FUNCTION(F1__clk1, XC1L15, D1_CLRN_SIGNAL, FD1L196); --XC1L2 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|jtag_break~47 XC1L2 = AMPP_FUNCTION(XC1_probepresent, XC1_jtag_break, N1_data_out); --FD1L40Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[21]~reg0 FD1L40Q = AMPP_FUNCTION(A1L336, FD1_sr[21], FD1L104); --FD1L39Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[20]~reg0 FD1L39Q = AMPP_FUNCTION(A1L336, FD1_sr[20], FD1L104); --XC1L4 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|jtag_break~53 XC1L4 = AMPP_FUNCTION(FD1L40Q, XC1_jtag_break, FD1L39Q); --Z1_M_iw[14] is system_0:u0|cpu_0:the_cpu_0|M_iw[14] Z1_M_iw[14] = AMPP_FUNCTION(F1__clk1, Z1_E_iw[14], N1_data_out, Z1_A_stall); --Z1_M_iw[16] is system_0:u0|cpu_0:the_cpu_0|M_iw[16] Z1_M_iw[16] = AMPP_FUNCTION(F1__clk1, Z1_E_iw[16], N1_data_out, Z1_A_stall); --Z1_M_iw[15] is system_0:u0|cpu_0:the_cpu_0|M_iw[15] Z1_M_iw[15] = AMPP_FUNCTION(F1__clk1, Z1_E_iw[15], N1_data_out, Z1_A_stall); --Z1_M_iw[13] is system_0:u0|cpu_0:the_cpu_0|M_iw[13] Z1_M_iw[13] = AMPP_FUNCTION(F1__clk1, Z1_E_iw[13], N1_data_out, Z1_A_stall); --Z1_M_iw[12] is system_0:u0|cpu_0:the_cpu_0|M_iw[12] Z1_M_iw[12] = AMPP_FUNCTION(F1__clk1, Z1_E_iw[12], N1_data_out, Z1_A_stall); --Z1L2329 is system_0:u0|cpu_0:the_cpu_0|M_op_eret~78 Z1L2329 = AMPP_FUNCTION(Z1_M_iw[16], Z1_M_iw[15], Z1_M_iw[13], Z1_M_iw[12]); --Z1_M_iw[11] is system_0:u0|cpu_0:the_cpu_0|M_iw[11] Z1_M_iw[11] = AMPP_FUNCTION(F1__clk1, Z1_E_iw[11], N1_data_out, Z1_A_stall); --Z1_M_iw[5] is system_0:u0|cpu_0:the_cpu_0|M_iw[5] Z1_M_iw[5] = AMPP_FUNCTION(F1__clk1, Z1_E_iw[5], N1_data_out, Z1_A_stall); --Z1_M_iw[4] is system_0:u0|cpu_0:the_cpu_0|M_iw[4] Z1_M_iw[4] = AMPP_FUNCTION(F1__clk1, Z1_E_iw[4], N1_data_out, Z1_A_stall); --Z1_M_iw[3] is system_0:u0|cpu_0:the_cpu_0|M_iw[3] Z1_M_iw[3] = AMPP_FUNCTION(F1__clk1, Z1_E_iw[3], N1_data_out, Z1_A_stall); --Z1L2330 is system_0:u0|cpu_0:the_cpu_0|M_op_eret~79 Z1L2330 = AMPP_FUNCTION(Z1_M_iw[11], Z1_M_iw[5], Z1_M_iw[4], Z1_M_iw[3]); --Z1_M_iw[1] is system_0:u0|cpu_0:the_cpu_0|M_iw[1] Z1_M_iw[1] = AMPP_FUNCTION(F1__clk1, Z1_E_iw[1], N1_data_out, Z1_A_stall); --Z1_M_iw[0] is system_0:u0|cpu_0:the_cpu_0|M_iw[0] Z1_M_iw[0] = AMPP_FUNCTION(F1__clk1, Z1_E_iw[0], N1_data_out, Z1_A_stall); --Z1L2331 is system_0:u0|cpu_0:the_cpu_0|M_op_eret~80 Z1L2331 = AMPP_FUNCTION(Z1_M_iw[1], Z1_M_iw[0]); --Z1_M_iw[2] is system_0:u0|cpu_0:the_cpu_0|M_iw[2] Z1_M_iw[2] = AMPP_FUNCTION(F1__clk1, Z1_E_iw[2], N1_data_out, Z1_A_stall); --Z1L2332 is system_0:u0|cpu_0:the_cpu_0|M_op_eret~81 Z1L2332 = AMPP_FUNCTION(Z1L2329, Z1L2330, Z1L2331, Z1_M_iw[2]); --Z1_M_ctrl_break is system_0:u0|cpu_0:the_cpu_0|M_ctrl_break Z1_M_ctrl_break = AMPP_FUNCTION(F1__clk1, Z1_E_ctrl_break, N1_data_out, Z1_A_stall); --Z1L3241 is system_0:u0|cpu_0:the_cpu_0|hbreak_enabled~63 Z1L3241 = AMPP_FUNCTION(Z1_M_iw[14], Z1L2332, Z1_hbreak_enabled, Z1_M_ctrl_break); --UC1_oci_single_step_mode is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_single_step_mode UC1_oci_single_step_mode = AMPP_FUNCTION(F1__clk1, UC1L15, N1_data_out); --Z1L3381 is system_0:u0|cpu_0:the_cpu_0|wait_for_one_post_bret_inst~126 Z1L3381 = AMPP_FUNCTION(UC1_oci_single_step_mode, Z1_hbreak_enabled, Z1_wait_for_one_post_bret_inst, Z1L3382); --Z1L3289 is system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_cnt_nxt[1]~40 Z1L3289 = AMPP_FUNCTION(BB1L250, Z1_ic_fill_ap_cnt[1], Z1_ic_fill_ap_cnt[0]); --Z1L3288 is system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_cnt_nxt[0]~41 Z1L3288 = AMPP_FUNCTION(BB1L250, Z1_ic_fill_ap_cnt[0]); --Z1L1645 is system_0:u0|cpu_0:the_cpu_0|E_mem_byte_en[1]~460 Z1L1645 = AMPP_FUNCTION(Z1_E_iw[4], Z1_E_iw[3], Z1L1481, Z1L1482); --Z1L1647 is system_0:u0|cpu_0:the_cpu_0|E_mem_byte_en[3]~461 Z1L1647 = AMPP_FUNCTION(Z1_E_iw[4], Z1_E_iw[3], Z1L1482, Z1L1481); --Z1L1646 is system_0:u0|cpu_0:the_cpu_0|E_mem_byte_en[2]~462 Z1L1646 = AMPP_FUNCTION(Z1_E_iw[4], Z1_E_iw[3], Z1L1482, Z1L1481); --Z1L1648 is system_0:u0|cpu_0:the_cpu_0|E_mem_byte_en~463 Z1L1648 = AMPP_FUNCTION(Z1_E_iw[4], Z1_E_iw[3], Z1L1481, Z1L1482); --JE1_stage_2 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|stage_2 JE1_stage_2 = DFFEAS(JE1L29, F1__clk1, , , HE1L18, , , , ); --JE1L28 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|p1_stage_1~10 JE1L28 = JE1_full_2 & JE1_stage_2 # !JE1_full_2 & (JB1L16); --FD1L17Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|ir_out[0]~reg0 FD1L17Q = AMPP_FUNCTION(A1L333, XC1_monitor_ready, D1_CLRN_SIGNAL); --G4_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[0] G4_Q[0] = AMPP_FUNCTION(A1L333, G4L4, D1_CLRN_SIGNAL); --G3_Q[4] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4] G3_Q[4] = AMPP_FUNCTION(A1L333, D1L34, D1_CLRN_SIGNAL, G3L5); --G3_Q[6] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[6] G3_Q[6] = AMPP_FUNCTION(A1L333, ~GND, altera_internal_jtag, D1_CLRN_SIGNAL, L1_state[4], D1_IRSR_ENA); --M1_dffe1a[3] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|dffe1a[3] M1_dffe1a[3] = AMPP_FUNCTION(A1L333, M1_w_anode38w[3], D1_CLRN_SIGNAL, D1L6); --D1L25 is sld_hub:sld_hub_inst|IR_MUX_SEL[1]~30 D1L25 = AMPP_FUNCTION(G3_Q[4], G3_Q[6], M1_dffe1a[3]); --G3_Q[3] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3] G3_Q[3] = AMPP_FUNCTION(A1L333, D1L33, D1_CLRN_SIGNAL, G3L5); --G3_Q[5] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5] G3_Q[5] = AMPP_FUNCTION(A1L333, G3L11, D1_CLRN_SIGNAL); --D1L24 is sld_hub:sld_hub_inst|IR_MUX_SEL[0]~31 D1L24 = AMPP_FUNCTION(G3_Q[3], G3_Q[5], M1_dffe1a[3]); --G3L4 is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1]~1170 G3L4 = AMPP_FUNCTION(FD1L17Q, G4_Q[0], D1L25, D1L24); --G3_Q[1] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1] G3_Q[1] = AMPP_FUNCTION(A1L333, G3L6, G3_Q[2], D1_CLRN_SIGNAL, L1_state[4], G3L5); --D1_IRSR_ENA is sld_hub:sld_hub_inst|IRSR_ENA D1_IRSR_ENA = AMPP_FUNCTION(D1_jtag_debug_mode_usr1, L1_state[3], L1_state[4]); --G3L5 is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1]~1171 G3L5 = AMPP_FUNCTION(D1_IRSR_ENA, L1_state[4], D1L25, D1L24); --D1L7 is sld_hub:sld_hub_inst|Equal~181 D1L7 = AMPP_FUNCTION(altera_internal_jtag, G3_Q[6]); --D1_OK_TO_UPDATE_IR_Q is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q D1_OK_TO_UPDATE_IR_Q = AMPP_FUNCTION(A1L333, D1L43); --D1L28 is sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 D1L28 = AMPP_FUNCTION(A1L335, L1_state[4], D1_jtag_debug_mode_usr1, D1_OK_TO_UPDATE_IR_Q); --H1_WORD_SR[1] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[1] H1_WORD_SR[1] = AMPP_FUNCTION(A1L333, H1L32, H1L26); --H1_word_counter[2] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[2] H1_word_counter[2] = AMPP_FUNCTION(A1L333, H1L10, H1L16, H1L17); --H1_word_counter[3] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[3] H1_word_counter[3] = AMPP_FUNCTION(A1L333, H1L13, H1L16, H1L17); --H1_word_counter[0] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0] H1_word_counter[0] = AMPP_FUNCTION(A1L333, H1L4, H1L16, H1L17); --H1_word_counter[1] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[1] H1_word_counter[1] = AMPP_FUNCTION(A1L333, H1L7, H1L16, H1L17); --H1L27 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~1833 H1L27 = AMPP_FUNCTION(H1_word_counter[2], H1_word_counter[3], H1_word_counter[0], H1_word_counter[1]); --H1_word_counter[4] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[4] H1_word_counter[4] = AMPP_FUNCTION(A1L333, H1L18, H1L16, H1L17); --H1L28 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~1834 H1L28 = AMPP_FUNCTION(D1_jtag_debug_mode_usr1, L1_state[8], L1_state[4], H1_word_counter[4]); --H1L25 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3]~1835 H1L25 = AMPP_FUNCTION(L1_state[4], D1_jtag_debug_mode_usr1, L1_state[8]); --H1L29 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~1836 H1L29 = AMPP_FUNCTION(H1_WORD_SR[1], H1L27, H1L28, H1L25); --D1_jtag_debug_mode_usr0 is sld_hub:sld_hub_inst|jtag_debug_mode_usr0 D1_jtag_debug_mode_usr0 = AMPP_FUNCTION(A1L333, D1L13, L1_state[0], L1_state[12]); --H1_clear_signal is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|clear_signal H1_clear_signal = AMPP_FUNCTION(D1_jtag_debug_mode_usr1, L1_state[8]); --H1L26 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3]~1837 H1L26 = AMPP_FUNCTION(L1_state[3], L1_state[4], D1_jtag_debug_mode_usr0, H1_clear_signal); --D1L17 is sld_hub:sld_hub_inst|HUB_BYPASS_REG~11 D1L17 = AMPP_FUNCTION(altera_internal_jtag, L1_state[4]); --D1L39 is sld_hub:sld_hub_inst|jtag_debug_mode~2 D1L39 = AMPP_FUNCTION(D1_jtag_debug_mode_usr1, D1_jtag_debug_mode_usr0); --G3_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] G3_Q[2] = AMPP_FUNCTION(A1L333, D1L32, D1_CLRN_SIGNAL, G3L5); --M1_w_anode1w[3] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|w_anode1w[3] M1_w_anode1w[3] = AMPP_FUNCTION(D1L39, G3_Q[3], G3_Q[1], G3_Q[2]); --D1L5 is sld_hub:sld_hub_inst|comb~77 D1L5 = AMPP_FUNCTION(L1_state[3], L1_state[4], D1_jtag_debug_mode_usr1, D1_jtag_debug_mode_usr0); --D1L6 is sld_hub:sld_hub_inst|comb~78 D1L6 = AMPP_FUNCTION(A1L335, D1L5, altera_internal_jtag, G3_Q[6]); --D1L8 is sld_hub:sld_hub_inst|Equal~182 D1L8 = AMPP_FUNCTION(altera_internal_jtag, G3_Q[6]); --D1L9 is sld_hub:sld_hub_inst|Equal~183 D1L9 = AMPP_FUNCTION(G3_Q[6], altera_internal_jtag); --FD1_sr[1] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[1] FD1_sr[1] = AMPP_FUNCTION(A1L333, FD1L123, D1_CLRN_SIGNAL, FD1L118); --FD1_DRsize.000 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.000 FD1_DRsize.000 = AMPP_FUNCTION(A1L333, GND, D1_CLRN_SIGNAL, FD1L195); --FD1L121 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4753 FD1L121 = AMPP_FUNCTION(FD1_sr[1], altera_internal_jtag, FD1_DRsize.000); --XC1_monitor_ready is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_ready XC1_monitor_ready = AMPP_FUNCTION(F1__clk1, XC1L13); --FD1L103 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4754 FD1L103 = AMPP_FUNCTION(XC1_monitor_ready, FD1_ir[1], FD1_ir[0]); --D1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode D1_jtag_debug_mode = AMPP_FUNCTION(A1L333, D1L41, L1_state[0]); --G2_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] G2_Q[0] = AMPP_FUNCTION(A1L333, G2L3, D1_CLRN_SIGNAL); --FD1L104 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4755 FD1L104 = AMPP_FUNCTION(G8_Q[0], D1_jtag_debug_mode, D1_jtag_debug_mode_usr1, G2_Q[0]); --FD1_in_between_shiftdr_and_updatedr is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|in_between_shiftdr_and_updatedr FD1_in_between_shiftdr_and_updatedr = AMPP_FUNCTION(A1L333, FD1L12, D1_CLRN_SIGNAL); --FD1L7 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|always2~2 FD1L7 = AMPP_FUNCTION(FD1L104, A1L332, FD1_in_between_shiftdr_and_updatedr); --FD1L105 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4756 FD1L105 = AMPP_FUNCTION(A1L332, FD1L104); --FD1L106 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4757 FD1L106 = AMPP_FUNCTION(FD1L121, FD1L103, FD1L7, FD1L105); --FD1L8 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|always4~0 FD1L8 = AMPP_FUNCTION(D1_jtag_debug_mode_usr1, G8_Q[0], D1_jtag_debug_mode, G2_Q[0]); --FD1L194Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updateir~113 FD1L194Q = AMPP_FUNCTION(A1L333, FD1L193, !A1L336); --FD1L195 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updateir~114 FD1L195 = AMPP_FUNCTION(FD1L8, A1L336, FD1L194Q, FD1L193); --FD1L118 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[36]~4758 FD1L118 = AMPP_FUNCTION(FD1L104, A1L332, FD1_in_between_shiftdr_and_updatedr, FD1L195); --VD1_td_shift[1] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[1] VD1_td_shift[1] = AMPP_FUNCTION(A1L333, VD1L61, G4_Q[0], D1_CLRN_SIGNAL, VD1L66, !L1_state[4], VD1L57); --VD1_rvalid is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rvalid VD1_rvalid = AMPP_FUNCTION(F1__clk1, VD1_rvalid0, N1_data_out); --VD1_count[9] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[9] VD1_count[9] = AMPP_FUNCTION(A1L333, VD1L59, D1_CLRN_SIGNAL, VD1L57); --VD1L80 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1329 VD1L80 = AMPP_FUNCTION(VD1_td_shift[1], VD1_rvalid, VD1_count[9]); --VD1_count[1] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[1] VD1_count[1] = AMPP_FUNCTION(A1L333, VD1L14, D1_CLRN_SIGNAL, VD1L57); --VD1_state is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|state VD1_state = AMPP_FUNCTION(A1L333, VD1L49, D1_CLRN_SIGNAL); --VD1_user_saw_rvalid is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|user_saw_rvalid VD1_user_saw_rvalid = AMPP_FUNCTION(A1L333, VD1L91, D1_CLRN_SIGNAL); --VD1_td_shift[9] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[9] VD1_td_shift[9] = AMPP_FUNCTION(A1L333, VD1L84, D1_CLRN_SIGNAL, !L1_state[4], VD1L57); --VD1L81 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1330 VD1L81 = AMPP_FUNCTION(VD1_count[1], VD1_state, VD1_user_saw_rvalid, VD1_td_shift[9]); --FB1_t_dav is system_0:u0|jtag_uart_0:the_jtag_uart_0|t_dav FB1_t_dav = DFFEAS(BE2_b_full, F1__clk1, N1_data_out, , , , , , ); --VD1L82 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1331 VD1L82 = AMPP_FUNCTION(altera_internal_jtag, VD1L81, VD1_state, FB1_t_dav); --VD1L83 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1332 VD1L83 = AMPP_FUNCTION(VD1L80, VD1L82, VD1L81, G4_Q[0]); --VD1L1 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~57 VD1L1 = AMPP_FUNCTION(G8_Q[1], D1_jtag_debug_mode, D1_jtag_debug_mode_usr1, G2_Q[0]); --VD1L57 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[0]~1333 VD1L57 = AMPP_FUNCTION(VD1L1, L1_state[3], L1_state[4]); --K1_dffs[1] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[1] K1_dffs[1] = AMPP_FUNCTION(A1L333, K1_dffs[2], L1_state[0], L1_state[11]); --K1_dffs[9] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] K1_dffs[9] = AMPP_FUNCTION(A1L333, altera_internal_jtag, L1_state[0], L1_state[11]); --K1_dffs[8] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[8] K1_dffs[8] = AMPP_FUNCTION(A1L333, K1_dffs[9], L1_state[0], L1_state[11]); --K1_dffs[7] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[7] K1_dffs[7] = AMPP_FUNCTION(A1L333, K1_dffs[8], L1_state[0], L1_state[11]); --K1_dffs[6] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[6] K1_dffs[6] = AMPP_FUNCTION(A1L333, K1_dffs[7], L1_state[0], L1_state[11]); --D1L10 is sld_hub:sld_hub_inst|Equal~184 D1L10 = AMPP_FUNCTION(K1_dffs[9], K1_dffs[8], K1_dffs[7], K1_dffs[6]); --K1_dffs[3] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[3] K1_dffs[3] = AMPP_FUNCTION(A1L333, K1_dffs[4], L1_state[0], L1_state[11]); --K1_dffs[2] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[2] K1_dffs[2] = AMPP_FUNCTION(A1L333, K1_dffs[3], L1_state[0], L1_state[11]); --K1_dffs[5] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[5] K1_dffs[5] = AMPP_FUNCTION(A1L333, K1_dffs[6], L1_state[0], L1_state[11]); --K1_dffs[4] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[4] K1_dffs[4] = AMPP_FUNCTION(A1L333, K1_dffs[5], L1_state[0], L1_state[11]); --D1L11 is sld_hub:sld_hub_inst|Equal~185 D1L11 = AMPP_FUNCTION(K1_dffs[3], K1_dffs[2], K1_dffs[5], K1_dffs[4]); --K1_dffs[0] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[0] K1_dffs[0] = AMPP_FUNCTION(A1L333, K1_dffs[1], L1_state[0], L1_state[11]); --D1L12 is sld_hub:sld_hub_inst|Equal~186 D1L12 = AMPP_FUNCTION(K1_dffs[1], D1L10, D1L11, K1_dffs[0]); --L1_state[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] L1_state[0] = AMPP_FUNCTION(A1L333, L1L31); --L1_state[12] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[12] L1_state[12] = AMPP_FUNCTION(A1L333, L1L32); --L1_state[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[2] L1_state[2] = AMPP_FUNCTION(A1L333, L1L33); --L1L19 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~10 L1L19 = AMPP_FUNCTION(L1_state[2], A1L335); --L1_state[7] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[7] L1_state[7] = AMPP_FUNCTION(A1L333, L1L23); --L1L20 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~11 L1L20 = AMPP_FUNCTION(L1_state[3], L1_state[4], L1_state[7]); --L1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5] L1_state[5] = AMPP_FUNCTION(A1L333, L1L21); --L1L24 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~18 L1L24 = AMPP_FUNCTION(L1_state[7], L1_state[5]); --GE1_entry_1[0] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[0] GE1_entry_1[0] = DFFEAS(AB1L28, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[0] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[0] GE1_entry_0[0] = DFFEAS(AB1L28, F1__clk1, , , GE1L47, , , , ); --HB1L112 is system_0:u0|sdram_0:the_sdram_0|Select~8216 HB1L112 = GE1_rd_address & GE1_entry_1[0] # !GE1_rd_address & (GE1_entry_0[0]); --HB1_active_data[0] is system_0:u0|sdram_0:the_sdram_0|active_data[0] HB1_active_data[0] = DFFEAS(HB1L112, F1__clk1, , , HB1L208, , , , ); --HB1L113 is system_0:u0|sdram_0:the_sdram_0|Select~8217 HB1L113 = HB1_m_state.000010000 & HB1_active_data[0] # !HB1_m_state.000010000 & (HB1_m_state.000000010 & HB1_active_data[0] # !HB1_m_state.000000010 & (HB1_m_data[0])); --HB1L114 is system_0:u0|sdram_0:the_sdram_0|Select~8218 HB1L114 = HB1_m_state.000010000 & (HB1_f_select & HB1L112 # !HB1_f_select & (HB1L113)) # !HB1_m_state.000010000 & (HB1L113); --GE1_entry_1[1] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[1] GE1_entry_1[1] = DFFEAS(AB1L29, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[1] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[1] GE1_entry_0[1] = DFFEAS(AB1L29, F1__clk1, , , GE1L47, , , , ); --HB1L115 is system_0:u0|sdram_0:the_sdram_0|Select~8219 HB1L115 = GE1_rd_address & GE1_entry_1[1] # !GE1_rd_address & (GE1_entry_0[1]); --HB1_active_data[1] is system_0:u0|sdram_0:the_sdram_0|active_data[1] HB1_active_data[1] = DFFEAS(HB1L115, F1__clk1, , , HB1L208, , , , ); --HB1L116 is system_0:u0|sdram_0:the_sdram_0|Select~8220 HB1L116 = HB1_m_state.000010000 & HB1_active_data[1] # !HB1_m_state.000010000 & (HB1_m_state.000000010 & HB1_active_data[1] # !HB1_m_state.000000010 & (HB1_m_data[1])); --HB1L117 is system_0:u0|sdram_0:the_sdram_0|Select~8221 HB1L117 = HB1_m_state.000010000 & (HB1_f_select & HB1L115 # !HB1_f_select & (HB1L116)) # !HB1_m_state.000010000 & (HB1L116); --GE1_entry_1[2] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[2] GE1_entry_1[2] = DFFEAS(AB1L30, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[2] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[2] GE1_entry_0[2] = DFFEAS(AB1L30, F1__clk1, , , GE1L47, , , , ); --HB1L118 is system_0:u0|sdram_0:the_sdram_0|Select~8222 HB1L118 = GE1_rd_address & GE1_entry_1[2] # !GE1_rd_address & (GE1_entry_0[2]); --HB1_active_data[2] is system_0:u0|sdram_0:the_sdram_0|active_data[2] HB1_active_data[2] = DFFEAS(HB1L118, F1__clk1, , , HB1L208, , , , ); --HB1L119 is system_0:u0|sdram_0:the_sdram_0|Select~8223 HB1L119 = HB1_m_state.000010000 & HB1_active_data[2] # !HB1_m_state.000010000 & (HB1_m_state.000000010 & HB1_active_data[2] # !HB1_m_state.000000010 & (HB1_m_data[2])); --HB1L120 is system_0:u0|sdram_0:the_sdram_0|Select~8224 HB1L120 = HB1_m_state.000010000 & (HB1_f_select & HB1L118 # !HB1_f_select & (HB1L119)) # !HB1_m_state.000010000 & (HB1L119); --GE1_entry_1[3] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[3] GE1_entry_1[3] = DFFEAS(AB1L31, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[3] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[3] GE1_entry_0[3] = DFFEAS(AB1L31, F1__clk1, , , GE1L47, , , , ); --HB1L121 is system_0:u0|sdram_0:the_sdram_0|Select~8225 HB1L121 = GE1_rd_address & GE1_entry_1[3] # !GE1_rd_address & (GE1_entry_0[3]); --HB1_active_data[3] is system_0:u0|sdram_0:the_sdram_0|active_data[3] HB1_active_data[3] = DFFEAS(HB1L121, F1__clk1, , , HB1L208, , , , ); --HB1L122 is system_0:u0|sdram_0:the_sdram_0|Select~8226 HB1L122 = HB1_m_state.000010000 & HB1_active_data[3] # !HB1_m_state.000010000 & (HB1_m_state.000000010 & HB1_active_data[3] # !HB1_m_state.000000010 & (HB1_m_data[3])); --HB1L123 is system_0:u0|sdram_0:the_sdram_0|Select~8227 HB1L123 = HB1_m_state.000010000 & (HB1_f_select & HB1L121 # !HB1_f_select & (HB1L122)) # !HB1_m_state.000010000 & (HB1L122); --GE1_entry_1[4] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[4] GE1_entry_1[4] = DFFEAS(AB1L32, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[4] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[4] GE1_entry_0[4] = DFFEAS(AB1L32, F1__clk1, , , GE1L47, , , , ); --HB1L124 is system_0:u0|sdram_0:the_sdram_0|Select~8228 HB1L124 = GE1_rd_address & GE1_entry_1[4] # !GE1_rd_address & (GE1_entry_0[4]); --HB1_active_data[4] is system_0:u0|sdram_0:the_sdram_0|active_data[4] HB1_active_data[4] = DFFEAS(HB1L124, F1__clk1, , , HB1L208, , , , ); --HB1L125 is system_0:u0|sdram_0:the_sdram_0|Select~8229 HB1L125 = HB1_m_state.000010000 & HB1_active_data[4] # !HB1_m_state.000010000 & (HB1_m_state.000000010 & HB1_active_data[4] # !HB1_m_state.000000010 & (HB1_m_data[4])); --HB1L126 is system_0:u0|sdram_0:the_sdram_0|Select~8230 HB1L126 = HB1_m_state.000010000 & (HB1_f_select & HB1L124 # !HB1_f_select & (HB1L125)) # !HB1_m_state.000010000 & (HB1L125); --GE1_entry_1[5] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[5] GE1_entry_1[5] = DFFEAS(AB1L33, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[5] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[5] GE1_entry_0[5] = DFFEAS(AB1L33, F1__clk1, , , GE1L47, , , , ); --HB1L127 is system_0:u0|sdram_0:the_sdram_0|Select~8231 HB1L127 = GE1_rd_address & GE1_entry_1[5] # !GE1_rd_address & (GE1_entry_0[5]); --HB1_active_data[5] is system_0:u0|sdram_0:the_sdram_0|active_data[5] HB1_active_data[5] = DFFEAS(HB1L127, F1__clk1, , , HB1L208, , , , ); --HB1L128 is system_0:u0|sdram_0:the_sdram_0|Select~8232 HB1L128 = HB1_m_state.000010000 & HB1_active_data[5] # !HB1_m_state.000010000 & (HB1_m_state.000000010 & HB1_active_data[5] # !HB1_m_state.000000010 & (HB1_m_data[5])); --HB1L129 is system_0:u0|sdram_0:the_sdram_0|Select~8233 HB1L129 = HB1_m_state.000010000 & (HB1_f_select & HB1L127 # !HB1_f_select & (HB1L128)) # !HB1_m_state.000010000 & (HB1L128); --GE1_entry_1[6] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[6] GE1_entry_1[6] = DFFEAS(AB1L34, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[6] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[6] GE1_entry_0[6] = DFFEAS(AB1L34, F1__clk1, , , GE1L47, , , , ); --HB1L130 is system_0:u0|sdram_0:the_sdram_0|Select~8234 HB1L130 = GE1_rd_address & GE1_entry_1[6] # !GE1_rd_address & (GE1_entry_0[6]); --HB1_active_data[6] is system_0:u0|sdram_0:the_sdram_0|active_data[6] HB1_active_data[6] = DFFEAS(HB1L130, F1__clk1, , , HB1L208, , , , ); --HB1L131 is system_0:u0|sdram_0:the_sdram_0|Select~8235 HB1L131 = HB1_m_state.000010000 & HB1_active_data[6] # !HB1_m_state.000010000 & (HB1_m_state.000000010 & HB1_active_data[6] # !HB1_m_state.000000010 & (HB1_m_data[6])); --HB1L132 is system_0:u0|sdram_0:the_sdram_0|Select~8236 HB1L132 = HB1_m_state.000010000 & (HB1_f_select & HB1L130 # !HB1_f_select & (HB1L131)) # !HB1_m_state.000010000 & (HB1L131); --GE1_entry_1[7] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[7] GE1_entry_1[7] = DFFEAS(AB1L35, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[7] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[7] GE1_entry_0[7] = DFFEAS(AB1L35, F1__clk1, , , GE1L47, , , , ); --HB1L133 is system_0:u0|sdram_0:the_sdram_0|Select~8237 HB1L133 = GE1_rd_address & GE1_entry_1[7] # !GE1_rd_address & (GE1_entry_0[7]); --HB1_active_data[7] is system_0:u0|sdram_0:the_sdram_0|active_data[7] HB1_active_data[7] = DFFEAS(HB1L133, F1__clk1, , , HB1L208, , , , ); --HB1L134 is system_0:u0|sdram_0:the_sdram_0|Select~8238 HB1L134 = HB1_m_state.000010000 & HB1_active_data[7] # !HB1_m_state.000010000 & (HB1_m_state.000000010 & HB1_active_data[7] # !HB1_m_state.000000010 & (HB1_m_data[7])); --HB1L135 is system_0:u0|sdram_0:the_sdram_0|Select~8239 HB1L135 = HB1_m_state.000010000 & (HB1_f_select & HB1L133 # !HB1_f_select & (HB1L134)) # !HB1_m_state.000010000 & (HB1L134); --GE1_entry_1[8] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[8] GE1_entry_1[8] = DFFEAS(AB1L36, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[8] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[8] GE1_entry_0[8] = DFFEAS(AB1L36, F1__clk1, , , GE1L47, , , , ); --HB1L136 is system_0:u0|sdram_0:the_sdram_0|Select~8240 HB1L136 = GE1_rd_address & GE1_entry_1[8] # !GE1_rd_address & (GE1_entry_0[8]); --HB1_active_data[8] is system_0:u0|sdram_0:the_sdram_0|active_data[8] HB1_active_data[8] = DFFEAS(HB1L136, F1__clk1, , , HB1L208, , , , ); --HB1L137 is system_0:u0|sdram_0:the_sdram_0|Select~8241 HB1L137 = HB1_m_state.000010000 & HB1_active_data[8] # !HB1_m_state.000010000 & (HB1_m_state.000000010 & HB1_active_data[8] # !HB1_m_state.000000010 & (HB1_m_data[8])); --HB1L138 is system_0:u0|sdram_0:the_sdram_0|Select~8242 HB1L138 = HB1_m_state.000010000 & (HB1_f_select & HB1L136 # !HB1_f_select & (HB1L137)) # !HB1_m_state.000010000 & (HB1L137); --GE1_entry_1[9] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[9] GE1_entry_1[9] = DFFEAS(AB1L37, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[9] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[9] GE1_entry_0[9] = DFFEAS(AB1L37, F1__clk1, , , GE1L47, , , , ); --HB1L139 is system_0:u0|sdram_0:the_sdram_0|Select~8243 HB1L139 = GE1_rd_address & GE1_entry_1[9] # !GE1_rd_address & (GE1_entry_0[9]); --HB1_active_data[9] is system_0:u0|sdram_0:the_sdram_0|active_data[9] HB1_active_data[9] = DFFEAS(HB1L139, F1__clk1, , , HB1L208, , , , ); --HB1L140 is system_0:u0|sdram_0:the_sdram_0|Select~8244 HB1L140 = HB1_m_state.000010000 & HB1_active_data[9] # !HB1_m_state.000010000 & (HB1_m_state.000000010 & HB1_active_data[9] # !HB1_m_state.000000010 & (HB1_m_data[9])); --HB1L141 is system_0:u0|sdram_0:the_sdram_0|Select~8245 HB1L141 = HB1_m_state.000010000 & (HB1_f_select & HB1L139 # !HB1_f_select & (HB1L140)) # !HB1_m_state.000010000 & (HB1L140); --GE1_entry_1[10] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[10] GE1_entry_1[10] = DFFEAS(AB1L38, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[10] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[10] GE1_entry_0[10] = DFFEAS(AB1L38, F1__clk1, , , GE1L47, , , , ); --HB1L142 is system_0:u0|sdram_0:the_sdram_0|Select~8246 HB1L142 = GE1_rd_address & GE1_entry_1[10] # !GE1_rd_address & (GE1_entry_0[10]); --HB1_active_data[10] is system_0:u0|sdram_0:the_sdram_0|active_data[10] HB1_active_data[10] = DFFEAS(HB1L142, F1__clk1, , , HB1L208, , , , ); --HB1L143 is system_0:u0|sdram_0:the_sdram_0|Select~8247 HB1L143 = HB1_m_state.000010000 & HB1_active_data[10] # !HB1_m_state.000010000 & (HB1_m_state.000000010 & HB1_active_data[10] # !HB1_m_state.000000010 & (HB1_m_data[10])); --HB1L144 is system_0:u0|sdram_0:the_sdram_0|Select~8248 HB1L144 = HB1_m_state.000010000 & (HB1_f_select & HB1L142 # !HB1_f_select & (HB1L143)) # !HB1_m_state.000010000 & (HB1L143); --GE1_entry_1[11] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[11] GE1_entry_1[11] = DFFEAS(AB1L39, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[11] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[11] GE1_entry_0[11] = DFFEAS(AB1L39, F1__clk1, , , GE1L47, , , , ); --HB1L145 is system_0:u0|sdram_0:the_sdram_0|Select~8249 HB1L145 = GE1_rd_address & GE1_entry_1[11] # !GE1_rd_address & (GE1_entry_0[11]); --HB1_active_data[11] is system_0:u0|sdram_0:the_sdram_0|active_data[11] HB1_active_data[11] = DFFEAS(HB1L145, F1__clk1, , , HB1L208, , , , ); --HB1L146 is system_0:u0|sdram_0:the_sdram_0|Select~8250 HB1L146 = HB1_m_state.000010000 & HB1_active_data[11] # !HB1_m_state.000010000 & (HB1_m_state.000000010 & HB1_active_data[11] # !HB1_m_state.000000010 & (HB1_m_data[11])); --HB1L147 is system_0:u0|sdram_0:the_sdram_0|Select~8251 HB1L147 = HB1_m_state.000010000 & (HB1_f_select & HB1L145 # !HB1_f_select & (HB1L146)) # !HB1_m_state.000010000 & (HB1L146); --GE1_entry_1[12] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[12] GE1_entry_1[12] = DFFEAS(AB1L40, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[12] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[12] GE1_entry_0[12] = DFFEAS(AB1L40, F1__clk1, , , GE1L47, , , , ); --HB1L148 is system_0:u0|sdram_0:the_sdram_0|Select~8252 HB1L148 = GE1_rd_address & GE1_entry_1[12] # !GE1_rd_address & (GE1_entry_0[12]); --HB1_active_data[12] is system_0:u0|sdram_0:the_sdram_0|active_data[12] HB1_active_data[12] = DFFEAS(HB1L148, F1__clk1, , , HB1L208, , , , ); --HB1L149 is system_0:u0|sdram_0:the_sdram_0|Select~8253 HB1L149 = HB1_m_state.000010000 & HB1_active_data[12] # !HB1_m_state.000010000 & (HB1_m_state.000000010 & HB1_active_data[12] # !HB1_m_state.000000010 & (HB1_m_data[12])); --HB1L150 is system_0:u0|sdram_0:the_sdram_0|Select~8254 HB1L150 = HB1_m_state.000010000 & (HB1_f_select & HB1L148 # !HB1_f_select & (HB1L149)) # !HB1_m_state.000010000 & (HB1L149); --GE1_entry_1[13] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[13] GE1_entry_1[13] = DFFEAS(AB1L41, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[13] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[13] GE1_entry_0[13] = DFFEAS(AB1L41, F1__clk1, , , GE1L47, , , , ); --HB1L151 is system_0:u0|sdram_0:the_sdram_0|Select~8255 HB1L151 = GE1_rd_address & GE1_entry_1[13] # !GE1_rd_address & (GE1_entry_0[13]); --HB1_active_data[13] is system_0:u0|sdram_0:the_sdram_0|active_data[13] HB1_active_data[13] = DFFEAS(HB1L151, F1__clk1, , , HB1L208, , , , ); --HB1L152 is system_0:u0|sdram_0:the_sdram_0|Select~8256 HB1L152 = HB1_m_state.000010000 & HB1_active_data[13] # !HB1_m_state.000010000 & (HB1_m_state.000000010 & HB1_active_data[13] # !HB1_m_state.000000010 & (HB1_m_data[13])); --HB1L153 is system_0:u0|sdram_0:the_sdram_0|Select~8257 HB1L153 = HB1_m_state.000010000 & (HB1_f_select & HB1L151 # !HB1_f_select & (HB1L152)) # !HB1_m_state.000010000 & (HB1L152); --GE1_entry_1[14] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[14] GE1_entry_1[14] = DFFEAS(AB1L42, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[14] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[14] GE1_entry_0[14] = DFFEAS(AB1L42, F1__clk1, , , GE1L47, , , , ); --HB1L154 is system_0:u0|sdram_0:the_sdram_0|Select~8258 HB1L154 = GE1_rd_address & GE1_entry_1[14] # !GE1_rd_address & (GE1_entry_0[14]); --HB1_active_data[14] is system_0:u0|sdram_0:the_sdram_0|active_data[14] HB1_active_data[14] = DFFEAS(HB1L154, F1__clk1, , , HB1L208, , , , ); --HB1L155 is system_0:u0|sdram_0:the_sdram_0|Select~8259 HB1L155 = HB1_m_state.000010000 & HB1_active_data[14] # !HB1_m_state.000010000 & (HB1_m_state.000000010 & HB1_active_data[14] # !HB1_m_state.000000010 & (HB1_m_data[14])); --HB1L156 is system_0:u0|sdram_0:the_sdram_0|Select~8260 HB1L156 = HB1_m_state.000010000 & (HB1_f_select & HB1L154 # !HB1_f_select & (HB1L155)) # !HB1_m_state.000010000 & (HB1L155); --GE1_entry_1[15] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[15] GE1_entry_1[15] = DFFEAS(AB1L43, F1__clk1, , , GE1L90, , , , ); --GE1_entry_0[15] is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[15] GE1_entry_0[15] = DFFEAS(AB1L43, F1__clk1, , , GE1L47, , , , ); --HB1L157 is system_0:u0|sdram_0:the_sdram_0|Select~8261 HB1L157 = GE1_rd_address & GE1_entry_1[15] # !GE1_rd_address & (GE1_entry_0[15]); --HB1_active_data[15] is system_0:u0|sdram_0:the_sdram_0|active_data[15] HB1_active_data[15] = DFFEAS(HB1L157, F1__clk1, , , HB1L208, , , , ); --HB1L158 is system_0:u0|sdram_0:the_sdram_0|Select~8262 HB1L158 = HB1_m_state.000010000 & HB1_active_data[15] # !HB1_m_state.000010000 & (HB1_m_state.000000010 & HB1_active_data[15] # !HB1_m_state.000000010 & (HB1_m_data[15])); --HB1L159 is system_0:u0|sdram_0:the_sdram_0|Select~8263 HB1L159 = HB1_m_state.000010000 & (HB1_f_select & HB1L157 # !HB1_f_select & (HB1L158)) # !HB1_m_state.000010000 & (HB1L158); --AB1L12 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[0]~88 AB1L12 = AB1_cpu_0_data_master_dbs_address[0] & (AB1_cpu_0_data_master_dbs_address[1]) # !AB1_cpu_0_data_master_dbs_address[0] & (AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[16] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[0])); --AB1L13 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[0]~89 AB1L13 = AB1_cpu_0_data_master_dbs_address[0] & (AB1L12 & (Z1_d_writedata[24]) # !AB1L12 & Z1_d_writedata[8]) # !AB1_cpu_0_data_master_dbs_address[0] & (AB1L12); --AB1L14 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[1]~90 AB1L14 = AB1_cpu_0_data_master_dbs_address[0] & (AB1_cpu_0_data_master_dbs_address[1]) # !AB1_cpu_0_data_master_dbs_address[0] & (AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[17] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[1])); --AB1L15 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[1]~91 AB1L15 = AB1_cpu_0_data_master_dbs_address[0] & (AB1L14 & (Z1_d_writedata[25]) # !AB1L14 & Z1_d_writedata[9]) # !AB1_cpu_0_data_master_dbs_address[0] & (AB1L14); --AB1L16 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[2]~92 AB1L16 = AB1_cpu_0_data_master_dbs_address[0] & (AB1_cpu_0_data_master_dbs_address[1]) # !AB1_cpu_0_data_master_dbs_address[0] & (AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[18] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[2])); --AB1L17 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[2]~93 AB1L17 = AB1_cpu_0_data_master_dbs_address[0] & (AB1L16 & (Z1_d_writedata[26]) # !AB1L16 & Z1_d_writedata[10]) # !AB1_cpu_0_data_master_dbs_address[0] & (AB1L16); --AB1L18 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[3]~94 AB1L18 = AB1_cpu_0_data_master_dbs_address[0] & (AB1_cpu_0_data_master_dbs_address[1]) # !AB1_cpu_0_data_master_dbs_address[0] & (AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[19] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[3])); --AB1L19 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[3]~95 AB1L19 = AB1_cpu_0_data_master_dbs_address[0] & (AB1L18 & (Z1_d_writedata[27]) # !AB1L18 & Z1_d_writedata[11]) # !AB1_cpu_0_data_master_dbs_address[0] & (AB1L18); --AB1L20 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[4]~96 AB1L20 = AB1_cpu_0_data_master_dbs_address[0] & (AB1_cpu_0_data_master_dbs_address[1]) # !AB1_cpu_0_data_master_dbs_address[0] & (AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[20] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[4])); --AB1L21 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[4]~97 AB1L21 = AB1_cpu_0_data_master_dbs_address[0] & (AB1L20 & (Z1_d_writedata[28]) # !AB1L20 & Z1_d_writedata[12]) # !AB1_cpu_0_data_master_dbs_address[0] & (AB1L20); --AB1L22 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[5]~98 AB1L22 = AB1_cpu_0_data_master_dbs_address[0] & (AB1_cpu_0_data_master_dbs_address[1]) # !AB1_cpu_0_data_master_dbs_address[0] & (AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[21] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[5])); --AB1L23 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[5]~99 AB1L23 = AB1_cpu_0_data_master_dbs_address[0] & (AB1L22 & (Z1_d_writedata[29]) # !AB1L22 & Z1_d_writedata[13]) # !AB1_cpu_0_data_master_dbs_address[0] & (AB1L22); --AB1L24 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[6]~100 AB1L24 = AB1_cpu_0_data_master_dbs_address[0] & (AB1_cpu_0_data_master_dbs_address[1]) # !AB1_cpu_0_data_master_dbs_address[0] & (AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[22] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[6])); --AB1L25 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[6]~101 AB1L25 = AB1_cpu_0_data_master_dbs_address[0] & (AB1L24 & (Z1_d_writedata[30]) # !AB1L24 & Z1_d_writedata[14]) # !AB1_cpu_0_data_master_dbs_address[0] & (AB1L24); --AB1L26 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[7]~102 AB1L26 = AB1_cpu_0_data_master_dbs_address[0] & (AB1_cpu_0_data_master_dbs_address[1]) # !AB1_cpu_0_data_master_dbs_address[0] & (AB1_cpu_0_data_master_dbs_address[1] & Z1_d_writedata[23] # !AB1_cpu_0_data_master_dbs_address[1] & (Z1_d_writedata[7])); --AB1L27 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[7]~103 AB1L27 = AB1_cpu_0_data_master_dbs_address[0] & (AB1L26 & (Z1_d_writedata[31]) # !AB1L26 & Z1_d_writedata[15]) # !AB1_cpu_0_data_master_dbs_address[0] & (AB1L26); --Z1_A_st_data[16] is system_0:u0|cpu_0:the_cpu_0|A_st_data[16] Z1_A_st_data[16] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[16], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[16] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[16] Z1_A_dc_victim_rd_data[16] = AMPP_FUNCTION(F1__clk1, Z1L2239, N1_data_out, Z1_A_stall); --Z1L3145 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[16]~304 Z1L3145 = AMPP_FUNCTION(Z1_A_st_data[16], Z1_A_dc_victim_rd_data[16], Z1_A_ctrl_st_bypass); --Z1_A_st_data[17] is system_0:u0|cpu_0:the_cpu_0|A_st_data[17] Z1_A_st_data[17] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[17], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[17] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[17] Z1_A_dc_victim_rd_data[17] = AMPP_FUNCTION(F1__clk1, Z1L2240, N1_data_out, Z1_A_stall); --Z1L3146 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[17]~305 Z1L3146 = AMPP_FUNCTION(Z1_A_st_data[17], Z1_A_dc_victim_rd_data[17], Z1_A_ctrl_st_bypass); --Z1_A_st_data[18] is system_0:u0|cpu_0:the_cpu_0|A_st_data[18] Z1_A_st_data[18] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[18], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[18] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[18] Z1_A_dc_victim_rd_data[18] = AMPP_FUNCTION(F1__clk1, Z1L2241, N1_data_out, Z1_A_stall); --Z1L3147 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[18]~306 Z1L3147 = AMPP_FUNCTION(Z1_A_st_data[18], Z1_A_dc_victim_rd_data[18], Z1_A_ctrl_st_bypass); --Z1_A_st_data[19] is system_0:u0|cpu_0:the_cpu_0|A_st_data[19] Z1_A_st_data[19] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[19], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[19] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[19] Z1_A_dc_victim_rd_data[19] = AMPP_FUNCTION(F1__clk1, Z1L2242, N1_data_out, Z1_A_stall); --Z1L3148 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[19]~307 Z1L3148 = AMPP_FUNCTION(Z1_A_st_data[19], Z1_A_dc_victim_rd_data[19], Z1_A_ctrl_st_bypass); --Z1_A_st_data[20] is system_0:u0|cpu_0:the_cpu_0|A_st_data[20] Z1_A_st_data[20] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[20], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[20] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[20] Z1_A_dc_victim_rd_data[20] = AMPP_FUNCTION(F1__clk1, Z1L2243, N1_data_out, Z1_A_stall); --Z1L3149 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[20]~308 Z1L3149 = AMPP_FUNCTION(Z1_A_st_data[20], Z1_A_dc_victim_rd_data[20], Z1_A_ctrl_st_bypass); --Z1_A_st_data[21] is system_0:u0|cpu_0:the_cpu_0|A_st_data[21] Z1_A_st_data[21] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[21], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[21] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[21] Z1_A_dc_victim_rd_data[21] = AMPP_FUNCTION(F1__clk1, Z1L2244, N1_data_out, Z1_A_stall); --Z1L3150 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[21]~309 Z1L3150 = AMPP_FUNCTION(Z1_A_st_data[21], Z1_A_dc_victim_rd_data[21], Z1_A_ctrl_st_bypass); --Z1_A_st_data[22] is system_0:u0|cpu_0:the_cpu_0|A_st_data[22] Z1_A_st_data[22] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[22], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[22] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[22] Z1_A_dc_victim_rd_data[22] = AMPP_FUNCTION(F1__clk1, Z1L2245, N1_data_out, Z1_A_stall); --Z1L3151 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[22]~310 Z1L3151 = AMPP_FUNCTION(Z1_A_st_data[22], Z1_A_dc_victim_rd_data[22], Z1_A_ctrl_st_bypass); --Z1_A_st_data[23] is system_0:u0|cpu_0:the_cpu_0|A_st_data[23] Z1_A_st_data[23] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[23], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[23] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[23] Z1_A_dc_victim_rd_data[23] = AMPP_FUNCTION(F1__clk1, Z1L2246, N1_data_out, Z1_A_stall); --Z1L3152 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[23]~311 Z1L3152 = AMPP_FUNCTION(Z1_A_st_data[23], Z1_A_dc_victim_rd_data[23], Z1_A_ctrl_st_bypass); --Z1_A_st_data[24] is system_0:u0|cpu_0:the_cpu_0|A_st_data[24] Z1_A_st_data[24] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[24], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[24] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[24] Z1_A_dc_victim_rd_data[24] = AMPP_FUNCTION(F1__clk1, Z1L2247, N1_data_out, Z1_A_stall); --Z1L3153 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[24]~312 Z1L3153 = AMPP_FUNCTION(Z1_A_st_data[24], Z1_A_dc_victim_rd_data[24], Z1_A_ctrl_st_bypass); --Z1_A_st_data[25] is system_0:u0|cpu_0:the_cpu_0|A_st_data[25] Z1_A_st_data[25] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[25], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[25] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[25] Z1_A_dc_victim_rd_data[25] = AMPP_FUNCTION(F1__clk1, Z1L2248, N1_data_out, Z1_A_stall); --Z1L3154 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[25]~313 Z1L3154 = AMPP_FUNCTION(Z1_A_st_data[25], Z1_A_dc_victim_rd_data[25], Z1_A_ctrl_st_bypass); --Z1_A_st_data[26] is system_0:u0|cpu_0:the_cpu_0|A_st_data[26] Z1_A_st_data[26] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[26], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[26] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[26] Z1_A_dc_victim_rd_data[26] = AMPP_FUNCTION(F1__clk1, Z1L2249, N1_data_out, Z1_A_stall); --Z1L3155 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[26]~314 Z1L3155 = AMPP_FUNCTION(Z1_A_st_data[26], Z1_A_dc_victim_rd_data[26], Z1_A_ctrl_st_bypass); --Z1_A_st_data[27] is system_0:u0|cpu_0:the_cpu_0|A_st_data[27] Z1_A_st_data[27] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[27], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[27] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[27] Z1_A_dc_victim_rd_data[27] = AMPP_FUNCTION(F1__clk1, Z1L2250, N1_data_out, Z1_A_stall); --Z1L3156 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[27]~315 Z1L3156 = AMPP_FUNCTION(Z1_A_st_data[27], Z1_A_dc_victim_rd_data[27], Z1_A_ctrl_st_bypass); --Z1_A_st_data[28] is system_0:u0|cpu_0:the_cpu_0|A_st_data[28] Z1_A_st_data[28] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[28], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[28] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[28] Z1_A_dc_victim_rd_data[28] = AMPP_FUNCTION(F1__clk1, Z1L2251, N1_data_out, Z1_A_stall); --Z1L3157 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[28]~316 Z1L3157 = AMPP_FUNCTION(Z1_A_st_data[28], Z1_A_dc_victim_rd_data[28], Z1_A_ctrl_st_bypass); --Z1_A_st_data[29] is system_0:u0|cpu_0:the_cpu_0|A_st_data[29] Z1_A_st_data[29] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[29], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[29] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[29] Z1_A_dc_victim_rd_data[29] = AMPP_FUNCTION(F1__clk1, Z1L2252, N1_data_out, Z1_A_stall); --Z1L3158 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[29]~317 Z1L3158 = AMPP_FUNCTION(Z1_A_st_data[29], Z1_A_dc_victim_rd_data[29], Z1_A_ctrl_st_bypass); --Z1_A_st_data[30] is system_0:u0|cpu_0:the_cpu_0|A_st_data[30] Z1_A_st_data[30] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[30], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[30] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[30] Z1_A_dc_victim_rd_data[30] = AMPP_FUNCTION(F1__clk1, Z1L2253, N1_data_out, Z1_A_stall); --Z1L3159 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[30]~318 Z1L3159 = AMPP_FUNCTION(Z1_A_st_data[30], Z1_A_dc_victim_rd_data[30], Z1_A_ctrl_st_bypass); --Z1_A_st_data[31] is system_0:u0|cpu_0:the_cpu_0|A_st_data[31] Z1_A_st_data[31] = AMPP_FUNCTION(F1__clk1, Z1_M_st_data[31], N1_data_out, Z1_A_stall); --Z1_A_dc_victim_rd_data[31] is system_0:u0|cpu_0:the_cpu_0|A_dc_victim_rd_data[31] Z1_A_dc_victim_rd_data[31] = AMPP_FUNCTION(F1__clk1, Z1L2254, N1_data_out, Z1_A_stall); --Z1L3160 is system_0:u0|cpu_0:the_cpu_0|d_writedata_nxt[31]~319 Z1L3160 = AMPP_FUNCTION(Z1_A_st_data[31], Z1_A_dc_victim_rd_data[31], Z1_A_ctrl_st_bypass); --Z1_E_src2_reg[0] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[0] Z1_E_src2_reg[0] = AMPP_FUNCTION(F1__clk1, Z1L1743, N1_data_out, Z1_A_stall); --Z1_d_readdata_d1[0] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[0] Z1_d_readdata_d1[0] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[0], N1_data_out); --Z1L3165 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[0]~1344 Z1L3165 = AMPP_FUNCTION(Z1_M_st_data[0], Z1_d_readdata_d1[0], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_A_ctrl_ld_initd_flushd_flushda is system_0:u0|cpu_0:the_cpu_0|A_ctrl_ld_initd_flushd_flushda Z1_A_ctrl_ld_initd_flushd_flushda = AMPP_FUNCTION(F1__clk1, Z1_M_ctrl_ld_initd_flushd_flushda, N1_data_out, Z1_A_stall); --Z1L3161 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_byte_en[0]~448 Z1L3161 = AMPP_FUNCTION(Z1_A_ctrl_ld_initd_flushd_flushda, Z1_M_mem_byte_en[0], Z1_A_dc_fill_wr_en, Z1_A_mem_byte_en[0]); --Z1_dc_data_wr_byte_0 is system_0:u0|cpu_0:the_cpu_0|dc_data_wr_byte_0 Z1_dc_data_wr_byte_0 = AMPP_FUNCTION(Z1L3198, Z1L3161); --Z1L67 is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_valid_byte_0~24 Z1L67 = AMPP_FUNCTION(Z1_A_stall, Z1L3198, Z1L3161, Z1_A_dc_latest_data_valid_byte_0); --FD1_sr[22] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[22] FD1_sr[22] = AMPP_FUNCTION(A1L333, FD1L125, D1_CLRN_SIGNAL, FD1L81); --G1_Q[0] is sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] G1_Q[0] = AMPP_FUNCTION(A1L333, G1L3, D1_jtag_debug_mode_usr1); --L1_state[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1] L1_state[1] = AMPP_FUNCTION(A1L333, L1L18, A1L335); --D1L4 is sld_hub:sld_hub_inst|CLRN_SIGNAL~0 D1L4 = AMPP_FUNCTION(G1_Q[0], L1_state[1]); --FD1_sr[34] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[34] FD1_sr[34] = AMPP_FUNCTION(A1L333, FD1L127, D1_CLRN_SIGNAL, FD1L81); --FD1_dr_update2 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|dr_update2 FD1_dr_update2 = AMPP_FUNCTION(F1__clk1, FD1_dr_update1); --FD1_dr_update1 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|dr_update1 FD1_dr_update1 = AMPP_FUNCTION(F1__clk1, FD1L192); --FD1L58 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jxdr~0 FD1L58 = AMPP_FUNCTION(FD1_dr_update2, FD1_dr_update1); --G5_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] G5_Q[1] = AMPP_FUNCTION(A1L333, D1L27, D1_CLRN_SIGNAL, D1L29); --FD1L16 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|ir[1]~0 FD1L16 = AMPP_FUNCTION(D1_CLRN_SIGNAL, FD1L195); --G5_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] G5_Q[0] = AMPP_FUNCTION(A1L333, D1L26, D1_CLRN_SIGNAL, D1L29); --FD1_sr[35] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35] FD1_sr[35] = AMPP_FUNCTION(A1L333, FD1L109, D1_CLRN_SIGNAL, FD1L110); --C1L3 is Reset_Delay:delay1|Cont[0]~1072 C1L3 = C1_Cont[0] $ VCC; --C1L4 is Reset_Delay:delay1|Cont[0]~1073 C1L4 = CARRY(C1_Cont[0]); --C1L6 is Reset_Delay:delay1|Cont[1]~1074 C1L6 = C1_Cont[1] & !C1L4 # !C1_Cont[1] & (C1L4 # GND); --C1L7 is Reset_Delay:delay1|Cont[1]~1075 C1L7 = CARRY(!C1L4 # !C1_Cont[1]); --C1L9 is Reset_Delay:delay1|Cont[2]~1076 C1L9 = C1_Cont[2] & (C1L7 $ GND) # !C1_Cont[2] & !C1L7 & VCC; --C1L10 is Reset_Delay:delay1|Cont[2]~1077 C1L10 = CARRY(C1_Cont[2] & !C1L7); --C1L12 is Reset_Delay:delay1|Cont[3]~1078 C1L12 = C1_Cont[3] & !C1L10 # !C1_Cont[3] & (C1L10 # GND); --C1L13 is Reset_Delay:delay1|Cont[3]~1079 C1L13 = CARRY(!C1L10 # !C1_Cont[3]); --C1L15 is Reset_Delay:delay1|Cont[4]~1080 C1L15 = C1_Cont[4] & (C1L13 $ GND) # !C1_Cont[4] & !C1L13 & VCC; --C1L16 is Reset_Delay:delay1|Cont[4]~1081 C1L16 = CARRY(C1_Cont[4] & !C1L13); --C1L18 is Reset_Delay:delay1|Cont[5]~1082 C1L18 = C1_Cont[5] & !C1L16 # !C1_Cont[5] & (C1L16 # GND); --C1L19 is Reset_Delay:delay1|Cont[5]~1083 C1L19 = CARRY(!C1L16 # !C1_Cont[5]); --C1L21 is Reset_Delay:delay1|Cont[6]~1084 C1L21 = C1_Cont[6] & (C1L19 $ GND) # !C1_Cont[6] & !C1L19 & VCC; --C1L22 is Reset_Delay:delay1|Cont[6]~1085 C1L22 = CARRY(C1_Cont[6] & !C1L19); --C1L24 is Reset_Delay:delay1|Cont[7]~1086 C1L24 = C1_Cont[7] & !C1L22 # !C1_Cont[7] & (C1L22 # GND); --C1L25 is Reset_Delay:delay1|Cont[7]~1087 C1L25 = CARRY(!C1L22 # !C1_Cont[7]); --C1L27 is Reset_Delay:delay1|Cont[8]~1088 C1L27 = C1_Cont[8] & (C1L25 $ GND) # !C1_Cont[8] & !C1L25 & VCC; --C1L28 is Reset_Delay:delay1|Cont[8]~1089 C1L28 = CARRY(C1_Cont[8] & !C1L25); --C1L30 is Reset_Delay:delay1|Cont[9]~1090 C1L30 = C1_Cont[9] & !C1L28 # !C1_Cont[9] & (C1L28 # GND); --C1L31 is Reset_Delay:delay1|Cont[9]~1091 C1L31 = CARRY(!C1L28 # !C1_Cont[9]); --C1L33 is Reset_Delay:delay1|Cont[10]~1092 C1L33 = C1_Cont[10] & (C1L31 $ GND) # !C1_Cont[10] & !C1L31 & VCC; --C1L34 is Reset_Delay:delay1|Cont[10]~1093 C1L34 = CARRY(C1_Cont[10] & !C1L31); --C1L36 is Reset_Delay:delay1|Cont[11]~1094 C1L36 = C1_Cont[11] & !C1L34 # !C1_Cont[11] & (C1L34 # GND); --C1L37 is Reset_Delay:delay1|Cont[11]~1095 C1L37 = CARRY(!C1L34 # !C1_Cont[11]); --C1L39 is Reset_Delay:delay1|Cont[12]~1096 C1L39 = C1_Cont[12] & (C1L37 $ GND) # !C1_Cont[12] & !C1L37 & VCC; --C1L40 is Reset_Delay:delay1|Cont[12]~1097 C1L40 = CARRY(C1_Cont[12] & !C1L37); --C1L42 is Reset_Delay:delay1|Cont[13]~1098 C1L42 = C1_Cont[13] & !C1L40 # !C1_Cont[13] & (C1L40 # GND); --C1L43 is Reset_Delay:delay1|Cont[13]~1099 C1L43 = CARRY(!C1L40 # !C1_Cont[13]); --C1L45 is Reset_Delay:delay1|Cont[14]~1100 C1L45 = C1_Cont[14] & (C1L43 $ GND) # !C1_Cont[14] & !C1L43 & VCC; --C1L46 is Reset_Delay:delay1|Cont[14]~1101 C1L46 = CARRY(C1_Cont[14] & !C1L43); --C1L48 is Reset_Delay:delay1|Cont[15]~1102 C1L48 = C1_Cont[15] & !C1L46 # !C1_Cont[15] & (C1L46 # GND); --C1L49 is Reset_Delay:delay1|Cont[15]~1103 C1L49 = CARRY(!C1L46 # !C1_Cont[15]); --C1L51 is Reset_Delay:delay1|Cont[16]~1104 C1L51 = C1_Cont[16] & (C1L49 $ GND) # !C1_Cont[16] & !C1L49 & VCC; --C1L52 is Reset_Delay:delay1|Cont[16]~1105 C1L52 = CARRY(C1_Cont[16] & !C1L49); --C1L54 is Reset_Delay:delay1|Cont[17]~1106 C1L54 = C1_Cont[17] & !C1L52 # !C1_Cont[17] & (C1L52 # GND); --C1L55 is Reset_Delay:delay1|Cont[17]~1107 C1L55 = CARRY(!C1L52 # !C1_Cont[17]); --C1L57 is Reset_Delay:delay1|Cont[18]~1108 C1L57 = C1_Cont[18] & (C1L55 $ GND) # !C1_Cont[18] & !C1L55 & VCC; --C1L58 is Reset_Delay:delay1|Cont[18]~1109 C1L58 = CARRY(C1_Cont[18] & !C1L55); --C1L60 is Reset_Delay:delay1|Cont[19]~1110 C1L60 = C1_Cont[19] & !C1L58 # !C1_Cont[19] & (C1L58 # GND); --C1L61 is Reset_Delay:delay1|Cont[19]~1111 C1L61 = CARRY(!C1L58 # !C1_Cont[19]); --C1L63 is Reset_Delay:delay1|Cont[20]~1112 C1L63 = C1_Cont[20] & (C1L61 $ GND) # !C1_Cont[20] & !C1L61 & VCC; --C1L64 is Reset_Delay:delay1|Cont[20]~1113 C1L64 = CARRY(C1_Cont[20] & !C1L61); --C1L66 is Reset_Delay:delay1|Cont[21]~1114 C1L66 = C1_Cont[21] & !C1L64 # !C1_Cont[21] & (C1L64 # GND); --C1L67 is Reset_Delay:delay1|Cont[21]~1115 C1L67 = CARRY(!C1L64 # !C1_Cont[21]); --C1L69 is Reset_Delay:delay1|Cont[22]~1116 C1L69 = C1_Cont[22] & (C1L67 $ GND) # !C1_Cont[22] & !C1L67 & VCC; --C1L70 is Reset_Delay:delay1|Cont[22]~1117 C1L70 = CARRY(C1_Cont[22] & !C1L67); --C1L72 is Reset_Delay:delay1|Cont[23]~1118 C1L72 = C1_Cont[23] $ C1L70; --Z1_E_src2_reg[1] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[1] Z1_E_src2_reg[1] = AMPP_FUNCTION(F1__clk1, Z1L1746, N1_data_out, Z1_A_stall); --Z1_d_readdata_d1[1] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[1] Z1_d_readdata_d1[1] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[1], N1_data_out); --Z1L3166 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[1]~1345 Z1L3166 = AMPP_FUNCTION(Z1_M_st_data[1], Z1_d_readdata_d1[1], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_E_src2_reg[2] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[2] Z1_E_src2_reg[2] = AMPP_FUNCTION(F1__clk1, Z1L1749, N1_data_out, Z1_A_stall); --Z1_d_readdata_d1[2] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[2] Z1_d_readdata_d1[2] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[2], N1_data_out); --Z1L3167 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[2]~1346 Z1L3167 = AMPP_FUNCTION(Z1_M_st_data[2], Z1_d_readdata_d1[2], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_E_src2_reg[3] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[3] Z1_E_src2_reg[3] = AMPP_FUNCTION(F1__clk1, Z1L1752, N1_data_out, Z1_A_stall); --Z1_d_readdata_d1[3] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[3] Z1_d_readdata_d1[3] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[3], N1_data_out); --Z1L3168 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[3]~1347 Z1L3168 = AMPP_FUNCTION(Z1_M_st_data[3], Z1_d_readdata_d1[3], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_E_src2_reg[4] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[4] Z1_E_src2_reg[4] = AMPP_FUNCTION(F1__clk1, Z1L1755, N1_data_out, Z1_A_stall); --Z1_d_readdata_d1[4] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[4] Z1_d_readdata_d1[4] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[4], N1_data_out); --Z1L3169 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[4]~1348 Z1L3169 = AMPP_FUNCTION(Z1_M_st_data[4], Z1_d_readdata_d1[4], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_E_src2_reg[5] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[5] Z1_E_src2_reg[5] = AMPP_FUNCTION(F1__clk1, Z1L1758, N1_data_out, Z1_A_stall); --Z1_d_readdata_d1[5] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[5] Z1_d_readdata_d1[5] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[5], N1_data_out); --Z1L3170 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[5]~1349 Z1L3170 = AMPP_FUNCTION(Z1_M_st_data[5], Z1_d_readdata_d1[5], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_E_src2_reg[6] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[6] Z1_E_src2_reg[6] = AMPP_FUNCTION(F1__clk1, Z1L1761, N1_data_out, Z1_A_stall); --Z1_d_readdata_d1[6] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[6] Z1_d_readdata_d1[6] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[6], N1_data_out); --Z1L3171 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[6]~1350 Z1L3171 = AMPP_FUNCTION(Z1_M_st_data[6], Z1_d_readdata_d1[6], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_E_src2_reg[7] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[7] Z1_E_src2_reg[7] = AMPP_FUNCTION(F1__clk1, Z1L1764, N1_data_out, Z1_A_stall); --Z1_d_readdata_d1[7] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[7] Z1_d_readdata_d1[7] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[7], N1_data_out); --Z1L3172 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[7]~1351 Z1L3172 = AMPP_FUNCTION(Z1_M_st_data[7], Z1_d_readdata_d1[7], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_E_src2_reg[8] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[8] Z1_E_src2_reg[8] = AMPP_FUNCTION(F1__clk1, Z1L1767, N1_data_out, Z1_A_stall); --Z1L1871 is system_0:u0|cpu_0:the_cpu_0|E_st_data[8]~776 Z1L1871 = AMPP_FUNCTION(Z1_E_src2_reg[8], Z1_E_src2_reg[0], Z1_E_iw[4], Z1_E_iw[3]); --Z1_d_readdata_d1[8] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[8] Z1_d_readdata_d1[8] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[8], N1_data_out); --Z1L3173 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[8]~1352 Z1L3173 = AMPP_FUNCTION(Z1_M_st_data[8], Z1_d_readdata_d1[8], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3162 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_byte_en[1]~449 Z1L3162 = AMPP_FUNCTION(Z1_A_ctrl_ld_initd_flushd_flushda, Z1_M_mem_byte_en[1], Z1_A_dc_fill_wr_en, Z1_A_mem_byte_en[1]); --Z1_dc_data_wr_byte_1 is system_0:u0|cpu_0:the_cpu_0|dc_data_wr_byte_1 Z1_dc_data_wr_byte_1 = AMPP_FUNCTION(Z1L3198, Z1L3162); --Z1L69 is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_valid_byte_1~24 Z1L69 = AMPP_FUNCTION(Z1_A_stall, Z1L3198, Z1L3162, Z1_A_dc_latest_data_valid_byte_1); --Z1_E_src2_reg[9] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[9] Z1_E_src2_reg[9] = AMPP_FUNCTION(F1__clk1, Z1L1770, N1_data_out, Z1_A_stall); --Z1L1872 is system_0:u0|cpu_0:the_cpu_0|E_st_data[9]~777 Z1L1872 = AMPP_FUNCTION(Z1_E_src2_reg[9], Z1_E_src2_reg[1], Z1_E_iw[4], Z1_E_iw[3]); --Z1_d_readdata_d1[9] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[9] Z1_d_readdata_d1[9] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[9], N1_data_out); --Z1L3174 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[9]~1353 Z1L3174 = AMPP_FUNCTION(Z1_M_st_data[9], Z1_d_readdata_d1[9], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_E_src2_reg[10] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[10] Z1_E_src2_reg[10] = AMPP_FUNCTION(F1__clk1, Z1L1773, N1_data_out, Z1_A_stall); --Z1L1873 is system_0:u0|cpu_0:the_cpu_0|E_st_data[10]~778 Z1L1873 = AMPP_FUNCTION(Z1_E_src2_reg[10], Z1_E_src2_reg[2], Z1_E_iw[4], Z1_E_iw[3]); --Z1_d_readdata_d1[10] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[10] Z1_d_readdata_d1[10] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[10], N1_data_out); --Z1L3175 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[10]~1354 Z1L3175 = AMPP_FUNCTION(Z1_M_st_data[10], Z1_d_readdata_d1[10], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_E_src2_reg[11] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[11] Z1_E_src2_reg[11] = AMPP_FUNCTION(F1__clk1, Z1L1776, N1_data_out, Z1_A_stall); --Z1L1874 is system_0:u0|cpu_0:the_cpu_0|E_st_data[11]~779 Z1L1874 = AMPP_FUNCTION(Z1_E_src2_reg[11], Z1_E_src2_reg[3], Z1_E_iw[4], Z1_E_iw[3]); --Z1_d_readdata_d1[11] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[11] Z1_d_readdata_d1[11] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[11], N1_data_out); --Z1L3176 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[11]~1355 Z1L3176 = AMPP_FUNCTION(Z1_M_st_data[11], Z1_d_readdata_d1[11], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_E_src2_reg[12] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[12] Z1_E_src2_reg[12] = AMPP_FUNCTION(F1__clk1, Z1L1779, N1_data_out, Z1_A_stall); --Z1L1875 is system_0:u0|cpu_0:the_cpu_0|E_st_data[12]~780 Z1L1875 = AMPP_FUNCTION(Z1_E_src2_reg[12], Z1_E_src2_reg[4], Z1_E_iw[4], Z1_E_iw[3]); --Z1_d_readdata_d1[12] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[12] Z1_d_readdata_d1[12] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[12], N1_data_out); --Z1L3177 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[12]~1356 Z1L3177 = AMPP_FUNCTION(Z1_M_st_data[12], Z1_d_readdata_d1[12], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_E_src2_reg[13] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[13] Z1_E_src2_reg[13] = AMPP_FUNCTION(F1__clk1, Z1L1782, N1_data_out, Z1_A_stall); --Z1L1876 is system_0:u0|cpu_0:the_cpu_0|E_st_data[13]~781 Z1L1876 = AMPP_FUNCTION(Z1_E_src2_reg[13], Z1_E_src2_reg[5], Z1_E_iw[4], Z1_E_iw[3]); --Z1_d_readdata_d1[13] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[13] Z1_d_readdata_d1[13] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[13], N1_data_out); --Z1L3178 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[13]~1357 Z1L3178 = AMPP_FUNCTION(Z1_M_st_data[13], Z1_d_readdata_d1[13], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_E_src2_reg[14] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[14] Z1_E_src2_reg[14] = AMPP_FUNCTION(F1__clk1, Z1L1785, N1_data_out, Z1_A_stall); --Z1L1877 is system_0:u0|cpu_0:the_cpu_0|E_st_data[14]~782 Z1L1877 = AMPP_FUNCTION(Z1_E_src2_reg[14], Z1_E_src2_reg[6], Z1_E_iw[4], Z1_E_iw[3]); --Z1_d_readdata_d1[14] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[14] Z1_d_readdata_d1[14] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[14], N1_data_out); --Z1L3179 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[14]~1358 Z1L3179 = AMPP_FUNCTION(Z1_M_st_data[14], Z1_d_readdata_d1[14], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_E_src2_reg[15] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[15] Z1_E_src2_reg[15] = AMPP_FUNCTION(F1__clk1, Z1L1788, N1_data_out, Z1_A_stall); --Z1L1878 is system_0:u0|cpu_0:the_cpu_0|E_st_data[15]~783 Z1L1878 = AMPP_FUNCTION(Z1_E_src2_reg[15], Z1_E_src2_reg[7], Z1_E_iw[4], Z1_E_iw[3]); --Z1_d_readdata_d1[15] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[15] Z1_d_readdata_d1[15] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[15], N1_data_out); --Z1L3180 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[15]~1359 Z1L3180 = AMPP_FUNCTION(Z1_M_st_data[15], Z1_d_readdata_d1[15], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --NE1_tx_ready is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|tx_ready NE1_tx_ready = DFFEAS(NE1L47, F1__clk1, N1_data_out, , , , , , ); --NE1L38 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|do_load_shifter~0 NE1L38 = !NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] & NE1L42 & NE1_tx_ready; --NE1_baud_rate_counter[0] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[0] NE1_baud_rate_counter[0] = DFFEAS(NE1L5, F1__clk1, N1_data_out, , , ~GND, , , NE1L1); --NE1_baud_rate_counter[1] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[1] NE1_baud_rate_counter[1] = DFFEAS(NE1L8, F1__clk1, N1_data_out, , , ~GND, , , NE1L1); --NE1_baud_rate_counter[2] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[2] NE1_baud_rate_counter[2] = DFFEAS(NE1L11, F1__clk1, N1_data_out, , , VCC, , , NE1L1); --NE1_baud_rate_counter[3] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[3] NE1_baud_rate_counter[3] = DFFEAS(NE1L14, F1__clk1, N1_data_out, , , ~GND, , , NE1L1); --NE1L34 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter_is_zero~139 NE1L34 = !NE1_baud_rate_counter[0] & !NE1_baud_rate_counter[1] & !NE1_baud_rate_counter[2] & !NE1_baud_rate_counter[3]; --NE1_baud_rate_counter[4] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[4] NE1_baud_rate_counter[4] = DFFEAS(NE1L17, F1__clk1, N1_data_out, , , ~GND, , , NE1L1); --NE1_baud_rate_counter[5] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[5] NE1_baud_rate_counter[5] = DFFEAS(NE1L20, F1__clk1, N1_data_out, , , VCC, , , NE1L1); --NE1_baud_rate_counter[6] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[6] NE1_baud_rate_counter[6] = DFFEAS(NE1L23, F1__clk1, N1_data_out, , , VCC, , , NE1L1); --NE1_baud_rate_counter[7] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[7] NE1_baud_rate_counter[7] = DFFEAS(NE1L26, F1__clk1, N1_data_out, , , ~GND, , , NE1L1); --NE1L35 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter_is_zero~140 NE1L35 = !NE1_baud_rate_counter[4] & !NE1_baud_rate_counter[5] & !NE1_baud_rate_counter[6] & !NE1_baud_rate_counter[7]; --NE1_baud_rate_counter[8] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[8] NE1_baud_rate_counter[8] = DFFEAS(NE1L29, F1__clk1, N1_data_out, , , VCC, , , NE1L1); --NE1_baud_rate_counter[9] is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[9] NE1_baud_rate_counter[9] = DFFEAS(NE1L32, F1__clk1, N1_data_out, , , VCC, , , NE1L1); --NE1L36 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter_is_zero~141 NE1L36 = NE1L34 & NE1L35 & !NE1_baud_rate_counter[8] & !NE1_baud_rate_counter[9]; --PB1L1 is system_0:u0|uart_0_s1_arbitrator:the_uart_0_s1|Equal~67 PB1L1 = Q1L1 & !Z1_d_address[6]; --NE1L50 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|tx_wr_strobe_onset~10 NE1L50 = Z1_d_write & Z1_d_address[2] & GB1L7 & PB1L1; --HB1L160 is system_0:u0|sdram_0:the_sdram_0|Select~8264 HB1L160 = HB1L70 # HB1_m_state.000000100 & (HB1L6 $ HB1_m_count[0]); --HB1L161 is system_0:u0|sdram_0:the_sdram_0|Select~8265 HB1L161 = HB1L160 # HB1_m_state.000100000 & (!HB1_m_count[0] # !HB1L6); --HB1L162 is system_0:u0|sdram_0:the_sdram_0|Select~8266 HB1L162 = HB1L161 # HB1_m_count[0] & !HB1L98 # !HB1L350; --HB1L391 is system_0:u0|sdram_0:the_sdram_0|reduce_or~6 HB1L391 = HB1_i_state.101 # HB1_i_state.011 # !HB1_i_state.000; --HB1_i_refs[0] is system_0:u0|sdram_0:the_sdram_0|i_refs[0] HB1_i_refs[0] = DFFEAS(HB1L172, F1__clk1, , , N1_data_out, , , , ); --HB1_i_refs[2] is system_0:u0|sdram_0:the_sdram_0|i_refs[2] HB1_i_refs[2] = DFFEAS(HB1L173, F1__clk1, , , N1_data_out, , , , ); --HB1_i_refs[1] is system_0:u0|sdram_0:the_sdram_0|i_refs[1] HB1_i_refs[1] = DFFEAS(HB1L174, F1__clk1, , , N1_data_out, , , , ); --HB1L163 is system_0:u0|sdram_0:the_sdram_0|Select~8267 HB1L163 = HB1_i_refs[0] & !HB1_i_refs[2] & !HB1_i_refs[1]; --HB1L164 is system_0:u0|sdram_0:the_sdram_0|Select~8268 HB1L164 = HB1_i_state.010 & (HB1L163 # HB1_i_next.111 & HB1L391) # !HB1_i_state.010 & HB1_i_next.111 & HB1L391; --HB1_i_count[0] is system_0:u0|sdram_0:the_sdram_0|i_count[0] HB1_i_count[0] = DFFEAS(HB1L176, F1__clk1, N1_data_out, , , , , , ); --HB1L165 is system_0:u0|sdram_0:the_sdram_0|Select~8269 HB1L165 = HB1_i_state.011 & (HB1_i_count[1] # HB1_i_count[0]); --HB1L393 is system_0:u0|sdram_0:the_sdram_0|reduce_or~73 HB1L393 = HB1_i_state.000 & !HB1_i_state.101; --HB1L166 is system_0:u0|sdram_0:the_sdram_0|Select~8270 HB1L166 = HB1_i_count[2] & (HB1L165 # !HB1L393) # !HB1L106; --HB1L167 is system_0:u0|sdram_0:the_sdram_0|Select~8271 HB1L167 = HB1_i_state.011 & (HB1_i_count[1] & HB1_i_count[0] # !HB1_i_count[1] & !HB1_i_count[0] & HB1_i_count[2]); --HB1L168 is system_0:u0|sdram_0:the_sdram_0|Select~8272 HB1L168 = HB1_i_state.010 # HB1L167 # HB1_i_count[1] & !HB1L393; --HB1L169 is system_0:u0|sdram_0:the_sdram_0|Select~8273 HB1L169 = HB1_i_state.111 # HB1_i_next.101 & HB1L391; --HB1L280 is system_0:u0|sdram_0:the_sdram_0|i_next.000~270 HB1L280 = HB1_i_next.000 # HB1_i_state.000 & !HB1_i_state.101 & !HB1_i_state.011; --HB1L170 is system_0:u0|sdram_0:the_sdram_0|Select~8274 HB1L170 = HB1_i_state.010 & (HB1_i_refs[2] # HB1_i_refs[1] # !HB1_i_refs[0]); --HB1L171 is system_0:u0|sdram_0:the_sdram_0|Select~8275 HB1L171 = HB1_i_state.001 # HB1L170 # HB1_i_next.010 & HB1L391; --HB1_rd_valid[0] is system_0:u0|sdram_0:the_sdram_0|rd_valid[0] HB1_rd_valid[0] = DFFEAS(HB1L386, F1__clk1, N1_data_out, , , , , , ); --HE1_stage_3 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|stage_3 HE1_stage_3 = DFFEAS(HE1L34, F1__clk1, , , HE1L17, , , , ); --JE1_full_3 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_3 JE1_full_3 = DFFEAS(HE1L33, F1__clk1, N1_data_out, , HE1L14, , , , ); --HE1L32 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|p2_stage_2~10 HE1L32 = JE1_full_3 & HE1_stage_3 # !JE1_full_3 & (JB1L7); --HE1L18 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|always8~1 HE1L18 = HB1_za_valid # JB1L5 & !JE1_full_2; --HE1L31 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|p2_full_2~9 HE1L31 = HB1_za_valid & (JB1L5 & JE1_full_1 # !JB1L5 & (JE1_full_3)) # !HB1_za_valid & JE1_full_1; --Z1L1151 is system_0:u0|cpu_0:the_cpu_0|D_op_call~833 Z1L1151 = AMPP_FUNCTION(Z1_D_iw[12], Z1_D_iw[16]); --Z1_D_ctrl_dst_data_sel_logic_result is system_0:u0|cpu_0:the_cpu_0|D_ctrl_dst_data_sel_logic_result Z1_D_ctrl_dst_data_sel_logic_result = AMPP_FUNCTION(Z1L1026, Z1L1151, Z1_D_iw[11], Z1L1031); --Z1L1032 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_dst_data_sel_pc_plus_one~217 Z1L1032 = AMPP_FUNCTION(Z1_D_iw[11], Z1L1894, Z1_D_iw[16], Z1_D_iw[12]); --Z1L1033 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_dst_data_sel_pc_plus_one~218 Z1L1033 = AMPP_FUNCTION(Z1L1048, Z1L1026, Z1L1032); --Z1L1097 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[20]~1078 Z1L1097 = AMPP_FUNCTION(Z1L3003, Z1_D_pc_plus_one[20], Z1_D_bht_data[1], Z1L1024); --Z1L1028 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_dst_data_sel_cmp~210 Z1L1028 = AMPP_FUNCTION(Z1L1147, Z1L1149, Z1_D_iw[4], Z1_D_iw[5]); --Z1L1029 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_dst_data_sel_cmp~211 Z1L1029 = AMPP_FUNCTION(Z1L1028, Z1_D_iw[4], Z1L1010); --Z1_E_ctrl_shift_rot is system_0:u0|cpu_0:the_cpu_0|E_ctrl_shift_rot Z1_E_ctrl_shift_rot = AMPP_FUNCTION(F1__clk1, Z1L1056, N1_data_out, Z1_A_stall); --Z1L615 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_cnt_nxt~1 Z1L615 = AMPP_FUNCTION(Z1_A_shift_rot_stall, Z1_A_shift_rot_cnt); --Z1L222 is system_0:u0|cpu_0:the_cpu_0|A_mul_cnt_nxt[1]~9 Z1L222 = AMPP_FUNCTION(Z1_A_mul_cnt[0], Z1_A_mul_cnt[1], Z1_A_mul_stall); --Z1L223 is system_0:u0|cpu_0:the_cpu_0|A_mul_cnt_nxt[2]~10 Z1L223 = AMPP_FUNCTION(Z1_A_mul_cnt[2], Z1_A_mul_cnt[0], Z1_A_mul_cnt[1], Z1_A_mul_stall); --Z1L221 is system_0:u0|cpu_0:the_cpu_0|A_mul_cnt_nxt[0]~11 Z1L221 = AMPP_FUNCTION(Z1_A_mul_cnt[0], Z1_A_mul_stall); --Z1_E_ctrl_mul_lsw is system_0:u0|cpu_0:the_cpu_0|E_ctrl_mul_lsw Z1_E_ctrl_mul_lsw = AMPP_FUNCTION(F1__clk1, Z1_D_ctrl_mul_lsw, N1_data_out, Z1_A_stall); --Z1L1522 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_initd_flushd_flushda~24 Z1L1522 = AMPP_FUNCTION(Z1_E_iw[4], Z1_E_iw[1], Z1_E_iw[0], Z1_E_iw[2]); --Z1_D_pc_plus_one[8] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[8] Z1_D_pc_plus_one[8] = AMPP_FUNCTION(F1__clk1, Z1L2955, N1_data_out, Z1_F_stall); --Z1L1085 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[8]~1079 Z1L1085 = AMPP_FUNCTION(Z1_D_br_taken_waddr_partial[8], Z1_D_pc_plus_one[8], Z1_D_bht_data[1], Z1L1024); --Z1_D_pc_plus_one[6] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[6] Z1_D_pc_plus_one[6] = AMPP_FUNCTION(F1__clk1, Z1L2951, N1_data_out, Z1_F_stall); --Z1L1083 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[6]~1080 Z1L1083 = AMPP_FUNCTION(Z1_D_br_taken_waddr_partial[6], Z1_D_pc_plus_one[6], Z1_D_bht_data[1], Z1L1024); --Z1_D_pc_plus_one[1] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[1] Z1_D_pc_plus_one[1] = AMPP_FUNCTION(F1__clk1, Z1L2941, N1_data_out, Z1_F_stall); --Z1L1078 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[1]~1081 Z1L1078 = AMPP_FUNCTION(Z1_D_br_taken_waddr_partial[1], Z1_D_pc_plus_one[1], Z1_D_bht_data[1], Z1L1024); --Z1_D_pc_plus_one[0] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[0] Z1_D_pc_plus_one[0] = AMPP_FUNCTION(F1__clk1, Z1L2939, N1_data_out, Z1_F_stall); --Z1L1077 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[0]~1082 Z1L1077 = AMPP_FUNCTION(Z1_D_br_taken_waddr_partial[0], Z1_D_pc_plus_one[0], Z1_D_bht_data[1], Z1L1024); --Z1_D_pc_plus_one[4] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[4] Z1_D_pc_plus_one[4] = AMPP_FUNCTION(F1__clk1, Z1L2947, N1_data_out, Z1_F_stall); --Z1L1081 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[4]~1083 Z1L1081 = AMPP_FUNCTION(Z1_D_br_taken_waddr_partial[4], Z1_D_pc_plus_one[4], Z1_D_bht_data[1], Z1L1024); --Z1_D_pc_plus_one[2] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[2] Z1_D_pc_plus_one[2] = AMPP_FUNCTION(F1__clk1, Z1L2943, N1_data_out, Z1_F_stall); --Z1L1079 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[2]~1084 Z1L1079 = AMPP_FUNCTION(Z1_D_br_taken_waddr_partial[2], Z1_D_pc_plus_one[2], Z1_D_bht_data[1], Z1L1024); --Z1_D_pc_plus_one[5] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[5] Z1_D_pc_plus_one[5] = AMPP_FUNCTION(F1__clk1, Z1L2949, N1_data_out, Z1_F_stall); --Z1L1082 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[5]~1085 Z1L1082 = AMPP_FUNCTION(Z1_D_br_taken_waddr_partial[5], Z1_D_pc_plus_one[5], Z1_D_bht_data[1], Z1L1024); --Z1_D_pc_plus_one[3] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[3] Z1_D_pc_plus_one[3] = AMPP_FUNCTION(F1__clk1, Z1L2945, N1_data_out, Z1_F_stall); --Z1L1080 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[3]~1086 Z1L1080 = AMPP_FUNCTION(Z1_D_br_taken_waddr_partial[3], Z1_D_pc_plus_one[3], Z1_D_bht_data[1], Z1L1024); --Z1_D_pc_plus_one[7] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[7] Z1_D_pc_plus_one[7] = AMPP_FUNCTION(F1__clk1, Z1L2953, N1_data_out, Z1_F_stall); --Z1L1084 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[7]~1087 Z1L1084 = AMPP_FUNCTION(Z1_D_br_taken_waddr_partial[7], Z1_D_pc_plus_one[7], Z1_D_bht_data[1], Z1L1024); --Z1_D_pc_plus_one[9] is system_0:u0|cpu_0:the_cpu_0|D_pc_plus_one[9] Z1_D_pc_plus_one[9] = AMPP_FUNCTION(F1__clk1, Z1L2957, N1_data_out, Z1_F_stall); --Z1L1086 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[9]~1088 Z1L1086 = AMPP_FUNCTION(Z1_D_br_taken_waddr_partial[9], Z1_D_pc_plus_one[9], Z1_D_bht_data[1], Z1L1024); --Z1L1098 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[21]~1089 Z1L1098 = AMPP_FUNCTION(Z1L3007, Z1_D_pc_plus_one[21], Z1_D_bht_data[1], Z1L1024); --Z1L1093 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[16]~1090 Z1L1093 = AMPP_FUNCTION(Z1L2995, Z1_D_pc_plus_one[16], Z1_D_bht_data[1], Z1L1024); --Z1L1094 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[17]~1091 Z1L1094 = AMPP_FUNCTION(Z1L2997, Z1_D_pc_plus_one[17], Z1_D_bht_data[1], Z1L1024); --Z1L1092 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[15]~1092 Z1L1092 = AMPP_FUNCTION(Z1L2993, Z1_D_pc_plus_one[15], Z1_D_bht_data[1], Z1L1024); --Z1L1091 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[14]~1093 Z1L1091 = AMPP_FUNCTION(Z1L2991, Z1_D_pc_plus_one[14], Z1_D_bht_data[1], Z1L1024); --Z1L1088 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[11]~1094 Z1L1088 = AMPP_FUNCTION(Z1L2985, Z1_D_pc_plus_one[11], Z1_D_bht_data[1], Z1L1024); --Z1L1095 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[18]~1095 Z1L1095 = AMPP_FUNCTION(Z1L2999, Z1_D_pc_plus_one[18], Z1_D_bht_data[1], Z1L1024); --Z1L1096 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[19]~1096 Z1L1096 = AMPP_FUNCTION(Z1L3001, Z1_D_pc_plus_one[19], Z1_D_bht_data[1], Z1L1024); --Z1L1089 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[12]~1097 Z1L1089 = AMPP_FUNCTION(Z1L2987, Z1_D_pc_plus_one[12], Z1_D_bht_data[1], Z1L1024); --Z1L1087 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[10]~1098 Z1L1087 = AMPP_FUNCTION(Z1L2983, Z1_D_pc_plus_one[10], Z1_D_bht_data[1], Z1L1024); --Z1L1090 is system_0:u0|cpu_0:the_cpu_0|D_extra_pc[13]~1099 Z1L1090 = AMPP_FUNCTION(Z1L2989, Z1_D_pc_plus_one[13], Z1_D_bht_data[1], Z1L1024); --JC1_q_a[21] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[21] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[21] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[21], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L2014 is system_0:u0|cpu_0:the_cpu_0|F_iw[21]~1590 Z1L2014 = AMPP_FUNCTION(JC1_q_a[21], Z1L1994); --JC1_q_a[20] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[20] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[20] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[20], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L2013 is system_0:u0|cpu_0:the_cpu_0|F_iw[20]~1591 Z1L2013 = AMPP_FUNCTION(JC1_q_a[20], Z1L1994); --JC1_q_a[19] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[19] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[19] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[19], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L2012 is system_0:u0|cpu_0:the_cpu_0|F_iw[19]~1592 Z1L2012 = AMPP_FUNCTION(JC1_q_a[19], Z1L1994); --JC1_q_a[18] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[18] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[18] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[18], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --JC1_q_a[17] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[17] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[17] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[17], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --JC1_q_a[10] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[10] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[10] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[10], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --JC1_q_a[9] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[9] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[9] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[9], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --JC1_q_a[8] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[8] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[8] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[8], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L969 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[0]~99 Z1L969 = AMPP_FUNCTION(JC1_q_a[8], Z1L2939, GND); --Z1L970 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[0]~100 Z1L970 = AMPP_FUNCTION(JC1_q_a[8], Z1L2939); --Z1L972 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[1]~101 Z1L972 = AMPP_FUNCTION(JC1_q_a[9], Z1L2941, GND, Z1L970); --Z1L973 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[1]~102 Z1L973 = AMPP_FUNCTION(JC1_q_a[9], Z1L2941, Z1L970); --Z1L975 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[2]~103 Z1L975 = AMPP_FUNCTION(JC1_q_a[10], Z1L2943, GND, Z1L973); --Z1L976 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[2]~104 Z1L976 = AMPP_FUNCTION(JC1_q_a[10], Z1L2943, Z1L973); --Z1L978 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[3]~105 Z1L978 = AMPP_FUNCTION(JC1_q_a[11], Z1L2945, GND, Z1L976); --Z1L979 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[3]~106 Z1L979 = AMPP_FUNCTION(JC1_q_a[11], Z1L2945, Z1L976); --Z1L981 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[4]~107 Z1L981 = AMPP_FUNCTION(JC1_q_a[12], Z1L2947, GND, Z1L979); --Z1L982 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[4]~108 Z1L982 = AMPP_FUNCTION(JC1_q_a[12], Z1L2947, Z1L979); --Z1L984 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[5]~109 Z1L984 = AMPP_FUNCTION(JC1_q_a[13], Z1L2949, GND, Z1L982); --Z1L985 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[5]~110 Z1L985 = AMPP_FUNCTION(JC1_q_a[13], Z1L2949, Z1L982); --Z1L987 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[6]~111 Z1L987 = AMPP_FUNCTION(JC1_q_a[14], Z1L2951, GND, Z1L985); --Z1L988 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[6]~112 Z1L988 = AMPP_FUNCTION(JC1_q_a[14], Z1L2951, Z1L985); --Z1L990 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[7]~113 Z1L990 = AMPP_FUNCTION(JC1_q_a[15], Z1L2953, GND, Z1L988); --Z1L991 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[7]~114 Z1L991 = AMPP_FUNCTION(JC1_q_a[15], Z1L2953, Z1L988); --Z1L993 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[8]~115 Z1L993 = AMPP_FUNCTION(JC1_q_a[16], Z1L2955, GND, Z1L991); --Z1L994 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[8]~116 Z1L994 = AMPP_FUNCTION(JC1_q_a[16], Z1L2955, Z1L991); --Z1L996 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[9]~117 Z1L996 = AMPP_FUNCTION(JC1_q_a[17], Z1L2957, GND, Z1L994); --Z1L997 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[9]~118 Z1L997 = AMPP_FUNCTION(JC1_q_a[17], Z1L2957, Z1L994); --Z1L999 is system_0:u0|cpu_0:the_cpu_0|D_br_taken_waddr_partial[10]~119 Z1L999 = AMPP_FUNCTION(Z1L997); --Z1L2019 is system_0:u0|cpu_0:the_cpu_0|F_iw[26]~1593 Z1L2019 = AMPP_FUNCTION(JC1_q_a[26], Z1L1994); --Z1_E_ctrl_break is system_0:u0|cpu_0:the_cpu_0|E_ctrl_break Z1_E_ctrl_break = AMPP_FUNCTION(F1__clk1, Z1L1027, N1_data_out, Z1_A_stall); --Z1_E_ctrl_exception is system_0:u0|cpu_0:the_cpu_0|E_ctrl_exception Z1_E_ctrl_exception = AMPP_FUNCTION(F1__clk1, Z1L1035, N1_data_out, Z1_A_stall); --Z1L2423 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[20]~1460 Z1L2423 = AMPP_FUNCTION(Z1_E_extra_pc[20], Z1_E_ctrl_break, Z1_E_ctrl_exception); --Z1_E_ctrl_jmp_indirect is system_0:u0|cpu_0:the_cpu_0|E_ctrl_jmp_indirect Z1_E_ctrl_jmp_indirect = AMPP_FUNCTION(F1__clk1, Z1L1050, N1_data_out, Z1_A_stall); --Z1L2398 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[20]~91 Z1L2398 = AMPP_FUNCTION(Z1_E_src1[22], Z1L2423, Z1_E_ctrl_jmp_indirect); --Z1_E_pc[20] is system_0:u0|cpu_0:the_cpu_0|E_pc[20] Z1_E_pc[20] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[20], N1_data_out, Z1_A_stall); --Z1L1935 is system_0:u0|cpu_0:the_cpu_0|F_ctrl_ignore_dst~210 Z1L1935 = AMPP_FUNCTION(JC1_q_a[1], JC1_q_a[0], JC1_q_a[2], Z1L1994); --Z1L2017 is system_0:u0|cpu_0:the_cpu_0|F_iw[24]~1594 Z1L2017 = AMPP_FUNCTION(JC1_q_a[24], Z1L1994); --Z1L2015 is system_0:u0|cpu_0:the_cpu_0|F_iw[22]~1595 Z1L2015 = AMPP_FUNCTION(JC1_q_a[22], Z1L1994); --Z1L2018 is system_0:u0|cpu_0:the_cpu_0|F_iw[25]~1596 Z1L2018 = AMPP_FUNCTION(JC1_q_a[25], Z1L1994); --Z1L2016 is system_0:u0|cpu_0:the_cpu_0|F_iw[23]~1597 Z1L2016 = AMPP_FUNCTION(JC1_q_a[23], Z1L1994); --Z1L3027 is system_0:u0|cpu_0:the_cpu_0|comb~1 Z1L3027 = AMPP_FUNCTION(Z1_i_readdatavalid_d1, Z1_M_valid_from_E, Z1_M_ctrl_invalidate_i); --Z1_i_readdata_d1[27] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[27] Z1_i_readdata_d1[27] = AMPP_FUNCTION(F1__clk1, BB1L121, N1_data_out); --Z1_i_readdata_d1[31] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[31] Z1_i_readdata_d1[31] = AMPP_FUNCTION(F1__clk1, BB1L137, N1_data_out); --Z1_i_readdata_d1[28] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[28] Z1_i_readdata_d1[28] = AMPP_FUNCTION(F1__clk1, BB1L125, N1_data_out); --Z1_i_readdata_d1[30] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[30] Z1_i_readdata_d1[30] = AMPP_FUNCTION(F1__clk1, BB1L133, N1_data_out); --Z1_i_readdata_d1[29] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[29] Z1_i_readdata_d1[29] = AMPP_FUNCTION(F1__clk1, BB1L129, N1_data_out); --Z1_i_readdata_d1[2] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[2] Z1_i_readdata_d1[2] = AMPP_FUNCTION(F1__clk1, BB1L34, N1_data_out); --Z1_A_ienable_reg[3] is system_0:u0|cpu_0:the_cpu_0|A_ienable_reg[3] Z1_A_ienable_reg[3] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[3], N1_data_out, Z1L138); --P1_irq_mask[3] is system_0:u0|KEY:the_KEY|irq_mask[3] P1_irq_mask[3] = DFFEAS(Z1_d_writedata[3], F1__clk1, N1_data_out, , P1L2, , , , ); --P1_irq_mask[1] is system_0:u0|KEY:the_KEY|irq_mask[1] P1_irq_mask[1] = DFFEAS(Z1_d_writedata[1], F1__clk1, N1_data_out, , P1L2, , , , ); --P1_edge_capture[1] is system_0:u0|KEY:the_KEY|edge_capture[1] P1_edge_capture[1] = DFFEAS(P1L19, F1__clk1, N1_data_out, , , , , , ); --P1_edge_capture[3] is system_0:u0|KEY:the_KEY|edge_capture[3] P1_edge_capture[3] = DFFEAS(P1L20, F1__clk1, N1_data_out, , , , , , ); --Z1L182 is system_0:u0|cpu_0:the_cpu_0|A_ipending_reg_nxt[3]~144 Z1L182 = AMPP_FUNCTION(P1_irq_mask[3], P1_irq_mask[1], P1_edge_capture[1], P1_edge_capture[3]); --P1_irq_mask[2] is system_0:u0|KEY:the_KEY|irq_mask[2] P1_irq_mask[2] = DFFEAS(Z1_d_writedata[2], F1__clk1, N1_data_out, , P1L2, , , , ); --P1_irq_mask[0] is system_0:u0|KEY:the_KEY|irq_mask[0] P1_irq_mask[0] = DFFEAS(Z1_d_writedata[0], F1__clk1, N1_data_out, , P1L2, , , , ); --P1_edge_capture[0] is system_0:u0|KEY:the_KEY|edge_capture[0] P1_edge_capture[0] = DFFEAS(P1L21, F1__clk1, N1_data_out, , , , , , ); --P1_edge_capture[2] is system_0:u0|KEY:the_KEY|edge_capture[2] P1_edge_capture[2] = DFFEAS(P1L22, F1__clk1, N1_data_out, , , , , , ); --Z1L183 is system_0:u0|cpu_0:the_cpu_0|A_ipending_reg_nxt[3]~145 Z1L183 = AMPP_FUNCTION(P1_irq_mask[2], P1_irq_mask[0], P1_edge_capture[0], P1_edge_capture[2]); --UC1_oci_ienable[3] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[3] UC1_oci_ienable[3] = AMPP_FUNCTION(F1__clk1, UC1L9, N1_data_out, UC1L16); --Z1L184 is system_0:u0|cpu_0:the_cpu_0|A_ipending_reg_nxt[3]~146 Z1L184 = AMPP_FUNCTION(Z1_A_ienable_reg[3], Z1L182, Z1L183, UC1_oci_ienable[3]); --SD1_irq_reg is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|irq_reg SD1_irq_reg = DFFEAS(SD1L138, F1__clk1, N1_data_out, , , , , , ); --Z1_A_ienable_reg[2] is system_0:u0|cpu_0:the_cpu_0|A_ienable_reg[2] Z1_A_ienable_reg[2] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[2], N1_data_out, Z1L138); --UC1_oci_ienable[2] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[2] UC1_oci_ienable[2] = AMPP_FUNCTION(F1__clk1, UC1L7, N1_data_out, UC1L16); --Z1L181 is system_0:u0|cpu_0:the_cpu_0|A_ipending_reg_nxt[2]~147 Z1L181 = AMPP_FUNCTION(SD1_irq_reg, Z1_A_ienable_reg[2], UC1_oci_ienable[2]); --LE1_irq is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|irq LE1_irq = DFFEAS(LE1_qualified_irq, F1__clk1, N1_data_out, , , , , , ); --Z1_A_ienable_reg[1] is system_0:u0|cpu_0:the_cpu_0|A_ienable_reg[1] Z1_A_ienable_reg[1] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[1], N1_data_out, Z1L138); --UC1_oci_ienable[1] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[1] UC1_oci_ienable[1] = AMPP_FUNCTION(F1__clk1, UC1L5, N1_data_out, UC1L16); --Z1L180 is system_0:u0|cpu_0:the_cpu_0|A_ipending_reg_nxt[1]~148 Z1L180 = AMPP_FUNCTION(LE1_irq, Z1_A_ienable_reg[1], UC1_oci_ienable[1]); --Z1_A_ienable_reg[0] is system_0:u0|cpu_0:the_cpu_0|A_ienable_reg[0] Z1_A_ienable_reg[0] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[0], N1_data_out, Z1L138); --FB1_ien_AF is system_0:u0|jtag_uart_0:the_jtag_uart_0|ien_AF FB1_ien_AF = DFFEAS(Z1_d_writedata[0], F1__clk1, N1_data_out, , FB1L49, , , , ); --FB1_fifo_AF is system_0:u0|jtag_uart_0:the_jtag_uart_0|fifo_AF FB1_fifo_AF = DFFEAS(FB1L3, F1__clk1, N1_data_out, , , , , , ); --FB1_pause_irq is system_0:u0|jtag_uart_0:the_jtag_uart_0|pause_irq FB1_pause_irq = DFFEAS(FB1L52, F1__clk1, N1_data_out, , , , , , ); --FB1L40 is system_0:u0|jtag_uart_0:the_jtag_uart_0|av_readdata[8]~130 FB1L40 = FB1_ien_AF & (FB1_fifo_AF # FB1_pause_irq); --FB1_fifo_AE is system_0:u0|jtag_uart_0:the_jtag_uart_0|fifo_AE FB1_fifo_AE = DFFEAS(FB1L5, F1__clk1, N1_data_out, , , , , , ); --FB1_ien_AE is system_0:u0|jtag_uart_0:the_jtag_uart_0|ien_AE FB1_ien_AE = DFFEAS(Z1_d_writedata[1], F1__clk1, N1_data_out, , FB1L49, , , , ); --Z1L178 is system_0:u0|cpu_0:the_cpu_0|A_ipending_reg_nxt[0]~149 Z1L178 = AMPP_FUNCTION(FB1_fifo_AE, FB1_ien_AE); --UC1_oci_ienable[0] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[0] UC1_oci_ienable[0] = AMPP_FUNCTION(F1__clk1, UC1L3, N1_data_out, UC1L16); --Z1L179 is system_0:u0|cpu_0:the_cpu_0|A_ipending_reg_nxt[0]~150 Z1L179 = AMPP_FUNCTION(Z1_A_ienable_reg[0], FB1L40, Z1L178, UC1_oci_ienable[0]); --Z1_M_iw[6] is system_0:u0|cpu_0:the_cpu_0|M_iw[6] Z1_M_iw[6] = AMPP_FUNCTION(F1__clk1, Z1_E_iw[6], N1_data_out, Z1_A_stall); --Z1_M_iw[7] is system_0:u0|cpu_0:the_cpu_0|M_iw[7] Z1_M_iw[7] = AMPP_FUNCTION(F1__clk1, Z1_E_iw[7], N1_data_out, Z1_A_stall); --Z1_M_ctrl_wrctl_inst is system_0:u0|cpu_0:the_cpu_0|M_ctrl_wrctl_inst Z1_M_ctrl_wrctl_inst = AMPP_FUNCTION(F1__clk1, Z1_E_op_wrctl, N1_data_out, Z1_A_stall); --Z1_M_iw[8] is system_0:u0|cpu_0:the_cpu_0|M_iw[8] Z1_M_iw[8] = AMPP_FUNCTION(F1__clk1, Z1_E_iw[8], N1_data_out, Z1_A_stall); --Z1L2670 is system_0:u0|cpu_0:the_cpu_0|M_wrctl_bstatus~10 Z1L2670 = AMPP_FUNCTION(Z1_M_iw[7], Z1_M_ctrl_wrctl_inst, Z1_M_iw[8]); --Z1L139 is system_0:u0|cpu_0:the_cpu_0|A_ienable_reg_nxt~0 Z1L139 = AMPP_FUNCTION(Z1_M_valid_from_E, Z1_M_iw[6], Z1L2670); --Z1_A_estatus_reg is system_0:u0|cpu_0:the_cpu_0|A_estatus_reg Z1_A_estatus_reg = AMPP_FUNCTION(F1__clk1, Z1L132, N1_data_out, Z1L3020); --Z1L837 is system_0:u0|cpu_0:the_cpu_0|A_status_reg_pie_inst_nxt~450 Z1L837 = AMPP_FUNCTION(Z1L2332, Z1_A_estatus_reg, Z1_M_iw[14]); --Z1_A_bstatus_reg is system_0:u0|cpu_0:the_cpu_0|A_bstatus_reg Z1_A_bstatus_reg = AMPP_FUNCTION(F1__clk1, Z1L3, N1_data_out, Z1L3020); --Z1L2671 is system_0:u0|cpu_0:the_cpu_0|M_wrctl_estatus~9 Z1L2671 = AMPP_FUNCTION(Z1_M_ctrl_wrctl_inst, Z1_M_iw[7], Z1_M_iw[8]); --Z1L838 is system_0:u0|cpu_0:the_cpu_0|A_status_reg_pie_inst_nxt~451 Z1L838 = AMPP_FUNCTION(Z1_A_status_reg_pie, Z1_M_alu_result[0], Z1L2671, Z1_M_iw[6]); --Z1L839 is system_0:u0|cpu_0:the_cpu_0|A_status_reg_pie_inst_nxt~452 Z1L839 = AMPP_FUNCTION(Z1_M_iw[14], Z1_A_bstatus_reg, Z1L838, Z1L2332); --Z1_M_ctrl_exception is system_0:u0|cpu_0:the_cpu_0|M_ctrl_exception Z1_M_ctrl_exception = AMPP_FUNCTION(F1__clk1, Z1_E_ctrl_exception, N1_data_out, Z1_A_stall); --Z1L840 is system_0:u0|cpu_0:the_cpu_0|A_status_reg_pie_inst_nxt~453 Z1L840 = AMPP_FUNCTION(Z1L837, Z1L839, Z1_M_ctrl_break, Z1_M_ctrl_exception); --Z1_i_readdata_d1[1] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[1] Z1_i_readdata_d1[1] = AMPP_FUNCTION(F1__clk1, BB1L31, N1_data_out); --Z1_i_readdata_d1[4] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[4] Z1_i_readdata_d1[4] = AMPP_FUNCTION(F1__clk1, BB1L40, N1_data_out); --Z1_i_readdata_d1[3] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[3] Z1_i_readdata_d1[3] = AMPP_FUNCTION(F1__clk1, BB1L37, N1_data_out); --Z1_i_readdata_d1[5] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[5] Z1_i_readdata_d1[5] = AMPP_FUNCTION(F1__clk1, BB1L43, N1_data_out); --Z1_i_readdata_d1[22] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[22] Z1_i_readdata_d1[22] = AMPP_FUNCTION(F1__clk1, BB1L101, N1_data_out); --Z1_i_readdata_d1[26] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[26] Z1_i_readdata_d1[26] = AMPP_FUNCTION(F1__clk1, BB1L117, N1_data_out); --Z1_i_readdata_d1[23] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[23] Z1_i_readdata_d1[23] = AMPP_FUNCTION(F1__clk1, BB1L105, N1_data_out); --Z1_i_readdata_d1[25] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[25] Z1_i_readdata_d1[25] = AMPP_FUNCTION(F1__clk1, BB1L113, N1_data_out); --Z1_i_readdata_d1[24] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[24] Z1_i_readdata_d1[24] = AMPP_FUNCTION(F1__clk1, BB1L109, N1_data_out); --Z1_i_readdata_d1[0] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[0] Z1_i_readdata_d1[0] = AMPP_FUNCTION(F1__clk1, BB1L28, N1_data_out); --Z1_M_ctrl_br_cond is system_0:u0|cpu_0:the_cpu_0|M_ctrl_br_cond Z1_M_ctrl_br_cond = AMPP_FUNCTION(F1__clk1, Z1_E_ctrl_br_cond, N1_data_out, Z1_A_stall); --Z1_M_bht_wr_en is system_0:u0|cpu_0:the_cpu_0|M_bht_wr_en Z1_M_bht_wr_en = AMPP_FUNCTION(Z1_M_valid_from_E, Z1_M_ctrl_br_cond); --Z1_M_br_cond_taken_history[0] is system_0:u0|cpu_0:the_cpu_0|M_br_cond_taken_history[0] Z1_M_br_cond_taken_history[0] = AMPP_FUNCTION(F1__clk1, Z1L1501, N1_data_out, Z1L2156); --Z1_F_bht_ptr_nxt[0] is system_0:u0|cpu_0:the_cpu_0|F_bht_ptr_nxt[0] Z1_F_bht_ptr_nxt[0] = AMPP_FUNCTION(Z1_M_pipe_flush, Z1_M_pipe_flush_waddr[0], Z1L1938, Z1_M_br_cond_taken_history[0]); --Z1_M_br_cond_taken_history[1] is system_0:u0|cpu_0:the_cpu_0|M_br_cond_taken_history[1] Z1_M_br_cond_taken_history[1] = AMPP_FUNCTION(F1__clk1, Z1_M_br_cond_taken_history[0], N1_data_out, Z1L2156); --Z1_F_bht_ptr_nxt[1] is system_0:u0|cpu_0:the_cpu_0|F_bht_ptr_nxt[1] Z1_F_bht_ptr_nxt[1] = AMPP_FUNCTION(Z1_M_pipe_flush, Z1_M_pipe_flush_waddr[1], Z1L1942, Z1_M_br_cond_taken_history[1]); --Z1_M_br_cond_taken_history[2] is system_0:u0|cpu_0:the_cpu_0|M_br_cond_taken_history[2] Z1_M_br_cond_taken_history[2] = AMPP_FUNCTION(F1__clk1, Z1_M_br_cond_taken_history[1], N1_data_out, Z1L2156); --Z1_F_bht_ptr_nxt[2] is system_0:u0|cpu_0:the_cpu_0|F_bht_ptr_nxt[2] Z1_F_bht_ptr_nxt[2] = AMPP_FUNCTION(Z1_M_pipe_flush, Z1_M_pipe_flush_waddr[2], Z1L1946, Z1_M_br_cond_taken_history[2]); --Z1_M_br_cond_taken_history[3] is system_0:u0|cpu_0:the_cpu_0|M_br_cond_taken_history[3] Z1_M_br_cond_taken_history[3] = AMPP_FUNCTION(F1__clk1, Z1_M_br_cond_taken_history[2], N1_data_out, Z1L2156); --Z1_F_bht_ptr_nxt[3] is system_0:u0|cpu_0:the_cpu_0|F_bht_ptr_nxt[3] Z1_F_bht_ptr_nxt[3] = AMPP_FUNCTION(Z1_M_pipe_flush, Z1_M_pipe_flush_waddr[3], Z1L1958, Z1_M_br_cond_taken_history[3]); --Z1_M_br_cond_taken_history[4] is system_0:u0|cpu_0:the_cpu_0|M_br_cond_taken_history[4] Z1_M_br_cond_taken_history[4] = AMPP_FUNCTION(F1__clk1, Z1_M_br_cond_taken_history[3], N1_data_out, Z1L2156); --Z1_F_bht_ptr_nxt[4] is system_0:u0|cpu_0:the_cpu_0|F_bht_ptr_nxt[4] Z1_F_bht_ptr_nxt[4] = AMPP_FUNCTION(Z1_M_pipe_flush, Z1_M_pipe_flush_waddr[4], Z1L1962, Z1_M_br_cond_taken_history[4]); --Z1_M_br_cond_taken_history[5] is system_0:u0|cpu_0:the_cpu_0|M_br_cond_taken_history[5] Z1_M_br_cond_taken_history[5] = AMPP_FUNCTION(F1__clk1, Z1_M_br_cond_taken_history[4], N1_data_out, Z1L2156); --Z1_F_bht_ptr_nxt[5] is system_0:u0|cpu_0:the_cpu_0|F_bht_ptr_nxt[5] Z1_F_bht_ptr_nxt[5] = AMPP_FUNCTION(Z1_M_pipe_flush, Z1_M_pipe_flush_waddr[5], Z1L1966, Z1_M_br_cond_taken_history[5]); --Z1_M_br_cond_taken_history[6] is system_0:u0|cpu_0:the_cpu_0|M_br_cond_taken_history[6] Z1_M_br_cond_taken_history[6] = AMPP_FUNCTION(F1__clk1, Z1_M_br_cond_taken_history[5], N1_data_out, Z1L2156); --Z1_F_bht_ptr_nxt[6] is system_0:u0|cpu_0:the_cpu_0|F_bht_ptr_nxt[6] Z1_F_bht_ptr_nxt[6] = AMPP_FUNCTION(Z1_M_pipe_flush, Z1_M_pipe_flush_waddr[6], Z1L1970, Z1_M_br_cond_taken_history[6]); --Z1_M_br_cond_taken_history[7] is system_0:u0|cpu_0:the_cpu_0|M_br_cond_taken_history[7] Z1_M_br_cond_taken_history[7] = AMPP_FUNCTION(F1__clk1, Z1_M_br_cond_taken_history[6], N1_data_out, Z1L2156); --Z1_F_bht_ptr_nxt[7] is system_0:u0|cpu_0:the_cpu_0|F_bht_ptr_nxt[7] Z1_F_bht_ptr_nxt[7] = AMPP_FUNCTION(Z1_M_pipe_flush, Z1_M_pipe_flush_waddr[7], Z1L1975, Z1_M_br_cond_taken_history[7]); --Z1_M_bht_data[1] is system_0:u0|cpu_0:the_cpu_0|M_bht_data[1] Z1_M_bht_data[1] = AMPP_FUNCTION(F1__clk1, Z1_E_bht_data[1], N1_data_out, Z1_A_stall); --Z1_M_bht_data[0] is system_0:u0|cpu_0:the_cpu_0|M_bht_data[0] Z1_M_bht_data[0] = AMPP_FUNCTION(F1__clk1, Z1_E_bht_data[0], N1_data_out, Z1_A_stall); --Z1_M_br_mispredict is system_0:u0|cpu_0:the_cpu_0|M_br_mispredict Z1_M_br_mispredict = AMPP_FUNCTION(F1__clk1, Z1_E_br_mispredict, N1_data_out, Z1_A_stall); --Z1L2151 is system_0:u0|cpu_0:the_cpu_0|M_bht_wr_data[1]~78 Z1L2151 = AMPP_FUNCTION(Z1_M_bht_data[1], Z1_M_bht_data[0], Z1_M_valid_from_E, Z1_M_br_mispredict); --Z1_M_bht_ptr[0] is system_0:u0|cpu_0:the_cpu_0|M_bht_ptr[0] Z1_M_bht_ptr[0] = AMPP_FUNCTION(F1__clk1, Z1_E_bht_ptr[0], N1_data_out, Z1_A_stall); --Z1_M_bht_ptr[1] is system_0:u0|cpu_0:the_cpu_0|M_bht_ptr[1] Z1_M_bht_ptr[1] = AMPP_FUNCTION(F1__clk1, Z1_E_bht_ptr[1], N1_data_out, Z1_A_stall); --Z1_M_bht_ptr[2] is system_0:u0|cpu_0:the_cpu_0|M_bht_ptr[2] Z1_M_bht_ptr[2] = AMPP_FUNCTION(F1__clk1, Z1_E_bht_ptr[2], N1_data_out, Z1_A_stall); --Z1_M_bht_ptr[3] is system_0:u0|cpu_0:the_cpu_0|M_bht_ptr[3] Z1_M_bht_ptr[3] = AMPP_FUNCTION(F1__clk1, Z1_E_bht_ptr[3], N1_data_out, Z1_A_stall); --Z1_M_bht_ptr[4] is system_0:u0|cpu_0:the_cpu_0|M_bht_ptr[4] Z1_M_bht_ptr[4] = AMPP_FUNCTION(F1__clk1, Z1_E_bht_ptr[4], N1_data_out, Z1_A_stall); --Z1_M_bht_ptr[5] is system_0:u0|cpu_0:the_cpu_0|M_bht_ptr[5] Z1_M_bht_ptr[5] = AMPP_FUNCTION(F1__clk1, Z1_E_bht_ptr[5], N1_data_out, Z1_A_stall); --Z1_M_bht_ptr[6] is system_0:u0|cpu_0:the_cpu_0|M_bht_ptr[6] Z1_M_bht_ptr[6] = AMPP_FUNCTION(F1__clk1, Z1_E_bht_ptr[6], N1_data_out, Z1_A_stall); --Z1_M_bht_ptr[7] is system_0:u0|cpu_0:the_cpu_0|M_bht_ptr[7] Z1_M_bht_ptr[7] = AMPP_FUNCTION(F1__clk1, Z1_E_bht_ptr[7], N1_data_out, Z1_A_stall); --Z1_i_readdata_d1[11] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[11] Z1_i_readdata_d1[11] = AMPP_FUNCTION(F1__clk1, BB1L61, N1_data_out); --Z1_i_readdata_d1[15] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[15] Z1_i_readdata_d1[15] = AMPP_FUNCTION(F1__clk1, BB1L73, N1_data_out); --Z1_i_readdata_d1[13] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[13] Z1_i_readdata_d1[13] = AMPP_FUNCTION(F1__clk1, BB1L67, N1_data_out); --Z1_i_readdata_d1[14] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[14] Z1_i_readdata_d1[14] = AMPP_FUNCTION(F1__clk1, BB1L70, N1_data_out); --Z1_i_readdata_d1[16] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[16] Z1_i_readdata_d1[16] = AMPP_FUNCTION(F1__clk1, BB1L77, N1_data_out); --Z1_i_readdata_d1[12] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[12] Z1_i_readdata_d1[12] = AMPP_FUNCTION(F1__clk1, BB1L64, N1_data_out); --Z1L1523 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_invalidate_i~116 Z1L1523 = AMPP_FUNCTION(Z1L1650, Z1_E_iw[16], Z1_E_iw[11], Z1_E_iw[13]); --Z1L1524 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_invalidate_i~117 Z1L1524 = AMPP_FUNCTION(Z1_E_iw[14], Z1L1523, Z1_E_iw[15], Z1_E_iw[12]); --Z1L2002 is system_0:u0|cpu_0:the_cpu_0|F_iw[9]~1598 Z1L2002 = AMPP_FUNCTION(JC1_q_a[9], Z1L1994); --Z1L2406 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[3]~1461 Z1L2406 = AMPP_FUNCTION(Z1_E_extra_pc[3], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2347 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[3]~71 Z1L2347 = AMPP_FUNCTION(Z1L2406, Z1_E_src1[5], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[3] is system_0:u0|cpu_0:the_cpu_0|E_pc[3] Z1_E_pc[3] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[3], N1_data_out, Z1_A_stall); --Z1L2003 is system_0:u0|cpu_0:the_cpu_0|F_iw[10]~1599 Z1L2003 = AMPP_FUNCTION(JC1_q_a[10], Z1L1994); --Z1L2407 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[4]~1462 Z1L2407 = AMPP_FUNCTION(Z1_E_extra_pc[4], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2350 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[4]~72 Z1L2350 = AMPP_FUNCTION(Z1L2407, Z1_E_src1[6], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[4] is system_0:u0|cpu_0:the_cpu_0|E_pc[4] Z1_E_pc[4] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[4], N1_data_out, Z1_A_stall); --Z1L2408 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[5]~1463 Z1L2408 = AMPP_FUNCTION(Z1_E_extra_pc[5], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2353 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[5]~73 Z1L2353 = AMPP_FUNCTION(Z1L2408, Z1_E_src1[7], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[5] is system_0:u0|cpu_0:the_cpu_0|E_pc[5] Z1_E_pc[5] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[5], N1_data_out, Z1_A_stall); --Z1L2409 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[6]~1464 Z1L2409 = AMPP_FUNCTION(Z1_E_extra_pc[6], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2356 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[6]~74 Z1L2356 = AMPP_FUNCTION(Z1L2409, Z1_E_src1[8], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[6] is system_0:u0|cpu_0:the_cpu_0|E_pc[6] Z1_E_pc[6] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[6], N1_data_out, Z1_A_stall); --Z1L2410 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[7]~1465 Z1L2410 = AMPP_FUNCTION(Z1_E_extra_pc[7], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2359 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[7]~75 Z1L2359 = AMPP_FUNCTION(Z1L2410, Z1_E_src1[9], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[7] is system_0:u0|cpu_0:the_cpu_0|E_pc[7] Z1_E_pc[7] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[7], N1_data_out, Z1_A_stall); --Z1L2411 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[8]~1466 Z1L2411 = AMPP_FUNCTION(Z1_E_extra_pc[8], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2362 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[8]~76 Z1L2362 = AMPP_FUNCTION(Z1L2411, Z1_E_src1[10], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[8] is system_0:u0|cpu_0:the_cpu_0|E_pc[8] Z1_E_pc[8] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[8], N1_data_out, Z1_A_stall); --Z1L2412 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[9]~1467 Z1L2412 = AMPP_FUNCTION(Z1_E_extra_pc[9], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2365 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[9]~77 Z1L2365 = AMPP_FUNCTION(Z1L2412, Z1_E_src1[11], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[9] is system_0:u0|cpu_0:the_cpu_0|E_pc[9] Z1_E_pc[9] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[9], N1_data_out, Z1_A_stall); --Z1L2413 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[10]~1468 Z1L2413 = AMPP_FUNCTION(Z1_E_extra_pc[10], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2368 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[10]~81 Z1L2368 = AMPP_FUNCTION(Z1L2413, Z1_E_src1[12], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[10] is system_0:u0|cpu_0:the_cpu_0|E_pc[10] Z1_E_pc[10] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[10], N1_data_out, Z1_A_stall); --Z1L2417 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[14]~1469 Z1L2417 = AMPP_FUNCTION(Z1_E_extra_pc[14], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2380 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[14]~85 Z1L2380 = AMPP_FUNCTION(Z1L2417, Z1_E_src1[16], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[14] is system_0:u0|cpu_0:the_cpu_0|E_pc[14] Z1_E_pc[14] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[14], N1_data_out, Z1_A_stall); --Z1L2415 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[12]~1470 Z1L2415 = AMPP_FUNCTION(Z1_E_extra_pc[12], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2374 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[12]~83 Z1L2374 = AMPP_FUNCTION(Z1L2415, Z1_E_src1[14], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[12] is system_0:u0|cpu_0:the_cpu_0|E_pc[12] Z1_E_pc[12] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[12], N1_data_out, Z1_A_stall); --Z1L2419 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[16]~1471 Z1L2419 = AMPP_FUNCTION(Z1_E_extra_pc[16], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2386 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[16]~87 Z1L2386 = AMPP_FUNCTION(Z1L2419, Z1_E_src1[18], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[16] is system_0:u0|cpu_0:the_cpu_0|E_pc[16] Z1_E_pc[16] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[16], N1_data_out, Z1_A_stall); --Z1L2020 is system_0:u0|cpu_0:the_cpu_0|F_iw[27]~1600 Z1L2020 = AMPP_FUNCTION(JC1_q_a[27], Z1L1994); --Z1L2424 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[21]~1472 Z1L2424 = AMPP_FUNCTION(Z1_E_ctrl_exception, Z1_E_extra_pc[21], Z1_E_ctrl_break); --Z1L2401 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[21]~92 Z1L2401 = AMPP_FUNCTION(Z1_E_src1[23], Z1L2424, Z1_E_ctrl_jmp_indirect); --Z1_E_pc[21] is system_0:u0|cpu_0:the_cpu_0|E_pc[21] Z1_E_pc[21] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[21], N1_data_out, Z1_A_stall); --Z1L2414 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[11]~1473 Z1L2414 = AMPP_FUNCTION(Z1_E_extra_pc[11], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2371 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[11]~82 Z1L2371 = AMPP_FUNCTION(Z1L2414, Z1_E_src1[13], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[11] is system_0:u0|cpu_0:the_cpu_0|E_pc[11] Z1_E_pc[11] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[11], N1_data_out, Z1_A_stall); --Z1L2418 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[15]~1474 Z1L2418 = AMPP_FUNCTION(Z1_E_extra_pc[15], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2383 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[15]~86 Z1L2383 = AMPP_FUNCTION(Z1L2418, Z1_E_src1[17], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[15] is system_0:u0|cpu_0:the_cpu_0|E_pc[15] Z1_E_pc[15] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[15], N1_data_out, Z1_A_stall); --Z1L2416 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[13]~1475 Z1L2416 = AMPP_FUNCTION(Z1_E_extra_pc[13], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2377 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[13]~84 Z1L2377 = AMPP_FUNCTION(Z1L2416, Z1_E_src1[15], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[13] is system_0:u0|cpu_0:the_cpu_0|E_pc[13] Z1_E_pc[13] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[13], N1_data_out, Z1_A_stall); --Z1L2422 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[19]~1476 Z1L2422 = AMPP_FUNCTION(Z1_E_extra_pc[19], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2395 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[19]~90 Z1L2395 = AMPP_FUNCTION(Z1L2422, Z1_E_src1[21], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[19] is system_0:u0|cpu_0:the_cpu_0|E_pc[19] Z1_E_pc[19] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[19], N1_data_out, Z1_A_stall); --Z1L3353 is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits_nxt[5]~966 Z1L3353 = AMPP_FUNCTION(Z1L3306, Z1L3304, Z1L3305); --Z1L3354 is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits_nxt[5]~967 Z1L3354 = AMPP_FUNCTION(Z1L3353, Z1L1099, Z1_ic_fill_valid_bits[5], Z1L3376); --Z1_ic_fill_valid_bits_en is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits_en Z1_ic_fill_valid_bits_en = AMPP_FUNCTION(Z1_i_readdatavalid_d1, Z1_M_valid_from_E, Z1_M_ctrl_invalidate_i, Z1L1099); --JC1_q_a[6] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[6] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[6] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[6], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L1999 is system_0:u0|cpu_0:the_cpu_0|F_iw[6]~1601 Z1L1999 = AMPP_FUNCTION(JC1_q_a[6], Z1L1994); --Z1L2403 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[0]~1477 Z1L2403 = AMPP_FUNCTION(Z1_E_extra_pc[0], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2338 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[0]~79 Z1L2338 = AMPP_FUNCTION(Z1L2403, Z1_E_src1[2], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[0] is system_0:u0|cpu_0:the_cpu_0|E_pc[0] Z1_E_pc[0] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[0], N1_data_out, Z1_A_stall); --Z1L3355 is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits_nxt[6]~968 Z1L3355 = AMPP_FUNCTION(Z1L3306, Z1L3305, Z1L3304); --Z1L3356 is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits_nxt[6]~969 Z1L3356 = AMPP_FUNCTION(Z1L3355, Z1L1099, Z1_ic_fill_valid_bits[6], Z1L3376); --JC1_q_a[7] is system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sr41:auto_generated|altsyncram_f9c1:altsyncram1|q_a[7] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1 --Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered JC1_q_a[7] = AMPP_FUNCTION(VCC, Z1L3027, F1__clk1, F1__clk1, Z1_F_stall, Z1L3027, GND, Z1L1939, Z1L1943, Z1L1947, Z1L1959, Z1L1963, Z1L1967, Z1L1971, Z1L1976, Z1L1981, Z1L1985, Z1_i_readdata_d1[7], Z1_ic_fill_dp_offset[0], Z1_ic_fill_dp_offset[1], Z1_ic_fill_dp_offset[2], Z1_ic_fill_line[0], Z1_ic_fill_line[1], Z1_ic_fill_line[2], Z1_ic_fill_line[3], Z1_ic_fill_line[4], Z1_ic_fill_line[5], Z1_ic_fill_line[6]); --Z1L2000 is system_0:u0|cpu_0:the_cpu_0|F_iw[7]~1602 Z1L2000 = AMPP_FUNCTION(JC1_q_a[7], Z1L1994); --Z1L2404 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[1]~1478 Z1L2404 = AMPP_FUNCTION(Z1_E_extra_pc[1], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2341 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[1]~78 Z1L2341 = AMPP_FUNCTION(Z1L2404, Z1_E_src1[3], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[1] is system_0:u0|cpu_0:the_cpu_0|E_pc[1] Z1_E_pc[1] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[1], N1_data_out, Z1_A_stall); --Z1L3351 is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits_nxt[4]~970 Z1L3351 = AMPP_FUNCTION(Z1L3306, Z1L3304, Z1L3305); --Z1L3352 is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits_nxt[4]~971 Z1L3352 = AMPP_FUNCTION(Z1L3351, Z1L1099, Z1_ic_fill_valid_bits[4], Z1L3376); --Z1L3357 is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits_nxt[7]~972 Z1L3357 = AMPP_FUNCTION(Z1L3306, Z1L3304, Z1L3305); --Z1L3358 is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits_nxt[7]~973 Z1L3358 = AMPP_FUNCTION(Z1L3357, Z1L1099, Z1_ic_fill_valid_bits[7], Z1L3376); --Z1L3347 is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits_nxt[2]~974 Z1L3347 = AMPP_FUNCTION(Z1L3305, Z1L3306, Z1L3304); --Z1L3348 is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits_nxt[2]~975 Z1L3348 = AMPP_FUNCTION(Z1L3347, Z1L1099, Z1_ic_fill_valid_bits[2], Z1L3376); --Z1L3345 is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits_nxt[1]~976 Z1L3345 = AMPP_FUNCTION(Z1L3304, Z1L3306, Z1L3305); --Z1L3346 is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits_nxt[1]~977 Z1L3346 = AMPP_FUNCTION(Z1L3345, Z1L1099, Z1_ic_fill_valid_bits[1], Z1L3376); --Z1L3343 is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits_nxt[0]~978 Z1L3343 = AMPP_FUNCTION(Z1L3306, Z1L3304, Z1L3305); --Z1L3344 is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits_nxt[0]~979 Z1L3344 = AMPP_FUNCTION(Z1L3343, Z1L1099, Z1_ic_fill_valid_bits[0], Z1L3376); --Z1L3349 is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits_nxt[3]~980 Z1L3349 = AMPP_FUNCTION(Z1L3304, Z1L3305, Z1L3306); --Z1L3350 is system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits_nxt[3]~981 Z1L3350 = AMPP_FUNCTION(Z1L3349, Z1L1099, Z1_ic_fill_valid_bits[3], Z1L3376); --Z1L2001 is system_0:u0|cpu_0:the_cpu_0|F_iw[8]~1603 Z1L2001 = AMPP_FUNCTION(JC1_q_a[8], Z1L1994); --Z1L2405 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[2]~1479 Z1L2405 = AMPP_FUNCTION(Z1_E_extra_pc[2], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2344 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[2]~80 Z1L2344 = AMPP_FUNCTION(Z1L2405, Z1_E_src1[4], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[2] is system_0:u0|cpu_0:the_cpu_0|E_pc[2] Z1_E_pc[2] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[2], N1_data_out, Z1_A_stall); --Z1L2420 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[17]~1480 Z1L2420 = AMPP_FUNCTION(Z1_E_extra_pc[17], Z1_E_ctrl_break, Z1_E_ctrl_exception); --Z1L2389 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[17]~88 Z1L2389 = AMPP_FUNCTION(Z1_E_src1[19], Z1L2420, Z1_E_ctrl_jmp_indirect); --Z1_E_pc[17] is system_0:u0|cpu_0:the_cpu_0|E_pc[17] Z1_E_pc[17] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[17], N1_data_out, Z1_A_stall); --Z1L2421 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr_nxt[18]~1481 Z1L2421 = AMPP_FUNCTION(Z1_E_extra_pc[18], Z1_E_ctrl_exception, Z1_E_ctrl_break); --Z1L2392 is system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[18]~89 Z1L2392 = AMPP_FUNCTION(Z1L2421, Z1_E_src1[20], Z1_E_ctrl_jmp_indirect); --Z1_E_pc[18] is system_0:u0|cpu_0:the_cpu_0|E_pc[18] Z1_E_pc[18] = AMPP_FUNCTION(F1__clk1, Z1_D_pc[18], N1_data_out, Z1_A_stall); --BB1L25 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_read_but_no_slave_selected~56 BB1L25 = !LB1L12 & !MB1L40 & !JB1L16 & !EB1L7; --BB1L24 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_read_but_no_slave_selected~0 BB1L24 = BB1L250 & BB1L25 & !CB1L5; --MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] = DFFEAS(MB1L47, F1__clk1, N1_data_out, , , , , , ); --BB1L3 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|add~279 BB1L3 = BB1_cpu_0_instruction_master_dbs_rdv_counter[0] $ (!JE1_stage_0 # !HB1_za_valid # !JE1_fifo_contains_ones_n); --Z1_A_wr_dst_reg_from_M is system_0:u0|cpu_0:the_cpu_0|A_wr_dst_reg_from_M Z1_A_wr_dst_reg_from_M = AMPP_FUNCTION(F1__clk1, Z1L952, N1_data_out, Z1_A_stall); --Z1_A_dst_regnum_from_M[0] is system_0:u0|cpu_0:the_cpu_0|A_dst_regnum_from_M[0] Z1_A_dst_regnum_from_M[0] = AMPP_FUNCTION(F1__clk1, Z1_M_dst_regnum[0], N1_data_out, Z1_A_stall); --Z1_A_dst_regnum_from_M[1] is system_0:u0|cpu_0:the_cpu_0|A_dst_regnum_from_M[1] Z1_A_dst_regnum_from_M[1] = AMPP_FUNCTION(F1__clk1, Z1_M_dst_regnum[1], N1_data_out, Z1_A_stall); --Z1_A_dst_regnum_from_M[2] is system_0:u0|cpu_0:the_cpu_0|A_dst_regnum_from_M[2] Z1_A_dst_regnum_from_M[2] = AMPP_FUNCTION(F1__clk1, Z1_M_dst_regnum[2], N1_data_out, Z1_A_stall); --Z1_A_dst_regnum_from_M[3] is system_0:u0|cpu_0:the_cpu_0|A_dst_regnum_from_M[3] Z1_A_dst_regnum_from_M[3] = AMPP_FUNCTION(F1__clk1, Z1_M_dst_regnum[3], N1_data_out, Z1_A_stall); --Z1_A_dst_regnum_from_M[4] is system_0:u0|cpu_0:the_cpu_0|A_dst_regnum_from_M[4] Z1_A_dst_regnum_from_M[4] = AMPP_FUNCTION(F1__clk1, Z1_M_dst_regnum[4], N1_data_out, Z1_A_stall); --Z1L2030 is system_0:u0|cpu_0:the_cpu_0|F_iw_b_rf[0]~280 Z1L2030 = AMPP_FUNCTION(Z1_D_iw[22], JC1_q_a[22], Z1_F_stall); --Z1L2031 is system_0:u0|cpu_0:the_cpu_0|F_iw_b_rf[1]~281 Z1L2031 = AMPP_FUNCTION(Z1_D_iw[23], JC1_q_a[23], Z1_F_stall); --Z1L2032 is system_0:u0|cpu_0:the_cpu_0|F_iw_b_rf[2]~282 Z1L2032 = AMPP_FUNCTION(Z1_D_iw[24], JC1_q_a[24], Z1_F_stall); --Z1L2033 is system_0:u0|cpu_0:the_cpu_0|F_iw_b_rf[3]~283 Z1L2033 = AMPP_FUNCTION(Z1_D_iw[25], JC1_q_a[25], Z1_F_stall); --Z1L2034 is system_0:u0|cpu_0:the_cpu_0|F_iw_b_rf[4]~284 Z1L2034 = AMPP_FUNCTION(Z1_D_iw[26], JC1_q_a[26], Z1_F_stall); --Z1_M_dst_regnum[1] is system_0:u0|cpu_0:the_cpu_0|M_dst_regnum[1] Z1_M_dst_regnum[1] = AMPP_FUNCTION(F1__clk1, Z1_E_dst_regnum[1], N1_data_out, Z1_A_stall); --Z1_M_dst_regnum[4] is system_0:u0|cpu_0:the_cpu_0|M_dst_regnum[4] Z1_M_dst_regnum[4] = AMPP_FUNCTION(F1__clk1, Z1_E_dst_regnum[4], N1_data_out, Z1_A_stall); --Z1L2430 is system_0:u0|cpu_0:the_cpu_0|M_regnum_b_cmp_F~34 Z1L2430 = AMPP_FUNCTION(JC1_q_a[26], JC1_q_a[23], Z1_M_dst_regnum[1], Z1_M_dst_regnum[4]); --Z1_M_dst_regnum[3] is system_0:u0|cpu_0:the_cpu_0|M_dst_regnum[3] Z1_M_dst_regnum[3] = AMPP_FUNCTION(F1__clk1, Z1_E_dst_regnum[3], N1_data_out, Z1_A_stall); --Z1_M_dst_regnum[0] is system_0:u0|cpu_0:the_cpu_0|M_dst_regnum[0] Z1_M_dst_regnum[0] = AMPP_FUNCTION(F1__clk1, Z1_E_dst_regnum[0], N1_data_out, Z1_A_stall); --Z1L2431 is system_0:u0|cpu_0:the_cpu_0|M_regnum_b_cmp_F~35 Z1L2431 = AMPP_FUNCTION(JC1_q_a[22], JC1_q_a[25], Z1_M_dst_regnum[3], Z1_M_dst_regnum[0]); --Z1_M_wr_dst_reg_from_E is system_0:u0|cpu_0:the_cpu_0|M_wr_dst_reg_from_E Z1_M_wr_dst_reg_from_E = AMPP_FUNCTION(F1__clk1, Z1L1893, N1_data_out, Z1_A_stall); --Z1_M_dst_regnum[2] is system_0:u0|cpu_0:the_cpu_0|M_dst_regnum[2] Z1_M_dst_regnum[2] = AMPP_FUNCTION(F1__clk1, Z1_E_dst_regnum[2], N1_data_out, Z1_A_stall); --Z1L1904 is system_0:u0|cpu_0:the_cpu_0|Equal~6225 Z1L1904 = AMPP_FUNCTION(JC1_q_a[24], Z1_M_dst_regnum[2]); --Z1L2432 is system_0:u0|cpu_0:the_cpu_0|M_regnum_b_cmp_F~36 Z1L2432 = AMPP_FUNCTION(Z1L2430, Z1L2431, Z1_M_wr_dst_reg_from_E, Z1L1904); --Z1L528 is system_0:u0|cpu_0:the_cpu_0|A_regnum_b_cmp_F~34 Z1L528 = AMPP_FUNCTION(JC1_q_a[26], JC1_q_a[23], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[4]); --Z1L529 is system_0:u0|cpu_0:the_cpu_0|A_regnum_b_cmp_F~35 Z1L529 = AMPP_FUNCTION(JC1_q_a[22], JC1_q_a[25], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[0]); --Z1L1905 is system_0:u0|cpu_0:the_cpu_0|Equal~6226 Z1L1905 = AMPP_FUNCTION(JC1_q_a[24], Z1_A_dst_regnum_from_M[2]); --Z1L530 is system_0:u0|cpu_0:the_cpu_0|A_regnum_b_cmp_F~36 Z1L530 = AMPP_FUNCTION(Z1L528, Z1L529, Z1_A_wr_dst_reg_from_M, Z1L1905); --Z1_A_mul_partial_prod[31] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[31] Z1_A_mul_partial_prod[31] = AMPP_FUNCTION(F1__clk1, Z1L287, N1_data_out); --Z1_A_mul_partial_prod[30] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[30] Z1_A_mul_partial_prod[30] = AMPP_FUNCTION(F1__clk1, Z1L284, N1_data_out); --Z1_A_mul_partial_prod[29] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[29] Z1_A_mul_partial_prod[29] = AMPP_FUNCTION(F1__clk1, Z1L281, N1_data_out); --Z1_A_mul_partial_prod[28] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[28] Z1_A_mul_partial_prod[28] = AMPP_FUNCTION(F1__clk1, Z1L278, N1_data_out); --Z1_A_mul_partial_prod[27] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[27] Z1_A_mul_partial_prod[27] = AMPP_FUNCTION(F1__clk1, Z1L275, N1_data_out); --Z1_A_mul_partial_prod[26] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[26] Z1_A_mul_partial_prod[26] = AMPP_FUNCTION(F1__clk1, Z1L272, N1_data_out); --Z1_A_mul_partial_prod[25] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[25] Z1_A_mul_partial_prod[25] = AMPP_FUNCTION(F1__clk1, Z1L269, N1_data_out); --Z1_A_mul_partial_prod[24] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[24] Z1_A_mul_partial_prod[24] = AMPP_FUNCTION(F1__clk1, Z1L266, N1_data_out); --Z1_A_mul_partial_prod[23] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[23] Z1_A_mul_partial_prod[23] = AMPP_FUNCTION(F1__clk1, Z1L263, N1_data_out); --Z1_A_mul_partial_prod[22] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[22] Z1_A_mul_partial_prod[22] = AMPP_FUNCTION(F1__clk1, Z1L260, N1_data_out); --Z1_A_mul_partial_prod[21] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[21] Z1_A_mul_partial_prod[21] = AMPP_FUNCTION(F1__clk1, Z1L257, N1_data_out); --Z1_A_mul_partial_prod[20] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[20] Z1_A_mul_partial_prod[20] = AMPP_FUNCTION(F1__clk1, Z1L254, N1_data_out); --Z1_A_mul_partial_prod[19] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[19] Z1_A_mul_partial_prod[19] = AMPP_FUNCTION(F1__clk1, Z1L251, N1_data_out); --Z1_A_mul_partial_prod[18] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[18] Z1_A_mul_partial_prod[18] = AMPP_FUNCTION(F1__clk1, Z1L248, N1_data_out); --Z1_A_mul_partial_prod[17] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[17] Z1_A_mul_partial_prod[17] = AMPP_FUNCTION(F1__clk1, Z1L245, N1_data_out); --Z1_A_mul_partial_prod[16] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[16] Z1_A_mul_partial_prod[16] = AMPP_FUNCTION(F1__clk1, Z1L242, N1_data_out); --Z1_A_mul_partial_prod[15] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[15] Z1_A_mul_partial_prod[15] = AMPP_FUNCTION(F1__clk1, QC1L48Q, N1_data_out); --Z1_A_mul_partial_prod[14] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[14] Z1_A_mul_partial_prod[14] = AMPP_FUNCTION(F1__clk1, QC1L47Q, N1_data_out); --Z1_A_mul_partial_prod[13] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[13] Z1_A_mul_partial_prod[13] = AMPP_FUNCTION(F1__clk1, QC1L46Q, N1_data_out); --Z1_A_mul_partial_prod[12] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[12] Z1_A_mul_partial_prod[12] = AMPP_FUNCTION(F1__clk1, QC1L45Q, N1_data_out); --Z1_A_mul_partial_prod[11] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[11] Z1_A_mul_partial_prod[11] = AMPP_FUNCTION(F1__clk1, QC1L44Q, N1_data_out); --Z1_A_mul_partial_prod[10] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[10] Z1_A_mul_partial_prod[10] = AMPP_FUNCTION(F1__clk1, QC1L43Q, N1_data_out); --Z1_A_mul_partial_prod[9] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[9] Z1_A_mul_partial_prod[9] = AMPP_FUNCTION(F1__clk1, QC1L42Q, N1_data_out); --Z1_A_mul_partial_prod[8] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[8] Z1_A_mul_partial_prod[8] = AMPP_FUNCTION(F1__clk1, QC1L41Q, N1_data_out); --Z1_A_mul_partial_prod[7] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[7] Z1_A_mul_partial_prod[7] = AMPP_FUNCTION(F1__clk1, QC1L40Q, N1_data_out); --Z1_A_mul_partial_prod[6] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[6] Z1_A_mul_partial_prod[6] = AMPP_FUNCTION(F1__clk1, QC1L39Q, N1_data_out); --Z1_A_mul_partial_prod[5] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[5] Z1_A_mul_partial_prod[5] = AMPP_FUNCTION(F1__clk1, QC1L38Q, N1_data_out); --Z1_A_mul_partial_prod[4] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[4] Z1_A_mul_partial_prod[4] = AMPP_FUNCTION(F1__clk1, QC1L37Q, N1_data_out); --Z1_A_mul_partial_prod[3] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[3] Z1_A_mul_partial_prod[3] = AMPP_FUNCTION(F1__clk1, QC1L36Q, N1_data_out); --Z1_A_mul_partial_prod[2] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[2] Z1_A_mul_partial_prod[2] = AMPP_FUNCTION(F1__clk1, QC1L35Q, N1_data_out); --Z1_A_mul_partial_prod[1] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[1] Z1_A_mul_partial_prod[1] = AMPP_FUNCTION(F1__clk1, QC1L34Q, N1_data_out); --Z1_A_mul_partial_prod[0] is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[0] Z1_A_mul_partial_prod[0] = AMPP_FUNCTION(F1__clk1, QC1_mac_out3, N1_data_out); --Z1L291 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[0]~256 Z1L291 = AMPP_FUNCTION(Z1_A_mul_result[0], Z1_A_mul_partial_prod[0], GND); --Z1L292 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[0]~257 Z1L292 = AMPP_FUNCTION(Z1_A_mul_result[0], Z1_A_mul_partial_prod[0]); --Z1L294 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[1]~258 Z1L294 = AMPP_FUNCTION(Z1_A_mul_result[1], Z1_A_mul_partial_prod[1], GND, Z1L292); --Z1L295 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[1]~259 Z1L295 = AMPP_FUNCTION(Z1_A_mul_result[1], Z1_A_mul_partial_prod[1], Z1L292); --Z1L297 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[2]~260 Z1L297 = AMPP_FUNCTION(Z1_A_mul_result[2], Z1_A_mul_partial_prod[2], GND, Z1L295); --Z1L298 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[2]~261 Z1L298 = AMPP_FUNCTION(Z1_A_mul_result[2], Z1_A_mul_partial_prod[2], Z1L295); --Z1L300 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[3]~262 Z1L300 = AMPP_FUNCTION(Z1_A_mul_result[3], Z1_A_mul_partial_prod[3], GND, Z1L298); --Z1L301 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[3]~263 Z1L301 = AMPP_FUNCTION(Z1_A_mul_result[3], Z1_A_mul_partial_prod[3], Z1L298); --Z1L303 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[4]~264 Z1L303 = AMPP_FUNCTION(Z1_A_mul_result[4], Z1_A_mul_partial_prod[4], GND, Z1L301); --Z1L304 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[4]~265 Z1L304 = AMPP_FUNCTION(Z1_A_mul_result[4], Z1_A_mul_partial_prod[4], Z1L301); --Z1L306 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[5]~266 Z1L306 = AMPP_FUNCTION(Z1_A_mul_result[5], Z1_A_mul_partial_prod[5], GND, Z1L304); --Z1L307 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[5]~267 Z1L307 = AMPP_FUNCTION(Z1_A_mul_result[5], Z1_A_mul_partial_prod[5], Z1L304); --Z1L309 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[6]~268 Z1L309 = AMPP_FUNCTION(Z1_A_mul_result[6], Z1_A_mul_partial_prod[6], GND, Z1L307); --Z1L310 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[6]~269 Z1L310 = AMPP_FUNCTION(Z1_A_mul_result[6], Z1_A_mul_partial_prod[6], Z1L307); --Z1L312 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[7]~270 Z1L312 = AMPP_FUNCTION(Z1_A_mul_result[7], Z1_A_mul_partial_prod[7], GND, Z1L310); --Z1L313 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[7]~271 Z1L313 = AMPP_FUNCTION(Z1_A_mul_result[7], Z1_A_mul_partial_prod[7], Z1L310); --Z1L315 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[8]~272 Z1L315 = AMPP_FUNCTION(Z1_A_mul_result[8], Z1_A_mul_partial_prod[8], GND, Z1L313); --Z1L316 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[8]~273 Z1L316 = AMPP_FUNCTION(Z1_A_mul_result[8], Z1_A_mul_partial_prod[8], Z1L313); --Z1L318 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[9]~274 Z1L318 = AMPP_FUNCTION(Z1_A_mul_result[9], Z1_A_mul_partial_prod[9], GND, Z1L316); --Z1L319 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[9]~275 Z1L319 = AMPP_FUNCTION(Z1_A_mul_result[9], Z1_A_mul_partial_prod[9], Z1L316); --Z1L321 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[10]~276 Z1L321 = AMPP_FUNCTION(Z1_A_mul_result[10], Z1_A_mul_partial_prod[10], GND, Z1L319); --Z1L322 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[10]~277 Z1L322 = AMPP_FUNCTION(Z1_A_mul_result[10], Z1_A_mul_partial_prod[10], Z1L319); --Z1L324 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[11]~278 Z1L324 = AMPP_FUNCTION(Z1_A_mul_result[11], Z1_A_mul_partial_prod[11], GND, Z1L322); --Z1L325 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[11]~279 Z1L325 = AMPP_FUNCTION(Z1_A_mul_result[11], Z1_A_mul_partial_prod[11], Z1L322); --Z1L327 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[12]~280 Z1L327 = AMPP_FUNCTION(Z1_A_mul_result[12], Z1_A_mul_partial_prod[12], GND, Z1L325); --Z1L328 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[12]~281 Z1L328 = AMPP_FUNCTION(Z1_A_mul_result[12], Z1_A_mul_partial_prod[12], Z1L325); --Z1L330 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[13]~282 Z1L330 = AMPP_FUNCTION(Z1_A_mul_result[13], Z1_A_mul_partial_prod[13], GND, Z1L328); --Z1L331 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[13]~283 Z1L331 = AMPP_FUNCTION(Z1_A_mul_result[13], Z1_A_mul_partial_prod[13], Z1L328); --Z1L333 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[14]~284 Z1L333 = AMPP_FUNCTION(Z1_A_mul_result[14], Z1_A_mul_partial_prod[14], GND, Z1L331); --Z1L334 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[14]~285 Z1L334 = AMPP_FUNCTION(Z1_A_mul_result[14], Z1_A_mul_partial_prod[14], Z1L331); --Z1L336 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[15]~286 Z1L336 = AMPP_FUNCTION(Z1_A_mul_result[15], Z1_A_mul_partial_prod[15], GND, Z1L334); --Z1L337 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[15]~287 Z1L337 = AMPP_FUNCTION(Z1_A_mul_result[15], Z1_A_mul_partial_prod[15], Z1L334); --Z1L339 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[16]~288 Z1L339 = AMPP_FUNCTION(Z1_A_mul_result[16], Z1_A_mul_partial_prod[16], GND, Z1L337); --Z1L340 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[16]~289 Z1L340 = AMPP_FUNCTION(Z1_A_mul_result[16], Z1_A_mul_partial_prod[16], Z1L337); --Z1L342 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[17]~290 Z1L342 = AMPP_FUNCTION(Z1_A_mul_result[17], Z1_A_mul_partial_prod[17], GND, Z1L340); --Z1L343 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[17]~291 Z1L343 = AMPP_FUNCTION(Z1_A_mul_result[17], Z1_A_mul_partial_prod[17], Z1L340); --Z1L345 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[18]~292 Z1L345 = AMPP_FUNCTION(Z1_A_mul_result[18], Z1_A_mul_partial_prod[18], GND, Z1L343); --Z1L346 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[18]~293 Z1L346 = AMPP_FUNCTION(Z1_A_mul_result[18], Z1_A_mul_partial_prod[18], Z1L343); --Z1L348 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[19]~294 Z1L348 = AMPP_FUNCTION(Z1_A_mul_result[19], Z1_A_mul_partial_prod[19], GND, Z1L346); --Z1L349 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[19]~295 Z1L349 = AMPP_FUNCTION(Z1_A_mul_result[19], Z1_A_mul_partial_prod[19], Z1L346); --Z1L351 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[20]~296 Z1L351 = AMPP_FUNCTION(Z1_A_mul_result[20], Z1_A_mul_partial_prod[20], GND, Z1L349); --Z1L352 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[20]~297 Z1L352 = AMPP_FUNCTION(Z1_A_mul_result[20], Z1_A_mul_partial_prod[20], Z1L349); --Z1L354 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[21]~298 Z1L354 = AMPP_FUNCTION(Z1_A_mul_result[21], Z1_A_mul_partial_prod[21], GND, Z1L352); --Z1L355 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[21]~299 Z1L355 = AMPP_FUNCTION(Z1_A_mul_result[21], Z1_A_mul_partial_prod[21], Z1L352); --Z1L357 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[22]~300 Z1L357 = AMPP_FUNCTION(Z1_A_mul_result[22], Z1_A_mul_partial_prod[22], GND, Z1L355); --Z1L358 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[22]~301 Z1L358 = AMPP_FUNCTION(Z1_A_mul_result[22], Z1_A_mul_partial_prod[22], Z1L355); --Z1L360 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[23]~302 Z1L360 = AMPP_FUNCTION(Z1_A_mul_result[23], Z1_A_mul_partial_prod[23], GND, Z1L358); --Z1L361 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[23]~303 Z1L361 = AMPP_FUNCTION(Z1_A_mul_result[23], Z1_A_mul_partial_prod[23], Z1L358); --Z1L363 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[24]~304 Z1L363 = AMPP_FUNCTION(Z1_A_mul_result[24], Z1_A_mul_partial_prod[24], GND, Z1L361); --Z1L364 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[24]~305 Z1L364 = AMPP_FUNCTION(Z1_A_mul_result[24], Z1_A_mul_partial_prod[24], Z1L361); --Z1L366 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[25]~306 Z1L366 = AMPP_FUNCTION(Z1_A_mul_result[25], Z1_A_mul_partial_prod[25], GND, Z1L364); --Z1L367 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[25]~307 Z1L367 = AMPP_FUNCTION(Z1_A_mul_result[25], Z1_A_mul_partial_prod[25], Z1L364); --Z1L369 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[26]~308 Z1L369 = AMPP_FUNCTION(Z1_A_mul_result[26], Z1_A_mul_partial_prod[26], GND, Z1L367); --Z1L370 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[26]~309 Z1L370 = AMPP_FUNCTION(Z1_A_mul_result[26], Z1_A_mul_partial_prod[26], Z1L367); --Z1L372 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[27]~310 Z1L372 = AMPP_FUNCTION(Z1_A_mul_result[27], Z1_A_mul_partial_prod[27], GND, Z1L370); --Z1L373 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[27]~311 Z1L373 = AMPP_FUNCTION(Z1_A_mul_result[27], Z1_A_mul_partial_prod[27], Z1L370); --Z1L375 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[28]~312 Z1L375 = AMPP_FUNCTION(Z1_A_mul_result[28], Z1_A_mul_partial_prod[28], GND, Z1L373); --Z1L376 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[28]~313 Z1L376 = AMPP_FUNCTION(Z1_A_mul_result[28], Z1_A_mul_partial_prod[28], Z1L373); --Z1L378 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[29]~314 Z1L378 = AMPP_FUNCTION(Z1_A_mul_result[29], Z1_A_mul_partial_prod[29], GND, Z1L376); --Z1L379 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[29]~315 Z1L379 = AMPP_FUNCTION(Z1_A_mul_result[29], Z1_A_mul_partial_prod[29], Z1L376); --Z1L381 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[30]~316 Z1L381 = AMPP_FUNCTION(Z1_A_mul_result[30], Z1_A_mul_partial_prod[30], GND, Z1L379); --Z1L382 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[30]~317 Z1L382 = AMPP_FUNCTION(Z1_A_mul_result[30], Z1_A_mul_partial_prod[30], Z1L379); --Z1L384 is system_0:u0|cpu_0:the_cpu_0|A_mul_result[31]~318 Z1L384 = AMPP_FUNCTION(Z1_A_mul_result[31], Z1_A_mul_partial_prod[31], Z1L382); --Z1_A_mul_stall_d3 is system_0:u0|cpu_0:the_cpu_0|A_mul_stall_d3 Z1_A_mul_stall_d3 = AMPP_FUNCTION(F1__clk1, Z1_A_mul_stall_d2, N1_data_out); --Z1_M_ctrl_ld_signed is system_0:u0|cpu_0:the_cpu_0|M_ctrl_ld_signed Z1_M_ctrl_ld_signed = AMPP_FUNCTION(F1__clk1, Z1L1535, N1_data_out, Z1_A_stall); --Z1_M_data_ram_ld_align_sign_bit_16_hi is system_0:u0|cpu_0:the_cpu_0|M_data_ram_ld_align_sign_bit_16_hi Z1_M_data_ram_ld_align_sign_bit_16_hi = AMPP_FUNCTION(F1__clk1, Z1L2197, N1_data_out, Z1_A_stall); --FC1_q_a[23] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[23] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[23] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3188, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3163); --Z1L2198 is system_0:u0|cpu_0:the_cpu_0|M_data_ram_ld_align_sign_bit~8 Z1L2198 = AMPP_FUNCTION(Z1_M_data_ram_ld_align_sign_bit_16_hi, FC1_q_a[23], Z1_M_alu_result[1], FC1_q_a[7]); --FC1_q_a[31] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[31] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[31] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3196, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3164); --Z1L2199 is system_0:u0|cpu_0:the_cpu_0|M_data_ram_ld_align_sign_bit~9 Z1L2199 = AMPP_FUNCTION(FC1_q_a[15], Z1_M_data_ram_ld_align_sign_bit_16_hi, Z1L2198, FC1_q_a[31]); --Z1_M_data_ram_ld_align_fill_bit is system_0:u0|cpu_0:the_cpu_0|M_data_ram_ld_align_fill_bit Z1_M_data_ram_ld_align_fill_bit = AMPP_FUNCTION(Z1_M_ctrl_ld_signed, Z1L2199); --Z1_M_ctrl_ld8_ld16 is system_0:u0|cpu_0:the_cpu_0|M_ctrl_ld8_ld16 Z1_M_ctrl_ld8_ld16 = AMPP_FUNCTION(F1__clk1, Z1L1527, N1_data_out, Z1_A_stall); --Z1L781 is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_sel_nxt~28 Z1L781 = AMPP_FUNCTION(Z1_A_dc_av_rd_req, Z1_A_stall); --Z1_A_ctrl_ld_signed is system_0:u0|cpu_0:the_cpu_0|A_ctrl_ld_signed Z1_A_ctrl_ld_signed = AMPP_FUNCTION(F1__clk1, Z1_M_ctrl_ld_signed, N1_data_out, Z1_A_stall); --Z1_A_mem_baddr[0] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[0] Z1_A_mem_baddr[0] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[0], N1_data_out, Z1_A_stall); --Z1_A_ctrl_ld16 is system_0:u0|cpu_0:the_cpu_0|A_ctrl_ld16 Z1_A_ctrl_ld16 = AMPP_FUNCTION(F1__clk1, Z1_M_ctrl_ld16, N1_data_out, Z1_A_stall); --Z1L799 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_data_sign_bit~0 Z1L799 = AMPP_FUNCTION(Z1_A_mem_baddr[0], Z1_A_ctrl_ld16); --Z1_d_readdata_d1[23] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[23] Z1_d_readdata_d1[23] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[23], N1_data_out); --Z1_A_mem_baddr[1] is system_0:u0|cpu_0:the_cpu_0|A_mem_baddr[1] Z1_A_mem_baddr[1] = AMPP_FUNCTION(F1__clk1, Z1_M_alu_result[1], N1_data_out, Z1_A_stall); --Z1L800 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_data_sign_bit~18 Z1L800 = AMPP_FUNCTION(Z1L799, Z1_d_readdata_d1[23], Z1_A_mem_baddr[1], Z1_d_readdata_d1[7]); --Z1_d_readdata_d1[31] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[31] Z1_d_readdata_d1[31] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[31], N1_data_out); --Z1L801 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_data_sign_bit~19 Z1L801 = AMPP_FUNCTION(Z1_d_readdata_d1[15], Z1L799, Z1L800, Z1_d_readdata_d1[31]); --Z1L797 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_byte3_data_aligned_nxt[7]~217 Z1L797 = AMPP_FUNCTION(Z1_A_ctrl_ld_signed, Z1L801, Z1_d_readdata_d1[31], Z1_A_ctrl_ld8_ld16); --Z1_A_ctrl_ld is system_0:u0|cpu_0:the_cpu_0|A_ctrl_ld Z1_A_ctrl_ld = AMPP_FUNCTION(F1__clk1, Z1_M_ctrl_ld, N1_data_out, Z1_A_stall); --Z1_M_ctrl_mem is system_0:u0|cpu_0:the_cpu_0|M_ctrl_mem Z1_M_ctrl_mem = AMPP_FUNCTION(F1__clk1, Z1L1543, N1_data_out, !Z1_E_iw[0], Z1_A_stall); --Z1L2305 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[31]~384 Z1L2305 = AMPP_FUNCTION(FC1_q_a[31], Z1_M_alu_result[31], Z1_M_ctrl_mem); --Z1_M_ctrl_rdctl_inst is system_0:u0|cpu_0:the_cpu_0|M_ctrl_rdctl_inst Z1_M_ctrl_rdctl_inst = AMPP_FUNCTION(F1__clk1, Z1_E_op_rdctl, N1_data_out, Z1_A_stall); --Z1_A_rot[31] is system_0:u0|cpu_0:the_cpu_0|A_rot[31] Z1_A_rot[31] = AMPP_FUNCTION(F1__clk1, Z1L582, N1_data_out, Z1_A_stall); --Z1_A_rot_fill_bit is system_0:u0|cpu_0:the_cpu_0|A_rot_fill_bit Z1_A_rot_fill_bit = AMPP_FUNCTION(F1__clk1, Z1_M_rot_fill_bit, N1_data_out, Z1_A_stall); --Z1_A_rot_mask[7] is system_0:u0|cpu_0:the_cpu_0|A_rot_mask[7] Z1_A_rot_mask[7] = AMPP_FUNCTION(F1__clk1, Z1_M_rot_mask[7], N1_data_out, Z1_A_stall); --Z1_A_rot_sel_fill3 is system_0:u0|cpu_0:the_cpu_0|A_rot_sel_fill3 Z1_A_rot_sel_fill3 = AMPP_FUNCTION(F1__clk1, Z1_M_rot_sel_fill3, N1_data_out, Z1_A_stall); --Z1L649 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4608 Z1L649 = AMPP_FUNCTION(Z1_A_rot_mask[7], Z1_A_rot_sel_fill3); --Z1_A_rot_pass3 is system_0:u0|cpu_0:the_cpu_0|A_rot_pass3 Z1_A_rot_pass3 = AMPP_FUNCTION(F1__clk1, Z1_M_rot_pass3, N1_data_out, Z1_A_stall); --Z1L650 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4609 Z1L650 = AMPP_FUNCTION(Z1_A_rot[31], Z1_A_rot_fill_bit, Z1L649, Z1_A_rot_pass3); --Z1L2025 is system_0:u0|cpu_0:the_cpu_0|F_iw_a_rf[0]~280 Z1L2025 = AMPP_FUNCTION(Z1_D_iw[27], JC1_q_a[27], Z1_F_stall); --Z1_D_iw[28] is system_0:u0|cpu_0:the_cpu_0|D_iw[28] Z1_D_iw[28] = AMPP_FUNCTION(F1__clk1, Z1L2021, N1_data_out, Z1_F_stall); --Z1L2026 is system_0:u0|cpu_0:the_cpu_0|F_iw_a_rf[1]~281 Z1L2026 = AMPP_FUNCTION(Z1_D_iw[28], JC1_q_a[28], Z1_F_stall); --Z1_D_iw[29] is system_0:u0|cpu_0:the_cpu_0|D_iw[29] Z1_D_iw[29] = AMPP_FUNCTION(F1__clk1, Z1L2022, N1_data_out, Z1_F_stall); --Z1L2027 is system_0:u0|cpu_0:the_cpu_0|F_iw_a_rf[2]~282 Z1L2027 = AMPP_FUNCTION(Z1_D_iw[29], JC1_q_a[29], Z1_F_stall); --Z1_D_iw[30] is system_0:u0|cpu_0:the_cpu_0|D_iw[30] Z1_D_iw[30] = AMPP_FUNCTION(F1__clk1, Z1L2023, N1_data_out, Z1_F_stall); --Z1L2028 is system_0:u0|cpu_0:the_cpu_0|F_iw_a_rf[3]~283 Z1L2028 = AMPP_FUNCTION(Z1_D_iw[30], JC1_q_a[30], Z1_F_stall); --Z1_D_iw[31] is system_0:u0|cpu_0:the_cpu_0|D_iw[31] Z1_D_iw[31] = AMPP_FUNCTION(F1__clk1, Z1L2024, N1_data_out, Z1_F_stall); --Z1L2029 is system_0:u0|cpu_0:the_cpu_0|F_iw_a_rf[4]~284 Z1L2029 = AMPP_FUNCTION(Z1_D_iw[31], JC1_q_a[31], Z1_F_stall); --Z1L2426 is system_0:u0|cpu_0:the_cpu_0|M_regnum_a_cmp_F~34 Z1L2426 = AMPP_FUNCTION(JC1_q_a[31], JC1_q_a[28], Z1_M_dst_regnum[1], Z1_M_dst_regnum[4]); --Z1L2427 is system_0:u0|cpu_0:the_cpu_0|M_regnum_a_cmp_F~35 Z1L2427 = AMPP_FUNCTION(JC1_q_a[27], JC1_q_a[30], Z1_M_dst_regnum[3], Z1_M_dst_regnum[0]); --Z1L1906 is system_0:u0|cpu_0:the_cpu_0|Equal~6227 Z1L1906 = AMPP_FUNCTION(JC1_q_a[29], Z1_M_dst_regnum[2]); --Z1L2428 is system_0:u0|cpu_0:the_cpu_0|M_regnum_a_cmp_F~36 Z1L2428 = AMPP_FUNCTION(Z1_M_wr_dst_reg_from_E, Z1L2426, Z1L2427, Z1L1906); --Z1L524 is system_0:u0|cpu_0:the_cpu_0|A_regnum_a_cmp_F~34 Z1L524 = AMPP_FUNCTION(JC1_q_a[31], JC1_q_a[28], Z1_A_dst_regnum_from_M[1], Z1_A_dst_regnum_from_M[4]); --Z1L525 is system_0:u0|cpu_0:the_cpu_0|A_regnum_a_cmp_F~35 Z1L525 = AMPP_FUNCTION(JC1_q_a[27], JC1_q_a[30], Z1_A_dst_regnum_from_M[3], Z1_A_dst_regnum_from_M[0]); --Z1L1907 is system_0:u0|cpu_0:the_cpu_0|Equal~6228 Z1L1907 = AMPP_FUNCTION(JC1_q_a[29], Z1_A_dst_regnum_from_M[2]); --Z1L526 is system_0:u0|cpu_0:the_cpu_0|A_regnum_a_cmp_F~36 Z1L526 = AMPP_FUNCTION(Z1L524, Z1L525, Z1_A_wr_dst_reg_from_M, Z1L1907); --Z1_d_readdata_d1[30] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[30] Z1_d_readdata_d1[30] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[30], N1_data_out); --Z1L796 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_byte3_data_aligned_nxt[6]~218 Z1L796 = AMPP_FUNCTION(Z1_A_ctrl_ld_signed, Z1L801, Z1_d_readdata_d1[30], Z1_A_ctrl_ld8_ld16); --FC1_q_a[30] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[30] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[30] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3195, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3164); --Z1L2304 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[30]~385 Z1L2304 = AMPP_FUNCTION(FC1_q_a[30], Z1_M_alu_result[30], Z1_M_ctrl_mem); --Z1_A_rot[30] is system_0:u0|cpu_0:the_cpu_0|A_rot[30] Z1_A_rot[30] = AMPP_FUNCTION(F1__clk1, Z1L583, N1_data_out, Z1_A_stall); --Z1_A_rot_mask[6] is system_0:u0|cpu_0:the_cpu_0|A_rot_mask[6] Z1_A_rot_mask[6] = AMPP_FUNCTION(F1__clk1, Z1_M_rot_mask[6], N1_data_out, Z1_A_stall); --Z1L651 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4610 Z1L651 = AMPP_FUNCTION(Z1_A_rot_mask[6], Z1_A_rot_sel_fill3); --Z1L652 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4611 Z1L652 = AMPP_FUNCTION(Z1_A_rot[30], Z1_A_rot_fill_bit, Z1L651, Z1_A_rot_pass3); --Z1_d_readdata_d1[29] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[29] Z1_d_readdata_d1[29] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[29], N1_data_out); --Z1L795 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_byte3_data_aligned_nxt[5]~219 Z1L795 = AMPP_FUNCTION(Z1_A_ctrl_ld_signed, Z1L801, Z1_d_readdata_d1[29], Z1_A_ctrl_ld8_ld16); --FC1_q_a[29] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[29] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[29] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3194, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3164); --Z1L2303 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[29]~386 Z1L2303 = AMPP_FUNCTION(FC1_q_a[29], Z1_M_alu_result[29], Z1_M_ctrl_mem); --Z1_A_rot[29] is system_0:u0|cpu_0:the_cpu_0|A_rot[29] Z1_A_rot[29] = AMPP_FUNCTION(F1__clk1, Z1L584, N1_data_out, Z1_A_stall); --Z1_A_rot_mask[5] is system_0:u0|cpu_0:the_cpu_0|A_rot_mask[5] Z1_A_rot_mask[5] = AMPP_FUNCTION(F1__clk1, Z1_M_rot_mask[5], N1_data_out, Z1_A_stall); --Z1L653 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4612 Z1L653 = AMPP_FUNCTION(Z1_A_rot_mask[5], Z1_A_rot_sel_fill3); --Z1L654 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4613 Z1L654 = AMPP_FUNCTION(Z1_A_rot[29], Z1_A_rot_fill_bit, Z1L653, Z1_A_rot_pass3); --Z1_d_readdata_d1[28] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[28] Z1_d_readdata_d1[28] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[28], N1_data_out); --Z1L794 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_byte3_data_aligned_nxt[4]~220 Z1L794 = AMPP_FUNCTION(Z1_A_ctrl_ld_signed, Z1L801, Z1_d_readdata_d1[28], Z1_A_ctrl_ld8_ld16); --FC1_q_a[28] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[28] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[28] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3193, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3164); --Z1L2302 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[28]~387 Z1L2302 = AMPP_FUNCTION(FC1_q_a[28], Z1_M_alu_result[28], Z1_M_ctrl_mem); --Z1_A_rot[28] is system_0:u0|cpu_0:the_cpu_0|A_rot[28] Z1_A_rot[28] = AMPP_FUNCTION(F1__clk1, Z1L585, N1_data_out, Z1_A_stall); --Z1_A_rot_mask[4] is system_0:u0|cpu_0:the_cpu_0|A_rot_mask[4] Z1_A_rot_mask[4] = AMPP_FUNCTION(F1__clk1, Z1_M_rot_mask[4], N1_data_out, Z1_A_stall); --Z1L655 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4614 Z1L655 = AMPP_FUNCTION(Z1_A_rot_mask[4], Z1_A_rot_sel_fill3); --Z1L656 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4615 Z1L656 = AMPP_FUNCTION(Z1_A_rot[28], Z1_A_rot_fill_bit, Z1L655, Z1_A_rot_pass3); --Z1_d_readdata_d1[27] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[27] Z1_d_readdata_d1[27] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[27], N1_data_out); --Z1L793 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_byte3_data_aligned_nxt[3]~221 Z1L793 = AMPP_FUNCTION(Z1_A_ctrl_ld_signed, Z1L801, Z1_d_readdata_d1[27], Z1_A_ctrl_ld8_ld16); --FC1_q_a[27] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[27] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[27] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3192, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3164); --Z1L2301 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[27]~388 Z1L2301 = AMPP_FUNCTION(FC1_q_a[27], Z1_M_alu_result[27], Z1_M_ctrl_mem); --Z1_A_rot[27] is system_0:u0|cpu_0:the_cpu_0|A_rot[27] Z1_A_rot[27] = AMPP_FUNCTION(F1__clk1, Z1L586, N1_data_out, Z1_A_stall); --Z1_A_rot_mask[3] is system_0:u0|cpu_0:the_cpu_0|A_rot_mask[3] Z1_A_rot_mask[3] = AMPP_FUNCTION(F1__clk1, Z1_M_rot_mask[3], N1_data_out, Z1_A_stall); --Z1L657 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4616 Z1L657 = AMPP_FUNCTION(Z1_A_rot_sel_fill3, Z1_A_rot_mask[3]); --Z1L658 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4617 Z1L658 = AMPP_FUNCTION(Z1_A_rot[27], Z1_A_rot_fill_bit, Z1L657, Z1_A_rot_pass3); --Z1_d_readdata_d1[26] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[26] Z1_d_readdata_d1[26] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[26], N1_data_out); --Z1L792 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_byte3_data_aligned_nxt[2]~222 Z1L792 = AMPP_FUNCTION(Z1_A_ctrl_ld_signed, Z1L801, Z1_d_readdata_d1[26], Z1_A_ctrl_ld8_ld16); --FC1_q_a[26] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[26] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[26] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3191, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3164); --Z1L2300 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[26]~389 Z1L2300 = AMPP_FUNCTION(FC1_q_a[26], Z1_M_alu_result[26], Z1_M_ctrl_mem); --Z1_A_rot[26] is system_0:u0|cpu_0:the_cpu_0|A_rot[26] Z1_A_rot[26] = AMPP_FUNCTION(F1__clk1, Z1L587, N1_data_out, Z1_A_stall); --Z1_A_rot_mask[2] is system_0:u0|cpu_0:the_cpu_0|A_rot_mask[2] Z1_A_rot_mask[2] = AMPP_FUNCTION(F1__clk1, Z1_M_rot_mask[2], N1_data_out, Z1_A_stall); --Z1L659 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4618 Z1L659 = AMPP_FUNCTION(Z1_A_rot_mask[2], Z1_A_rot_sel_fill3); --Z1L660 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4619 Z1L660 = AMPP_FUNCTION(Z1_A_rot[26], Z1_A_rot_fill_bit, Z1L659, Z1_A_rot_pass3); --Z1_d_readdata_d1[25] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[25] Z1_d_readdata_d1[25] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[25], N1_data_out); --Z1L791 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_byte3_data_aligned_nxt[1]~223 Z1L791 = AMPP_FUNCTION(Z1_A_ctrl_ld_signed, Z1L801, Z1_d_readdata_d1[25], Z1_A_ctrl_ld8_ld16); --FC1_q_a[25] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[25] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[25] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3190, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3164); --Z1L2299 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[25]~390 Z1L2299 = AMPP_FUNCTION(FC1_q_a[25], Z1_M_alu_result[25], Z1_M_ctrl_mem); --Z1_A_rot[25] is system_0:u0|cpu_0:the_cpu_0|A_rot[25] Z1_A_rot[25] = AMPP_FUNCTION(F1__clk1, Z1L588, N1_data_out, Z1_A_stall); --Z1_A_rot_mask[1] is system_0:u0|cpu_0:the_cpu_0|A_rot_mask[1] Z1_A_rot_mask[1] = AMPP_FUNCTION(F1__clk1, Z1_M_rot_mask[1], N1_data_out, Z1_A_stall); --Z1L661 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4620 Z1L661 = AMPP_FUNCTION(Z1_A_rot_mask[1], Z1_A_rot_sel_fill3); --Z1L662 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4621 Z1L662 = AMPP_FUNCTION(Z1_A_rot[25], Z1_A_rot_fill_bit, Z1L661, Z1_A_rot_pass3); --Z1_d_readdata_d1[24] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[24] Z1_d_readdata_d1[24] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[24], N1_data_out); --Z1L790 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_byte3_data_aligned_nxt[0]~224 Z1L790 = AMPP_FUNCTION(Z1_A_ctrl_ld_signed, Z1L801, Z1_d_readdata_d1[24], Z1_A_ctrl_ld8_ld16); --FC1_q_a[24] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[24] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[24] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3189, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3164); --Z1L2298 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[24]~391 Z1L2298 = AMPP_FUNCTION(FC1_q_a[24], Z1_M_alu_result[24], Z1_M_ctrl_mem); --Z1_A_rot[24] is system_0:u0|cpu_0:the_cpu_0|A_rot[24] Z1_A_rot[24] = AMPP_FUNCTION(F1__clk1, Z1L589, N1_data_out, Z1_A_stall); --Z1_A_rot_mask[0] is system_0:u0|cpu_0:the_cpu_0|A_rot_mask[0] Z1_A_rot_mask[0] = AMPP_FUNCTION(F1__clk1, Z1_M_rot_mask[0], N1_data_out, Z1_A_stall); --Z1L663 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4622 Z1L663 = AMPP_FUNCTION(Z1_A_rot_mask[0], Z1_A_rot_sel_fill3); --Z1L664 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4623 Z1L664 = AMPP_FUNCTION(Z1_A_rot[24], Z1_A_rot_fill_bit, Z1L663, Z1_A_rot_pass3); --Z1L789 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_byte2_data_aligned_nxt[7]~96 Z1L789 = AMPP_FUNCTION(Z1_A_ctrl_ld_signed, Z1L801, Z1_d_readdata_d1[23], Z1_A_ctrl_ld8_ld16); --Z1L2297 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[23]~392 Z1L2297 = AMPP_FUNCTION(FC1_q_a[23], Z1_M_alu_result[23], Z1_M_ctrl_mem); --Z1_A_rot[23] is system_0:u0|cpu_0:the_cpu_0|A_rot[23] Z1_A_rot[23] = AMPP_FUNCTION(F1__clk1, Z1L590, N1_data_out, Z1_A_stall); --Z1_A_rot_sel_fill2 is system_0:u0|cpu_0:the_cpu_0|A_rot_sel_fill2 Z1_A_rot_sel_fill2 = AMPP_FUNCTION(F1__clk1, Z1_M_rot_sel_fill2, N1_data_out, Z1_A_stall); --Z1L665 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4624 Z1L665 = AMPP_FUNCTION(Z1_A_rot_sel_fill2, Z1_A_rot_mask[7]); --Z1_A_rot_pass2 is system_0:u0|cpu_0:the_cpu_0|A_rot_pass2 Z1_A_rot_pass2 = AMPP_FUNCTION(F1__clk1, Z1_M_rot_pass2, N1_data_out, Z1_A_stall); --Z1L666 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4625 Z1L666 = AMPP_FUNCTION(Z1_A_rot[23], Z1_A_rot_fill_bit, Z1L665, Z1_A_rot_pass2); --Z1_d_readdata_d1[22] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[22] Z1_d_readdata_d1[22] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[22], N1_data_out); --Z1L788 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_byte2_data_aligned_nxt[6]~97 Z1L788 = AMPP_FUNCTION(Z1_A_ctrl_ld_signed, Z1L801, Z1_d_readdata_d1[22], Z1_A_ctrl_ld8_ld16); --FC1_q_a[22] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[22] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[22] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3187, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3163); --Z1L2296 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[22]~393 Z1L2296 = AMPP_FUNCTION(FC1_q_a[22], Z1_M_alu_result[22], Z1_M_ctrl_mem); --Z1_A_rot[22] is system_0:u0|cpu_0:the_cpu_0|A_rot[22] Z1_A_rot[22] = AMPP_FUNCTION(F1__clk1, Z1L591, N1_data_out, Z1_A_stall); --Z1L667 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4626 Z1L667 = AMPP_FUNCTION(Z1_A_rot_sel_fill2, Z1_A_rot_mask[6]); --Z1L668 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4627 Z1L668 = AMPP_FUNCTION(Z1_A_rot[22], Z1_A_rot_fill_bit, Z1L667, Z1_A_rot_pass2); --Z1_d_readdata_d1[21] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[21] Z1_d_readdata_d1[21] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[21], N1_data_out); --Z1L787 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_byte2_data_aligned_nxt[5]~98 Z1L787 = AMPP_FUNCTION(Z1_A_ctrl_ld_signed, Z1L801, Z1_d_readdata_d1[21], Z1_A_ctrl_ld8_ld16); --FC1_q_a[21] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[21] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[21] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3186, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3163); --Z1L2295 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[21]~394 Z1L2295 = AMPP_FUNCTION(FC1_q_a[21], Z1_M_alu_result[21], Z1_M_ctrl_mem); --Z1_A_rot[21] is system_0:u0|cpu_0:the_cpu_0|A_rot[21] Z1_A_rot[21] = AMPP_FUNCTION(F1__clk1, Z1L592, N1_data_out, Z1_A_stall); --Z1L669 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4628 Z1L669 = AMPP_FUNCTION(Z1_A_rot_sel_fill2, Z1_A_rot_mask[5]); --Z1L670 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4629 Z1L670 = AMPP_FUNCTION(Z1_A_rot[21], Z1_A_rot_fill_bit, Z1L669, Z1_A_rot_pass2); --Z1_d_readdata_d1[20] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[20] Z1_d_readdata_d1[20] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[20], N1_data_out); --Z1L786 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_byte2_data_aligned_nxt[4]~99 Z1L786 = AMPP_FUNCTION(Z1_A_ctrl_ld_signed, Z1L801, Z1_d_readdata_d1[20], Z1_A_ctrl_ld8_ld16); --FC1_q_a[20] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[20] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[20] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3185, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3163); --Z1L2294 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[20]~395 Z1L2294 = AMPP_FUNCTION(FC1_q_a[20], Z1_M_alu_result[20], Z1_M_ctrl_mem); --Z1_A_rot[20] is system_0:u0|cpu_0:the_cpu_0|A_rot[20] Z1_A_rot[20] = AMPP_FUNCTION(F1__clk1, Z1L593, N1_data_out, Z1_A_stall); --Z1L671 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4630 Z1L671 = AMPP_FUNCTION(Z1_A_rot_sel_fill2, Z1_A_rot_mask[4]); --Z1L672 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4631 Z1L672 = AMPP_FUNCTION(Z1_A_rot[20], Z1_A_rot_fill_bit, Z1L671, Z1_A_rot_pass2); --Z1_d_readdata_d1[19] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[19] Z1_d_readdata_d1[19] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[19], N1_data_out); --Z1L785 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_byte2_data_aligned_nxt[3]~100 Z1L785 = AMPP_FUNCTION(Z1_A_ctrl_ld_signed, Z1L801, Z1_d_readdata_d1[19], Z1_A_ctrl_ld8_ld16); --FC1_q_a[19] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[19] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[19] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3184, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3163); --Z1L2293 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[19]~396 Z1L2293 = AMPP_FUNCTION(FC1_q_a[19], Z1_M_alu_result[19], Z1_M_ctrl_mem); --Z1_A_rot[19] is system_0:u0|cpu_0:the_cpu_0|A_rot[19] Z1_A_rot[19] = AMPP_FUNCTION(F1__clk1, Z1L594, N1_data_out, Z1_A_stall); --Z1L673 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4632 Z1L673 = AMPP_FUNCTION(Z1_A_rot_sel_fill2, Z1_A_rot_mask[3]); --Z1L674 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4633 Z1L674 = AMPP_FUNCTION(Z1_A_rot[19], Z1_A_rot_fill_bit, Z1L673, Z1_A_rot_pass2); --Z1_d_readdata_d1[18] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[18] Z1_d_readdata_d1[18] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[18], N1_data_out); --Z1L784 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_byte2_data_aligned_nxt[2]~101 Z1L784 = AMPP_FUNCTION(Z1_A_ctrl_ld_signed, Z1L801, Z1_d_readdata_d1[18], Z1_A_ctrl_ld8_ld16); --FC1_q_a[18] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[18] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[18] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3183, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3163); --Z1L2292 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[18]~397 Z1L2292 = AMPP_FUNCTION(FC1_q_a[18], Z1_M_alu_result[18], Z1_M_ctrl_mem); --Z1_A_rot[18] is system_0:u0|cpu_0:the_cpu_0|A_rot[18] Z1_A_rot[18] = AMPP_FUNCTION(F1__clk1, Z1L595, N1_data_out, Z1_A_stall); --Z1L675 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4634 Z1L675 = AMPP_FUNCTION(Z1_A_rot_sel_fill2, Z1_A_rot_mask[2]); --Z1L676 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4635 Z1L676 = AMPP_FUNCTION(Z1_A_rot[18], Z1_A_rot_fill_bit, Z1L675, Z1_A_rot_pass2); --Z1_d_readdata_d1[17] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[17] Z1_d_readdata_d1[17] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[17], N1_data_out); --Z1L783 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_byte2_data_aligned_nxt[1]~102 Z1L783 = AMPP_FUNCTION(Z1_A_ctrl_ld_signed, Z1L801, Z1_d_readdata_d1[17], Z1_A_ctrl_ld8_ld16); --FC1_q_a[17] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[17] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[17] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3182, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3163); --Z1L2291 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[17]~398 Z1L2291 = AMPP_FUNCTION(FC1_q_a[17], Z1_M_alu_result[17], Z1_M_ctrl_mem); --Z1_A_rot[17] is system_0:u0|cpu_0:the_cpu_0|A_rot[17] Z1_A_rot[17] = AMPP_FUNCTION(F1__clk1, Z1L596, N1_data_out, Z1_A_stall); --Z1L677 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4636 Z1L677 = AMPP_FUNCTION(Z1_A_rot_mask[1], Z1_A_rot_sel_fill2); --Z1L678 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4637 Z1L678 = AMPP_FUNCTION(Z1_A_rot[17], Z1_A_rot_fill_bit, Z1L677, Z1_A_rot_pass2); --Z1_d_readdata_d1[16] is system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[16] Z1_d_readdata_d1[16] = AMPP_FUNCTION(F1__clk1, AB1_cpu_0_data_master_readdata[16], N1_data_out); --Z1L782 is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_byte2_data_aligned_nxt[0]~103 Z1L782 = AMPP_FUNCTION(Z1_A_ctrl_ld_signed, Z1L801, Z1_d_readdata_d1[16], Z1_A_ctrl_ld8_ld16); --FC1_q_a[16] is system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_q1r1:auto_generated|q_a[16] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1 --Port A Logical Depth: 512, Port A Logical Width: 32, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered FC1_q_a[16] = AMPP_FUNCTION(VCC, Z1L3198, F1__clk1, F1__clk1, Z1_A_stall, ~GND, Z1L1553, Z1L1554, Z1L1555, Z1L1556, Z1L1557, Z1L1558, Z1L1559, Z1L1560, Z1L1561, Z1L3181, Z1L3216, Z1L3217, Z1L3218, Z1L3219, Z1L3220, Z1L3221, Z1L3222, Z1L3223, Z1L3224, Z1L3163); --Z1L2290 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[16]~399 Z1L2290 = AMPP_FUNCTION(FC1_q_a[16], Z1_M_alu_result[16], Z1_M_ctrl_mem); --Z1_A_rot[16] is system_0:u0|cpu_0:the_cpu_0|A_rot[16] Z1_A_rot[16] = AMPP_FUNCTION(F1__clk1, Z1L597, N1_data_out, Z1_A_stall); --Z1L679 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4638 Z1L679 = AMPP_FUNCTION(Z1_A_rot_sel_fill2, Z1_A_rot_mask[0]); --Z1L680 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4639 Z1L680 = AMPP_FUNCTION(Z1_A_rot[16], Z1_A_rot_fill_bit, Z1L679, Z1_A_rot_pass2); --Z1_M_ctrl_ld8 is system_0:u0|cpu_0:the_cpu_0|M_ctrl_ld8 Z1_M_ctrl_ld8 = AMPP_FUNCTION(F1__clk1, Z1L1528, N1_data_out, Z1_A_stall); --Z1L762 is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[15]~1079 Z1L762 = AMPP_FUNCTION(Z1_d_readdata_d1[15], Z1_d_readdata_d1[31], Z1_A_ld_align_sh16); --Z1_A_slow_ld_data_fill_bit is system_0:u0|cpu_0:the_cpu_0|A_slow_ld_data_fill_bit Z1_A_slow_ld_data_fill_bit = AMPP_FUNCTION(Z1_A_ctrl_ld_signed, Z1L801); --Z1L2289 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[15]~400 Z1L2289 = AMPP_FUNCTION(FC1_q_a[15], Z1_M_alu_result[15], Z1_M_ctrl_mem); --Z1_M_ctrl_ld16 is system_0:u0|cpu_0:the_cpu_0|M_ctrl_ld16 Z1_M_ctrl_ld16 = AMPP_FUNCTION(F1__clk1, Z1L1529, N1_data_out, Z1_A_stall); --Z1L2323 is system_0:u0|cpu_0:the_cpu_0|M_ld_align_sh16~17 Z1L2323 = AMPP_FUNCTION(Z1_M_alu_result[1], Z1_M_ctrl_ld8, Z1_M_ctrl_ld16); --Z1_A_rot[15] is system_0:u0|cpu_0:the_cpu_0|A_rot[15] Z1_A_rot[15] = AMPP_FUNCTION(F1__clk1, Z1L598, N1_data_out, Z1_A_stall); --Z1_A_rot_sel_fill1 is system_0:u0|cpu_0:the_cpu_0|A_rot_sel_fill1 Z1_A_rot_sel_fill1 = AMPP_FUNCTION(F1__clk1, Z1_M_rot_sel_fill1, N1_data_out, Z1_A_stall); --Z1L681 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4640 Z1L681 = AMPP_FUNCTION(Z1_A_rot_sel_fill1, Z1_A_rot_mask[7]); --Z1_A_rot_pass1 is system_0:u0|cpu_0:the_cpu_0|A_rot_pass1 Z1_A_rot_pass1 = AMPP_FUNCTION(F1__clk1, Z1_M_rot_pass1, N1_data_out, Z1_A_stall); --Z1L682 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4641 Z1L682 = AMPP_FUNCTION(Z1_A_rot[15], Z1_A_rot_fill_bit, Z1L681, Z1_A_rot_pass1); --Z1L759 is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[14]~1078 Z1L759 = AMPP_FUNCTION(Z1_d_readdata_d1[14], Z1_d_readdata_d1[30], Z1_A_ld_align_sh16); --Z1L2288 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[14]~401 Z1L2288 = AMPP_FUNCTION(FC1_q_a[14], Z1_M_alu_result[14], Z1_M_ctrl_mem); --Z1_A_rot[14] is system_0:u0|cpu_0:the_cpu_0|A_rot[14] Z1_A_rot[14] = AMPP_FUNCTION(F1__clk1, Z1L599, N1_data_out, Z1_A_stall); --Z1L683 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4642 Z1L683 = AMPP_FUNCTION(Z1_A_rot_sel_fill1, Z1_A_rot_mask[6]); --Z1L684 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4643 Z1L684 = AMPP_FUNCTION(Z1_A_rot[14], Z1_A_rot_fill_bit, Z1L683, Z1_A_rot_pass1); --Z1L756 is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[13]~1077 Z1L756 = AMPP_FUNCTION(Z1_d_readdata_d1[13], Z1_d_readdata_d1[29], Z1_A_ld_align_sh16); --Z1L2287 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[13]~402 Z1L2287 = AMPP_FUNCTION(FC1_q_a[13], Z1_M_alu_result[13], Z1_M_ctrl_mem); --Z1_A_rot[13] is system_0:u0|cpu_0:the_cpu_0|A_rot[13] Z1_A_rot[13] = AMPP_FUNCTION(F1__clk1, Z1L600, N1_data_out, Z1_A_stall); --Z1L685 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4644 Z1L685 = AMPP_FUNCTION(Z1_A_rot_mask[5], Z1_A_rot_sel_fill1); --Z1L686 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4645 Z1L686 = AMPP_FUNCTION(Z1_A_rot[13], Z1_A_rot_fill_bit, Z1L685, Z1_A_rot_pass1); --Z1L753 is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[12]~1076 Z1L753 = AMPP_FUNCTION(Z1_d_readdata_d1[12], Z1_d_readdata_d1[28], Z1_A_ld_align_sh16); --Z1L2286 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[12]~403 Z1L2286 = AMPP_FUNCTION(FC1_q_a[12], Z1_M_alu_result[12], Z1_M_ctrl_mem); --Z1_A_rot[12] is system_0:u0|cpu_0:the_cpu_0|A_rot[12] Z1_A_rot[12] = AMPP_FUNCTION(F1__clk1, Z1L601, N1_data_out, Z1_A_stall); --Z1L687 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4646 Z1L687 = AMPP_FUNCTION(Z1_A_rot_mask[4], Z1_A_rot_sel_fill1); --Z1L688 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4647 Z1L688 = AMPP_FUNCTION(Z1_A_rot[12], Z1_A_rot_fill_bit, Z1L687, Z1_A_rot_pass1); --Z1L750 is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[11]~1075 Z1L750 = AMPP_FUNCTION(Z1_d_readdata_d1[11], Z1_d_readdata_d1[27], Z1_A_ld_align_sh16); --Z1L2285 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[11]~404 Z1L2285 = AMPP_FUNCTION(FC1_q_a[11], Z1_M_alu_result[11], Z1_M_ctrl_mem); --Z1_A_rot[11] is system_0:u0|cpu_0:the_cpu_0|A_rot[11] Z1_A_rot[11] = AMPP_FUNCTION(F1__clk1, Z1L602, N1_data_out, Z1_A_stall); --Z1L689 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4648 Z1L689 = AMPP_FUNCTION(Z1_A_rot_sel_fill1, Z1_A_rot_mask[3]); --Z1L690 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4649 Z1L690 = AMPP_FUNCTION(Z1_A_rot[11], Z1_A_rot_fill_bit, Z1L689, Z1_A_rot_pass1); --Z1L747 is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[10]~1074 Z1L747 = AMPP_FUNCTION(Z1_d_readdata_d1[10], Z1_d_readdata_d1[26], Z1_A_ld_align_sh16); --Z1L2284 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[10]~405 Z1L2284 = AMPP_FUNCTION(FC1_q_a[10], Z1_M_alu_result[10], Z1_M_ctrl_mem); --Z1_A_rot[10] is system_0:u0|cpu_0:the_cpu_0|A_rot[10] Z1_A_rot[10] = AMPP_FUNCTION(F1__clk1, Z1L603, N1_data_out, Z1_A_stall); --Z1L691 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4650 Z1L691 = AMPP_FUNCTION(Z1_A_rot_sel_fill1, Z1_A_rot_mask[2]); --Z1L692 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4651 Z1L692 = AMPP_FUNCTION(Z1_A_rot[10], Z1_A_rot_fill_bit, Z1L691, Z1_A_rot_pass1); --Z1L744 is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[9]~1073 Z1L744 = AMPP_FUNCTION(Z1_d_readdata_d1[9], Z1_d_readdata_d1[25], Z1_A_ld_align_sh16); --Z1L2283 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[9]~406 Z1L2283 = AMPP_FUNCTION(FC1_q_a[9], Z1_M_alu_result[9], Z1_M_ctrl_mem); --Z1_A_rot[9] is system_0:u0|cpu_0:the_cpu_0|A_rot[9] Z1_A_rot[9] = AMPP_FUNCTION(F1__clk1, Z1L604, N1_data_out, Z1_A_stall); --Z1L693 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4652 Z1L693 = AMPP_FUNCTION(Z1_A_rot_mask[1], Z1_A_rot_sel_fill1); --Z1L694 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4653 Z1L694 = AMPP_FUNCTION(Z1_A_rot[9], Z1_A_rot_fill_bit, Z1L693, Z1_A_rot_pass1); --Z1L741 is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[8]~1072 Z1L741 = AMPP_FUNCTION(Z1_d_readdata_d1[8], Z1_d_readdata_d1[24], Z1_A_ld_align_sh16); --Z1L2282 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[8]~407 Z1L2282 = AMPP_FUNCTION(FC1_q_a[8], Z1_M_alu_result[8], Z1_M_ctrl_mem); --Z1_A_rot[8] is system_0:u0|cpu_0:the_cpu_0|A_rot[8] Z1_A_rot[8] = AMPP_FUNCTION(F1__clk1, Z1L605, N1_data_out, Z1_A_stall); --Z1L695 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4654 Z1L695 = AMPP_FUNCTION(Z1_A_rot_mask[0], Z1_A_rot_sel_fill1); --Z1L696 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4655 Z1L696 = AMPP_FUNCTION(Z1_A_rot[8], Z1_A_rot_fill_bit, Z1L695, Z1_A_rot_pass1); --Z1_A_rot[7] is system_0:u0|cpu_0:the_cpu_0|A_rot[7] Z1_A_rot[7] = AMPP_FUNCTION(F1__clk1, Z1L606, N1_data_out, Z1_A_stall); --Z1_A_rot_sel_fill0 is system_0:u0|cpu_0:the_cpu_0|A_rot_sel_fill0 Z1_A_rot_sel_fill0 = AMPP_FUNCTION(F1__clk1, Z1_M_rot_sel_fill0, N1_data_out, Z1_A_stall); --Z1L697 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4656 Z1L697 = AMPP_FUNCTION(Z1_A_rot_sel_fill0, Z1_A_rot_mask[7]); --Z1_A_rot_pass0 is system_0:u0|cpu_0:the_cpu_0|A_rot_pass0 Z1_A_rot_pass0 = AMPP_FUNCTION(F1__clk1, Z1_M_rot_pass0, N1_data_out, Z1_A_stall); --Z1L698 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4657 Z1L698 = AMPP_FUNCTION(Z1_A_rot[7], Z1_A_rot_fill_bit, Z1L697, Z1_A_rot_pass0); --Z1_M_ld_align_sh8 is system_0:u0|cpu_0:the_cpu_0|M_ld_align_sh8 Z1_M_ld_align_sh8 = AMPP_FUNCTION(Z1_M_alu_result[0], Z1_M_ctrl_ld8); --Z1L738 is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[7]~1071 Z1L738 = AMPP_FUNCTION(Z1_d_readdata_d1[7], Z1_d_readdata_d1[23], Z1_A_ld_align_sh16); --Z1L2281 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[7]~408 Z1L2281 = AMPP_FUNCTION(FC1_q_a[7], Z1_M_alu_result[7], Z1_M_ctrl_mem); --Z1_A_rot[6] is system_0:u0|cpu_0:the_cpu_0|A_rot[6] Z1_A_rot[6] = AMPP_FUNCTION(F1__clk1, Z1L607, N1_data_out, Z1_A_stall); --Z1L699 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4658 Z1L699 = AMPP_FUNCTION(Z1_A_rot_sel_fill0, Z1_A_rot_mask[6]); --Z1L700 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4659 Z1L700 = AMPP_FUNCTION(Z1_A_rot[6], Z1_A_rot_fill_bit, Z1L699, Z1_A_rot_pass0); --Z1L735 is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[6]~1070 Z1L735 = AMPP_FUNCTION(Z1_d_readdata_d1[6], Z1_d_readdata_d1[22], Z1_A_ld_align_sh16); --Z1L2280 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[6]~409 Z1L2280 = AMPP_FUNCTION(FC1_q_a[6], Z1_M_alu_result[6], Z1_M_ctrl_mem); --Z1_A_rot[5] is system_0:u0|cpu_0:the_cpu_0|A_rot[5] Z1_A_rot[5] = AMPP_FUNCTION(F1__clk1, Z1L608, N1_data_out, Z1_A_stall); --Z1L701 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4660 Z1L701 = AMPP_FUNCTION(Z1_A_rot_sel_fill0, Z1_A_rot_mask[5]); --Z1L702 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4661 Z1L702 = AMPP_FUNCTION(Z1_A_rot[5], Z1_A_rot_fill_bit, Z1L701, Z1_A_rot_pass0); --Z1L732 is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[5]~1069 Z1L732 = AMPP_FUNCTION(Z1_d_readdata_d1[5], Z1_d_readdata_d1[21], Z1_A_ld_align_sh16); --Z1L2279 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[5]~410 Z1L2279 = AMPP_FUNCTION(FC1_q_a[5], Z1_M_alu_result[5], Z1_M_ctrl_mem); --Z1_A_rot[4] is system_0:u0|cpu_0:the_cpu_0|A_rot[4] Z1_A_rot[4] = AMPP_FUNCTION(F1__clk1, Z1L609, N1_data_out, Z1_A_stall); --Z1L703 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4662 Z1L703 = AMPP_FUNCTION(Z1_A_rot_sel_fill0, Z1_A_rot_mask[4]); --Z1L704 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4663 Z1L704 = AMPP_FUNCTION(Z1_A_rot[4], Z1_A_rot_fill_bit, Z1L703, Z1_A_rot_pass0); --Z1L729 is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[4]~1068 Z1L729 = AMPP_FUNCTION(Z1_d_readdata_d1[4], Z1_d_readdata_d1[20], Z1_A_ld_align_sh16); --Z1L2278 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[4]~411 Z1L2278 = AMPP_FUNCTION(FC1_q_a[4], Z1_M_alu_result[4], Z1_M_ctrl_mem); --Z1_A_rot[3] is system_0:u0|cpu_0:the_cpu_0|A_rot[3] Z1_A_rot[3] = AMPP_FUNCTION(F1__clk1, Z1L610, N1_data_out, Z1_A_stall); --Z1L705 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4664 Z1L705 = AMPP_FUNCTION(Z1_A_rot_sel_fill0, Z1_A_rot_mask[3]); --Z1L706 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4665 Z1L706 = AMPP_FUNCTION(Z1_A_rot[3], Z1_A_rot_fill_bit, Z1L705, Z1_A_rot_pass0); --Z1L726 is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[3]~1067 Z1L726 = AMPP_FUNCTION(Z1_d_readdata_d1[3], Z1_d_readdata_d1[19], Z1_A_ld_align_sh16); --Z1L2277 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[3]~412 Z1L2277 = AMPP_FUNCTION(FC1_q_a[3], Z1_M_alu_result[3], Z1_M_ctrl_mem); --Z1_M_control_rd_data[3] is system_0:u0|cpu_0:the_cpu_0|M_control_rd_data[3] Z1_M_control_rd_data[3] = AMPP_FUNCTION(F1__clk1, Z1_E_control_rd_data_without_mmu_regs[3], N1_data_out, Z1_A_stall); --Z1_A_rot[2] is system_0:u0|cpu_0:the_cpu_0|A_rot[2] Z1_A_rot[2] = AMPP_FUNCTION(F1__clk1, Z1L611, N1_data_out, Z1_A_stall); --Z1L707 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4666 Z1L707 = AMPP_FUNCTION(Z1_A_rot_sel_fill0, Z1_A_rot_mask[2]); --Z1L708 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4667 Z1L708 = AMPP_FUNCTION(Z1_A_rot[2], Z1_A_rot_fill_bit, Z1L707, Z1_A_rot_pass0); --Z1L723 is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[2]~1066 Z1L723 = AMPP_FUNCTION(Z1_d_readdata_d1[2], Z1_d_readdata_d1[18], Z1_A_ld_align_sh16); --Z1L2276 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[2]~413 Z1L2276 = AMPP_FUNCTION(FC1_q_a[2], Z1_M_alu_result[2], Z1_M_ctrl_mem); --Z1_M_control_rd_data[2] is system_0:u0|cpu_0:the_cpu_0|M_control_rd_data[2] Z1_M_control_rd_data[2] = AMPP_FUNCTION(F1__clk1, Z1_E_control_rd_data_without_mmu_regs[2], N1_data_out, Z1_A_stall); --Z1_A_rot[1] is system_0:u0|cpu_0:the_cpu_0|A_rot[1] Z1_A_rot[1] = AMPP_FUNCTION(F1__clk1, Z1L612, N1_data_out, Z1_A_stall); --Z1L709 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4668 Z1L709 = AMPP_FUNCTION(Z1_A_rot_mask[1], Z1_A_rot_sel_fill0); --Z1L710 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4669 Z1L710 = AMPP_FUNCTION(Z1_A_rot[1], Z1_A_rot_fill_bit, Z1L709, Z1_A_rot_pass0); --Z1L720 is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[1]~1065 Z1L720 = AMPP_FUNCTION(Z1_d_readdata_d1[1], Z1_d_readdata_d1[17], Z1_A_ld_align_sh16); --Z1L2275 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[1]~414 Z1L2275 = AMPP_FUNCTION(FC1_q_a[1], Z1_M_alu_result[1], Z1_M_ctrl_mem); --Z1_M_control_rd_data[1] is system_0:u0|cpu_0:the_cpu_0|M_control_rd_data[1] Z1_M_control_rd_data[1] = AMPP_FUNCTION(F1__clk1, Z1_E_control_rd_data_without_mmu_regs[1], N1_data_out, Z1_A_stall); --Z1_A_rot[0] is system_0:u0|cpu_0:the_cpu_0|A_rot[0] Z1_A_rot[0] = AMPP_FUNCTION(F1__clk1, Z1L613, N1_data_out, Z1_A_stall); --Z1L711 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4670 Z1L711 = AMPP_FUNCTION(Z1_A_rot_mask[0], Z1_A_rot_sel_fill0); --Z1L712 is system_0:u0|cpu_0:the_cpu_0|A_shift_rot_result~4671 Z1L712 = AMPP_FUNCTION(Z1_A_rot[0], Z1_A_rot_fill_bit, Z1L711, Z1_A_rot_pass0); --Z1L717 is system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[0]~1064 Z1L717 = AMPP_FUNCTION(Z1_d_readdata_d1[0], Z1_d_readdata_d1[16], Z1_A_ld_align_sh16); --Z1L2274 is system_0:u0|cpu_0:the_cpu_0|M_inst_result[0]~415 Z1L2274 = AMPP_FUNCTION(FC1_q_a[0], Z1_M_alu_result[0], Z1_M_ctrl_mem); --Z1_M_control_rd_data[0] is system_0:u0|cpu_0:the_cpu_0|M_control_rd_data[0] Z1_M_control_rd_data[0] = AMPP_FUNCTION(F1__clk1, Z1_E_control_rd_data_without_mmu_regs[0], N1_data_out, Z1_A_stall); --FD1L38Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[19]~reg0 FD1L38Q = AMPP_FUNCTION(A1L336, FD1_sr[19], FD1L104); --FD1L37Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[18]~reg0 FD1L37Q = AMPP_FUNCTION(A1L336, FD1_sr[18], FD1L104); --XC1L15 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|probepresent~7 XC1L15 = AMPP_FUNCTION(FD1L38Q, XC1_probepresent, FD1L37Q); --FD1_sr[21] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[21] FD1_sr[21] = AMPP_FUNCTION(A1L333, FD1L129, D1_CLRN_SIGNAL, FD1L81); --FD1_sr[20] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[20] FD1_sr[20] = AMPP_FUNCTION(A1L333, FD1L131, D1_CLRN_SIGNAL, FD1L81); --CB1L14 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_address[8]~117 CB1L14 = CB1L30 & Z1_d_address[10] # !CB1L30 & (Z1_ic_fill_line[5]); --CB1L8 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_address[2]~118 CB1L8 = CB1L30 & Z1_d_address[4] # !CB1L30 & (Z1_ic_fill_ap_offset[2]); --CB1L7 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_address[1]~119 CB1L7 = CB1L30 & Z1_d_address[3] # !CB1L30 & (Z1_ic_fill_ap_offset[1]); --CB1L12 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_address[6]~120 CB1L12 = CB1L30 & Z1_d_address[8] # !CB1L30 & (Z1_ic_fill_line[3]); --UC1L10 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_reg_00_addressed~67 UC1L10 = AMPP_FUNCTION(CB1L14, CB1L8, CB1L7, CB1L12); --CB1L10 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_address[4]~121 CB1L10 = CB1L30 & Z1_d_address[6] # !CB1L30 & (Z1_ic_fill_line[1]); --CB1L11 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_address[5]~122 CB1L11 = CB1L30 & Z1_d_address[7] # !CB1L30 & (Z1_ic_fill_line[2]); --CB1L13 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_address[7]~123 CB1L13 = CB1L30 & Z1_d_address[9] # !CB1L30 & (Z1_ic_fill_line[4]); --CB1L9 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_address[3]~124 CB1L9 = CB1L30 & Z1_d_address[5] # !CB1L30 & (Z1_ic_fill_line[0]); --UC1L11 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_reg_00_addressed~68 UC1L11 = AMPP_FUNCTION(CB1L10, CB1L11, CB1L13, CB1L9); --CB1L6 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_address[0]~125 CB1L6 = CB1L30 & Z1_d_address[2] # !CB1L30 & (Z1_ic_fill_ap_offset[0]); --UC1L12 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_reg_00_addressed~69 UC1L12 = AMPP_FUNCTION(UC1L10, UC1L11, CB1L6); --ED1L107 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|comb~25 ED1L107 = AMPP_FUNCTION(Z1_d_write, Z1_hbreak_enabled, CB1L30); --UC1L15 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_single_step_mode~7 UC1L15 = AMPP_FUNCTION(Z1_d_writedata[3], UC1_oci_single_step_mode, UC1L12, ED1L107); --JE1_stage_3 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|stage_3 JE1_stage_3 = DFFEAS(JE1L30, F1__clk1, , , HE1L17, , , , ); --JE1L29 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|p2_stage_2~10 JE1L29 = JE1_full_3 & JE1_stage_3 # !JE1_full_3 & (JB1L16); --G6_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:2:S_IRF|Q[0] G6_Q[0] = AMPP_FUNCTION(A1L333, G6L3, D1_CLRN_SIGNAL); --G4L3 is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[0]~184 G4L3 = AMPP_FUNCTION(G6_Q[0], G3_Q[0], G2_Q[0]); --M1_dffe1a[2] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|dffe1a[2] M1_dffe1a[2] = AMPP_FUNCTION(A1L333, M1_w_anode28w[3], D1_CLRN_SIGNAL, D1L6); --D1L30 is sld_hub:sld_hub_inst|IRF_ENABLE[2]~124 D1L30 = AMPP_FUNCTION(G9_Q[0], M1_dffe1a[2], G8_Q[1], G2_Q[0]); --D1L15 is sld_hub:sld_hub_inst|GEN_SHADOW_IRF~18 D1L15 = AMPP_FUNCTION(D1_OK_TO_UPDATE_IR_Q, L1_state[5]); --G4L4 is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[0]~185 G4L4 = AMPP_FUNCTION(G4L3, G4_Q[0], D1L30, D1L15); --D1L34 is sld_hub:sld_hub_inst|IRSR_D[4]~30 D1L34 = AMPP_FUNCTION(L1_state[4], G3_Q[5]); --M1_w_anode38w[3] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|w_anode38w[3] M1_w_anode38w[3] = AMPP_FUNCTION(G3_Q[1], G3_Q[2], D1L39, G3_Q[3]); --D1L33 is sld_hub:sld_hub_inst|IRSR_D[3]~31 D1L33 = AMPP_FUNCTION(L1_state[4], G3_Q[4]); --G3L11 is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5]~1172 G3L11 = AMPP_FUNCTION(G3_Q[6], G3_Q[5], L1_state[4], D1_jtag_debug_mode_usr1); --FD1L18Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|ir_out[1]~reg0 FD1L18Q = AMPP_FUNCTION(A1L333, Z1_hbreak_enabled, D1_CLRN_SIGNAL); --G3L6 is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1]~1173 G3L6 = AMPP_FUNCTION(FD1L18Q, M1_dffe1a[3], G3_Q[6], G3_Q[4]); --D1L43 is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q~56 D1L43 = AMPP_FUNCTION(D1_jtag_debug_mode_usr1, D1_OK_TO_UPDATE_IR_Q, L1_state[4], L1_state[8]); --H1L30 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~1838 H1L30 = AMPP_FUNCTION(H1_word_counter[1], D1_jtag_debug_mode_usr1, L1_state[8], L1_state[4]); --H1L31 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~1839 H1L31 = AMPP_FUNCTION(H1_word_counter[3], H1_word_counter[0], H1_word_counter[2]); --H1_WORD_SR[2] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[2] H1_WORD_SR[2] = AMPP_FUNCTION(A1L333, H1L36, H1L26); --H1L32 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~1840 H1L32 = AMPP_FUNCTION(H1L25, H1L30, H1L31, H1_WORD_SR[2]); --H1L4 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~899 H1L4 = AMPP_FUNCTION(H1_word_counter[0], GND); --H1L5 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~900 H1L5 = AMPP_FUNCTION(H1_word_counter[0]); --H1L7 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[1]~901 H1L7 = AMPP_FUNCTION(H1_word_counter[1], GND, H1L5); --H1L8 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[1]~902 H1L8 = AMPP_FUNCTION(H1_word_counter[1], H1L5); --H1L10 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[2]~903 H1L10 = AMPP_FUNCTION(H1_word_counter[2], GND, H1L8); --H1L11 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[2]~904 H1L11 = AMPP_FUNCTION(H1_word_counter[2], H1L8); --H1L33 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~1841 H1L33 = AMPP_FUNCTION(H1_word_counter[1], H1_word_counter[0], H1_word_counter[2]); --H1L16 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[4]~905 H1L16 = AMPP_FUNCTION(H1_word_counter[3], H1L33, H1_word_counter[4], H1_clear_signal); --H1L17 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[4]~906 H1L17 = AMPP_FUNCTION(L1_state[4], L1_state[3], D1_jtag_debug_mode_usr0, H1_clear_signal); --H1L13 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[3]~907 H1L13 = AMPP_FUNCTION(H1_word_counter[3], GND, H1L11); --H1L14 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[3]~908 H1L14 = AMPP_FUNCTION(H1_word_counter[3], H1L11); --H1L18 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[4]~909 H1L18 = AMPP_FUNCTION(H1_word_counter[4], H1L14); --D1L13 is sld_hub:sld_hub_inst|Equal~187 D1L13 = AMPP_FUNCTION(D1L10, D1L11, K1_dffs[1], K1_dffs[0]); --D1L32 is sld_hub:sld_hub_inst|IRSR_D[2]~32 D1L32 = AMPP_FUNCTION(L1_state[4], G3_Q[3]); --ED1_MonDReg[0] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[0] ED1_MonDReg[0] = AMPP_FUNCTION(F1__clk1, ED1L65, D1_CLRN_SIGNAL, ED1L33); --VC1_break_readreg[0] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[0] VC1_break_readreg[0] = AMPP_FUNCTION(F1__clk1, VC1L35, D1_CLRN_SIGNAL, VC1L26); --FD1L122 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4759 FD1L122 = AMPP_FUNCTION(ED1_MonDReg[0], FD1_ir[0], FD1_ir[1], VC1_break_readreg[0]); --FD1_sr[2] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[2] FD1_sr[2] = AMPP_FUNCTION(A1L333, FD1L133, D1_CLRN_SIGNAL, FD1L118); --FD1L123 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4760 FD1L123 = AMPP_FUNCTION(FD1L122, FD1_sr[2], FD1L7); --FD1L44Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[25]~reg0 FD1L44Q = AMPP_FUNCTION(A1L336, FD1_sr[25], FD1L104); --XC1L11 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_ready~121 XC1L11 = AMPP_FUNCTION(FD1L196, FD1L44Q); --XC1L12 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_ready~122 XC1L12 = AMPP_FUNCTION(UC1L12, ED1L107, FD1L196); --XC1L13 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_ready~123 XC1L13 = AMPP_FUNCTION(Z1_d_writedata[0], XC1_monitor_ready, XC1L11, XC1L12); --D1L40 is sld_hub:sld_hub_inst|jtag_debug_mode~171 D1L40 = AMPP_FUNCTION(L1_state[12], A1L335, L1_state[2]); --L1_state[15] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15] L1_state[15] = AMPP_FUNCTION(A1L333, L1L29, !A1L335); --D1L41 is sld_hub:sld_hub_inst|jtag_debug_mode~172 D1L41 = AMPP_FUNCTION(D1L39, D1_jtag_debug_mode, D1L40, L1_state[15]); --M1_dffe1a[1] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|dffe1a[1] M1_dffe1a[1] = AMPP_FUNCTION(A1L333, M1_w_anode18w[3], D1_CLRN_SIGNAL, D1L6); --D1L1 is sld_hub:sld_hub_inst|BROADCAST_ENA~28 D1L1 = AMPP_FUNCTION(L1_state[8], D1_OK_TO_UPDATE_IR_Q, M1_dffe1a[2], M1_dffe1a[1]); --G2L3 is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]~71 G2L3 = AMPP_FUNCTION(M1_dffe1a[1], G2_Q[0], G9_Q[0], D1L1); --FD1_st_shiftdr is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_shiftdr FD1_st_shiftdr = AMPP_FUNCTION(A1L333, FD1L105, !A1L336); --FD1L191Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updatedr~100 FD1L191Q = AMPP_FUNCTION(A1L333, FD1L190, !A1L336); --FD1L192 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updatedr~101 FD1L192 = AMPP_FUNCTION(FD1L104, A1L336, FD1L191Q, FD1L190); --FD1L12 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|in_between_shiftdr_and_updatedr~80 FD1L12 = AMPP_FUNCTION(FD1_st_shiftdr, FD1_in_between_shiftdr_and_updatedr, FD1L192); --VD1_td_shift[2] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[2] VD1_td_shift[2] = AMPP_FUNCTION(A1L333, VD1L64, G4_Q[0], D1_CLRN_SIGNAL, VD1L66, !L1_state[4], VD1L57); --VD1_write_stalled is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|write_stalled VD1_write_stalled = AMPP_FUNCTION(A1L333, VD1L104, D1_CLRN_SIGNAL, VD1L94); --VD1L61 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[1]~683 VD1L61 = AMPP_FUNCTION(VD1_td_shift[2], VD1_write_stalled, VD1_count[9]); --VD1L66 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[2]~1334 VD1L66 = AMPP_FUNCTION(G4_Q[0], L1_state[4], VD1L81); --VD1_rvalid0 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rvalid0 VD1_rvalid0 = AMPP_FUNCTION(F1__clk1, VD1L46, N1_data_out); --VD1_count[8] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[8] VD1_count[8] = AMPP_FUNCTION(A1L333, VD1L15, D1_CLRN_SIGNAL, VD1L57); --VD1L58 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[0]~1335 VD1L58 = AMPP_FUNCTION(altera_internal_jtag, VD1_state); --VD1L59 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[0]~1336 VD1L59 = AMPP_FUNCTION(L1_state[4], VD1_count[8], VD1L58, G4_Q[0]); --VD1_count[0] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[0] VD1_count[0] = AMPP_FUNCTION(A1L333, VD1L16, D1_CLRN_SIGNAL, VD1L57); --VD1L14 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count~215 VD1L14 = AMPP_FUNCTION(L1_state[4], VD1_count[0]); --VD1L48 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|state~191 VD1L48 = AMPP_FUNCTION(D1L17, VD1L1, G4_Q[0], VD1_state); --VD1L49 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|state~192 VD1L49 = AMPP_FUNCTION(VD1L48, VD1_state, L1_state[3], VD1L1); --VD1L90 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|user_saw_rvalid~130 VD1L90 = AMPP_FUNCTION(L1_state[4], VD1_state, VD1L1, G4_Q[0]); --VD1L91 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|user_saw_rvalid~131 VD1L91 = AMPP_FUNCTION(VD1_td_shift[0], VD1_user_saw_rvalid, VD1_count[0], VD1L90); --VD1_td_shift[10] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[10] VD1_td_shift[10] = AMPP_FUNCTION(A1L333, D1L17, D1_CLRN_SIGNAL, VD1L57); --VD1_rdata[7] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[7] VD1_rdata[7] = AMPP_FUNCTION(F1__clk1, FE1_q_b[7], N1_data_out, VD1L28); --VD1L84 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1337 VD1L84 = AMPP_FUNCTION(VD1_td_shift[10], VD1_rdata[7], VD1_count[9]); --BE2_b_full is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|b_full BE2_b_full = DFFEAS(BE2L6, F1__clk1, , , , , , , ); --L1_state[11] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[11] L1_state[11] = AMPP_FUNCTION(A1L333, L1L26, A1L335); --L1_state[9] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9] L1_state[9] = AMPP_FUNCTION(A1L333, D1L44); --L1_tms_cnt[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[2] L1_tms_cnt[2] = AMPP_FUNCTION(A1L333, L1L40, !A1L335); --L1_tms_cnt[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] L1_tms_cnt[0] = AMPP_FUNCTION(A1L333, L1L38); --L1_tms_cnt[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[1] L1_tms_cnt[1] = AMPP_FUNCTION(A1L333, L1L39, !A1L335); --L1L30 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~435 L1L30 = AMPP_FUNCTION(L1_tms_cnt[2], L1_tms_cnt[0], L1_tms_cnt[1]); --L1L31 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~436 L1L31 = AMPP_FUNCTION(A1L335, L1_state[9], L1L30, L1_state[0]); --L1_state[10] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[10] L1_state[10] = AMPP_FUNCTION(A1L333, L1L25); --L1L32 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~437 L1L32 = AMPP_FUNCTION(A1L335, L1_state[11], L1_state[10]); --L1L33 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~438 L1L33 = AMPP_FUNCTION(A1L335, L1_state[8], L1_state[1], L1_state[15]); --L1_state[6] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[6] L1_state[6] = AMPP_FUNCTION(A1L333, L1L22, A1L335); --L1L23 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~17 L1L23 = AMPP_FUNCTION(A1L335, L1_state[6]); --L1L21 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~14 L1L21 = AMPP_FUNCTION(A1L335, L1_state[3], L1_state[4]); --Z1_M_st_data[16] is system_0:u0|cpu_0:the_cpu_0|M_st_data[16] Z1_M_st_data[16] = AMPP_FUNCTION(F1__clk1, Z1L1879, N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_2[0] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_2[0] Z1_A_dc_latest_data_byte_2[0] = AMPP_FUNCTION(F1__clk1, Z1L3181, N1_data_out, Z1_dc_data_wr_byte_2); --Z1_A_dc_latest_data_valid_byte_2 is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_valid_byte_2 Z1_A_dc_latest_data_valid_byte_2 = AMPP_FUNCTION(F1__clk1, Z1L71, N1_data_out); --Z1L2239 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_2[0]~480 Z1L2239 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_2[0], FC1_q_a[16], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_2); --Z1_M_st_data[17] is system_0:u0|cpu_0:the_cpu_0|M_st_data[17] Z1_M_st_data[17] = AMPP_FUNCTION(F1__clk1, Z1L1880, N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_2[1] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_2[1] Z1_A_dc_latest_data_byte_2[1] = AMPP_FUNCTION(F1__clk1, Z1L3182, N1_data_out, Z1_dc_data_wr_byte_2); --Z1L2240 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_2[1]~481 Z1L2240 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_2[1], FC1_q_a[17], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_2); --Z1_M_st_data[18] is system_0:u0|cpu_0:the_cpu_0|M_st_data[18] Z1_M_st_data[18] = AMPP_FUNCTION(F1__clk1, Z1L1881, N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_2[2] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_2[2] Z1_A_dc_latest_data_byte_2[2] = AMPP_FUNCTION(F1__clk1, Z1L3183, N1_data_out, Z1_dc_data_wr_byte_2); --Z1L2241 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_2[2]~482 Z1L2241 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_2[2], FC1_q_a[18], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_2); --Z1_M_st_data[19] is system_0:u0|cpu_0:the_cpu_0|M_st_data[19] Z1_M_st_data[19] = AMPP_FUNCTION(F1__clk1, Z1L1882, N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_2[3] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_2[3] Z1_A_dc_latest_data_byte_2[3] = AMPP_FUNCTION(F1__clk1, Z1L3184, N1_data_out, Z1_dc_data_wr_byte_2); --Z1L2242 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_2[3]~483 Z1L2242 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_2[3], FC1_q_a[19], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_2); --Z1_M_st_data[20] is system_0:u0|cpu_0:the_cpu_0|M_st_data[20] Z1_M_st_data[20] = AMPP_FUNCTION(F1__clk1, Z1L1883, N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_2[4] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_2[4] Z1_A_dc_latest_data_byte_2[4] = AMPP_FUNCTION(F1__clk1, Z1L3185, N1_data_out, Z1_dc_data_wr_byte_2); --Z1L2243 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_2[4]~484 Z1L2243 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_2[4], FC1_q_a[20], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_2); --Z1_M_st_data[21] is system_0:u0|cpu_0:the_cpu_0|M_st_data[21] Z1_M_st_data[21] = AMPP_FUNCTION(F1__clk1, Z1L1884, N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_2[5] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_2[5] Z1_A_dc_latest_data_byte_2[5] = AMPP_FUNCTION(F1__clk1, Z1L3186, N1_data_out, Z1_dc_data_wr_byte_2); --Z1L2244 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_2[5]~485 Z1L2244 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_2[5], FC1_q_a[21], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_2); --Z1_M_st_data[22] is system_0:u0|cpu_0:the_cpu_0|M_st_data[22] Z1_M_st_data[22] = AMPP_FUNCTION(F1__clk1, Z1L1885, N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_2[6] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_2[6] Z1_A_dc_latest_data_byte_2[6] = AMPP_FUNCTION(F1__clk1, Z1L3187, N1_data_out, Z1_dc_data_wr_byte_2); --Z1L2245 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_2[6]~486 Z1L2245 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_2[6], FC1_q_a[22], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_2); --Z1_M_st_data[23] is system_0:u0|cpu_0:the_cpu_0|M_st_data[23] Z1_M_st_data[23] = AMPP_FUNCTION(F1__clk1, Z1L1886, N1_data_out, Z1_A_stall); --Z1_A_dc_latest_data_byte_2[7] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_2[7] Z1_A_dc_latest_data_byte_2[7] = AMPP_FUNCTION(F1__clk1, Z1L3188, N1_data_out, Z1_dc_data_wr_byte_2); --Z1L2246 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_2[7]~487 Z1L2246 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_2[7], FC1_q_a[23], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_2); --Z1_M_st_data[24] is system_0:u0|cpu_0:the_cpu_0|M_st_data[24] Z1_M_st_data[24] = AMPP_FUNCTION(F1__clk1, Z1L2645, Z1_E_src2_reg[24], N1_data_out, Z1_E_iw[4], Z1_A_stall); --Z1_A_dc_latest_data_byte_3[0] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_3[0] Z1_A_dc_latest_data_byte_3[0] = AMPP_FUNCTION(F1__clk1, Z1L3189, N1_data_out, Z1_dc_data_wr_byte_3); --Z1_A_dc_latest_data_valid_byte_3 is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_valid_byte_3 Z1_A_dc_latest_data_valid_byte_3 = AMPP_FUNCTION(F1__clk1, Z1L73, N1_data_out); --Z1L2247 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_3[0]~480 Z1L2247 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_3[0], FC1_q_a[24], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_3); --Z1_M_st_data[25] is system_0:u0|cpu_0:the_cpu_0|M_st_data[25] Z1_M_st_data[25] = AMPP_FUNCTION(F1__clk1, Z1L2648, Z1_E_src2_reg[25], N1_data_out, Z1_E_iw[4], Z1_A_stall); --Z1_A_dc_latest_data_byte_3[1] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_3[1] Z1_A_dc_latest_data_byte_3[1] = AMPP_FUNCTION(F1__clk1, Z1L3190, N1_data_out, Z1_dc_data_wr_byte_3); --Z1L2248 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_3[1]~481 Z1L2248 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_3[1], FC1_q_a[25], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_3); --Z1_M_st_data[26] is system_0:u0|cpu_0:the_cpu_0|M_st_data[26] Z1_M_st_data[26] = AMPP_FUNCTION(F1__clk1, Z1L2651, Z1_E_src2_reg[26], N1_data_out, Z1_E_iw[4], Z1_A_stall); --Z1_A_dc_latest_data_byte_3[2] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_3[2] Z1_A_dc_latest_data_byte_3[2] = AMPP_FUNCTION(F1__clk1, Z1L3191, N1_data_out, Z1_dc_data_wr_byte_3); --Z1L2249 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_3[2]~482 Z1L2249 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_3[2], FC1_q_a[26], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_3); --Z1_M_st_data[27] is system_0:u0|cpu_0:the_cpu_0|M_st_data[27] Z1_M_st_data[27] = AMPP_FUNCTION(F1__clk1, Z1L2654, Z1_E_src2_reg[27], N1_data_out, Z1_E_iw[4], Z1_A_stall); --Z1_A_dc_latest_data_byte_3[3] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_3[3] Z1_A_dc_latest_data_byte_3[3] = AMPP_FUNCTION(F1__clk1, Z1L3192, N1_data_out, Z1_dc_data_wr_byte_3); --Z1L2250 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_3[3]~483 Z1L2250 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_3[3], FC1_q_a[27], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_3); --Z1_M_st_data[28] is system_0:u0|cpu_0:the_cpu_0|M_st_data[28] Z1_M_st_data[28] = AMPP_FUNCTION(F1__clk1, Z1L2657, Z1_E_src2_reg[28], N1_data_out, Z1_E_iw[4], Z1_A_stall); --Z1_A_dc_latest_data_byte_3[4] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_3[4] Z1_A_dc_latest_data_byte_3[4] = AMPP_FUNCTION(F1__clk1, Z1L3193, N1_data_out, Z1_dc_data_wr_byte_3); --Z1L2251 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_3[4]~484 Z1L2251 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_3[4], FC1_q_a[28], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_3); --Z1_M_st_data[29] is system_0:u0|cpu_0:the_cpu_0|M_st_data[29] Z1_M_st_data[29] = AMPP_FUNCTION(F1__clk1, Z1L2660, Z1_E_src2_reg[29], N1_data_out, Z1_E_iw[4], Z1_A_stall); --Z1_A_dc_latest_data_byte_3[5] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_3[5] Z1_A_dc_latest_data_byte_3[5] = AMPP_FUNCTION(F1__clk1, Z1L3194, N1_data_out, Z1_dc_data_wr_byte_3); --Z1L2252 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_3[5]~485 Z1L2252 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_3[5], FC1_q_a[29], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_3); --Z1_M_st_data[30] is system_0:u0|cpu_0:the_cpu_0|M_st_data[30] Z1_M_st_data[30] = AMPP_FUNCTION(F1__clk1, Z1L2663, Z1_E_src2_reg[30], N1_data_out, Z1_E_iw[4], Z1_A_stall); --Z1_A_dc_latest_data_byte_3[6] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_3[6] Z1_A_dc_latest_data_byte_3[6] = AMPP_FUNCTION(F1__clk1, Z1L3195, N1_data_out, Z1_dc_data_wr_byte_3); --Z1L2253 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_3[6]~486 Z1L2253 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_3[6], FC1_q_a[30], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_3); --Z1_M_st_data[31] is system_0:u0|cpu_0:the_cpu_0|M_st_data[31] Z1_M_st_data[31] = AMPP_FUNCTION(F1__clk1, Z1L2666, Z1_E_src2_reg[31], N1_data_out, Z1_E_iw[4], Z1_A_stall); --Z1_A_dc_latest_data_byte_3[7] is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_byte_3[7] Z1_A_dc_latest_data_byte_3[7] = AMPP_FUNCTION(F1__clk1, Z1L3196, N1_data_out, Z1_dc_data_wr_byte_3); --Z1L2254 is system_0:u0|cpu_0:the_cpu_0|M_dc_victim_rd_data_byte_3[7]~487 Z1L2254 = AMPP_FUNCTION(Z1_A_dc_latest_data_byte_3[7], FC1_q_a[31], Z1_M_A_dc_latest_line_match, Z1_A_dc_latest_data_valid_byte_3); --XC1_monitor_error is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_error XC1_monitor_error = AMPP_FUNCTION(F1__clk1, XC1L6); --RD1_q_a[0] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[0] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[0] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[0], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L24, ED1_MonDReg[0], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[0] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[0] RD1_q_b[0] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[0], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L24, ED1_MonDReg[0], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AC1L1 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|readdata[0]~1369 AC1L1 = AMPP_FUNCTION(UC1L12, XC1_monitor_error, RD1_q_a[0], CB1L14); --AC1L2 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|readdata[0]~1370 AC1L2 = AMPP_FUNCTION(CB1L6, CB1L14, UC1L10, UC1L11); --AB1L207 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~25 AB1L207 = AC1L1 # AC1L2 & !UC1_oci_ienable[0] # !CB1_cpu_0_data_master_requests_cpu_0_jtag_debug_module; --AB1_dbs_16_reg_segment_0[0] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[0] AB1_dbs_16_reg_segment_0[0] = DFFEAS(AB1L291, F1__clk1, N1_data_out, , AB1L2, , , , ); --AB1L211 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~281 AB1L211 = Z1_d_address[19] # AB1_dbs_16_reg_segment_0[0] # !LB1L10 # !LB1L1; --AB1_registered_cpu_0_data_master_readdata[0] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[0] AB1_registered_cpu_0_data_master_readdata[0] = DFFEAS(AB1L308, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_0[0] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_0[0] AB1_dbs_8_reg_segment_0[0] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[0], F1__clk1, N1_data_out, , AB1L3, , , , ); --AB1L47 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[0]~2651 AB1L47 = AB1_registered_cpu_0_data_master_readdata[0] & (AB1_dbs_8_reg_segment_0[0] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[0] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_0[0] # !MB1L38); --LE1_readdata[0] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[0] LE1_readdata[0] = DFFEAS(LE1L35, F1__clk1, N1_data_out, , , , , Z1_d_address[4], ); --PB1_cpu_0_data_master_qualified_request_uart_0_s1 is system_0:u0|uart_0_s1_arbitrator:the_uart_0_s1|cpu_0_data_master_qualified_request_uart_0_s1 PB1_cpu_0_data_master_qualified_request_uart_0_s1 = Q1L1 & !Z1_d_address[6] & (Z1_d_write # Z1_d_read); --AB1L48 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[0]~2652 AB1L48 = AB1L211 & AB1L47 & (LE1_readdata[0] # !PB1_cpu_0_data_master_qualified_request_uart_0_s1); --X1_readdata[0] is system_0:u0|Switch:the_Switch|readdata[0] X1_readdata[0] = DFFEAS(X1_read_mux_out[0], F1__clk1, N1_data_out, , , , , , ); --AB1L221 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~2653 AB1L221 = !Q1L1 # !Z1_d_address[6] # !Z1_d_address[4] # !Z1_d_read; --GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave is system_0:u0|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave|cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave = LB1L10 & Z1_d_address[6] & GB1L6 & GB1L7; --AB1L49 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[0]~2654 AB1L49 = AB1_registered_cpu_0_data_master_readdata[0] & (X1_readdata[0] # AB1L221) # !AB1_registered_cpu_0_data_master_readdata[0] & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (X1_readdata[0] # AB1L221); --P1_readdata[0] is system_0:u0|KEY:the_KEY|readdata[0] P1_readdata[0] = DFFEAS(P1L34, F1__clk1, N1_data_out, , , P1L28, , , Z1_d_address[2]); --Q1_cpu_0_data_master_requests_KEY_s1 is system_0:u0|KEY_s1_arbitrator:the_KEY_s1|cpu_0_data_master_requests_KEY_s1 Q1_cpu_0_data_master_requests_KEY_s1 = LB1L10 & Z1_d_address[6] & Q1L1 & !Z1_d_address[4]; --AB1L50 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[0]~2655 AB1L50 = AB1L48 & AB1L49 & (P1_readdata[0] # !Q1_cpu_0_data_master_requests_KEY_s1); --DB1L1 is system_0:u0|epcs_controller:the_epcs_controller|epcs_select~61 DB1L1 = EB1L26 & Z1_d_address[9] # !EB1L26 & (Z1_ic_fill_line[4] & EB1L7); --UD1_q_a[0] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[0] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[0]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[0]_PORT_A_address_reg = DFFE(UD1_q_a[0]_PORT_A_address, UD1_q_a[0]_clock_0, , , ); UD1_q_a[0]_clock_0 = F1__clk1; UD1_q_a[0]_PORT_A_data_out = MEMORY(, , UD1_q_a[0]_PORT_A_address_reg, , , , , , UD1_q_a[0]_clock_0, , , , , ); UD1_q_a[0] = UD1_q_a[0]_PORT_A_data_out[0]; --SD1_data_to_cpu[0] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0] SD1_data_to_cpu[0] = DFFEAS(SD1L141, F1__clk1, N1_data_out, , , , , , ); --BB1L160 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~2948 BB1L160 = DB1L1 & (!SD1_data_to_cpu[0]) # !DB1L1 & !UD1_q_a[0]; --AB1_cpu_0_data_master_readdata[0] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[0] AB1_cpu_0_data_master_readdata[0] = AB1L207 & AB1L50 & (!BB1L160 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --Z1_M_ctrl_ld_initd_flushd_flushda is system_0:u0|cpu_0:the_cpu_0|M_ctrl_ld_initd_flushd_flushda Z1_M_ctrl_ld_initd_flushd_flushda = AMPP_FUNCTION(F1__clk1, Z1L1531, N1_data_out, Z1_A_stall); --FD1L75 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[14]~4761 FD1L75 = AMPP_FUNCTION(FD1_ir[1], FD1L7, FD1_ir[0]); --FD1L76 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[14]~4762 FD1L76 = AMPP_FUNCTION(FD1_ir[0], FD1L104, A1L332, FD1_in_between_shiftdr_and_updatedr); --FD1L77 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[14]~4763 FD1L77 = AMPP_FUNCTION(FD1L7, FD1_ir[1], FD1_ir[0]); --FD1_sr[23] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[23] FD1_sr[23] = AMPP_FUNCTION(A1L333, FD1L135, D1_CLRN_SIGNAL, FD1L81); --FD1L78 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[14]~4764 FD1L78 = AMPP_FUNCTION(A1L332, FD1_ir[0], FD1_in_between_shiftdr_and_updatedr, FD1L104); --ED1_MonDReg[21] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[21] ED1_MonDReg[21] = AMPP_FUNCTION(F1__clk1, ED1L66, D1_CLRN_SIGNAL, ED1L33); --FD1L124 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4765 FD1L124 = AMPP_FUNCTION(FD1L77, FD1_sr[23], FD1L78, ED1_MonDReg[21]); --VC1_break_readreg[21] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[21] VC1_break_readreg[21] = AMPP_FUNCTION(F1__clk1, VC1L36, D1_CLRN_SIGNAL, VC1L26); --FD1L125 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4766 FD1L125 = AMPP_FUNCTION(FD1L75, FD1L76, FD1L124, VC1_break_readreg[21]); --FD1L98 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[32]~4767 FD1L98 = AMPP_FUNCTION(FD1_ir[1], FD1_ir[0]); --FD1L81 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[16]~4768 FD1L81 = AMPP_FUNCTION(FD1L195, FD1L98, FD1L7, FD1L105); --M1_dffe1a[7] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|dffe1a[7] M1_dffe1a[7] = AMPP_FUNCTION(A1L333, M1_w_anode78w[3], D1_CLRN_SIGNAL, D1L6); --D1L2 is sld_hub:sld_hub_inst|BROADCAST_ENA~29 D1L2 = AMPP_FUNCTION(L1_state[8], D1_OK_TO_UPDATE_IR_Q); --G1L3 is sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0]~58 G1L3 = AMPP_FUNCTION(G1_Q[0], M1_dffe1a[7], D1L2, G2_Q[0]); --L1L18 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5 L1L18 = AMPP_FUNCTION(L1_state[8], L1_state[1], L1_state[15], L1_state[0]); --FD1L126 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4769 FD1L126 = AMPP_FUNCTION(FD1_ir[1], FD1L7, FD1_ir[0], XC1_monitor_error); --FD1L127 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4770 FD1L127 = AMPP_FUNCTION(FD1L7, FD1_ir[0], FD1L126, FD1_sr[35]); --G7_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[1] G7_Q[1] = AMPP_FUNCTION(A1L333, G3_Q[1], D1_CLRN_SIGNAL, D1L14); --D1L27 is sld_hub:sld_hub_inst|IRF_D[1][1]~40 D1L27 = AMPP_FUNCTION(G7_Q[1], G3_Q[1], G2_Q[0]); --D1L31 is sld_hub:sld_hub_inst|IRF_ENABLE[2]~125 D1L31 = AMPP_FUNCTION(G9_Q[0], G2_Q[0], M1_dffe1a[2]); --D1L29 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~126 D1L29 = AMPP_FUNCTION(D1L15, D1L31, G8_Q[0], G2_Q[0]); --G7_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[0] G7_Q[0] = AMPP_FUNCTION(A1L333, G3_Q[0], D1_CLRN_SIGNAL, D1L14); --D1L26 is sld_hub:sld_hub_inst|IRF_D[1][0]~41 D1L26 = AMPP_FUNCTION(G7_Q[0], G3_Q[0], G2_Q[0]); --FD1L107 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4771 FD1L107 = AMPP_FUNCTION(A1L332, FD1_ir[1], FD1_ir[0], FD1L104); --FD1_sr[36] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[36] FD1_sr[36] = AMPP_FUNCTION(A1L333, ~GND, FD1_sr[37], D1_CLRN_SIGNAL, FD1L7, FD1L119); --FD1_DRsize.100 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.100 FD1_DRsize.100 = AMPP_FUNCTION(A1L333, FD1L4, D1_CLRN_SIGNAL, FD1L195); --FD1L108 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4772 FD1L108 = AMPP_FUNCTION(FD1L107, altera_internal_jtag, FD1_sr[36], FD1_DRsize.100); --FD1L109 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4773 FD1L109 = AMPP_FUNCTION(FD1L108, Z1_hbreak_enabled, FD1L102, FD1L105); --FD1L110 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4774 FD1L110 = AMPP_FUNCTION(FD1L105, FD1L7, FD1L98, FD1L195); --RD1_q_a[1] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[1] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[1] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[1], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L24, ED1_MonDReg[1], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[1] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[1] RD1_q_b[1] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[1], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L24, ED1_MonDReg[1], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AC1L3 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|readdata[1]~1371 AC1L3 = AMPP_FUNCTION(XC1_monitor_ready, UC1L12, RD1_q_a[1], CB1L14); --AB1L208 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~26 AB1L208 = AC1L3 # AC1L2 & !UC1_oci_ienable[1] # !CB1_cpu_0_data_master_requests_cpu_0_jtag_debug_module; --AB1_dbs_16_reg_segment_0[1] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[1] AB1_dbs_16_reg_segment_0[1] = DFFEAS(AB1L292, F1__clk1, N1_data_out, , AB1L2, , , , ); --AB1L212 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~282 AB1L212 = Z1_d_address[19] # AB1_dbs_16_reg_segment_0[1] # !LB1L10 # !LB1L1; --AB1_registered_cpu_0_data_master_readdata[1] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[1] AB1_registered_cpu_0_data_master_readdata[1] = DFFEAS(AB1L310, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_0[1] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_0[1] AB1_dbs_8_reg_segment_0[1] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[1], F1__clk1, N1_data_out, , AB1L3, , , , ); --AB1L52 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[1]~2656 AB1L52 = AB1_registered_cpu_0_data_master_readdata[1] & (AB1_dbs_8_reg_segment_0[1] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[1] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_0[1] # !MB1L38); --LE1_readdata[1] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[1] LE1_readdata[1] = DFFEAS(LE1L37, F1__clk1, N1_data_out, , , , , , ); --AB1L53 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[1]~2657 AB1L53 = AB1L212 & AB1L52 & (LE1_readdata[1] # !PB1_cpu_0_data_master_qualified_request_uart_0_s1); --X1_readdata[1] is system_0:u0|Switch:the_Switch|readdata[1] X1_readdata[1] = DFFEAS(X1_read_mux_out[1], F1__clk1, N1_data_out, , , , , , ); --AB1L54 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[1]~2658 AB1L54 = AB1_registered_cpu_0_data_master_readdata[1] & (AB1L221 # X1_readdata[1]) # !AB1_registered_cpu_0_data_master_readdata[1] & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (AB1L221 # X1_readdata[1]); --P1_readdata[1] is system_0:u0|KEY:the_KEY|readdata[1] P1_readdata[1] = DFFEAS(P1L37, F1__clk1, N1_data_out, , , P1L29, , , Z1_d_address[2]); --AB1L55 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[1]~2659 AB1L55 = AB1L53 & AB1L54 & (P1_readdata[1] # !Q1_cpu_0_data_master_requests_KEY_s1); --UD1_q_a[1] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[1] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[1]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[1]_PORT_A_address_reg = DFFE(UD1_q_a[1]_PORT_A_address, UD1_q_a[1]_clock_0, , , ); UD1_q_a[1]_clock_0 = F1__clk1; UD1_q_a[1]_PORT_A_data_out = MEMORY(, , UD1_q_a[1]_PORT_A_address_reg, , , , , , UD1_q_a[1]_clock_0, , , , , ); UD1_q_a[1] = UD1_q_a[1]_PORT_A_data_out[0]; --SD1_data_to_cpu[1] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[1] SD1_data_to_cpu[1] = DFFEAS(SD1L143, F1__clk1, N1_data_out, , , , , , ); --BB1L161 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~2949 BB1L161 = DB1L1 & (!SD1_data_to_cpu[1]) # !DB1L1 & !UD1_q_a[1]; --AB1_cpu_0_data_master_readdata[1] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[1] AB1_cpu_0_data_master_readdata[1] = AB1L208 & AB1L55 & (!BB1L161 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --XC1_monitor_go is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_go XC1_monitor_go = AMPP_FUNCTION(F1__clk1, XC1L9); --RD1_q_a[2] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[2] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[2] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[2], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L24, ED1_MonDReg[2], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[2] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[2] RD1_q_b[2] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[2], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L24, ED1_MonDReg[2], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AC1L4 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|readdata[2]~1372 AC1L4 = AMPP_FUNCTION(UC1L12, XC1_monitor_go, RD1_q_a[2], CB1L14); --AB1L209 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~27 AB1L209 = AC1L4 # AC1L2 & !UC1_oci_ienable[2] # !CB1_cpu_0_data_master_requests_cpu_0_jtag_debug_module; --AB1_dbs_16_reg_segment_0[2] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[2] AB1_dbs_16_reg_segment_0[2] = DFFEAS(AB1L293, F1__clk1, N1_data_out, , AB1L2, , , , ); --AB1L213 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~283 AB1L213 = Z1_d_address[19] # AB1_dbs_16_reg_segment_0[2] # !LB1L10 # !LB1L1; --AB1_registered_cpu_0_data_master_readdata[2] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[2] AB1_registered_cpu_0_data_master_readdata[2] = DFFEAS(AB1L312, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_0[2] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_0[2] AB1_dbs_8_reg_segment_0[2] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[2], F1__clk1, N1_data_out, , AB1L3, , , , ); --AB1L57 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[2]~2660 AB1L57 = AB1_registered_cpu_0_data_master_readdata[2] & (AB1_dbs_8_reg_segment_0[2] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[2] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_0[2] # !MB1L38); --LE1_readdata[2] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[2] LE1_readdata[2] = DFFEAS(LE1L39, F1__clk1, N1_data_out, , , , , , ); --AB1L58 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[2]~2661 AB1L58 = AB1L213 & AB1L57 & (LE1_readdata[2] # !PB1_cpu_0_data_master_qualified_request_uart_0_s1); --X1_readdata[2] is system_0:u0|Switch:the_Switch|readdata[2] X1_readdata[2] = DFFEAS(X1_read_mux_out[2], F1__clk1, N1_data_out, , , , , , ); --AB1L59 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[2]~2662 AB1L59 = AB1_registered_cpu_0_data_master_readdata[2] & (AB1L221 # X1_readdata[2]) # !AB1_registered_cpu_0_data_master_readdata[2] & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (AB1L221 # X1_readdata[2]); --P1_readdata[2] is system_0:u0|KEY:the_KEY|readdata[2] P1_readdata[2] = DFFEAS(P1L40, F1__clk1, N1_data_out, , , P1L30, , , Z1_d_address[2]); --AB1L60 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[2]~2663 AB1L60 = AB1L58 & AB1L59 & (P1_readdata[2] # !Q1_cpu_0_data_master_requests_KEY_s1); --UD1_q_a[2] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[2] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[2]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[2]_PORT_A_address_reg = DFFE(UD1_q_a[2]_PORT_A_address, UD1_q_a[2]_clock_0, , , ); UD1_q_a[2]_clock_0 = F1__clk1; UD1_q_a[2]_PORT_A_data_out = MEMORY(, , UD1_q_a[2]_PORT_A_address_reg, , , , , , UD1_q_a[2]_clock_0, , , , , ); UD1_q_a[2] = UD1_q_a[2]_PORT_A_data_out[0]; --SD1_data_to_cpu[2] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[2] SD1_data_to_cpu[2] = DFFEAS(SD1L145, F1__clk1, N1_data_out, , , , , , ); --BB1L162 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~2950 BB1L162 = DB1L1 & (!SD1_data_to_cpu[2]) # !DB1L1 & !UD1_q_a[2]; --AB1_cpu_0_data_master_readdata[2] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[2] AB1_cpu_0_data_master_readdata[2] = AB1L209 & AB1L60 & (!BB1L162 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --RD1_q_a[3] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[3] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[3] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[3], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L24, ED1_MonDReg[3], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[3] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[3] RD1_q_b[3] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[3], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L24, ED1_MonDReg[3], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AC1L5 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|readdata[3]~1373 AC1L5 = AMPP_FUNCTION(UC1_oci_single_step_mode, UC1L12, RD1_q_a[3], CB1L14); --AB1L210 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~28 AB1L210 = AC1L5 # AC1L2 & !UC1_oci_ienable[3] # !CB1_cpu_0_data_master_requests_cpu_0_jtag_debug_module; --AB1_dbs_16_reg_segment_0[3] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[3] AB1_dbs_16_reg_segment_0[3] = DFFEAS(AB1L294, F1__clk1, N1_data_out, , AB1L2, , , , ); --AB1L214 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~284 AB1L214 = Z1_d_address[19] # AB1_dbs_16_reg_segment_0[3] # !LB1L10 # !LB1L1; --AB1_registered_cpu_0_data_master_readdata[3] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[3] AB1_registered_cpu_0_data_master_readdata[3] = DFFEAS(AB1L314, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_0[3] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_0[3] AB1_dbs_8_reg_segment_0[3] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[3], F1__clk1, N1_data_out, , AB1L3, , , , ); --AB1L62 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[3]~2664 AB1L62 = AB1_registered_cpu_0_data_master_readdata[3] & (AB1_dbs_8_reg_segment_0[3] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[3] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_0[3] # !MB1L38); --LE1_readdata[3] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[3] LE1_readdata[3] = DFFEAS(LE1L41, F1__clk1, N1_data_out, , , , , , ); --AB1L63 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[3]~2665 AB1L63 = AB1L214 & AB1L62 & (LE1_readdata[3] # !PB1_cpu_0_data_master_qualified_request_uart_0_s1); --X1_readdata[3] is system_0:u0|Switch:the_Switch|readdata[3] X1_readdata[3] = DFFEAS(X1_read_mux_out[3], F1__clk1, N1_data_out, , , , , , ); --AB1L64 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[3]~2666 AB1L64 = AB1_registered_cpu_0_data_master_readdata[3] & (AB1L221 # X1_readdata[3]) # !AB1_registered_cpu_0_data_master_readdata[3] & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (AB1L221 # X1_readdata[3]); --P1_readdata[3] is system_0:u0|KEY:the_KEY|readdata[3] P1_readdata[3] = DFFEAS(P1L43, F1__clk1, N1_data_out, , , P1L31, , , Z1_d_address[2]); --AB1L65 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[3]~2667 AB1L65 = AB1L63 & AB1L64 & (P1_readdata[3] # !Q1_cpu_0_data_master_requests_KEY_s1); --UD1_q_a[3] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[3] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[3]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[3]_PORT_A_address_reg = DFFE(UD1_q_a[3]_PORT_A_address, UD1_q_a[3]_clock_0, , , ); UD1_q_a[3]_clock_0 = F1__clk1; UD1_q_a[3]_PORT_A_data_out = MEMORY(, , UD1_q_a[3]_PORT_A_address_reg, , , , , , UD1_q_a[3]_clock_0, , , , , ); UD1_q_a[3] = UD1_q_a[3]_PORT_A_data_out[0]; --SD1_data_to_cpu[3] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[3] SD1_data_to_cpu[3] = DFFEAS(SD1L148, F1__clk1, N1_data_out, , , , , , ); --BB1L163 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~2951 BB1L163 = DB1L1 & (!SD1_data_to_cpu[3]) # !DB1L1 & !UD1_q_a[3]; --AB1_cpu_0_data_master_readdata[3] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[3] AB1_cpu_0_data_master_readdata[3] = AB1L210 & AB1L65 & (!BB1L163 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --AB1_registered_cpu_0_data_master_readdata[4] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[4] AB1_registered_cpu_0_data_master_readdata[4] = DFFEAS(AB1L316, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_0[4] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_0[4] AB1_dbs_8_reg_segment_0[4] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[4], F1__clk1, N1_data_out, , AB1L3, , , , ); --AB1L67 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[4]~2668 AB1L67 = AB1_registered_cpu_0_data_master_readdata[4] & (AB1_dbs_8_reg_segment_0[4] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[4] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_0[4] # !MB1L38); --AB1_dbs_16_reg_segment_0[4] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[4] AB1_dbs_16_reg_segment_0[4] = DFFEAS(AB1L295, F1__clk1, N1_data_out, , AB1L2, , , , ); --AB1L68 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[4]~2669 AB1L68 = AB1L67 & (AB1_dbs_16_reg_segment_0[4] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --X1_readdata[4] is system_0:u0|Switch:the_Switch|readdata[4] X1_readdata[4] = DFFEAS(X1_read_mux_out[4], F1__clk1, N1_data_out, , , , , , ); --AB1L69 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[4]~2670 AB1L69 = AB1L68 & !Q1_cpu_0_data_master_requests_KEY_s1 & (AB1L221 # X1_readdata[4]); --LE1_readdata[4] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[4] LE1_readdata[4] = DFFEAS(LE1L43, F1__clk1, N1_data_out, , , , , , ); --AB1L70 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[4]~2671 AB1L70 = AB1_registered_cpu_0_data_master_readdata[4] & (LE1_readdata[4] # !PB1_cpu_0_data_master_qualified_request_uart_0_s1) # !AB1_registered_cpu_0_data_master_readdata[4] & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (LE1_readdata[4] # !PB1_cpu_0_data_master_qualified_request_uart_0_s1); --UD1_q_a[4] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[4] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[4]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[4]_PORT_A_address_reg = DFFE(UD1_q_a[4]_PORT_A_address, UD1_q_a[4]_clock_0, , , ); UD1_q_a[4]_clock_0 = F1__clk1; UD1_q_a[4]_PORT_A_data_out = MEMORY(, , UD1_q_a[4]_PORT_A_address_reg, , , , , , UD1_q_a[4]_clock_0, , , , , ); UD1_q_a[4] = UD1_q_a[4]_PORT_A_data_out[0]; --SD1_data_to_cpu[4] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[4] SD1_data_to_cpu[4] = DFFEAS(SD1L151, F1__clk1, N1_data_out, , , , , , ); --BB1L164 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~2952 BB1L164 = DB1L1 & (!SD1_data_to_cpu[4]) # !DB1L1 & !UD1_q_a[4]; --AB1L71 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[4]~2672 AB1L71 = AB1L69 & AB1L70 & (!BB1L164 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --RD1_q_a[4] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[4] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[4] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[4], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L24, ED1_MonDReg[4], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[4] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[4] RD1_q_b[4] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[4], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L24, ED1_MonDReg[4], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --UC1L13 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_reg_01_addressed~28 UC1L13 = AMPP_FUNCTION(CB1L6, UC1L10, UC1L11); --AB1L222 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~2673 AB1L222 = CB1_cpu_0_data_master_requests_cpu_0_jtag_debug_module & (!UC1L13 # !CB1L14); --AB1_cpu_0_data_master_readdata[4] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[4] AB1_cpu_0_data_master_readdata[4] = AB1L71 & (RD1_q_a[4] & !CB1L14 # !AB1L222); --AB1_registered_cpu_0_data_master_readdata[5] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[5] AB1_registered_cpu_0_data_master_readdata[5] = DFFEAS(AB1L318, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_0[5] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_0[5] AB1_dbs_8_reg_segment_0[5] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[5], F1__clk1, N1_data_out, , AB1L3, , , , ); --AB1L73 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[5]~2674 AB1L73 = AB1_registered_cpu_0_data_master_readdata[5] & (AB1_dbs_8_reg_segment_0[5] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[5] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_0[5] # !MB1L38); --AB1_dbs_16_reg_segment_0[5] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[5] AB1_dbs_16_reg_segment_0[5] = DFFEAS(AB1L296, F1__clk1, N1_data_out, , AB1L2, , , , ); --AB1L74 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[5]~2675 AB1L74 = AB1L73 & (AB1_dbs_16_reg_segment_0[5] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --X1_readdata[5] is system_0:u0|Switch:the_Switch|readdata[5] X1_readdata[5] = DFFEAS(X1_read_mux_out[5], F1__clk1, N1_data_out, , , , , , ); --AB1L75 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[5]~2676 AB1L75 = AB1L74 & !Q1_cpu_0_data_master_requests_KEY_s1 & (AB1L221 # X1_readdata[5]); --LE1_readdata[5] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[5] LE1_readdata[5] = DFFEAS(LE1L45, F1__clk1, N1_data_out, , , , , , ); --AB1L76 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[5]~2677 AB1L76 = AB1_registered_cpu_0_data_master_readdata[5] & (LE1_readdata[5] # !PB1_cpu_0_data_master_qualified_request_uart_0_s1) # !AB1_registered_cpu_0_data_master_readdata[5] & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (LE1_readdata[5] # !PB1_cpu_0_data_master_qualified_request_uart_0_s1); --UD1_q_a[5] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[5] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[5]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[5]_PORT_A_address_reg = DFFE(UD1_q_a[5]_PORT_A_address, UD1_q_a[5]_clock_0, , , ); UD1_q_a[5]_clock_0 = F1__clk1; UD1_q_a[5]_PORT_A_data_out = MEMORY(, , UD1_q_a[5]_PORT_A_address_reg, , , , , , UD1_q_a[5]_clock_0, , , , , ); UD1_q_a[5] = UD1_q_a[5]_PORT_A_data_out[0]; --SD1_data_to_cpu[5] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[5] SD1_data_to_cpu[5] = DFFEAS(SD1L155, F1__clk1, N1_data_out, , , , , , ); --BB1L165 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~2953 BB1L165 = DB1L1 & (!SD1_data_to_cpu[5]) # !DB1L1 & !UD1_q_a[5]; --AB1L77 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[5]~2678 AB1L77 = AB1L75 & AB1L76 & (!BB1L165 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --RD1_q_a[5] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[5] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[5] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[5], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L24, ED1_MonDReg[5], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[5] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[5] RD1_q_b[5] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[5], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L24, ED1_MonDReg[5], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AB1_cpu_0_data_master_readdata[5] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[5] AB1_cpu_0_data_master_readdata[5] = AB1L77 & (RD1_q_a[5] & !CB1L14 # !AB1L222); --AB1_registered_cpu_0_data_master_readdata[6] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[6] AB1_registered_cpu_0_data_master_readdata[6] = DFFEAS(AB1L320, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_0[6] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_0[6] AB1_dbs_8_reg_segment_0[6] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[6], F1__clk1, N1_data_out, , AB1L3, , , , ); --AB1L79 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[6]~2679 AB1L79 = AB1_registered_cpu_0_data_master_readdata[6] & (AB1_dbs_8_reg_segment_0[6] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[6] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_0[6] # !MB1L38); --AB1_dbs_16_reg_segment_0[6] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[6] AB1_dbs_16_reg_segment_0[6] = DFFEAS(AB1L297, F1__clk1, N1_data_out, , AB1L2, , , , ); --AB1L80 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[6]~2680 AB1L80 = AB1L79 & (AB1_dbs_16_reg_segment_0[6] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --X1_readdata[6] is system_0:u0|Switch:the_Switch|readdata[6] X1_readdata[6] = DFFEAS(X1_read_mux_out[6], F1__clk1, N1_data_out, , , , , , ); --AB1L81 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[6]~2681 AB1L81 = AB1L80 & !Q1_cpu_0_data_master_requests_KEY_s1 & (AB1L221 # X1_readdata[6]); --LE1_readdata[6] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[6] LE1_readdata[6] = DFFEAS(LE1L47, F1__clk1, N1_data_out, , , , , , ); --AB1L82 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[6]~2682 AB1L82 = AB1_registered_cpu_0_data_master_readdata[6] & (LE1_readdata[6] # !PB1_cpu_0_data_master_qualified_request_uart_0_s1) # !AB1_registered_cpu_0_data_master_readdata[6] & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (LE1_readdata[6] # !PB1_cpu_0_data_master_qualified_request_uart_0_s1); --UD1_q_a[6] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[6] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[6]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[6]_PORT_A_address_reg = DFFE(UD1_q_a[6]_PORT_A_address, UD1_q_a[6]_clock_0, , , ); UD1_q_a[6]_clock_0 = F1__clk1; UD1_q_a[6]_PORT_A_data_out = MEMORY(, , UD1_q_a[6]_PORT_A_address_reg, , , , , , UD1_q_a[6]_clock_0, , , , , ); UD1_q_a[6] = UD1_q_a[6]_PORT_A_data_out[0]; --SD1_data_to_cpu[6] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[6] SD1_data_to_cpu[6] = DFFEAS(SD1L158, F1__clk1, N1_data_out, , , , , , ); --BB1L166 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~2954 BB1L166 = DB1L1 & (!SD1_data_to_cpu[6]) # !DB1L1 & !UD1_q_a[6]; --AB1L83 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[6]~2683 AB1L83 = AB1L81 & AB1L82 & (!BB1L166 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --RD1_q_a[6] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[6] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[6] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[6], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L24, ED1_MonDReg[6], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[6] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[6] RD1_q_b[6] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[6], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L24, ED1_MonDReg[6], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AB1_cpu_0_data_master_readdata[6] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[6] AB1_cpu_0_data_master_readdata[6] = AB1L83 & (RD1_q_a[6] & !CB1L14 # !AB1L222); --AB1_registered_cpu_0_data_master_readdata[7] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[7] AB1_registered_cpu_0_data_master_readdata[7] = DFFEAS(AB1L322, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_0[7] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_0[7] AB1_dbs_8_reg_segment_0[7] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[7], F1__clk1, N1_data_out, , AB1L3, , , , ); --AB1L85 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[7]~2684 AB1L85 = AB1_registered_cpu_0_data_master_readdata[7] & (AB1_dbs_8_reg_segment_0[7] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[7] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_0[7] # !MB1L38); --AB1_dbs_16_reg_segment_0[7] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[7] AB1_dbs_16_reg_segment_0[7] = DFFEAS(AB1L298, F1__clk1, N1_data_out, , AB1L2, , , , ); --AB1L86 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[7]~2685 AB1L86 = AB1L85 & (AB1_dbs_16_reg_segment_0[7] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --X1_readdata[7] is system_0:u0|Switch:the_Switch|readdata[7] X1_readdata[7] = DFFEAS(X1_read_mux_out[7], F1__clk1, N1_data_out, , , , , , ); --AB1L87 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[7]~2686 AB1L87 = AB1L86 & !Q1_cpu_0_data_master_requests_KEY_s1 & (AB1L221 # X1_readdata[7]); --LE1_readdata[7] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[7] LE1_readdata[7] = DFFEAS(LE1L49, F1__clk1, N1_data_out, , , , , , ); --AB1L88 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[7]~2687 AB1L88 = AB1_registered_cpu_0_data_master_readdata[7] & (LE1_readdata[7] # !PB1_cpu_0_data_master_qualified_request_uart_0_s1) # !AB1_registered_cpu_0_data_master_readdata[7] & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (LE1_readdata[7] # !PB1_cpu_0_data_master_qualified_request_uart_0_s1); --UD1_q_a[7] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[7] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[7]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[7]_PORT_A_address_reg = DFFE(UD1_q_a[7]_PORT_A_address, UD1_q_a[7]_clock_0, , , ); UD1_q_a[7]_clock_0 = F1__clk1; UD1_q_a[7]_PORT_A_data_out = MEMORY(, , UD1_q_a[7]_PORT_A_address_reg, , , , , , UD1_q_a[7]_clock_0, , , , , ); UD1_q_a[7] = UD1_q_a[7]_PORT_A_data_out[0]; --SD1_data_to_cpu[7] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[7] SD1_data_to_cpu[7] = DFFEAS(SD1L161, F1__clk1, N1_data_out, , , , , , ); --BB1L167 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~2955 BB1L167 = DB1L1 & (!SD1_data_to_cpu[7]) # !DB1L1 & !UD1_q_a[7]; --AB1L89 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[7]~2688 AB1L89 = AB1L87 & AB1L88 & (!BB1L167 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --RD1_q_a[7] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[7] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[7] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[7], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L24, ED1_MonDReg[7], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[7] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[7] RD1_q_b[7] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[7], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L24, ED1_MonDReg[7], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AB1_cpu_0_data_master_readdata[7] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[7] AB1_cpu_0_data_master_readdata[7] = AB1L89 & (RD1_q_a[7] & !CB1L14 # !AB1L222); --AB1_registered_cpu_0_data_master_readdata[8] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[8] AB1_registered_cpu_0_data_master_readdata[8] = DFFEAS(AB1L323, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_1[0] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_1[0] AB1_dbs_8_reg_segment_1[0] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[0], F1__clk1, N1_data_out, , AB1L4, , , , ); --AB1L91 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[8]~2689 AB1L91 = AB1_registered_cpu_0_data_master_readdata[8] & (AB1_dbs_8_reg_segment_1[0] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[8] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_1[0] # !MB1L38); --AB1_dbs_16_reg_segment_0[8] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[8] AB1_dbs_16_reg_segment_0[8] = DFFEAS(AB1L299, F1__clk1, N1_data_out, , AB1L2, , , , ); --AB1L92 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[8]~2690 AB1L92 = AB1L91 & (AB1_dbs_16_reg_segment_0[8] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --X1_readdata[8] is system_0:u0|Switch:the_Switch|readdata[8] X1_readdata[8] = DFFEAS(X1_read_mux_out[8], F1__clk1, N1_data_out, , , , , , ); --AB1L93 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[8]~2691 AB1L93 = AB1L92 & !Q1_cpu_0_data_master_requests_KEY_s1 & (AB1L221 # X1_readdata[8]); --LE1_readdata[8] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[8] LE1_readdata[8] = DFFEAS(LE1_selected_read_data[8], F1__clk1, N1_data_out, , , , , , ); --AB1L94 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[8]~2692 AB1L94 = AB1_registered_cpu_0_data_master_readdata[8] & (LE1_readdata[8] # !PB1_cpu_0_data_master_qualified_request_uart_0_s1) # !AB1_registered_cpu_0_data_master_readdata[8] & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (LE1_readdata[8] # !PB1_cpu_0_data_master_qualified_request_uart_0_s1); --UD1_q_a[8] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[8] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[8]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[8]_PORT_A_address_reg = DFFE(UD1_q_a[8]_PORT_A_address, UD1_q_a[8]_clock_0, , , ); UD1_q_a[8]_clock_0 = F1__clk1; UD1_q_a[8]_PORT_A_data_out = MEMORY(, , UD1_q_a[8]_PORT_A_address_reg, , , , , , UD1_q_a[8]_clock_0, , , , , ); UD1_q_a[8] = UD1_q_a[8]_PORT_A_data_out[0]; --SD1_data_to_cpu[8] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[8] SD1_data_to_cpu[8] = DFFEAS(SD1L164, F1__clk1, N1_data_out, , , , , , ); --BB1L168 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~2956 BB1L168 = DB1L1 & (!SD1_data_to_cpu[8]) # !DB1L1 & !UD1_q_a[8]; --AB1L95 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[8]~2693 AB1L95 = AB1L93 & AB1L94 & (!BB1L168 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --RD1_q_a[8] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[8] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[8] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[8], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L25, ED1_MonDReg[8], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[8] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[8] RD1_q_b[8] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[8], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L25, ED1_MonDReg[8], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AB1_cpu_0_data_master_readdata[8] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[8] AB1_cpu_0_data_master_readdata[8] = AB1L95 & (RD1_q_a[8] & !CB1L14 # !AB1L222); --AB1_registered_cpu_0_data_master_readdata[9] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[9] AB1_registered_cpu_0_data_master_readdata[9] = DFFEAS(AB1L324, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_1[1] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_1[1] AB1_dbs_8_reg_segment_1[1] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[1], F1__clk1, N1_data_out, , AB1L4, , , , ); --AB1L97 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[9]~2694 AB1L97 = AB1_registered_cpu_0_data_master_readdata[9] & (AB1_dbs_8_reg_segment_1[1] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[9] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_1[1] # !MB1L38); --AB1_dbs_16_reg_segment_0[9] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[9] AB1_dbs_16_reg_segment_0[9] = DFFEAS(AB1L300, F1__clk1, N1_data_out, , AB1L2, , , , ); --AB1L98 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[9]~2695 AB1L98 = AB1L97 & (AB1_dbs_16_reg_segment_0[9] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --X1_readdata[9] is system_0:u0|Switch:the_Switch|readdata[9] X1_readdata[9] = DFFEAS(X1_read_mux_out[9], F1__clk1, N1_data_out, , , , , , ); --AB1L99 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[9]~2696 AB1L99 = AB1L98 & !Q1_cpu_0_data_master_requests_KEY_s1 & (AB1L221 # X1_readdata[9]); --LE1_readdata[9] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[9] LE1_readdata[9] = DFFEAS(LE1L58, F1__clk1, N1_data_out, , , , , , ); --AB1L100 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[9]~2697 AB1L100 = AB1_registered_cpu_0_data_master_readdata[9] & (LE1_readdata[9] # !PB1_cpu_0_data_master_qualified_request_uart_0_s1) # !AB1_registered_cpu_0_data_master_readdata[9] & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (LE1_readdata[9] # !PB1_cpu_0_data_master_qualified_request_uart_0_s1); --UD1_q_a[9] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[9] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[9]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[9]_PORT_A_address_reg = DFFE(UD1_q_a[9]_PORT_A_address, UD1_q_a[9]_clock_0, , , ); UD1_q_a[9]_clock_0 = F1__clk1; UD1_q_a[9]_PORT_A_data_out = MEMORY(, , UD1_q_a[9]_PORT_A_address_reg, , , , , , UD1_q_a[9]_clock_0, , , , , ); UD1_q_a[9] = UD1_q_a[9]_PORT_A_data_out[0]; --SD1_data_to_cpu[9] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[9] SD1_data_to_cpu[9] = DFFEAS(SD1L167, F1__clk1, N1_data_out, , , , , , ); --BB1L169 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~2957 BB1L169 = DB1L1 & (!SD1_data_to_cpu[9]) # !DB1L1 & !UD1_q_a[9]; --AB1L101 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[9]~2698 AB1L101 = AB1L99 & AB1L100 & (!BB1L169 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --RD1_q_a[9] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[9] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[9] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[9], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L25, ED1_MonDReg[9], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[9] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[9] RD1_q_b[9] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[9], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L25, ED1_MonDReg[9], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AB1_cpu_0_data_master_readdata[9] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[9] AB1_cpu_0_data_master_readdata[9] = AB1L101 & (RD1_q_a[9] & !CB1L14 # !AB1L222); --AB1L127 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[16]~2699 AB1L127 = AB1L221 & !Q1_cpu_0_data_master_requests_KEY_s1 & !PB1_cpu_0_data_master_qualified_request_uart_0_s1; --AB1_dbs_16_reg_segment_0[10] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[10] AB1_dbs_16_reg_segment_0[10] = DFFEAS(AB1L301, F1__clk1, N1_data_out, , AB1L2, , , , ); --AB1L215 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~291 AB1L215 = Z1_d_address[19] # AB1_dbs_16_reg_segment_0[10] # !LB1L10 # !LB1L1; --AB1_registered_cpu_0_data_master_readdata[10] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[10] AB1_registered_cpu_0_data_master_readdata[10] = DFFEAS(AB1L325, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_1[2] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_1[2] AB1_dbs_8_reg_segment_1[2] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[2], F1__clk1, N1_data_out, , AB1L4, , , , ); --AB1L103 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[10]~2700 AB1L103 = AB1_registered_cpu_0_data_master_readdata[10] & (AB1_dbs_8_reg_segment_1[2] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[10] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_1[2] # !MB1L38); --AB1L104 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[10]~2701 AB1L104 = AB1L215 & AB1L103 & (AB1_registered_cpu_0_data_master_readdata[10] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --UD1_q_a[10] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[10] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[10]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[10]_PORT_A_address_reg = DFFE(UD1_q_a[10]_PORT_A_address, UD1_q_a[10]_clock_0, , , ); UD1_q_a[10]_clock_0 = F1__clk1; UD1_q_a[10]_PORT_A_data_out = MEMORY(, , UD1_q_a[10]_PORT_A_address_reg, , , , , , UD1_q_a[10]_clock_0, , , , , ); UD1_q_a[10] = UD1_q_a[10]_PORT_A_data_out[0]; --SD1_data_to_cpu[10] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[10] SD1_data_to_cpu[10] = DFFEAS(SD1L175, F1__clk1, N1_data_out, , , , , , ); --BB1L170 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~2958 BB1L170 = DB1L1 & (!SD1_data_to_cpu[10]) # !DB1L1 & !UD1_q_a[10]; --AB1L105 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[10]~2702 AB1L105 = AB1L127 & AB1L104 & (!BB1L170 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --RD1_q_a[10] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[10] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[10] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[10], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L25, ED1_MonDReg[10], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[10] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[10] RD1_q_b[10] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[10], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L25, ED1_MonDReg[10], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AB1_cpu_0_data_master_readdata[10] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[10] AB1_cpu_0_data_master_readdata[10] = AB1L105 & (RD1_q_a[10] & !CB1L14 # !AB1L222); --AB1_dbs_16_reg_segment_0[11] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[11] AB1_dbs_16_reg_segment_0[11] = DFFEAS(AB1L302, F1__clk1, N1_data_out, , AB1L2, , , , ); --AB1L216 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~292 AB1L216 = Z1_d_address[19] # AB1_dbs_16_reg_segment_0[11] # !LB1L10 # !LB1L1; --AB1_registered_cpu_0_data_master_readdata[11] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[11] AB1_registered_cpu_0_data_master_readdata[11] = DFFEAS(AB1L326, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_1[3] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_1[3] AB1_dbs_8_reg_segment_1[3] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[3], F1__clk1, N1_data_out, , AB1L4, , , , ); --AB1L107 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[11]~2703 AB1L107 = AB1_registered_cpu_0_data_master_readdata[11] & (AB1_dbs_8_reg_segment_1[3] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[11] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_1[3] # !MB1L38); --AB1L108 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[11]~2704 AB1L108 = AB1L216 & AB1L107 & (AB1_registered_cpu_0_data_master_readdata[11] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --UD1_q_a[11] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[11] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[11]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[11]_PORT_A_address_reg = DFFE(UD1_q_a[11]_PORT_A_address, UD1_q_a[11]_clock_0, , , ); UD1_q_a[11]_clock_0 = F1__clk1; UD1_q_a[11]_PORT_A_data_out = MEMORY(, , UD1_q_a[11]_PORT_A_address_reg, , , , , , UD1_q_a[11]_clock_0, , , , , ); UD1_q_a[11] = UD1_q_a[11]_PORT_A_data_out[0]; --SD1_data_to_cpu[11] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[11] SD1_data_to_cpu[11] = DFFEAS(SD1L169, F1__clk1, N1_data_out, , , , , , ); --BB1L171 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~2959 BB1L171 = DB1L1 & (!SD1_data_to_cpu[11]) # !DB1L1 & !UD1_q_a[11]; --AB1L109 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[11]~2705 AB1L109 = AB1L127 & AB1L108 & (!BB1L171 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --RD1_q_a[11] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[11] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[11] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[11], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L25, ED1_MonDReg[11], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[11] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[11] RD1_q_b[11] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[11], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L25, ED1_MonDReg[11], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AB1_cpu_0_data_master_readdata[11] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[11] AB1_cpu_0_data_master_readdata[11] = AB1L109 & (RD1_q_a[11] & !CB1L14 # !AB1L222); --AB1_dbs_16_reg_segment_0[12] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[12] AB1_dbs_16_reg_segment_0[12] = DFFEAS(AB1L303, F1__clk1, N1_data_out, , AB1L2, , , , ); --AB1L217 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~293 AB1L217 = Z1_d_address[19] # AB1_dbs_16_reg_segment_0[12] # !LB1L10 # !LB1L1; --AB1_registered_cpu_0_data_master_readdata[12] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[12] AB1_registered_cpu_0_data_master_readdata[12] = DFFEAS(AB1L327, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_1[4] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_1[4] AB1_dbs_8_reg_segment_1[4] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[4], F1__clk1, N1_data_out, , AB1L4, , , , ); --AB1L111 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[12]~2706 AB1L111 = AB1_registered_cpu_0_data_master_readdata[12] & (AB1_dbs_8_reg_segment_1[4] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[12] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_1[4] # !MB1L38); --AB1L112 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[12]~2707 AB1L112 = AB1L217 & AB1L111 & (AB1_registered_cpu_0_data_master_readdata[12] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --UD1_q_a[12] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[12] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[12]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[12]_PORT_A_address_reg = DFFE(UD1_q_a[12]_PORT_A_address, UD1_q_a[12]_clock_0, , , ); UD1_q_a[12]_clock_0 = F1__clk1; UD1_q_a[12]_PORT_A_data_out = MEMORY(, , UD1_q_a[12]_PORT_A_address_reg, , , , , , UD1_q_a[12]_clock_0, , , , , ); UD1_q_a[12] = UD1_q_a[12]_PORT_A_data_out[0]; --SD1_data_to_cpu[12] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[12] SD1_data_to_cpu[12] = DFFEAS(SD1L170, F1__clk1, N1_data_out, , , , , , ); --BB1L172 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~2960 BB1L172 = DB1L1 & (!SD1_data_to_cpu[12]) # !DB1L1 & !UD1_q_a[12]; --AB1L113 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[12]~2708 AB1L113 = AB1L127 & AB1L112 & (!BB1L172 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --RD1_q_a[12] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[12] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[12] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[12], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L25, ED1_MonDReg[12], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[12] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[12] RD1_q_b[12] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[12], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L25, ED1_MonDReg[12], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AB1_cpu_0_data_master_readdata[12] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[12] AB1_cpu_0_data_master_readdata[12] = AB1L113 & (RD1_q_a[12] & !CB1L14 # !AB1L222); --AB1_dbs_16_reg_segment_0[13] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[13] AB1_dbs_16_reg_segment_0[13] = DFFEAS(AB1L304, F1__clk1, N1_data_out, , AB1L2, , , , ); --AB1L218 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~294 AB1L218 = Z1_d_address[19] # AB1_dbs_16_reg_segment_0[13] # !LB1L10 # !LB1L1; --AB1_registered_cpu_0_data_master_readdata[13] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[13] AB1_registered_cpu_0_data_master_readdata[13] = DFFEAS(AB1L328, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_1[5] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_1[5] AB1_dbs_8_reg_segment_1[5] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[5], F1__clk1, N1_data_out, , AB1L4, , , , ); --AB1L115 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[13]~2709 AB1L115 = AB1_registered_cpu_0_data_master_readdata[13] & (AB1_dbs_8_reg_segment_1[5] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[13] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_1[5] # !MB1L38); --AB1L116 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[13]~2710 AB1L116 = AB1L218 & AB1L115 & (AB1_registered_cpu_0_data_master_readdata[13] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --UD1_q_a[13] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[13] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[13]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[13]_PORT_A_address_reg = DFFE(UD1_q_a[13]_PORT_A_address, UD1_q_a[13]_clock_0, , , ); UD1_q_a[13]_clock_0 = F1__clk1; UD1_q_a[13]_PORT_A_data_out = MEMORY(, , UD1_q_a[13]_PORT_A_address_reg, , , , , , UD1_q_a[13]_clock_0, , , , , ); UD1_q_a[13] = UD1_q_a[13]_PORT_A_data_out[0]; --SD1_data_to_cpu[13] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[13] SD1_data_to_cpu[13] = DFFEAS(SD1L171, F1__clk1, N1_data_out, , , , , , ); --BB1L173 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~2961 BB1L173 = DB1L1 & (!SD1_data_to_cpu[13]) # !DB1L1 & !UD1_q_a[13]; --AB1L117 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[13]~2711 AB1L117 = AB1L127 & AB1L116 & (!BB1L173 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --RD1_q_a[13] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[13] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[13] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[13], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L25, ED1_MonDReg[13], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[13] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[13] RD1_q_b[13] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[13], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L25, ED1_MonDReg[13], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AB1_cpu_0_data_master_readdata[13] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[13] AB1_cpu_0_data_master_readdata[13] = AB1L117 & (RD1_q_a[13] & !CB1L14 # !AB1L222); --AB1_dbs_16_reg_segment_0[14] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[14] AB1_dbs_16_reg_segment_0[14] = DFFEAS(AB1L305, F1__clk1, N1_data_out, , AB1L2, , , , ); --AB1L219 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~295 AB1L219 = Z1_d_address[19] # AB1_dbs_16_reg_segment_0[14] # !LB1L10 # !LB1L1; --AB1_registered_cpu_0_data_master_readdata[14] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[14] AB1_registered_cpu_0_data_master_readdata[14] = DFFEAS(AB1L329, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_1[6] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_1[6] AB1_dbs_8_reg_segment_1[6] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[6], F1__clk1, N1_data_out, , AB1L4, , , , ); --AB1L119 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[14]~2712 AB1L119 = AB1_registered_cpu_0_data_master_readdata[14] & (AB1_dbs_8_reg_segment_1[6] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[14] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_1[6] # !MB1L38); --AB1L120 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[14]~2713 AB1L120 = AB1L219 & AB1L119 & (AB1_registered_cpu_0_data_master_readdata[14] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --UD1_q_a[14] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[14] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[14]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[14]_PORT_A_address_reg = DFFE(UD1_q_a[14]_PORT_A_address, UD1_q_a[14]_clock_0, , , ); UD1_q_a[14]_clock_0 = F1__clk1; UD1_q_a[14]_PORT_A_data_out = MEMORY(, , UD1_q_a[14]_PORT_A_address_reg, , , , , , UD1_q_a[14]_clock_0, , , , , ); UD1_q_a[14] = UD1_q_a[14]_PORT_A_data_out[0]; --SD1_data_to_cpu[14] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[14] SD1_data_to_cpu[14] = DFFEAS(SD1L172, F1__clk1, N1_data_out, , , , , , ); --BB1L174 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~2962 BB1L174 = DB1L1 & (!SD1_data_to_cpu[14]) # !DB1L1 & !UD1_q_a[14]; --AB1L121 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[14]~2714 AB1L121 = AB1L127 & AB1L120 & (!BB1L174 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --RD1_q_a[14] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[14] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[14] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[14], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L25, ED1_MonDReg[14], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[14] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[14] RD1_q_b[14] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[14], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L25, ED1_MonDReg[14], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AB1_cpu_0_data_master_readdata[14] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[14] AB1_cpu_0_data_master_readdata[14] = AB1L121 & (RD1_q_a[14] & !CB1L14 # !AB1L222); --AB1_dbs_16_reg_segment_0[15] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[15] AB1_dbs_16_reg_segment_0[15] = DFFEAS(AB1L306, F1__clk1, N1_data_out, , AB1L2, , , , ); --AB1L220 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~296 AB1L220 = Z1_d_address[19] # AB1_dbs_16_reg_segment_0[15] # !LB1L10 # !LB1L1; --AB1_registered_cpu_0_data_master_readdata[15] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[15] AB1_registered_cpu_0_data_master_readdata[15] = DFFEAS(AB1L330, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_1[7] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_1[7] AB1_dbs_8_reg_segment_1[7] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[7], F1__clk1, N1_data_out, , AB1L4, , , , ); --AB1L123 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[15]~2715 AB1L123 = AB1_registered_cpu_0_data_master_readdata[15] & (AB1_dbs_8_reg_segment_1[7] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[15] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_1[7] # !MB1L38); --AB1L124 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[15]~2716 AB1L124 = AB1L220 & AB1L123 & (AB1_registered_cpu_0_data_master_readdata[15] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --UD1_q_a[15] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[15] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[15]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[15]_PORT_A_address_reg = DFFE(UD1_q_a[15]_PORT_A_address, UD1_q_a[15]_clock_0, , , ); UD1_q_a[15]_clock_0 = F1__clk1; UD1_q_a[15]_PORT_A_data_out = MEMORY(, , UD1_q_a[15]_PORT_A_address_reg, , , , , , UD1_q_a[15]_clock_0, , , , , ); UD1_q_a[15] = UD1_q_a[15]_PORT_A_data_out[0]; --SD1_data_to_cpu[15] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[15] SD1_data_to_cpu[15] = DFFEAS(SD1L173, F1__clk1, N1_data_out, , , , , , ); --BB1L175 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~2963 BB1L175 = DB1L1 & (!SD1_data_to_cpu[15]) # !DB1L1 & !UD1_q_a[15]; --AB1L125 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[15]~2717 AB1L125 = AB1L127 & AB1L124 & (!BB1L175 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --RD1_q_a[15] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[15] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[15] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[15], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L25, ED1_MonDReg[15], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[15] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[15] RD1_q_b[15] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[15], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L25, ED1_MonDReg[15], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AB1_cpu_0_data_master_readdata[15] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[15] AB1_cpu_0_data_master_readdata[15] = AB1L125 & (RD1_q_a[15] & !CB1L14 # !AB1L222); --PB1_d1_reasons_to_wait is system_0:u0|uart_0_s1_arbitrator:the_uart_0_s1|d1_reasons_to_wait PB1_d1_reasons_to_wait = DFFEAS(PB1L4, F1__clk1, N1_data_out, , , , , , ); --NE1L47 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|tx_ready~34 NE1L47 = NE1_do_load_shifter & !PB1_d1_reasons_to_wait & NE1L50 # !NE1_do_load_shifter & (NE1_tx_ready # !PB1_d1_reasons_to_wait & NE1L50); --NE1L5 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[0]~122 NE1L5 = NE1_baud_rate_counter[0] $ VCC; --NE1L6 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[0]~123 NE1L6 = CARRY(NE1_baud_rate_counter[0]); --NE1L1 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|always4~0 NE1L1 = NE1_do_load_shifter # NE1L36; --NE1L8 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[1]~124 NE1L8 = NE1_baud_rate_counter[1] & NE1L6 & VCC # !NE1_baud_rate_counter[1] & !NE1L6; --NE1L9 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[1]~125 NE1L9 = CARRY(!NE1_baud_rate_counter[1] & !NE1L6); --NE1L11 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[2]~126 NE1L11 = NE1_baud_rate_counter[2] & (GND # !NE1L9) # !NE1_baud_rate_counter[2] & (NE1L9 $ GND); --NE1L12 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[2]~127 NE1L12 = CARRY(NE1_baud_rate_counter[2] # !NE1L9); --NE1L14 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[3]~128 NE1L14 = NE1_baud_rate_counter[3] & NE1L12 & VCC # !NE1_baud_rate_counter[3] & !NE1L12; --NE1L15 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[3]~129 NE1L15 = CARRY(!NE1_baud_rate_counter[3] & !NE1L12); --NE1L17 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[4]~130 NE1L17 = NE1_baud_rate_counter[4] & (GND # !NE1L15) # !NE1_baud_rate_counter[4] & (NE1L15 $ GND); --NE1L18 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[4]~131 NE1L18 = CARRY(NE1_baud_rate_counter[4] # !NE1L15); --NE1L20 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[5]~132 NE1L20 = NE1_baud_rate_counter[5] & NE1L18 & VCC # !NE1_baud_rate_counter[5] & !NE1L18; --NE1L21 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[5]~133 NE1L21 = CARRY(!NE1_baud_rate_counter[5] & !NE1L18); --NE1L23 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[6]~134 NE1L23 = NE1_baud_rate_counter[6] & (GND # !NE1L21) # !NE1_baud_rate_counter[6] & (NE1L21 $ GND); --NE1L24 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[6]~135 NE1L24 = CARRY(NE1_baud_rate_counter[6] # !NE1L21); --NE1L26 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[7]~136 NE1L26 = NE1_baud_rate_counter[7] & NE1L24 & VCC # !NE1_baud_rate_counter[7] & !NE1L24; --NE1L27 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[7]~137 NE1L27 = CARRY(!NE1_baud_rate_counter[7] & !NE1L24); --NE1L29 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[8]~138 NE1L29 = NE1_baud_rate_counter[8] & (GND # !NE1L27) # !NE1_baud_rate_counter[8] & (NE1L27 $ GND); --NE1L30 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[8]~139 NE1L30 = CARRY(NE1_baud_rate_counter[8] # !NE1L27); --NE1L32 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|baud_rate_counter[9]~140 NE1L32 = NE1_baud_rate_counter[9] $ !NE1L30; --HB1L172 is system_0:u0|sdram_0:the_sdram_0|Select~8276 HB1L172 = HB1_i_state.010 & (!HB1_i_refs[0]) # !HB1_i_state.010 & HB1_i_state.000 & HB1_i_refs[0]; --HB1L261 is system_0:u0|sdram_0:the_sdram_0|add~420 HB1L261 = HB1_i_refs[1] & HB1_i_refs[0]; --HB1L173 is system_0:u0|sdram_0:the_sdram_0|Select~8277 HB1L173 = HB1_i_state.010 & (HB1_i_refs[2] $ HB1L261) # !HB1_i_state.010 & HB1_i_state.000 & HB1_i_refs[2]; --HB1L174 is system_0:u0|sdram_0:the_sdram_0|Select~8278 HB1L174 = HB1_i_state.010 & (HB1_i_refs[1] $ HB1_i_refs[0]) # !HB1_i_state.010 & HB1_i_state.000 & HB1_i_refs[1]; --HB1L175 is system_0:u0|sdram_0:the_sdram_0|Select~8279 HB1L175 = HB1_i_state.010 # HB1_i_state.001 # HB1_i_count[0] & !HB1L393; --HB1L176 is system_0:u0|sdram_0:the_sdram_0|Select~8280 HB1L176 = HB1L175 # HB1_i_state.011 & (HB1L7 $ HB1_i_count[0]); --HB1L386 is system_0:u0|sdram_0:the_sdram_0|rd_strobe~28 HB1L386 = HB1_m_cmd[1] & !HB1_m_cmd[0] & !HB1_m_cmd[2]; --HE1_stage_4 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|stage_4 HE1_stage_4 = DFFEAS(HE1L36, F1__clk1, , , HE1L16, , , , ); --JE1_full_4 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_4 JE1_full_4 = DFFEAS(HE1L35, F1__clk1, N1_data_out, , HE1L14, , , , ); --HE1L34 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|p3_stage_3~10 HE1L34 = JE1_full_4 & HE1_stage_4 # !JE1_full_4 & (JB1L7); --HE1L17 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|always6~1 HE1L17 = HB1_za_valid # JB1L5 & !JE1_full_3; --HE1L33 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|p3_full_3~9 HE1L33 = HB1_za_valid & (JB1L5 & JE1_full_2 # !JB1L5 & (JE1_full_4)) # !HB1_za_valid & JE1_full_2; --Z1L1056 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_rot~33 Z1L1056 = AMPP_FUNCTION(Z1_D_iw[12], Z1L1142, Z1_D_iw[13]); --Z1L1908 is system_0:u0|cpu_0:the_cpu_0|Equal~6229 Z1L1908 = AMPP_FUNCTION(Z1_D_iw[11], Z1_D_iw[16], Z1_D_iw[12], Z1L1026); --Z1_i_readdata_d1[21] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[21] Z1_i_readdata_d1[21] = AMPP_FUNCTION(F1__clk1, BB1L97, N1_data_out); --Z1_i_readdata_d1[20] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[20] Z1_i_readdata_d1[20] = AMPP_FUNCTION(F1__clk1, BB1L93, N1_data_out); --Z1_i_readdata_d1[19] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[19] Z1_i_readdata_d1[19] = AMPP_FUNCTION(F1__clk1, BB1L89, N1_data_out); --Z1_i_readdata_d1[18] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[18] Z1_i_readdata_d1[18] = AMPP_FUNCTION(F1__clk1, BB1L85, N1_data_out); --Z1_i_readdata_d1[17] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[17] Z1_i_readdata_d1[17] = AMPP_FUNCTION(F1__clk1, BB1L81, N1_data_out); --Z1_i_readdata_d1[10] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[10] Z1_i_readdata_d1[10] = AMPP_FUNCTION(F1__clk1, BB1L58, N1_data_out); --Z1_i_readdata_d1[9] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[9] Z1_i_readdata_d1[9] = AMPP_FUNCTION(F1__clk1, BB1L55, N1_data_out); --Z1_i_readdata_d1[8] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[8] Z1_i_readdata_d1[8] = AMPP_FUNCTION(F1__clk1, BB1L52, N1_data_out); --Z1L1909 is system_0:u0|cpu_0:the_cpu_0|Equal~6230 Z1L1909 = AMPP_FUNCTION(Z1_D_iw[15], Z1_D_iw[14]); --Z1L1027 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_break~28 Z1L1027 = AMPP_FUNCTION(Z1_D_iw[16], Z1L1909, Z1L1026, Z1_D_iw[12]); --Z1L1034 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_exception~164 Z1L1034 = AMPP_FUNCTION(Z1_D_iw[15], Z1_D_iw[14], Z1_D_iw[12], Z1_D_iw[11]); --Z1L1035 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_exception~165 Z1L1035 = AMPP_FUNCTION(Z1_D_iw[16], Z1L1026, Z1_D_iw[12], Z1L1034); --MB1_incoming_tri_state_bridge_0_data[3] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[3] MB1_incoming_tri_state_bridge_0_data[3] = DFFEAS(A1L103, F1__clk1, N1_data_out, , , , , , ); --HB1_za_data[11] is system_0:u0|sdram_0:the_sdram_0|za_data[11] HB1_za_data[11] = DFFEAS(A1L57, F1__clk1, N1_data_out, , , , , , ); --BB1L118 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[27]~2964 BB1L118 = MB1_incoming_tri_state_bridge_0_data[3] & (HB1_za_data[11] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !MB1_incoming_tri_state_bridge_0_data[3] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (HB1_za_data[11] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L119 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[27]~2965 BB1L119 = BB1L118 & (KE1_oDATA[11] # !LB1L14); --UD1_q_a[27] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[27] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[27]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[27]_PORT_A_address_reg = DFFE(UD1_q_a[27]_PORT_A_address, UD1_q_a[27]_clock_0, , , ); UD1_q_a[27]_clock_0 = F1__clk1; UD1_q_a[27]_PORT_A_data_out = MEMORY(, , UD1_q_a[27]_PORT_A_address_reg, , , , , , UD1_q_a[27]_clock_0, , , , , ); UD1_q_a[27] = UD1_q_a[27]_PORT_A_data_out[0]; --BB1L120 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[27]~2966 BB1L120 = BB1L119 & (UD1_q_a[27] & !DB1L1 # !EB1L29); --RD1_q_a[27] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[27] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[27] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[27], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L27, ED1_MonDReg[27], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[27] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[27] RD1_q_b[27] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[27], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L27, ED1_MonDReg[27], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --BB1L121 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[27]~2967 BB1L121 = BB1L120 & (RD1_q_a[27] & !CB1L14 # !BB1L176); --MB1_incoming_tri_state_bridge_0_data[7] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[7] MB1_incoming_tri_state_bridge_0_data[7] = DFFEAS(A1L111, F1__clk1, N1_data_out, , , , , , ); --HB1_za_data[15] is system_0:u0|sdram_0:the_sdram_0|za_data[15] HB1_za_data[15] = DFFEAS(A1L65, F1__clk1, N1_data_out, , , , , , ); --BB1L134 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[31]~2968 BB1L134 = MB1_incoming_tri_state_bridge_0_data[7] & (HB1_za_data[15] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !MB1_incoming_tri_state_bridge_0_data[7] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (HB1_za_data[15] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L135 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[31]~2969 BB1L135 = BB1L134 & (KE1_oDATA[15] # !LB1L14); --UD1_q_a[31] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[31] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[31]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[31]_PORT_A_address_reg = DFFE(UD1_q_a[31]_PORT_A_address, UD1_q_a[31]_clock_0, , , ); UD1_q_a[31]_clock_0 = F1__clk1; UD1_q_a[31]_PORT_A_data_out = MEMORY(, , UD1_q_a[31]_PORT_A_address_reg, , , , , , UD1_q_a[31]_clock_0, , , , , ); UD1_q_a[31] = UD1_q_a[31]_PORT_A_data_out[0]; --BB1L136 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[31]~2970 BB1L136 = BB1L135 & (UD1_q_a[31] & !DB1L1 # !EB1L29); --RD1_q_a[31] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[31] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[31] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[31], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L27, ED1_MonDReg[31], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[31] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[31] RD1_q_b[31] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[31], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L27, ED1_MonDReg[31], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --BB1L137 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[31]~2971 BB1L137 = BB1L136 & (RD1_q_a[31] & !CB1L14 # !BB1L176); --MB1_incoming_tri_state_bridge_0_data[4] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[4] MB1_incoming_tri_state_bridge_0_data[4] = DFFEAS(A1L105, F1__clk1, N1_data_out, , , , , , ); --HB1_za_data[12] is system_0:u0|sdram_0:the_sdram_0|za_data[12] HB1_za_data[12] = DFFEAS(A1L59, F1__clk1, N1_data_out, , , , , , ); --BB1L122 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[28]~2972 BB1L122 = MB1_incoming_tri_state_bridge_0_data[4] & (HB1_za_data[12] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !MB1_incoming_tri_state_bridge_0_data[4] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (HB1_za_data[12] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L123 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[28]~2973 BB1L123 = BB1L122 & (KE1_oDATA[12] # !LB1L14); --UD1_q_a[28] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[28] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[28]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[28]_PORT_A_address_reg = DFFE(UD1_q_a[28]_PORT_A_address, UD1_q_a[28]_clock_0, , , ); UD1_q_a[28]_clock_0 = F1__clk1; UD1_q_a[28]_PORT_A_data_out = MEMORY(, , UD1_q_a[28]_PORT_A_address_reg, , , , , , UD1_q_a[28]_clock_0, , , , , ); UD1_q_a[28] = UD1_q_a[28]_PORT_A_data_out[0]; --BB1L124 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[28]~2974 BB1L124 = BB1L123 & (UD1_q_a[28] & !DB1L1 # !EB1L29); --RD1_q_a[28] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[28] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[28] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[28], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L27, ED1_MonDReg[28], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[28] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[28] RD1_q_b[28] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[28], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L27, ED1_MonDReg[28], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --BB1L125 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[28]~2975 BB1L125 = BB1L124 & (RD1_q_a[28] & !CB1L14 # !BB1L176); --MB1_incoming_tri_state_bridge_0_data[6] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[6] MB1_incoming_tri_state_bridge_0_data[6] = DFFEAS(A1L109, F1__clk1, N1_data_out, , , , , , ); --HB1_za_data[14] is system_0:u0|sdram_0:the_sdram_0|za_data[14] HB1_za_data[14] = DFFEAS(A1L63, F1__clk1, N1_data_out, , , , , , ); --BB1L130 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[30]~2976 BB1L130 = MB1_incoming_tri_state_bridge_0_data[6] & (HB1_za_data[14] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !MB1_incoming_tri_state_bridge_0_data[6] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (HB1_za_data[14] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L131 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[30]~2977 BB1L131 = BB1L130 & (KE1_oDATA[14] # !LB1L14); --UD1_q_a[30] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[30] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[30]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[30]_PORT_A_address_reg = DFFE(UD1_q_a[30]_PORT_A_address, UD1_q_a[30]_clock_0, , , ); UD1_q_a[30]_clock_0 = F1__clk1; UD1_q_a[30]_PORT_A_data_out = MEMORY(, , UD1_q_a[30]_PORT_A_address_reg, , , , , , UD1_q_a[30]_clock_0, , , , , ); UD1_q_a[30] = UD1_q_a[30]_PORT_A_data_out[0]; --BB1L132 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[30]~2978 BB1L132 = BB1L131 & (UD1_q_a[30] & !DB1L1 # !EB1L29); --RD1_q_a[30] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[30] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[30] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[30], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L27, ED1_MonDReg[30], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[30] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[30] RD1_q_b[30] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[30], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L27, ED1_MonDReg[30], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --BB1L133 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[30]~2979 BB1L133 = BB1L132 & (RD1_q_a[30] & !CB1L14 # !BB1L176); --MB1_incoming_tri_state_bridge_0_data[5] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[5] MB1_incoming_tri_state_bridge_0_data[5] = DFFEAS(A1L107, F1__clk1, N1_data_out, , , , , , ); --HB1_za_data[13] is system_0:u0|sdram_0:the_sdram_0|za_data[13] HB1_za_data[13] = DFFEAS(A1L61, F1__clk1, N1_data_out, , , , , , ); --BB1L126 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[29]~2980 BB1L126 = MB1_incoming_tri_state_bridge_0_data[5] & (HB1_za_data[13] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !MB1_incoming_tri_state_bridge_0_data[5] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (HB1_za_data[13] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L127 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[29]~2981 BB1L127 = BB1L126 & (KE1_oDATA[13] # !LB1L14); --UD1_q_a[29] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[29] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[29]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[29]_PORT_A_address_reg = DFFE(UD1_q_a[29]_PORT_A_address, UD1_q_a[29]_clock_0, , , ); UD1_q_a[29]_clock_0 = F1__clk1; UD1_q_a[29]_PORT_A_data_out = MEMORY(, , UD1_q_a[29]_PORT_A_address_reg, , , , , , UD1_q_a[29]_clock_0, , , , , ); UD1_q_a[29] = UD1_q_a[29]_PORT_A_data_out[0]; --BB1L128 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[29]~2982 BB1L128 = BB1L127 & (UD1_q_a[29] & !DB1L1 # !EB1L29); --RD1_q_a[29] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[29] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[29] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[29], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L27, ED1_MonDReg[29], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[29] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[29] RD1_q_b[29] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[29], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L27, ED1_MonDReg[29], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --BB1L129 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[29]~2983 BB1L129 = BB1L128 & (RD1_q_a[29] & !CB1L14 # !BB1L176); --BB1L146 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~2 BB1L146 = AC1L4 # AC1L2 & !UC1_oci_ienable[2] # !CB1L28; --BB1_dbs_latent_8_reg_segment_0[2] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_0[2] BB1_dbs_latent_8_reg_segment_0[2] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[2], F1__clk1, N1_data_out, , BB1L6, , , , ); --BB1_dbs_latent_16_reg_segment_0[2] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_16_reg_segment_0[2] BB1_dbs_latent_16_reg_segment_0[2] = DFFEAS(HB1_za_data[2], F1__clk1, N1_data_out, , BB1L4, , , , ); --BB1L32 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[2]~2984 BB1L32 = BB1_dbs_latent_8_reg_segment_0[2] & (BB1_dbs_latent_16_reg_segment_0[2] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_0[2] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (BB1_dbs_latent_16_reg_segment_0[2] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1_dbs_16_reg_segment_0[2] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[2] BB1_dbs_16_reg_segment_0[2] = DFFEAS(KE1_oDATA[2], F1__clk1, N1_data_out, , BB1L5, , , , ); --BB1L33 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[2]~2985 BB1L33 = BB1L32 & (BB1_dbs_16_reg_segment_0[2] # !LB1L14); --BB1L34 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[2]~2986 BB1L34 = BB1L146 & BB1L33 & (!BB1L162 # !EB1L29); --Z1L138 is system_0:u0|cpu_0:the_cpu_0|A_ienable_reg[3]~825 Z1L138 = AMPP_FUNCTION(Z1_M_valid_from_E, Z1_M_iw[6], Z1L2670, Z1_A_stall); --Q1L2 is system_0:u0|KEY_s1_arbitrator:the_KEY_s1|Equal~64 Q1L2 = Z1_d_address[6] & Q1L1 & !Z1_d_address[4]; --P1L2 is system_0:u0|KEY:the_KEY|always1~29 P1L2 = Z1_d_address[3] & P1L1 & Q1L2 & !Z1_d_address[2]; --P1_d2_data_in[1] is system_0:u0|KEY:the_KEY|d2_data_in[1] P1_d2_data_in[1] = DFFEAS(P1_d1_data_in[1], F1__clk1, N1_data_out, , , , , , ); --P1_d1_data_in[1] is system_0:u0|KEY:the_KEY|d1_data_in[1] P1_d1_data_in[1] = DFFEAS(KEY[1], F1__clk1, N1_data_out, , , , , , ); --P1L18 is system_0:u0|KEY:the_KEY|edge_capture_wr_strobe~10 P1L18 = Z1_d_address[2] & Z1_d_address[3] & P1L1 & Q1L2; --P1L19 is system_0:u0|KEY:the_KEY|edge_capture~108 P1L19 = !P1L18 & (P1_edge_capture[1] # P1_d2_data_in[1] & !P1_d1_data_in[1]); --P1_d2_data_in[3] is system_0:u0|KEY:the_KEY|d2_data_in[3] P1_d2_data_in[3] = DFFEAS(P1_d1_data_in[3], F1__clk1, N1_data_out, , , , , , ); --P1_d1_data_in[3] is system_0:u0|KEY:the_KEY|d1_data_in[3] P1_d1_data_in[3] = DFFEAS(KEY[3], F1__clk1, N1_data_out, , , , , , ); --P1L20 is system_0:u0|KEY:the_KEY|edge_capture~109 P1L20 = !P1L18 & (P1_edge_capture[3] # P1_d2_data_in[3] & !P1_d1_data_in[3]); --P1_d2_data_in[0] is system_0:u0|KEY:the_KEY|d2_data_in[0] P1_d2_data_in[0] = DFFEAS(P1_d1_data_in[0], F1__clk1, N1_data_out, , , , , , ); --P1_d1_data_in[0] is system_0:u0|KEY:the_KEY|d1_data_in[0] P1_d1_data_in[0] = DFFEAS(KEY[0], F1__clk1, N1_data_out, , , , , , ); --P1L21 is system_0:u0|KEY:the_KEY|edge_capture~110 P1L21 = !P1L18 & (P1_edge_capture[0] # P1_d2_data_in[0] & !P1_d1_data_in[0]); --P1_d2_data_in[2] is system_0:u0|KEY:the_KEY|d2_data_in[2] P1_d2_data_in[2] = DFFEAS(P1_d1_data_in[2], F1__clk1, N1_data_out, , , , , , ); --P1_d1_data_in[2] is system_0:u0|KEY:the_KEY|d1_data_in[2] P1_d1_data_in[2] = DFFEAS(KEY[2], F1__clk1, N1_data_out, , , , , , ); --P1L22 is system_0:u0|KEY:the_KEY|edge_capture~111 P1L22 = !P1L18 & (P1_edge_capture[2] # P1_d2_data_in[2] & !P1_d1_data_in[2]); --UC1L16 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|take_action_oci_intr_mask_reg~8 UC1L16 = AMPP_FUNCTION(CB1L6, UC1L10, UC1L11, ED1L107); --SD1_iE_reg is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|iE_reg SD1_iE_reg = DFFEAS(Z1_d_writedata[8], F1__clk1, N1_data_out, , SD1_control_wr_strobe, , , , ); --SD1_ROE is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|ROE SD1_ROE = DFFEAS(SD1L27, F1__clk1, N1_data_out, , , , , , ); --SD1_iROE_reg is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|iROE_reg SD1_iROE_reg = DFFEAS(Z1_d_writedata[3], F1__clk1, N1_data_out, , SD1_control_wr_strobe, , , , ); --SD1_TOE is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|TOE SD1_TOE = DFFEAS(SD1L38, F1__clk1, N1_data_out, , , , , , ); --SD1L135 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|irq_reg~115 SD1L135 = SD1_iE_reg & (SD1_ROE # SD1_TOE) # !SD1_iE_reg & SD1_ROE & SD1_iROE_reg; --SD1_iRRDY_reg is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|iRRDY_reg SD1_iRRDY_reg = DFFEAS(Z1_d_writedata[7], F1__clk1, N1_data_out, , SD1_control_wr_strobe, , , , ); --SD1_iEOP_reg is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|iEOP_reg SD1_iEOP_reg = DFFEAS(Z1_d_writedata[9], F1__clk1, N1_data_out, , SD1_control_wr_strobe, , , , ); --SD1_EOP is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP SD1_EOP = DFFEAS(SD1L17, F1__clk1, N1_data_out, , , , , , ); --SD1_RRDY is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|RRDY SD1_RRDY = DFFEAS(SD1L29, F1__clk1, N1_data_out, , , , , , ); --SD1L136 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|irq_reg~116 SD1L136 = SD1_iRRDY_reg & (SD1_RRDY # SD1_iEOP_reg & SD1_EOP) # !SD1_iRRDY_reg & SD1_iEOP_reg & SD1_EOP; --SD1_iTRDY_reg is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|iTRDY_reg SD1_iTRDY_reg = DFFEAS(Z1_d_writedata[6], F1__clk1, N1_data_out, , SD1_control_wr_strobe, , , , ); --SD1_tx_holding_primed is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_primed SD1_tx_holding_primed = DFFEAS(SD1L228, F1__clk1, N1_data_out, , , , , , ); --SD1_transmitting is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|transmitting SD1_transmitting = DFFEAS(SD1L226, F1__clk1, N1_data_out, , , , , , ); --SD1L39 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|TRDY~0 SD1L39 = !SD1_transmitting # !SD1_tx_holding_primed; --SD1_iTOE_reg is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|iTOE_reg SD1_iTOE_reg = DFFEAS(Z1_d_writedata[4], F1__clk1, N1_data_out, , SD1_control_wr_strobe, , , , ); --SD1L137 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|irq_reg~117 SD1L137 = SD1_TOE & (SD1_iTOE_reg # SD1_iTRDY_reg & SD1L39) # !SD1_TOE & SD1_iTRDY_reg & SD1L39; --SD1L138 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|irq_reg~118 SD1L138 = SD1L135 # SD1L136 # SD1L137; --NE1_tx_overrun is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|tx_overrun NE1_tx_overrun = DFFEAS(NE1L45, F1__clk1, N1_data_out, , , , , , ); --LE1_control_reg[4] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|control_reg[4] LE1_control_reg[4] = DFFEAS(Z1_d_writedata[4], F1__clk1, N1_data_out, , LE1L15, , , , ); --LE1_control_reg[5] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|control_reg[5] LE1_control_reg[5] = DFFEAS(Z1_d_writedata[5], F1__clk1, N1_data_out, , LE1L15, , , , ); --NE1_tx_shift_empty is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|tx_shift_empty NE1_tx_shift_empty = DFFEAS(NE1L49, F1__clk1, N1_data_out, , , , , , ); --LE1L18 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|qualified_irq~115 LE1L18 = NE1_tx_overrun & (LE1_control_reg[4] # LE1_control_reg[5] & !NE1_tx_shift_empty) # !NE1_tx_overrun & (LE1_control_reg[5] & !NE1_tx_shift_empty); --ME1_framing_error is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|framing_error ME1_framing_error = DFFEAS(ME1L56, F1__clk1, N1_data_out, , , , , , ); --LE1_control_reg[1] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|control_reg[1] LE1_control_reg[1] = DFFEAS(Z1_d_writedata[1], F1__clk1, N1_data_out, , LE1L15, , , , ); --LE1_control_reg[6] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|control_reg[6] LE1_control_reg[6] = DFFEAS(Z1_d_writedata[6], F1__clk1, N1_data_out, , LE1L15, , , , ); --LE1L19 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|qualified_irq~116 LE1L19 = ME1_framing_error & (LE1_control_reg[1] # LE1_control_reg[6] & !NE1_tx_ready) # !ME1_framing_error & (LE1_control_reg[6] & !NE1_tx_ready); --LE1_control_reg[8] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|control_reg[8] LE1_control_reg[8] = DFFEAS(Z1_d_writedata[8], F1__clk1, N1_data_out, , LE1L15, , , , ); --ME1_break_detect is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|break_detect ME1_break_detect = DFFEAS(ME1L49, F1__clk1, N1_data_out, , , , , , ); --ME1_rx_overrun is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|rx_overrun ME1_rx_overrun = DFFEAS(ME1L74, F1__clk1, N1_data_out, , , , , , ); --LE1L59 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|status_reg[8]~18 LE1L59 = ME1_framing_error # ME1_break_detect # ME1_rx_overrun # NE1_tx_overrun; --LE1L20 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|qualified_irq~117 LE1L20 = LE1L18 # LE1L19 # LE1_control_reg[8] & LE1L59; --LE1_control_reg[3] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|control_reg[3] LE1_control_reg[3] = DFFEAS(Z1_d_writedata[3], F1__clk1, N1_data_out, , LE1L15, , , , ); --LE1_control_reg[2] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|control_reg[2] LE1_control_reg[2] = DFFEAS(Z1_d_writedata[2], F1__clk1, N1_data_out, , LE1L15, , , , ); --LE1L21 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|qualified_irq~118 LE1L21 = ME1_break_detect & (LE1_control_reg[2] # ME1_rx_overrun & LE1_control_reg[3]) # !ME1_break_detect & ME1_rx_overrun & LE1_control_reg[3]; --LE1_control_reg[7] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|control_reg[7] LE1_control_reg[7] = DFFEAS(Z1_d_writedata[7], F1__clk1, N1_data_out, , LE1L15, , , , ); --ME1_rx_char_ready is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|rx_char_ready ME1_rx_char_ready = DFFEAS(ME1L63, F1__clk1, N1_data_out, , , , , , ); --LE1_qualified_irq is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|qualified_irq LE1_qualified_irq = LE1L20 # LE1L21 # LE1_control_reg[7] & ME1_rx_char_ready; --FB1L49 is system_0:u0|jtag_uart_0:the_jtag_uart_0|ien_AE~703 FB1L49 = Z1_d_write & Z1_d_address[2] & GB1L8 & !AB1_cpu_0_data_master_waitrequest; --EE2_safe_q[4] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|safe_q[4] EE2_safe_q[4] = DFFEAS(EE2_counter_comb_bita4, F1__clk1, , , BE2L1, , , , ); --EE2_safe_q[3] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|safe_q[3] EE2_safe_q[3] = DFFEAS(EE2_counter_comb_bita3, F1__clk1, , , BE2L1, , , , ); --EE2_safe_q[2] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|safe_q[2] EE2_safe_q[2] = DFFEAS(EE2_counter_comb_bita2, F1__clk1, , , BE2L1, , , , ); --EE2_safe_q[1] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|safe_q[1] EE2_safe_q[1] = DFFEAS(EE2_counter_comb_bita1, F1__clk1, , , BE2L1, , , , ); --EE2_safe_q[0] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|safe_q[0] EE2_safe_q[0] = DFFEAS(EE2_counter_comb_bita0, F1__clk1, , , BE2L1, , , , ); --FB1L10 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~403 FB1L10 = CARRY(!EE2_safe_q[0]); --FB1L11 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~404 FB1L11 = EE2_safe_q[1] & (FB1L10 # GND) # !EE2_safe_q[1] & !FB1L10; --FB1L12 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~405 FB1L12 = CARRY(EE2_safe_q[1] # !FB1L10); --FB1L13 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~406 FB1L13 = EE2_safe_q[2] & !FB1L12 & VCC # !EE2_safe_q[2] & (FB1L12 $ GND); --FB1L14 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~407 FB1L14 = CARRY(!EE2_safe_q[2] & !FB1L12); --FB1L15 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~408 FB1L15 = EE2_safe_q[3] & (FB1L14 # GND) # !EE2_safe_q[3] & !FB1L14; --FB1L16 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~409 FB1L16 = CARRY(EE2_safe_q[3] # !FB1L14); --FB1L17 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~410 FB1L17 = EE2_safe_q[4] & !FB1L16 & VCC # !EE2_safe_q[4] & (FB1L16 $ GND); --FB1L18 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~411 FB1L18 = CARRY(!EE2_safe_q[4] & !FB1L16); --EE2_safe_q[5] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|safe_q[5] EE2_safe_q[5] = DFFEAS(EE2_counter_comb_bita5, F1__clk1, , , BE2L1, , , , ); --FB1L19 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~412 FB1L19 = EE2_safe_q[5] & (FB1L18 # GND) # !EE2_safe_q[5] & !FB1L18; --FB1L20 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~413 FB1L20 = CARRY(EE2_safe_q[5] # !FB1L18); --FB1L21 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~414 FB1L21 = BE2_b_full & (FB1L20 $ GND) # !BE2_b_full & (GND # !FB1L20); --FB1L22 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~415 FB1L22 = CARRY(!FB1L20 # !BE2_b_full); --FB1L23 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~416 FB1L23 = FB1L22; --FB1L1 is system_0:u0|jtag_uart_0:the_jtag_uart_0|LessThan~397 FB1L1 = FB1L17 # FB1L19 # FB1L21 # !FB1L23; --FB1L2 is system_0:u0|jtag_uart_0:the_jtag_uart_0|LessThan~398 FB1L2 = FB1L11 # FB1L13; --FB1L3 is system_0:u0|jtag_uart_0:the_jtag_uart_0|LessThan~399 FB1L3 = !FB1L1 & (!EE2_safe_q[0] & !FB1L2 # !FB1L15); --BE2_b_non_empty is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty BE2_b_non_empty = DFFEAS(BE2L9, F1__clk1, , , , , , , ); --VD1L54Q is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|t_pause~reg0 VD1L54Q = AMPP_FUNCTION(F1__clk1, VD1L53, N1_data_out); --FB1_read_0 is system_0:u0|jtag_uart_0:the_jtag_uart_0|read_0 FB1_read_0 = DFFEAS(FB1L45, F1__clk1, N1_data_out, , , , , , ); --FB1L52 is system_0:u0|jtag_uart_0:the_jtag_uart_0|pause_irq~11 FB1L52 = BE2_b_non_empty & (VD1L54Q # FB1_pause_irq & !FB1_read_0) # !BE2_b_non_empty & (FB1_pause_irq & !FB1_read_0); --EE1_safe_q[3] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|safe_q[3] EE1_safe_q[3] = DFFEAS(EE1_counter_comb_bita3, F1__clk1, , , BE1L1, , , , ); --EE1_safe_q[0] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|safe_q[0] EE1_safe_q[0] = DFFEAS(EE1_counter_comb_bita0, F1__clk1, , , BE1L1, , , , ); --EE1_safe_q[2] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|safe_q[2] EE1_safe_q[2] = DFFEAS(EE1_counter_comb_bita2, F1__clk1, , , BE1L1, , , , ); --EE1_safe_q[1] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|safe_q[1] EE1_safe_q[1] = DFFEAS(EE1_counter_comb_bita1, F1__clk1, , , BE1L1, , , , ); --FB1L4 is system_0:u0|jtag_uart_0:the_jtag_uart_0|LessThan~400 FB1L4 = EE1_safe_q[3] & (EE1_safe_q[0] # EE1_safe_q[2] # EE1_safe_q[1]); --BE1_b_full is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|b_full BE1_b_full = DFFEAS(BE1L5, F1__clk1, , , , , , , ); --EE1_safe_q[5] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|safe_q[5] EE1_safe_q[5] = DFFEAS(EE1_counter_comb_bita5, F1__clk1, , , BE1L1, , , , ); --EE1_safe_q[4] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|safe_q[4] EE1_safe_q[4] = DFFEAS(EE1_counter_comb_bita4, F1__clk1, , , BE1L1, , , , ); --FB1L5 is system_0:u0|jtag_uart_0:the_jtag_uart_0|LessThan~401 FB1L5 = !FB1L4 & !BE1_b_full & !EE1_safe_q[5] & !EE1_safe_q[4]; --Z1_E_iw[6] is system_0:u0|cpu_0:the_cpu_0|E_iw[6] Z1_E_iw[6] = AMPP_FUNCTION(F1__clk1, Z1_D_iw[6], N1_data_out, Z1_A_stall); --Z1_E_iw[7] is system_0:u0|cpu_0:the_cpu_0|E_iw[7] Z1_E_iw[7] = AMPP_FUNCTION(F1__clk1, Z1_D_iw[7], N1_data_out, Z1_A_stall); --Z1L1653 is system_0:u0|cpu_0:the_cpu_0|E_op_wrctl~24 Z1L1653 = AMPP_FUNCTION(Z1L1591, Z1_E_iw[12], Z1_E_iw[15], Z1_E_iw[11]); --Z1_E_op_wrctl is system_0:u0|cpu_0:the_cpu_0|E_op_wrctl Z1_E_op_wrctl = AMPP_FUNCTION(Z1_E_iw[14], Z1L1653); --Z1_E_iw[8] is system_0:u0|cpu_0:the_cpu_0|E_iw[8] Z1_E_iw[8] = AMPP_FUNCTION(F1__clk1, Z1_D_iw[8], N1_data_out, Z1_A_stall); --Z1L131 is system_0:u0|cpu_0:the_cpu_0|A_estatus_reg_inst_nxt~271 Z1L131 = AMPP_FUNCTION(Z1_M_alu_result[0], Z1_A_estatus_reg, Z1_M_iw[6], Z1L2671); --Z1L132 is system_0:u0|cpu_0:the_cpu_0|A_estatus_reg_inst_nxt~272 Z1L132 = AMPP_FUNCTION(Z1_A_status_reg_pie, Z1L131, Z1_M_ctrl_exception); --Z1L2 is system_0:u0|cpu_0:the_cpu_0|A_bstatus_reg_inst_nxt~271 Z1L2 = AMPP_FUNCTION(Z1_A_bstatus_reg, Z1_M_alu_result[0], Z1L2670, Z1_M_iw[6]); --Z1L3 is system_0:u0|cpu_0:the_cpu_0|A_bstatus_reg_inst_nxt~272 Z1L3 = AMPP_FUNCTION(Z1_A_status_reg_pie, Z1L2, Z1_M_ctrl_break); --BB1L145 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~1 BB1L145 = AC1L3 # AC1L2 & !UC1_oci_ienable[1] # !CB1L28; --BB1_dbs_latent_8_reg_segment_0[1] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_0[1] BB1_dbs_latent_8_reg_segment_0[1] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[1], F1__clk1, N1_data_out, , BB1L6, , , , ); --BB1_dbs_latent_16_reg_segment_0[1] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_16_reg_segment_0[1] BB1_dbs_latent_16_reg_segment_0[1] = DFFEAS(HB1_za_data[1], F1__clk1, N1_data_out, , BB1L4, , , , ); --BB1L29 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[1]~2987 BB1L29 = BB1_dbs_latent_8_reg_segment_0[1] & (BB1_dbs_latent_16_reg_segment_0[1] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_0[1] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (BB1_dbs_latent_16_reg_segment_0[1] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1_dbs_16_reg_segment_0[1] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[1] BB1_dbs_16_reg_segment_0[1] = DFFEAS(KE1_oDATA[1], F1__clk1, N1_data_out, , BB1L5, , , , ); --BB1L30 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[1]~2988 BB1L30 = BB1L29 & (BB1_dbs_16_reg_segment_0[1] # !LB1L14); --BB1L31 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[1]~2989 BB1L31 = BB1L145 & BB1L30 & (!BB1L161 # !EB1L29); --BB1_dbs_16_reg_segment_0[4] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[4] BB1_dbs_16_reg_segment_0[4] = DFFEAS(KE1_oDATA[4], F1__clk1, N1_data_out, , BB1L5, , , , ); --BB1L148 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~164 BB1L148 = BB1_dbs_16_reg_segment_0[4] # !LB1L14; --BB1_dbs_latent_8_reg_segment_0[4] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_0[4] BB1_dbs_latent_8_reg_segment_0[4] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[4], F1__clk1, N1_data_out, , BB1L6, , , , ); --BB1_dbs_latent_16_reg_segment_0[4] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_16_reg_segment_0[4] BB1_dbs_latent_16_reg_segment_0[4] = DFFEAS(HB1_za_data[4], F1__clk1, N1_data_out, , BB1L4, , , , ); --BB1L38 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[4]~2990 BB1L38 = BB1_dbs_latent_8_reg_segment_0[4] & (BB1_dbs_latent_16_reg_segment_0[4] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_0[4] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (BB1_dbs_latent_16_reg_segment_0[4] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L39 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[4]~2991 BB1L39 = BB1L148 & BB1L38 & (!BB1L164 # !EB1L29); --BB1L40 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[4]~2992 BB1L40 = BB1L39 & (RD1_q_a[4] & !CB1L14 # !BB1L176); --BB1L147 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~3 BB1L147 = AC1L5 # AC1L2 & !UC1_oci_ienable[3] # !CB1L28; --BB1_dbs_latent_8_reg_segment_0[3] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_0[3] BB1_dbs_latent_8_reg_segment_0[3] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[3], F1__clk1, N1_data_out, , BB1L6, , , , ); --BB1_dbs_latent_16_reg_segment_0[3] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_16_reg_segment_0[3] BB1_dbs_latent_16_reg_segment_0[3] = DFFEAS(HB1_za_data[3], F1__clk1, N1_data_out, , BB1L4, , , , ); --BB1L35 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[3]~2993 BB1L35 = BB1_dbs_latent_8_reg_segment_0[3] & (BB1_dbs_latent_16_reg_segment_0[3] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_0[3] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (BB1_dbs_latent_16_reg_segment_0[3] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1_dbs_16_reg_segment_0[3] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[3] BB1_dbs_16_reg_segment_0[3] = DFFEAS(KE1_oDATA[3], F1__clk1, N1_data_out, , BB1L5, , , , ); --BB1L36 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[3]~2994 BB1L36 = BB1L35 & (BB1_dbs_16_reg_segment_0[3] # !LB1L14); --BB1L37 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[3]~2995 BB1L37 = BB1L147 & BB1L36 & (!BB1L163 # !EB1L29); --BB1_dbs_16_reg_segment_0[5] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[5] BB1_dbs_16_reg_segment_0[5] = DFFEAS(KE1_oDATA[5], F1__clk1, N1_data_out, , BB1L5, , , , ); --BB1L149 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~165 BB1L149 = BB1_dbs_16_reg_segment_0[5] # !LB1L14; --BB1_dbs_latent_8_reg_segment_0[5] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_0[5] BB1_dbs_latent_8_reg_segment_0[5] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[5], F1__clk1, N1_data_out, , BB1L6, , , , ); --BB1_dbs_latent_16_reg_segment_0[5] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_16_reg_segment_0[5] BB1_dbs_latent_16_reg_segment_0[5] = DFFEAS(HB1_za_data[5], F1__clk1, N1_data_out, , BB1L4, , , , ); --BB1L41 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[5]~2996 BB1L41 = BB1_dbs_latent_8_reg_segment_0[5] & (BB1_dbs_latent_16_reg_segment_0[5] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_0[5] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (BB1_dbs_latent_16_reg_segment_0[5] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L42 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[5]~2997 BB1L42 = BB1L149 & BB1L41 & (!BB1L165 # !EB1L29); --BB1L43 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[5]~2998 BB1L43 = BB1L42 & (RD1_q_a[5] & !CB1L14 # !BB1L176); --BB1_dbs_latent_8_reg_segment_2[6] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_2[6] BB1_dbs_latent_8_reg_segment_2[6] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[6], F1__clk1, N1_data_out, , BB1L8, , , , ); --HB1_za_data[6] is system_0:u0|sdram_0:the_sdram_0|za_data[6] HB1_za_data[6] = DFFEAS(A1L47, F1__clk1, N1_data_out, , , , , , ); --BB1L98 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[22]~2999 BB1L98 = BB1_dbs_latent_8_reg_segment_2[6] & (HB1_za_data[6] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_2[6] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (HB1_za_data[6] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L99 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[22]~3000 BB1L99 = BB1L98 & (KE1_oDATA[6] # !LB1L14); --UD1_q_a[22] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[22] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[22]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[22]_PORT_A_address_reg = DFFE(UD1_q_a[22]_PORT_A_address, UD1_q_a[22]_clock_0, , , ); UD1_q_a[22]_clock_0 = F1__clk1; UD1_q_a[22]_PORT_A_data_out = MEMORY(, , UD1_q_a[22]_PORT_A_address_reg, , , , , , UD1_q_a[22]_clock_0, , , , , ); UD1_q_a[22] = UD1_q_a[22]_PORT_A_data_out[0]; --BB1L100 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[22]~3001 BB1L100 = BB1L99 & (UD1_q_a[22] & !DB1L1 # !EB1L29); --RD1_q_a[22] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[22] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[22] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[22], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L26, ED1_MonDReg[22], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[22] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[22] RD1_q_b[22] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[22], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L26, ED1_MonDReg[22], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --BB1L101 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[22]~3002 BB1L101 = BB1L100 & (RD1_q_a[22] & !CB1L14 # !BB1L176); --MB1_incoming_tri_state_bridge_0_data[2] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[2] MB1_incoming_tri_state_bridge_0_data[2] = DFFEAS(A1L101, F1__clk1, N1_data_out, , , , , , ); --HB1_za_data[10] is system_0:u0|sdram_0:the_sdram_0|za_data[10] HB1_za_data[10] = DFFEAS(A1L55, F1__clk1, N1_data_out, , , , , , ); --BB1L114 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[26]~3003 BB1L114 = MB1_incoming_tri_state_bridge_0_data[2] & (HB1_za_data[10] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !MB1_incoming_tri_state_bridge_0_data[2] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (HB1_za_data[10] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L115 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[26]~3004 BB1L115 = BB1L114 & (KE1_oDATA[10] # !LB1L14); --UD1_q_a[26] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[26] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[26]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[26]_PORT_A_address_reg = DFFE(UD1_q_a[26]_PORT_A_address, UD1_q_a[26]_clock_0, , , ); UD1_q_a[26]_clock_0 = F1__clk1; UD1_q_a[26]_PORT_A_data_out = MEMORY(, , UD1_q_a[26]_PORT_A_address_reg, , , , , , UD1_q_a[26]_clock_0, , , , , ); UD1_q_a[26] = UD1_q_a[26]_PORT_A_data_out[0]; --BB1L116 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[26]~3005 BB1L116 = BB1L115 & (UD1_q_a[26] & !DB1L1 # !EB1L29); --RD1_q_a[26] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[26] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[26] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[26], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L27, ED1_MonDReg[26], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[26] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[26] RD1_q_b[26] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[26], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L27, ED1_MonDReg[26], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --BB1L117 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[26]~3006 BB1L117 = BB1L116 & (RD1_q_a[26] & !CB1L14 # !BB1L176); --BB1_dbs_latent_8_reg_segment_2[7] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_2[7] BB1_dbs_latent_8_reg_segment_2[7] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[7], F1__clk1, N1_data_out, , BB1L8, , , , ); --HB1_za_data[7] is system_0:u0|sdram_0:the_sdram_0|za_data[7] HB1_za_data[7] = DFFEAS(A1L49, F1__clk1, N1_data_out, , , , , , ); --BB1L102 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[23]~3007 BB1L102 = BB1_dbs_latent_8_reg_segment_2[7] & (HB1_za_data[7] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_2[7] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (HB1_za_data[7] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L103 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[23]~3008 BB1L103 = BB1L102 & (KE1_oDATA[7] # !LB1L14); --UD1_q_a[23] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[23] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[23]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[23]_PORT_A_address_reg = DFFE(UD1_q_a[23]_PORT_A_address, UD1_q_a[23]_clock_0, , , ); UD1_q_a[23]_clock_0 = F1__clk1; UD1_q_a[23]_PORT_A_data_out = MEMORY(, , UD1_q_a[23]_PORT_A_address_reg, , , , , , UD1_q_a[23]_clock_0, , , , , ); UD1_q_a[23] = UD1_q_a[23]_PORT_A_data_out[0]; --BB1L104 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[23]~3009 BB1L104 = BB1L103 & (UD1_q_a[23] & !DB1L1 # !EB1L29); --RD1_q_a[23] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[23] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[23] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[23], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L26, ED1_MonDReg[23], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[23] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[23] RD1_q_b[23] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[23], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L26, ED1_MonDReg[23], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --BB1L105 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[23]~3010 BB1L105 = BB1L104 & (RD1_q_a[23] & !CB1L14 # !BB1L176); --MB1_incoming_tri_state_bridge_0_data[1] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[1] MB1_incoming_tri_state_bridge_0_data[1] = DFFEAS(A1L99, F1__clk1, N1_data_out, , , , , , ); --HB1_za_data[9] is system_0:u0|sdram_0:the_sdram_0|za_data[9] HB1_za_data[9] = DFFEAS(A1L53, F1__clk1, N1_data_out, , , , , , ); --BB1L110 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[25]~3011 BB1L110 = MB1_incoming_tri_state_bridge_0_data[1] & (HB1_za_data[9] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !MB1_incoming_tri_state_bridge_0_data[1] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (HB1_za_data[9] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L111 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[25]~3012 BB1L111 = BB1L110 & (KE1_oDATA[9] # !LB1L14); --UD1_q_a[25] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[25] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[25]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[25]_PORT_A_address_reg = DFFE(UD1_q_a[25]_PORT_A_address, UD1_q_a[25]_clock_0, , , ); UD1_q_a[25]_clock_0 = F1__clk1; UD1_q_a[25]_PORT_A_data_out = MEMORY(, , UD1_q_a[25]_PORT_A_address_reg, , , , , , UD1_q_a[25]_clock_0, , , , , ); UD1_q_a[25] = UD1_q_a[25]_PORT_A_data_out[0]; --BB1L112 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[25]~3013 BB1L112 = BB1L111 & (UD1_q_a[25] & !DB1L1 # !EB1L29); --RD1_q_a[25] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[25] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[25] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[25], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L27, ED1_MonDReg[25], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[25] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[25] RD1_q_b[25] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[25], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L27, ED1_MonDReg[25], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --BB1L113 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[25]~3014 BB1L113 = BB1L112 & (RD1_q_a[25] & !CB1L14 # !BB1L176); --MB1_incoming_tri_state_bridge_0_data[0] is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[0] MB1_incoming_tri_state_bridge_0_data[0] = DFFEAS(A1L97, F1__clk1, N1_data_out, , , , , , ); --HB1_za_data[8] is system_0:u0|sdram_0:the_sdram_0|za_data[8] HB1_za_data[8] = DFFEAS(A1L51, F1__clk1, N1_data_out, , , , , , ); --BB1L106 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[24]~3015 BB1L106 = MB1_incoming_tri_state_bridge_0_data[0] & (HB1_za_data[8] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !MB1_incoming_tri_state_bridge_0_data[0] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (HB1_za_data[8] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L107 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[24]~3016 BB1L107 = BB1L106 & (KE1_oDATA[8] # !LB1L14); --UD1_q_a[24] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[24] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[24]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[24]_PORT_A_address_reg = DFFE(UD1_q_a[24]_PORT_A_address, UD1_q_a[24]_clock_0, , , ); UD1_q_a[24]_clock_0 = F1__clk1; UD1_q_a[24]_PORT_A_data_out = MEMORY(, , UD1_q_a[24]_PORT_A_address_reg, , , , , , UD1_q_a[24]_clock_0, , , , , ); UD1_q_a[24] = UD1_q_a[24]_PORT_A_data_out[0]; --BB1L108 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[24]~3017 BB1L108 = BB1L107 & (UD1_q_a[24] & !DB1L1 # !EB1L29); --RD1_q_a[24] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[24] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[24] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[24], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L27, ED1_MonDReg[24], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[24] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[24] RD1_q_b[24] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[24], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L27, ED1_MonDReg[24], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --BB1L109 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[24]~3018 BB1L109 = BB1L108 & (RD1_q_a[24] & !CB1L14 # !BB1L176); --BB1L144 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~0 BB1L144 = AC1L1 # AC1L2 & !UC1_oci_ienable[0] # !CB1L28; --BB1_dbs_latent_8_reg_segment_0[0] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_0[0] BB1_dbs_latent_8_reg_segment_0[0] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[0], F1__clk1, N1_data_out, , BB1L6, , , , ); --BB1_dbs_latent_16_reg_segment_0[0] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_16_reg_segment_0[0] BB1_dbs_latent_16_reg_segment_0[0] = DFFEAS(HB1_za_data[0], F1__clk1, N1_data_out, , BB1L4, , , , ); --BB1L26 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[0]~3019 BB1L26 = BB1_dbs_latent_8_reg_segment_0[0] & (BB1_dbs_latent_16_reg_segment_0[0] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_0[0] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (BB1_dbs_latent_16_reg_segment_0[0] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1_dbs_16_reg_segment_0[0] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[0] BB1_dbs_16_reg_segment_0[0] = DFFEAS(KE1_oDATA[0], F1__clk1, N1_data_out, , BB1L5, , , , ); --BB1L27 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[0]~3020 BB1L27 = BB1L26 & (BB1_dbs_16_reg_segment_0[0] # !LB1L14); --BB1L28 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[0]~3021 BB1L28 = BB1L144 & BB1L27 & (!BB1L160 # !EB1L29); --Z1L2156 is system_0:u0|cpu_0:the_cpu_0|M_br_cond_taken_history[0]~7 Z1L2156 = AMPP_FUNCTION(Z1L1890, Z1_E_ctrl_br_cond, Z1_A_stall, Z1L2334); --Z1_E_bht_data[0] is system_0:u0|cpu_0:the_cpu_0|E_bht_data[0] Z1_E_bht_data[0] = AMPP_FUNCTION(F1__clk1, Z1_D_bht_data[0], N1_data_out, Z1_A_stall); --Z1_E_bht_ptr[0] is system_0:u0|cpu_0:the_cpu_0|E_bht_ptr[0] Z1_E_bht_ptr[0] = AMPP_FUNCTION(F1__clk1, Z1_D_bht_ptr[0], N1_data_out, Z1_A_stall); --Z1_E_bht_ptr[1] is system_0:u0|cpu_0:the_cpu_0|E_bht_ptr[1] Z1_E_bht_ptr[1] = AMPP_FUNCTION(F1__clk1, Z1_D_bht_ptr[1], N1_data_out, Z1_A_stall); --Z1_E_bht_ptr[2] is system_0:u0|cpu_0:the_cpu_0|E_bht_ptr[2] Z1_E_bht_ptr[2] = AMPP_FUNCTION(F1__clk1, Z1_D_bht_ptr[2], N1_data_out, Z1_A_stall); --Z1_E_bht_ptr[3] is system_0:u0|cpu_0:the_cpu_0|E_bht_ptr[3] Z1_E_bht_ptr[3] = AMPP_FUNCTION(F1__clk1, Z1_D_bht_ptr[3], N1_data_out, Z1_A_stall); --Z1_E_bht_ptr[4] is system_0:u0|cpu_0:the_cpu_0|E_bht_ptr[4] Z1_E_bht_ptr[4] = AMPP_FUNCTION(F1__clk1, Z1_D_bht_ptr[4], N1_data_out, Z1_A_stall); --Z1_E_bht_ptr[5] is system_0:u0|cpu_0:the_cpu_0|E_bht_ptr[5] Z1_E_bht_ptr[5] = AMPP_FUNCTION(F1__clk1, Z1_D_bht_ptr[5], N1_data_out, Z1_A_stall); --Z1_E_bht_ptr[6] is system_0:u0|cpu_0:the_cpu_0|E_bht_ptr[6] Z1_E_bht_ptr[6] = AMPP_FUNCTION(F1__clk1, Z1_D_bht_ptr[6], N1_data_out, Z1_A_stall); --Z1_E_bht_ptr[7] is system_0:u0|cpu_0:the_cpu_0|E_bht_ptr[7] Z1_E_bht_ptr[7] = AMPP_FUNCTION(F1__clk1, Z1_D_bht_ptr[7], N1_data_out, Z1_A_stall); --BB1_dbs_16_reg_segment_0[11] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[11] BB1_dbs_16_reg_segment_0[11] = DFFEAS(KE1_oDATA[11], F1__clk1, N1_data_out, , BB1L5, , , , ); --BB1L155 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~171 BB1L155 = BB1_dbs_16_reg_segment_0[11] # !LB1L14; --BB1_dbs_latent_8_reg_segment_1[3] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_1[3] BB1_dbs_latent_8_reg_segment_1[3] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[3], F1__clk1, N1_data_out, , BB1L7, , , , ); --BB1_dbs_latent_16_reg_segment_0[11] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_16_reg_segment_0[11] BB1_dbs_latent_16_reg_segment_0[11] = DFFEAS(HB1_za_data[11], F1__clk1, N1_data_out, , BB1L4, , , , ); --BB1L59 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[11]~3022 BB1L59 = BB1_dbs_latent_8_reg_segment_1[3] & (BB1_dbs_latent_16_reg_segment_0[11] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_1[3] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (BB1_dbs_latent_16_reg_segment_0[11] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L60 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[11]~3023 BB1L60 = BB1L155 & BB1L59 & (!BB1L171 # !EB1L29); --BB1L61 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[11]~3024 BB1L61 = BB1L60 & (RD1_q_a[11] & !CB1L14 # !BB1L176); --BB1_dbs_16_reg_segment_0[15] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[15] BB1_dbs_16_reg_segment_0[15] = DFFEAS(KE1_oDATA[15], F1__clk1, N1_data_out, , BB1L5, , , , ); --BB1L159 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~175 BB1L159 = BB1_dbs_16_reg_segment_0[15] # !LB1L14; --BB1_dbs_latent_8_reg_segment_1[7] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_1[7] BB1_dbs_latent_8_reg_segment_1[7] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[7], F1__clk1, N1_data_out, , BB1L7, , , , ); --BB1_dbs_latent_16_reg_segment_0[15] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_16_reg_segment_0[15] BB1_dbs_latent_16_reg_segment_0[15] = DFFEAS(HB1_za_data[15], F1__clk1, N1_data_out, , BB1L4, , , , ); --BB1L71 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[15]~3025 BB1L71 = BB1_dbs_latent_8_reg_segment_1[7] & (BB1_dbs_latent_16_reg_segment_0[15] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_1[7] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (BB1_dbs_latent_16_reg_segment_0[15] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L72 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[15]~3026 BB1L72 = BB1L159 & BB1L71 & (!BB1L175 # !EB1L29); --BB1L73 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[15]~3027 BB1L73 = BB1L72 & (RD1_q_a[15] & !CB1L14 # !BB1L176); --BB1_dbs_16_reg_segment_0[13] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[13] BB1_dbs_16_reg_segment_0[13] = DFFEAS(KE1_oDATA[13], F1__clk1, N1_data_out, , BB1L5, , , , ); --BB1L157 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~173 BB1L157 = BB1_dbs_16_reg_segment_0[13] # !LB1L14; --BB1_dbs_latent_8_reg_segment_1[5] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_1[5] BB1_dbs_latent_8_reg_segment_1[5] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[5], F1__clk1, N1_data_out, , BB1L7, , , , ); --BB1_dbs_latent_16_reg_segment_0[13] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_16_reg_segment_0[13] BB1_dbs_latent_16_reg_segment_0[13] = DFFEAS(HB1_za_data[13], F1__clk1, N1_data_out, , BB1L4, , , , ); --BB1L65 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[13]~3028 BB1L65 = BB1_dbs_latent_8_reg_segment_1[5] & (BB1_dbs_latent_16_reg_segment_0[13] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_1[5] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (BB1_dbs_latent_16_reg_segment_0[13] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L66 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[13]~3029 BB1L66 = BB1L157 & BB1L65 & (!BB1L173 # !EB1L29); --BB1L67 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[13]~3030 BB1L67 = BB1L66 & (RD1_q_a[13] & !CB1L14 # !BB1L176); --BB1_dbs_16_reg_segment_0[14] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[14] BB1_dbs_16_reg_segment_0[14] = DFFEAS(KE1_oDATA[14], F1__clk1, N1_data_out, , BB1L5, , , , ); --BB1L158 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~174 BB1L158 = BB1_dbs_16_reg_segment_0[14] # !LB1L14; --BB1_dbs_latent_8_reg_segment_1[6] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_1[6] BB1_dbs_latent_8_reg_segment_1[6] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[6], F1__clk1, N1_data_out, , BB1L7, , , , ); --BB1_dbs_latent_16_reg_segment_0[14] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_16_reg_segment_0[14] BB1_dbs_latent_16_reg_segment_0[14] = DFFEAS(HB1_za_data[14], F1__clk1, N1_data_out, , BB1L4, , , , ); --BB1L68 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[14]~3031 BB1L68 = BB1_dbs_latent_8_reg_segment_1[6] & (BB1_dbs_latent_16_reg_segment_0[14] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_1[6] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (BB1_dbs_latent_16_reg_segment_0[14] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L69 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[14]~3032 BB1L69 = BB1L158 & BB1L68 & (!BB1L174 # !EB1L29); --BB1L70 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[14]~3033 BB1L70 = BB1L69 & (RD1_q_a[14] & !CB1L14 # !BB1L176); --BB1_dbs_latent_8_reg_segment_2[0] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_2[0] BB1_dbs_latent_8_reg_segment_2[0] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[0], F1__clk1, N1_data_out, , BB1L8, , , , ); --HB1_za_data[0] is system_0:u0|sdram_0:the_sdram_0|za_data[0] HB1_za_data[0] = DFFEAS(A1L35, F1__clk1, N1_data_out, , , , , , ); --BB1L74 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[16]~3034 BB1L74 = BB1_dbs_latent_8_reg_segment_2[0] & (HB1_za_data[0] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_2[0] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (HB1_za_data[0] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L75 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[16]~3035 BB1L75 = BB1L74 & (KE1_oDATA[0] # !LB1L14); --UD1_q_a[16] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[16] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[16]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[16]_PORT_A_address_reg = DFFE(UD1_q_a[16]_PORT_A_address, UD1_q_a[16]_clock_0, , , ); UD1_q_a[16]_clock_0 = F1__clk1; UD1_q_a[16]_PORT_A_data_out = MEMORY(, , UD1_q_a[16]_PORT_A_address_reg, , , , , , UD1_q_a[16]_clock_0, , , , , ); UD1_q_a[16] = UD1_q_a[16]_PORT_A_data_out[0]; --BB1L76 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[16]~3036 BB1L76 = BB1L75 & (UD1_q_a[16] & !DB1L1 # !EB1L29); --RD1_q_a[16] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[16] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[16] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[16], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L26, ED1_MonDReg[16], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[16] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[16] RD1_q_b[16] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[16], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L26, ED1_MonDReg[16], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --BB1L77 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[16]~3037 BB1L77 = BB1L76 & (RD1_q_a[16] & !CB1L14 # !BB1L176); --BB1_dbs_16_reg_segment_0[12] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[12] BB1_dbs_16_reg_segment_0[12] = DFFEAS(KE1_oDATA[12], F1__clk1, N1_data_out, , BB1L5, , , , ); --BB1L156 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~172 BB1L156 = BB1_dbs_16_reg_segment_0[12] # !LB1L14; --BB1_dbs_latent_8_reg_segment_1[4] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_1[4] BB1_dbs_latent_8_reg_segment_1[4] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[4], F1__clk1, N1_data_out, , BB1L7, , , , ); --BB1_dbs_latent_16_reg_segment_0[12] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_16_reg_segment_0[12] BB1_dbs_latent_16_reg_segment_0[12] = DFFEAS(HB1_za_data[12], F1__clk1, N1_data_out, , BB1L4, , , , ); --BB1L62 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[12]~3038 BB1L62 = BB1_dbs_latent_8_reg_segment_1[4] & (BB1_dbs_latent_16_reg_segment_0[12] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_1[4] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (BB1_dbs_latent_16_reg_segment_0[12] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L63 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[12]~3039 BB1L63 = BB1L156 & BB1L62 & (!BB1L172 # !EB1L29); --BB1L64 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[12]~3040 BB1L64 = BB1L63 & (RD1_q_a[12] & !CB1L14 # !BB1L176); --Z1_i_readdata_d1[6] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[6] Z1_i_readdata_d1[6] = AMPP_FUNCTION(F1__clk1, BB1L46, N1_data_out); --Z1_i_readdata_d1[7] is system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[7] Z1_i_readdata_d1[7] = AMPP_FUNCTION(F1__clk1, BB1L49, N1_data_out); --QC2_mac_out3 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3 --DSP Block Operation Mode: Simple Multiplier (18-bit) QC2_mac_out3 = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC2_mac_mult2); --QC2L34Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT1 QC2L34Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC2L2); --QC2L35Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT2 QC2L35Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC2L3); --QC2L36Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT3 QC2L36Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC2L4); --QC2L37Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT4 QC2L37Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC2L5); --QC2L38Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT5 QC2L38Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC2L6); --QC2L39Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT6 QC2L39Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC2L7); --QC2L40Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT7 QC2L40Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC2L8); --QC2L41Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT8 QC2L41Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC2L9); --QC2L42Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT9 QC2L42Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC2L10); --QC2L43Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT10 QC2L43Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC2L11); --QC2L44Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT11 QC2L44Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC2L12); --QC2L45Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT12 QC2L45Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC2L13); --QC2L46Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT13 QC2L46Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC2L14); --QC2L47Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT14 QC2L47Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC2L15); --QC2L48Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT15 QC2L48Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC2L16); --QC1_mac_out3 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3 --DSP Block Operation Mode: Simple Multiplier (18-bit) QC1_mac_out3 = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1_mac_mult2); --QC1L34Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT1 QC1L34Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L2); --QC1L35Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT2 QC1L35Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L3); --QC1L36Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT3 QC1L36Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L4); --QC1L37Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT4 QC1L37Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L5); --QC1L38Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT5 QC1L38Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L6); --QC1L39Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT6 QC1L39Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L7); --QC1L40Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT7 QC1L40Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L8); --QC1L41Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT8 QC1L41Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L9); --QC1L42Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT9 QC1L42Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L10); --QC1L43Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT10 QC1L43Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L11); --QC1L44Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT11 QC1L44Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L12); --QC1L45Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT12 QC1L45Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L13); --QC1L46Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT13 QC1L46Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L14); --QC1L47Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT14 QC1L47Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L15); --QC1L48Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT15 QC1L48Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L16); --QC1L49Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT16 QC1L49Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L17); --QC1L50Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT17 QC1L50Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L18); --QC1L51Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT18 QC1L51Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L19); --QC1L52Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT19 QC1L52Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L20); --QC1L53Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT20 QC1L53Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L21); --QC1L54Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT21 QC1L54Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L22); --QC1L55Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT22 QC1L55Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L23); --QC1L56Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT23 QC1L56Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L24); --QC1L57Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT24 QC1L57Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L25); --QC1L58Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT25 QC1L58Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L26); --QC1L59Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT26 QC1L59Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L27); --QC1L60Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT27 QC1L60Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L28); --QC1L61Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT28 QC1L61Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L29); --QC1L62Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT29 QC1L62Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L30); --QC1L63Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT30 QC1L63Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L31); --QC1L64Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_out3~DATAOUT31 QC1L64Q = AMPP_FUNCTION(F1__clk1, N1_data_out, GND, QC1L32); --Z1L242 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[16]~160 Z1L242 = AMPP_FUNCTION(QC2_mac_out3, QC1L49Q, GND); --Z1L243 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[16]~161 Z1L243 = AMPP_FUNCTION(QC2_mac_out3, QC1L49Q); --Z1L245 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[17]~162 Z1L245 = AMPP_FUNCTION(QC2L34Q, QC1L50Q, GND, Z1L243); --Z1L246 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[17]~163 Z1L246 = AMPP_FUNCTION(QC2L34Q, QC1L50Q, Z1L243); --Z1L248 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[18]~164 Z1L248 = AMPP_FUNCTION(QC2L35Q, QC1L51Q, GND, Z1L246); --Z1L249 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[18]~165 Z1L249 = AMPP_FUNCTION(QC2L35Q, QC1L51Q, Z1L246); --Z1L251 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[19]~166 Z1L251 = AMPP_FUNCTION(QC2L36Q, QC1L52Q, GND, Z1L249); --Z1L252 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[19]~167 Z1L252 = AMPP_FUNCTION(QC2L36Q, QC1L52Q, Z1L249); --Z1L254 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[20]~168 Z1L254 = AMPP_FUNCTION(QC2L37Q, QC1L53Q, GND, Z1L252); --Z1L255 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[20]~169 Z1L255 = AMPP_FUNCTION(QC2L37Q, QC1L53Q, Z1L252); --Z1L257 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[21]~170 Z1L257 = AMPP_FUNCTION(QC2L38Q, QC1L54Q, GND, Z1L255); --Z1L258 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[21]~171 Z1L258 = AMPP_FUNCTION(QC2L38Q, QC1L54Q, Z1L255); --Z1L260 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[22]~172 Z1L260 = AMPP_FUNCTION(QC2L39Q, QC1L55Q, GND, Z1L258); --Z1L261 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[22]~173 Z1L261 = AMPP_FUNCTION(QC2L39Q, QC1L55Q, Z1L258); --Z1L263 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[23]~174 Z1L263 = AMPP_FUNCTION(QC2L40Q, QC1L56Q, GND, Z1L261); --Z1L264 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[23]~175 Z1L264 = AMPP_FUNCTION(QC2L40Q, QC1L56Q, Z1L261); --Z1L266 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[24]~176 Z1L266 = AMPP_FUNCTION(QC2L41Q, QC1L57Q, GND, Z1L264); --Z1L267 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[24]~177 Z1L267 = AMPP_FUNCTION(QC2L41Q, QC1L57Q, Z1L264); --Z1L269 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[25]~178 Z1L269 = AMPP_FUNCTION(QC2L42Q, QC1L58Q, GND, Z1L267); --Z1L270 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[25]~179 Z1L270 = AMPP_FUNCTION(QC2L42Q, QC1L58Q, Z1L267); --Z1L272 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[26]~180 Z1L272 = AMPP_FUNCTION(QC2L43Q, QC1L59Q, GND, Z1L270); --Z1L273 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[26]~181 Z1L273 = AMPP_FUNCTION(QC2L43Q, QC1L59Q, Z1L270); --Z1L275 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[27]~182 Z1L275 = AMPP_FUNCTION(QC2L44Q, QC1L60Q, GND, Z1L273); --Z1L276 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[27]~183 Z1L276 = AMPP_FUNCTION(QC2L44Q, QC1L60Q, Z1L273); --Z1L278 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[28]~184 Z1L278 = AMPP_FUNCTION(QC2L45Q, QC1L61Q, GND, Z1L276); --Z1L279 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[28]~185 Z1L279 = AMPP_FUNCTION(QC2L45Q, QC1L61Q, Z1L276); --Z1L281 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[29]~186 Z1L281 = AMPP_FUNCTION(QC2L46Q, QC1L62Q, GND, Z1L279); --Z1L282 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[29]~187 Z1L282 = AMPP_FUNCTION(QC2L46Q, QC1L62Q, Z1L279); --Z1L284 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[30]~188 Z1L284 = AMPP_FUNCTION(QC2L47Q, QC1L63Q, GND, Z1L282); --Z1L285 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[30]~189 Z1L285 = AMPP_FUNCTION(QC2L47Q, QC1L63Q, Z1L282); --Z1L287 is system_0:u0|cpu_0:the_cpu_0|A_mul_partial_prod[31]~190 Z1L287 = AMPP_FUNCTION(QC2L48Q, QC1L64Q, Z1L285); --Z1_A_mul_stall_d2 is system_0:u0|cpu_0:the_cpu_0|A_mul_stall_d2 Z1_A_mul_stall_d2 = AMPP_FUNCTION(F1__clk1, Z1_A_mul_stall_d1, N1_data_out); --Z1L1535 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_ld_signed~17 Z1L1535 = AMPP_FUNCTION(Z1_E_iw[2], Z1_E_iw[1], Z1_E_iw[0]); --Z1L1527 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_ld8_ld16~14 Z1L1527 = AMPP_FUNCTION(Z1_E_iw[1], Z1_E_iw[0], Z1_E_iw[4]); --Z1L2197 is system_0:u0|cpu_0:the_cpu_0|M_data_ram_ld_align_sign_bit_16_hi~0 Z1L2197 = AMPP_FUNCTION(Z1L1481, Z1_E_iw[3], Z1L1527); --Z1L3188 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[23]~1360 Z1L3188 = AMPP_FUNCTION(Z1_M_st_data[23], Z1_d_readdata_d1[23], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3163 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_byte_en[2]~450 Z1L3163 = AMPP_FUNCTION(Z1_A_ctrl_ld_initd_flushd_flushda, Z1_M_mem_byte_en[2], Z1_A_dc_fill_wr_en, Z1_A_mem_byte_en[2]); --Z1L3196 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[31]~1361 Z1L3196 = AMPP_FUNCTION(Z1_M_st_data[31], Z1_d_readdata_d1[31], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1L3164 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_byte_en[3]~451 Z1L3164 = AMPP_FUNCTION(Z1_A_ctrl_ld_initd_flushd_flushda, Z1_M_mem_byte_en[3], Z1_A_dc_fill_wr_en, Z1_A_mem_byte_en[3]); --AB1_registered_cpu_0_data_master_readdata[23] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[23] AB1_registered_cpu_0_data_master_readdata[23] = DFFEAS(AB1L345, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_2[7] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[7] AB1_dbs_8_reg_segment_2[7] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[7], F1__clk1, N1_data_out, , AB1L5, , , , ); --AB1L163 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[23]~2718 AB1L163 = AB1_registered_cpu_0_data_master_readdata[23] & (AB1_dbs_8_reg_segment_2[7] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[23] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_2[7] # !MB1L38); --AB1L164 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[23]~2719 AB1L164 = AB1L163 & (KE1_oDATA[7] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --AB1L165 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[23]~2720 AB1L165 = AB1L127 & AB1L164 & (AB1_registered_cpu_0_data_master_readdata[23] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --AB1L166 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[23]~2721 AB1L166 = AB1L165 & (UD1_q_a[23] & !DB1L1 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --AB1_cpu_0_data_master_readdata[23] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[23] AB1_cpu_0_data_master_readdata[23] = AB1L166 & (RD1_q_a[23] & !CB1L14 # !AB1L222); --AB1_registered_cpu_0_data_master_readdata[31] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[31] AB1_registered_cpu_0_data_master_readdata[31] = DFFEAS(AB1L353, F1__clk1, N1_data_out, , , , , , ); --AB1L203 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[31]~2722 AB1L203 = AB1_registered_cpu_0_data_master_readdata[31] & (MB1_incoming_tri_state_bridge_0_data[7] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[31] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (MB1_incoming_tri_state_bridge_0_data[7] # !MB1L38); --AB1L204 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[31]~2723 AB1L204 = AB1L203 & (KE1_oDATA[15] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --AB1L205 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[31]~2724 AB1L205 = AB1L127 & AB1L204 & (AB1_registered_cpu_0_data_master_readdata[31] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --AB1L206 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[31]~2725 AB1L206 = AB1L205 & (UD1_q_a[31] & !DB1L1 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --AB1_cpu_0_data_master_readdata[31] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[31] AB1_cpu_0_data_master_readdata[31] = AB1L206 & (RD1_q_a[31] & !CB1L14 # !AB1L222); --Z1L1543 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_mem~102 Z1L1543 = AMPP_FUNCTION(Z1L1649, Z1_E_iw[5], Z1_E_iw[3]); --Z1_E_op_rdctl is system_0:u0|cpu_0:the_cpu_0|E_op_rdctl Z1_E_op_rdctl = AMPP_FUNCTION(Z1L1653, Z1_E_iw[14]); --Z1_Mn_rot_step2[15] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[15] Z1_Mn_rot_step2[15] = AMPP_FUNCTION(!F1__clk1, Z1L2719, Z1L2695, N1_data_out, Z1_M_rot_rn[3]); --Z1_Mn_rot_step2[31] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[31] Z1_Mn_rot_step2[31] = AMPP_FUNCTION(!F1__clk1, Z1L2767, Z1L2743, N1_data_out, Z1_M_rot_rn[3]); --Z1_M_rot_rn[4] is system_0:u0|cpu_0:the_cpu_0|M_rot_rn[4] Z1_M_rot_rn[4] = AMPP_FUNCTION(F1__clk1, Z1L3018, N1_data_out, Z1_A_stall); --Z1L582 is system_0:u0|cpu_0:the_cpu_0|A_rot~416 Z1L582 = AMPP_FUNCTION(Z1_Mn_rot_step2[15], Z1_Mn_rot_step2[31], Z1_M_rot_rn[4]); --Z1_M_rot_fill_bit is system_0:u0|cpu_0:the_cpu_0|M_rot_fill_bit Z1_M_rot_fill_bit = AMPP_FUNCTION(F1__clk1, Z1L1685, N1_data_out, Z1_A_stall); --Z1_M_rot_mask[7] is system_0:u0|cpu_0:the_cpu_0|M_rot_mask[7] Z1_M_rot_mask[7] = AMPP_FUNCTION(F1__clk1, Z1L1691, N1_data_out, Z1_A_stall); --Z1_M_rot_sel_fill3 is system_0:u0|cpu_0:the_cpu_0|M_rot_sel_fill3 Z1_M_rot_sel_fill3 = AMPP_FUNCTION(F1__clk1, Z1L1703, N1_data_out, Z1_A_stall); --Z1_M_rot_pass3 is system_0:u0|cpu_0:the_cpu_0|M_rot_pass3 Z1_M_rot_pass3 = AMPP_FUNCTION(F1__clk1, Z1L1699, N1_data_out, Z1_A_stall); --Z1L2021 is system_0:u0|cpu_0:the_cpu_0|F_iw[28]~1604 Z1L2021 = AMPP_FUNCTION(JC1_q_a[28], Z1L1994); --Z1L2022 is system_0:u0|cpu_0:the_cpu_0|F_iw[29]~1605 Z1L2022 = AMPP_FUNCTION(JC1_q_a[29], Z1L1994); --Z1L2023 is system_0:u0|cpu_0:the_cpu_0|F_iw[30]~1606 Z1L2023 = AMPP_FUNCTION(JC1_q_a[30], Z1L1994); --Z1L2024 is system_0:u0|cpu_0:the_cpu_0|F_iw[31]~1607 Z1L2024 = AMPP_FUNCTION(JC1_q_a[31], Z1L1994); --AB1_registered_cpu_0_data_master_readdata[30] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[30] AB1_registered_cpu_0_data_master_readdata[30] = DFFEAS(AB1L352, F1__clk1, N1_data_out, , , , , , ); --AB1L198 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2726 AB1L198 = AB1_registered_cpu_0_data_master_readdata[30] & (MB1_incoming_tri_state_bridge_0_data[6] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[30] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (MB1_incoming_tri_state_bridge_0_data[6] # !MB1L38); --AB1L199 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2727 AB1L199 = AB1L198 & (KE1_oDATA[14] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --AB1L200 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2728 AB1L200 = AB1L127 & AB1L199 & (AB1_registered_cpu_0_data_master_readdata[30] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --AB1L201 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2729 AB1L201 = AB1L200 & (UD1_q_a[30] & !DB1L1 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --AB1_cpu_0_data_master_readdata[30] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30] AB1_cpu_0_data_master_readdata[30] = AB1L201 & (RD1_q_a[30] & !CB1L14 # !AB1L222); --Z1L3195 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[30]~1362 Z1L3195 = AMPP_FUNCTION(Z1_M_st_data[30], Z1_d_readdata_d1[30], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_Mn_rot_step2[14] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[14] Z1_Mn_rot_step2[14] = AMPP_FUNCTION(!F1__clk1, Z1L2716, Z1L2692, N1_data_out, Z1_M_rot_rn[3]); --Z1_Mn_rot_step2[30] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[30] Z1_Mn_rot_step2[30] = AMPP_FUNCTION(!F1__clk1, Z1L2764, Z1L2740, N1_data_out, Z1_M_rot_rn[3]); --Z1L583 is system_0:u0|cpu_0:the_cpu_0|A_rot~417 Z1L583 = AMPP_FUNCTION(Z1_Mn_rot_step2[14], Z1_Mn_rot_step2[30], Z1_M_rot_rn[4]); --Z1_M_rot_mask[6] is system_0:u0|cpu_0:the_cpu_0|M_rot_mask[6] Z1_M_rot_mask[6] = AMPP_FUNCTION(F1__clk1, Z1L1693, N1_data_out, Z1_A_stall); --AB1_registered_cpu_0_data_master_readdata[29] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[29] AB1_registered_cpu_0_data_master_readdata[29] = DFFEAS(AB1L351, F1__clk1, N1_data_out, , , , , , ); --AB1L193 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[29]~2730 AB1L193 = AB1_registered_cpu_0_data_master_readdata[29] & (MB1_incoming_tri_state_bridge_0_data[5] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[29] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (MB1_incoming_tri_state_bridge_0_data[5] # !MB1L38); --AB1L194 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[29]~2731 AB1L194 = AB1L193 & (KE1_oDATA[13] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --AB1L195 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[29]~2732 AB1L195 = AB1L127 & AB1L194 & (AB1_registered_cpu_0_data_master_readdata[29] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --AB1L196 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[29]~2733 AB1L196 = AB1L195 & (UD1_q_a[29] & !DB1L1 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --AB1_cpu_0_data_master_readdata[29] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[29] AB1_cpu_0_data_master_readdata[29] = AB1L196 & (RD1_q_a[29] & !CB1L14 # !AB1L222); --Z1L3194 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[29]~1363 Z1L3194 = AMPP_FUNCTION(Z1_M_st_data[29], Z1_d_readdata_d1[29], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_Mn_rot_step2[13] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[13] Z1_Mn_rot_step2[13] = AMPP_FUNCTION(!F1__clk1, Z1L2713, Z1L2689, N1_data_out, Z1_M_rot_rn[3]); --Z1_Mn_rot_step2[29] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[29] Z1_Mn_rot_step2[29] = AMPP_FUNCTION(!F1__clk1, Z1L2761, Z1L2737, N1_data_out, Z1_M_rot_rn[3]); --Z1L584 is system_0:u0|cpu_0:the_cpu_0|A_rot~418 Z1L584 = AMPP_FUNCTION(Z1_Mn_rot_step2[13], Z1_Mn_rot_step2[29], Z1_M_rot_rn[4]); --Z1_M_rot_mask[5] is system_0:u0|cpu_0:the_cpu_0|M_rot_mask[5] Z1_M_rot_mask[5] = AMPP_FUNCTION(F1__clk1, Z1L1692, N1_data_out, Z1_A_stall); --AB1_registered_cpu_0_data_master_readdata[28] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[28] AB1_registered_cpu_0_data_master_readdata[28] = DFFEAS(AB1L350, F1__clk1, N1_data_out, , , , , , ); --AB1L188 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[28]~2734 AB1L188 = AB1_registered_cpu_0_data_master_readdata[28] & (MB1_incoming_tri_state_bridge_0_data[4] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[28] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (MB1_incoming_tri_state_bridge_0_data[4] # !MB1L38); --AB1L189 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[28]~2735 AB1L189 = AB1L188 & (KE1_oDATA[12] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --AB1L190 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[28]~2736 AB1L190 = AB1L127 & AB1L189 & (AB1_registered_cpu_0_data_master_readdata[28] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --AB1L191 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[28]~2737 AB1L191 = AB1L190 & (UD1_q_a[28] & !DB1L1 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --AB1_cpu_0_data_master_readdata[28] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[28] AB1_cpu_0_data_master_readdata[28] = AB1L191 & (RD1_q_a[28] & !CB1L14 # !AB1L222); --Z1L3193 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[28]~1364 Z1L3193 = AMPP_FUNCTION(Z1_M_st_data[28], Z1_d_readdata_d1[28], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_Mn_rot_step2[12] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[12] Z1_Mn_rot_step2[12] = AMPP_FUNCTION(!F1__clk1, Z1L2710, Z1L2686, N1_data_out, Z1_M_rot_rn[3]); --Z1_Mn_rot_step2[28] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[28] Z1_Mn_rot_step2[28] = AMPP_FUNCTION(!F1__clk1, Z1L2758, Z1L2734, N1_data_out, Z1_M_rot_rn[3]); --Z1L585 is system_0:u0|cpu_0:the_cpu_0|A_rot~419 Z1L585 = AMPP_FUNCTION(Z1_Mn_rot_step2[12], Z1_Mn_rot_step2[28], Z1_M_rot_rn[4]); --Z1_M_rot_mask[4] is system_0:u0|cpu_0:the_cpu_0|M_rot_mask[4] Z1_M_rot_mask[4] = AMPP_FUNCTION(F1__clk1, Z1L1690, N1_data_out, Z1_A_stall); --AB1_registered_cpu_0_data_master_readdata[27] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[27] AB1_registered_cpu_0_data_master_readdata[27] = DFFEAS(AB1L349, F1__clk1, N1_data_out, , , , , , ); --AB1L183 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[27]~2738 AB1L183 = AB1_registered_cpu_0_data_master_readdata[27] & (MB1_incoming_tri_state_bridge_0_data[3] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[27] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (MB1_incoming_tri_state_bridge_0_data[3] # !MB1L38); --AB1L184 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[27]~2739 AB1L184 = AB1L183 & (KE1_oDATA[11] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --AB1L185 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[27]~2740 AB1L185 = AB1L127 & AB1L184 & (AB1_registered_cpu_0_data_master_readdata[27] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --AB1L186 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[27]~2741 AB1L186 = AB1L185 & (UD1_q_a[27] & !DB1L1 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --AB1_cpu_0_data_master_readdata[27] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[27] AB1_cpu_0_data_master_readdata[27] = AB1L186 & (RD1_q_a[27] & !CB1L14 # !AB1L222); --Z1L3192 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[27]~1365 Z1L3192 = AMPP_FUNCTION(Z1_M_st_data[27], Z1_d_readdata_d1[27], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_Mn_rot_step2[11] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[11] Z1_Mn_rot_step2[11] = AMPP_FUNCTION(!F1__clk1, Z1L2707, Z1L2683, N1_data_out, Z1_M_rot_rn[3]); --Z1_Mn_rot_step2[27] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[27] Z1_Mn_rot_step2[27] = AMPP_FUNCTION(!F1__clk1, Z1L2755, Z1L2731, N1_data_out, Z1_M_rot_rn[3]); --Z1L586 is system_0:u0|cpu_0:the_cpu_0|A_rot~420 Z1L586 = AMPP_FUNCTION(Z1_Mn_rot_step2[11], Z1_Mn_rot_step2[27], Z1_M_rot_rn[4]); --Z1_M_rot_mask[3] is system_0:u0|cpu_0:the_cpu_0|M_rot_mask[3] Z1_M_rot_mask[3] = AMPP_FUNCTION(F1__clk1, Z1L1689, N1_data_out, Z1_A_stall); --AB1_registered_cpu_0_data_master_readdata[26] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[26] AB1_registered_cpu_0_data_master_readdata[26] = DFFEAS(AB1L348, F1__clk1, N1_data_out, , , , , , ); --AB1L178 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[26]~2742 AB1L178 = AB1_registered_cpu_0_data_master_readdata[26] & (MB1_incoming_tri_state_bridge_0_data[2] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[26] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (MB1_incoming_tri_state_bridge_0_data[2] # !MB1L38); --AB1L179 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[26]~2743 AB1L179 = AB1L178 & (KE1_oDATA[10] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --AB1L180 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[26]~2744 AB1L180 = AB1L127 & AB1L179 & (AB1_registered_cpu_0_data_master_readdata[26] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --AB1L181 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[26]~2745 AB1L181 = AB1L180 & (UD1_q_a[26] & !DB1L1 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --AB1_cpu_0_data_master_readdata[26] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[26] AB1_cpu_0_data_master_readdata[26] = AB1L181 & (RD1_q_a[26] & !CB1L14 # !AB1L222); --Z1L3191 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[26]~1366 Z1L3191 = AMPP_FUNCTION(Z1_M_st_data[26], Z1_d_readdata_d1[26], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_Mn_rot_step2[10] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[10] Z1_Mn_rot_step2[10] = AMPP_FUNCTION(!F1__clk1, Z1L2704, Z1L2680, N1_data_out, Z1_M_rot_rn[3]); --Z1_Mn_rot_step2[26] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[26] Z1_Mn_rot_step2[26] = AMPP_FUNCTION(!F1__clk1, Z1L2752, Z1L2728, N1_data_out, Z1_M_rot_rn[3]); --Z1L587 is system_0:u0|cpu_0:the_cpu_0|A_rot~421 Z1L587 = AMPP_FUNCTION(Z1_Mn_rot_step2[10], Z1_Mn_rot_step2[26], Z1_M_rot_rn[4]); --Z1_M_rot_mask[2] is system_0:u0|cpu_0:the_cpu_0|M_rot_mask[2] Z1_M_rot_mask[2] = AMPP_FUNCTION(F1__clk1, Z1L1687, N1_data_out, Z1_A_stall); --AB1_registered_cpu_0_data_master_readdata[25] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[25] AB1_registered_cpu_0_data_master_readdata[25] = DFFEAS(AB1L347, F1__clk1, N1_data_out, , , , , , ); --AB1L173 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[25]~2746 AB1L173 = AB1_registered_cpu_0_data_master_readdata[25] & (MB1_incoming_tri_state_bridge_0_data[1] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[25] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (MB1_incoming_tri_state_bridge_0_data[1] # !MB1L38); --AB1L174 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[25]~2747 AB1L174 = AB1L173 & (KE1_oDATA[9] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --AB1L175 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[25]~2748 AB1L175 = AB1L127 & AB1L174 & (AB1_registered_cpu_0_data_master_readdata[25] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --AB1L176 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[25]~2749 AB1L176 = AB1L175 & (UD1_q_a[25] & !DB1L1 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --AB1_cpu_0_data_master_readdata[25] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[25] AB1_cpu_0_data_master_readdata[25] = AB1L176 & (RD1_q_a[25] & !CB1L14 # !AB1L222); --Z1L3190 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[25]~1367 Z1L3190 = AMPP_FUNCTION(Z1_M_st_data[25], Z1_d_readdata_d1[25], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_Mn_rot_step2[9] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[9] Z1_Mn_rot_step2[9] = AMPP_FUNCTION(!F1__clk1, Z1L2701, Z1L2677, N1_data_out, Z1_M_rot_rn[3]); --Z1_Mn_rot_step2[25] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[25] Z1_Mn_rot_step2[25] = AMPP_FUNCTION(!F1__clk1, Z1L2749, Z1L2725, N1_data_out, Z1_M_rot_rn[3]); --Z1L588 is system_0:u0|cpu_0:the_cpu_0|A_rot~422 Z1L588 = AMPP_FUNCTION(Z1_Mn_rot_step2[9], Z1_Mn_rot_step2[25], Z1_M_rot_rn[4]); --Z1_M_rot_mask[1] is system_0:u0|cpu_0:the_cpu_0|M_rot_mask[1] Z1_M_rot_mask[1] = AMPP_FUNCTION(F1__clk1, Z1L1686, N1_data_out, Z1_A_stall); --AB1_registered_cpu_0_data_master_readdata[24] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[24] AB1_registered_cpu_0_data_master_readdata[24] = DFFEAS(AB1L346, F1__clk1, N1_data_out, , , , , , ); --AB1L168 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[24]~2750 AB1L168 = AB1_registered_cpu_0_data_master_readdata[24] & (MB1_incoming_tri_state_bridge_0_data[0] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[24] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (MB1_incoming_tri_state_bridge_0_data[0] # !MB1L38); --AB1L169 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[24]~2751 AB1L169 = AB1L168 & (KE1_oDATA[8] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --AB1L170 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[24]~2752 AB1L170 = AB1L127 & AB1L169 & (AB1_registered_cpu_0_data_master_readdata[24] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --AB1L171 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[24]~2753 AB1L171 = AB1L170 & (UD1_q_a[24] & !DB1L1 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --AB1_cpu_0_data_master_readdata[24] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[24] AB1_cpu_0_data_master_readdata[24] = AB1L171 & (RD1_q_a[24] & !CB1L14 # !AB1L222); --Z1L3189 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[24]~1368 Z1L3189 = AMPP_FUNCTION(Z1_M_st_data[24], Z1_d_readdata_d1[24], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_Mn_rot_step2[8] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[8] Z1_Mn_rot_step2[8] = AMPP_FUNCTION(!F1__clk1, Z1L2698, Z1L2674, N1_data_out, Z1_M_rot_rn[3]); --Z1_Mn_rot_step2[24] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[24] Z1_Mn_rot_step2[24] = AMPP_FUNCTION(!F1__clk1, Z1L2746, Z1L2722, N1_data_out, Z1_M_rot_rn[3]); --Z1L589 is system_0:u0|cpu_0:the_cpu_0|A_rot~423 Z1L589 = AMPP_FUNCTION(Z1_Mn_rot_step2[8], Z1_Mn_rot_step2[24], Z1_M_rot_rn[4]); --Z1_M_rot_mask[0] is system_0:u0|cpu_0:the_cpu_0|M_rot_mask[0] Z1_M_rot_mask[0] = AMPP_FUNCTION(F1__clk1, Z1L1688, N1_data_out, Z1_A_stall); --Z1_Mn_rot_step2[7] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[7] Z1_Mn_rot_step2[7] = AMPP_FUNCTION(!F1__clk1, Z1L2695, Z1L2767, N1_data_out, Z1_M_rot_rn[3]); --Z1_Mn_rot_step2[23] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[23] Z1_Mn_rot_step2[23] = AMPP_FUNCTION(!F1__clk1, Z1L2743, Z1L2719, N1_data_out, Z1_M_rot_rn[3]); --Z1L590 is system_0:u0|cpu_0:the_cpu_0|A_rot~424 Z1L590 = AMPP_FUNCTION(Z1_Mn_rot_step2[7], Z1_Mn_rot_step2[23], Z1_M_rot_rn[4]); --Z1_M_rot_sel_fill2 is system_0:u0|cpu_0:the_cpu_0|M_rot_sel_fill2 Z1_M_rot_sel_fill2 = AMPP_FUNCTION(F1__clk1, Z1L1702, N1_data_out, Z1_A_stall); --Z1_M_rot_pass2 is system_0:u0|cpu_0:the_cpu_0|M_rot_pass2 Z1_M_rot_pass2 = AMPP_FUNCTION(F1__clk1, Z1L1698, N1_data_out, Z1_A_stall); --AB1_registered_cpu_0_data_master_readdata[22] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[22] AB1_registered_cpu_0_data_master_readdata[22] = DFFEAS(AB1L344, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_2[6] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6] AB1_dbs_8_reg_segment_2[6] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[6], F1__clk1, N1_data_out, , AB1L5, , , , ); --AB1L158 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[22]~2754 AB1L158 = AB1_registered_cpu_0_data_master_readdata[22] & (AB1_dbs_8_reg_segment_2[6] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[22] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_2[6] # !MB1L38); --AB1L159 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[22]~2755 AB1L159 = AB1L158 & (KE1_oDATA[6] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --AB1L160 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[22]~2756 AB1L160 = AB1L127 & AB1L159 & (AB1_registered_cpu_0_data_master_readdata[22] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --AB1L161 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[22]~2757 AB1L161 = AB1L160 & (UD1_q_a[22] & !DB1L1 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --AB1_cpu_0_data_master_readdata[22] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[22] AB1_cpu_0_data_master_readdata[22] = AB1L161 & (RD1_q_a[22] & !CB1L14 # !AB1L222); --Z1L3187 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[22]~1369 Z1L3187 = AMPP_FUNCTION(Z1_M_st_data[22], Z1_d_readdata_d1[22], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_Mn_rot_step2[6] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[6] Z1_Mn_rot_step2[6] = AMPP_FUNCTION(!F1__clk1, Z1L2692, Z1L2764, N1_data_out, Z1_M_rot_rn[3]); --Z1_Mn_rot_step2[22] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[22] Z1_Mn_rot_step2[22] = AMPP_FUNCTION(!F1__clk1, Z1L2740, Z1L2716, N1_data_out, Z1_M_rot_rn[3]); --Z1L591 is system_0:u0|cpu_0:the_cpu_0|A_rot~425 Z1L591 = AMPP_FUNCTION(Z1_Mn_rot_step2[6], Z1_Mn_rot_step2[22], Z1_M_rot_rn[4]); --AB1_registered_cpu_0_data_master_readdata[21] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[21] AB1_registered_cpu_0_data_master_readdata[21] = DFFEAS(AB1L342, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_2[5] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[5] AB1_dbs_8_reg_segment_2[5] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[5], F1__clk1, N1_data_out, , AB1L5, , , , ); --AB1L153 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~2758 AB1L153 = AB1_registered_cpu_0_data_master_readdata[21] & (AB1_dbs_8_reg_segment_2[5] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[21] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_2[5] # !MB1L38); --AB1L154 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~2759 AB1L154 = AB1L153 & (KE1_oDATA[5] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --AB1L155 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~2760 AB1L155 = AB1L127 & AB1L154 & (AB1_registered_cpu_0_data_master_readdata[21] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --UD1_q_a[21] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[21] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[21]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[21]_PORT_A_address_reg = DFFE(UD1_q_a[21]_PORT_A_address, UD1_q_a[21]_clock_0, , , ); UD1_q_a[21]_clock_0 = F1__clk1; UD1_q_a[21]_PORT_A_data_out = MEMORY(, , UD1_q_a[21]_PORT_A_address_reg, , , , , , UD1_q_a[21]_clock_0, , , , , ); UD1_q_a[21] = UD1_q_a[21]_PORT_A_data_out[0]; --AB1L156 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~2761 AB1L156 = AB1L155 & (UD1_q_a[21] & !DB1L1 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --RD1_q_a[21] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[21] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[21] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[21], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L26, ED1_MonDReg[21], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[21] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[21] RD1_q_b[21] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[21], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L26, ED1_MonDReg[21], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AB1_cpu_0_data_master_readdata[21] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21] AB1_cpu_0_data_master_readdata[21] = AB1L156 & (RD1_q_a[21] & !CB1L14 # !AB1L222); --Z1L3186 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[21]~1370 Z1L3186 = AMPP_FUNCTION(Z1_M_st_data[21], Z1_d_readdata_d1[21], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_Mn_rot_step2[5] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[5] Z1_Mn_rot_step2[5] = AMPP_FUNCTION(!F1__clk1, Z1L2689, Z1L2761, N1_data_out, Z1_M_rot_rn[3]); --Z1_Mn_rot_step2[21] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[21] Z1_Mn_rot_step2[21] = AMPP_FUNCTION(!F1__clk1, Z1L2737, Z1L2713, N1_data_out, Z1_M_rot_rn[3]); --Z1L592 is system_0:u0|cpu_0:the_cpu_0|A_rot~426 Z1L592 = AMPP_FUNCTION(Z1_Mn_rot_step2[5], Z1_Mn_rot_step2[21], Z1_M_rot_rn[4]); --AB1_registered_cpu_0_data_master_readdata[20] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[20] AB1_registered_cpu_0_data_master_readdata[20] = DFFEAS(AB1L340, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_2[4] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[4] AB1_dbs_8_reg_segment_2[4] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[4], F1__clk1, N1_data_out, , AB1L5, , , , ); --AB1L148 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[20]~2762 AB1L148 = AB1_registered_cpu_0_data_master_readdata[20] & (AB1_dbs_8_reg_segment_2[4] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[20] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_2[4] # !MB1L38); --AB1L149 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[20]~2763 AB1L149 = AB1L148 & (KE1_oDATA[4] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --AB1L150 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[20]~2764 AB1L150 = AB1L127 & AB1L149 & (AB1_registered_cpu_0_data_master_readdata[20] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --UD1_q_a[20] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[20] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[20]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[20]_PORT_A_address_reg = DFFE(UD1_q_a[20]_PORT_A_address, UD1_q_a[20]_clock_0, , , ); UD1_q_a[20]_clock_0 = F1__clk1; UD1_q_a[20]_PORT_A_data_out = MEMORY(, , UD1_q_a[20]_PORT_A_address_reg, , , , , , UD1_q_a[20]_clock_0, , , , , ); UD1_q_a[20] = UD1_q_a[20]_PORT_A_data_out[0]; --AB1L151 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[20]~2765 AB1L151 = AB1L150 & (UD1_q_a[20] & !DB1L1 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --RD1_q_a[20] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[20] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[20] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[20], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L26, ED1_MonDReg[20], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[20] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[20] RD1_q_b[20] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[20], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L26, ED1_MonDReg[20], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AB1_cpu_0_data_master_readdata[20] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[20] AB1_cpu_0_data_master_readdata[20] = AB1L151 & (RD1_q_a[20] & !CB1L14 # !AB1L222); --Z1L3185 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[20]~1371 Z1L3185 = AMPP_FUNCTION(Z1_M_st_data[20], Z1_d_readdata_d1[20], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_Mn_rot_step2[4] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[4] Z1_Mn_rot_step2[4] = AMPP_FUNCTION(!F1__clk1, Z1L2686, Z1L2758, N1_data_out, Z1_M_rot_rn[3]); --Z1_Mn_rot_step2[20] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[20] Z1_Mn_rot_step2[20] = AMPP_FUNCTION(!F1__clk1, Z1L2734, Z1L2710, N1_data_out, Z1_M_rot_rn[3]); --Z1L593 is system_0:u0|cpu_0:the_cpu_0|A_rot~427 Z1L593 = AMPP_FUNCTION(Z1_Mn_rot_step2[4], Z1_Mn_rot_step2[20], Z1_M_rot_rn[4]); --AB1_registered_cpu_0_data_master_readdata[19] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[19] AB1_registered_cpu_0_data_master_readdata[19] = DFFEAS(AB1L338, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_2[3] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[3] AB1_dbs_8_reg_segment_2[3] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[3], F1__clk1, N1_data_out, , AB1L5, , , , ); --AB1L143 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[19]~2766 AB1L143 = AB1_registered_cpu_0_data_master_readdata[19] & (AB1_dbs_8_reg_segment_2[3] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[19] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_2[3] # !MB1L38); --AB1L144 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[19]~2767 AB1L144 = AB1L143 & (KE1_oDATA[3] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --AB1L145 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[19]~2768 AB1L145 = AB1L127 & AB1L144 & (AB1_registered_cpu_0_data_master_readdata[19] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --UD1_q_a[19] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[19] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[19]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[19]_PORT_A_address_reg = DFFE(UD1_q_a[19]_PORT_A_address, UD1_q_a[19]_clock_0, , , ); UD1_q_a[19]_clock_0 = F1__clk1; UD1_q_a[19]_PORT_A_data_out = MEMORY(, , UD1_q_a[19]_PORT_A_address_reg, , , , , , UD1_q_a[19]_clock_0, , , , , ); UD1_q_a[19] = UD1_q_a[19]_PORT_A_data_out[0]; --AB1L146 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[19]~2769 AB1L146 = AB1L145 & (UD1_q_a[19] & !DB1L1 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --RD1_q_a[19] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[19] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[19] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[19], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L26, ED1_MonDReg[19], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[19] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[19] RD1_q_b[19] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[19], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L26, ED1_MonDReg[19], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AB1_cpu_0_data_master_readdata[19] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[19] AB1_cpu_0_data_master_readdata[19] = AB1L146 & (RD1_q_a[19] & !CB1L14 # !AB1L222); --Z1L3184 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[19]~1372 Z1L3184 = AMPP_FUNCTION(Z1_M_st_data[19], Z1_d_readdata_d1[19], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_Mn_rot_step2[3] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[3] Z1_Mn_rot_step2[3] = AMPP_FUNCTION(!F1__clk1, Z1L2683, Z1L2755, N1_data_out, Z1_M_rot_rn[3]); --Z1_Mn_rot_step2[19] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[19] Z1_Mn_rot_step2[19] = AMPP_FUNCTION(!F1__clk1, Z1L2731, Z1L2707, N1_data_out, Z1_M_rot_rn[3]); --Z1L594 is system_0:u0|cpu_0:the_cpu_0|A_rot~428 Z1L594 = AMPP_FUNCTION(Z1_Mn_rot_step2[3], Z1_Mn_rot_step2[19], Z1_M_rot_rn[4]); --AB1_registered_cpu_0_data_master_readdata[18] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[18] AB1_registered_cpu_0_data_master_readdata[18] = DFFEAS(AB1L336, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_2[2] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[2] AB1_dbs_8_reg_segment_2[2] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[2], F1__clk1, N1_data_out, , AB1L5, , , , ); --AB1L138 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[18]~2770 AB1L138 = AB1_registered_cpu_0_data_master_readdata[18] & (AB1_dbs_8_reg_segment_2[2] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[18] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_2[2] # !MB1L38); --AB1L139 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[18]~2771 AB1L139 = AB1L138 & (KE1_oDATA[2] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --AB1L140 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[18]~2772 AB1L140 = AB1L127 & AB1L139 & (AB1_registered_cpu_0_data_master_readdata[18] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --UD1_q_a[18] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[18] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[18]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[18]_PORT_A_address_reg = DFFE(UD1_q_a[18]_PORT_A_address, UD1_q_a[18]_clock_0, , , ); UD1_q_a[18]_clock_0 = F1__clk1; UD1_q_a[18]_PORT_A_data_out = MEMORY(, , UD1_q_a[18]_PORT_A_address_reg, , , , , , UD1_q_a[18]_clock_0, , , , , ); UD1_q_a[18] = UD1_q_a[18]_PORT_A_data_out[0]; --AB1L141 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[18]~2773 AB1L141 = AB1L140 & (UD1_q_a[18] & !DB1L1 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --RD1_q_a[18] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[18] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[18] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[18], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L26, ED1_MonDReg[18], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[18] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[18] RD1_q_b[18] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[18], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L26, ED1_MonDReg[18], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AB1_cpu_0_data_master_readdata[18] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[18] AB1_cpu_0_data_master_readdata[18] = AB1L141 & (RD1_q_a[18] & !CB1L14 # !AB1L222); --Z1L3183 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[18]~1373 Z1L3183 = AMPP_FUNCTION(Z1_M_st_data[18], Z1_d_readdata_d1[18], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_Mn_rot_step2[2] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[2] Z1_Mn_rot_step2[2] = AMPP_FUNCTION(!F1__clk1, Z1L2680, Z1L2752, N1_data_out, Z1_M_rot_rn[3]); --Z1_Mn_rot_step2[18] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[18] Z1_Mn_rot_step2[18] = AMPP_FUNCTION(!F1__clk1, Z1L2728, Z1L2704, N1_data_out, Z1_M_rot_rn[3]); --Z1L595 is system_0:u0|cpu_0:the_cpu_0|A_rot~429 Z1L595 = AMPP_FUNCTION(Z1_Mn_rot_step2[2], Z1_Mn_rot_step2[18], Z1_M_rot_rn[4]); --AB1_registered_cpu_0_data_master_readdata[17] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[17] AB1_registered_cpu_0_data_master_readdata[17] = DFFEAS(AB1L334, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_2[1] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[1] AB1_dbs_8_reg_segment_2[1] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[1], F1__clk1, N1_data_out, , AB1L5, , , , ); --AB1L133 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[17]~2774 AB1L133 = AB1_registered_cpu_0_data_master_readdata[17] & (AB1_dbs_8_reg_segment_2[1] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[17] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_2[1] # !MB1L38); --AB1L134 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[17]~2775 AB1L134 = AB1L133 & (KE1_oDATA[1] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --AB1L135 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[17]~2776 AB1L135 = AB1L127 & AB1L134 & (AB1_registered_cpu_0_data_master_readdata[17] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --UD1_q_a[17] is system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_5ms:auto_generated|q_a[17] --RAM Block Operation Mode: ROM --Port A Depth: 128, Port A Width: 1 --Port A Logical Depth: 128, Port A Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered UD1_q_a[17]_PORT_A_address = BUS(EB1L9, EB1L10, EB1L11, EB1L12, EB1L13, EB1L14, EB1L15); UD1_q_a[17]_PORT_A_address_reg = DFFE(UD1_q_a[17]_PORT_A_address, UD1_q_a[17]_clock_0, , , ); UD1_q_a[17]_clock_0 = F1__clk1; UD1_q_a[17]_PORT_A_data_out = MEMORY(, , UD1_q_a[17]_PORT_A_address_reg, , , , , , UD1_q_a[17]_clock_0, , , , , ); UD1_q_a[17] = UD1_q_a[17]_PORT_A_data_out[0]; --AB1L136 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[17]~2777 AB1L136 = AB1L135 & (UD1_q_a[17] & !DB1L1 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --RD1_q_a[17] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_a[17] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered RD1_q_a[17] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[17], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L26, ED1_MonDReg[17], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --RD1_q_b[17] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_s202:auto_generated|q_b[17] RD1_q_b[17] = AMPP_FUNCTION(ED1L108, ED1_MonWr, F1__clk1, F1__clk1, Z1_d_writedata[17], CB1L6, CB1L7, CB1L8, CB1L9, CB1L10, CB1L11, CB1L12, CB1L13, CB1L26, ED1_MonDReg[17], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4], ED1_MonAReg[5], ED1_MonAReg[6], ED1_MonAReg[7], ED1_MonAReg[8], ED1_MonAReg[9]); --AB1_cpu_0_data_master_readdata[17] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[17] AB1_cpu_0_data_master_readdata[17] = AB1L136 & (RD1_q_a[17] & !CB1L14 # !AB1L222); --Z1L3182 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[17]~1374 Z1L3182 = AMPP_FUNCTION(Z1_M_st_data[17], Z1_d_readdata_d1[17], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_Mn_rot_step2[1] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[1] Z1_Mn_rot_step2[1] = AMPP_FUNCTION(!F1__clk1, Z1L2677, Z1L2749, N1_data_out, Z1_M_rot_rn[3]); --Z1_Mn_rot_step2[17] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[17] Z1_Mn_rot_step2[17] = AMPP_FUNCTION(!F1__clk1, Z1L2725, Z1L2701, N1_data_out, Z1_M_rot_rn[3]); --Z1L596 is system_0:u0|cpu_0:the_cpu_0|A_rot~430 Z1L596 = AMPP_FUNCTION(Z1_Mn_rot_step2[1], Z1_Mn_rot_step2[17], Z1_M_rot_rn[4]); --AB1_registered_cpu_0_data_master_readdata[16] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[16] AB1_registered_cpu_0_data_master_readdata[16] = DFFEAS(AB1L332, F1__clk1, N1_data_out, , , , , , ); --AB1_dbs_8_reg_segment_2[0] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[0] AB1_dbs_8_reg_segment_2[0] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[0], F1__clk1, N1_data_out, , AB1L5, , , , ); --AB1L128 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[16]~2778 AB1L128 = AB1_registered_cpu_0_data_master_readdata[16] & (AB1_dbs_8_reg_segment_2[0] # !MB1L38) # !AB1_registered_cpu_0_data_master_readdata[16] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (AB1_dbs_8_reg_segment_2[0] # !MB1L38); --AB1L129 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[16]~2779 AB1L129 = AB1L128 & (KE1_oDATA[0] # !LB1_cpu_0_data_master_requests_sram_0_avalonS); --AB1L130 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[16]~2780 AB1L130 = AB1L127 & AB1L129 & (AB1_registered_cpu_0_data_master_readdata[16] # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --AB1L131 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[16]~2781 AB1L131 = AB1L130 & (UD1_q_a[16] & !DB1L1 # !EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port); --AB1_cpu_0_data_master_readdata[16] is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[16] AB1_cpu_0_data_master_readdata[16] = AB1L131 & (RD1_q_a[16] & !CB1L14 # !AB1L222); --Z1L3181 is system_0:u0|cpu_0:the_cpu_0|dc_data_portb_wr_data[16]~1375 Z1L3181 = AMPP_FUNCTION(Z1_M_st_data[16], Z1_d_readdata_d1[16], Z1_av_process_readdata, Z1_A_ctrl_ld_bypass); --Z1_Mn_rot_step2[0] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[0] Z1_Mn_rot_step2[0] = AMPP_FUNCTION(!F1__clk1, Z1L2674, Z1L2746, N1_data_out, Z1_M_rot_rn[3]); --Z1_Mn_rot_step2[16] is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[16] Z1_Mn_rot_step2[16] = AMPP_FUNCTION(!F1__clk1, Z1L2722, Z1L2698, N1_data_out, Z1_M_rot_rn[3]); --Z1L597 is system_0:u0|cpu_0:the_cpu_0|A_rot~431 Z1L597 = AMPP_FUNCTION(Z1_Mn_rot_step2[0], Z1_Mn_rot_step2[16], Z1_M_rot_rn[4]); --Z1L1528 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_ld8~13 Z1L1528 = AMPP_FUNCTION(Z1_E_iw[1], Z1_E_iw[0], Z1_E_iw[4], Z1_E_iw[3]); --Z1L1529 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_ld16~20 Z1L1529 = AMPP_FUNCTION(Z1_E_iw[1], Z1_E_iw[3], Z1_E_iw[0], Z1_E_iw[4]); --Z1L598 is system_0:u0|cpu_0:the_cpu_0|A_rot~432 Z1L598 = AMPP_FUNCTION(Z1_Mn_rot_step2[31], Z1_Mn_rot_step2[15], Z1_M_rot_rn[4]); --Z1_M_rot_sel_fill1 is system_0:u0|cpu_0:the_cpu_0|M_rot_sel_fill1 Z1_M_rot_sel_fill1 = AMPP_FUNCTION(F1__clk1, Z1L1701, N1_data_out, Z1_A_stall); --Z1_M_rot_pass1 is system_0:u0|cpu_0:the_cpu_0|M_rot_pass1 Z1_M_rot_pass1 = AMPP_FUNCTION(F1__clk1, Z1L1696, N1_data_out, Z1_A_stall); --Z1L599 is system_0:u0|cpu_0:the_cpu_0|A_rot~433 Z1L599 = AMPP_FUNCTION(Z1_Mn_rot_step2[30], Z1_Mn_rot_step2[14], Z1_M_rot_rn[4]); --Z1L600 is system_0:u0|cpu_0:the_cpu_0|A_rot~434 Z1L600 = AMPP_FUNCTION(Z1_Mn_rot_step2[29], Z1_Mn_rot_step2[13], Z1_M_rot_rn[4]); --Z1L601 is system_0:u0|cpu_0:the_cpu_0|A_rot~435 Z1L601 = AMPP_FUNCTION(Z1_Mn_rot_step2[28], Z1_Mn_rot_step2[12], Z1_M_rot_rn[4]); --Z1L602 is system_0:u0|cpu_0:the_cpu_0|A_rot~436 Z1L602 = AMPP_FUNCTION(Z1_Mn_rot_step2[27], Z1_Mn_rot_step2[11], Z1_M_rot_rn[4]); --Z1L603 is system_0:u0|cpu_0:the_cpu_0|A_rot~437 Z1L603 = AMPP_FUNCTION(Z1_Mn_rot_step2[26], Z1_Mn_rot_step2[10], Z1_M_rot_rn[4]); --Z1L604 is system_0:u0|cpu_0:the_cpu_0|A_rot~438 Z1L604 = AMPP_FUNCTION(Z1_Mn_rot_step2[25], Z1_Mn_rot_step2[9], Z1_M_rot_rn[4]); --Z1L605 is system_0:u0|cpu_0:the_cpu_0|A_rot~439 Z1L605 = AMPP_FUNCTION(Z1_Mn_rot_step2[24], Z1_Mn_rot_step2[8], Z1_M_rot_rn[4]); --Z1L606 is system_0:u0|cpu_0:the_cpu_0|A_rot~440 Z1L606 = AMPP_FUNCTION(Z1_Mn_rot_step2[23], Z1_Mn_rot_step2[7], Z1_M_rot_rn[4]); --Z1_M_rot_sel_fill0 is system_0:u0|cpu_0:the_cpu_0|M_rot_sel_fill0 Z1_M_rot_sel_fill0 = AMPP_FUNCTION(F1__clk1, Z1L1700, N1_data_out, Z1_A_stall); --Z1_M_rot_pass0 is system_0:u0|cpu_0:the_cpu_0|M_rot_pass0 Z1_M_rot_pass0 = AMPP_FUNCTION(F1__clk1, Z1L1694, N1_data_out, Z1_A_stall); --Z1L607 is system_0:u0|cpu_0:the_cpu_0|A_rot~441 Z1L607 = AMPP_FUNCTION(Z1_Mn_rot_step2[22], Z1_Mn_rot_step2[6], Z1_M_rot_rn[4]); --Z1L608 is system_0:u0|cpu_0:the_cpu_0|A_rot~442 Z1L608 = AMPP_FUNCTION(Z1_Mn_rot_step2[21], Z1_Mn_rot_step2[5], Z1_M_rot_rn[4]); --Z1L609 is system_0:u0|cpu_0:the_cpu_0|A_rot~443 Z1L609 = AMPP_FUNCTION(Z1_Mn_rot_step2[20], Z1_Mn_rot_step2[4], Z1_M_rot_rn[4]); --Z1L610 is system_0:u0|cpu_0:the_cpu_0|A_rot~444 Z1L610 = AMPP_FUNCTION(Z1_Mn_rot_step2[19], Z1_Mn_rot_step2[3], Z1_M_rot_rn[4]); --Z1_E_control_rd_data_without_mmu_regs[3] is system_0:u0|cpu_0:the_cpu_0|E_control_rd_data_without_mmu_regs[3] Z1_E_control_rd_data_without_mmu_regs[3] = AMPP_FUNCTION(F1__clk1, Z1L1006, N1_data_out, Z1_A_stall); --Z1L611 is system_0:u0|cpu_0:the_cpu_0|A_rot~445 Z1L611 = AMPP_FUNCTION(Z1_Mn_rot_step2[18], Z1_Mn_rot_step2[2], Z1_M_rot_rn[4]); --Z1_E_control_rd_data_without_mmu_regs[2] is system_0:u0|cpu_0:the_cpu_0|E_control_rd_data_without_mmu_regs[2] Z1_E_control_rd_data_without_mmu_regs[2] = AMPP_FUNCTION(F1__clk1, Z1L1005, N1_data_out, Z1_A_stall); --Z1L612 is system_0:u0|cpu_0:the_cpu_0|A_rot~446 Z1L612 = AMPP_FUNCTION(Z1_Mn_rot_step2[17], Z1_Mn_rot_step2[1], Z1_M_rot_rn[4]); --Z1_E_control_rd_data_without_mmu_regs[1] is system_0:u0|cpu_0:the_cpu_0|E_control_rd_data_without_mmu_regs[1] Z1_E_control_rd_data_without_mmu_regs[1] = AMPP_FUNCTION(F1__clk1, Z1L1004, N1_data_out, Z1_A_stall); --Z1L613 is system_0:u0|cpu_0:the_cpu_0|A_rot~447 Z1L613 = AMPP_FUNCTION(Z1_Mn_rot_step2[16], Z1_Mn_rot_step2[0], Z1_M_rot_rn[4]); --Z1_E_control_rd_data_without_mmu_regs[0] is system_0:u0|cpu_0:the_cpu_0|E_control_rd_data_without_mmu_regs[0] Z1_E_control_rd_data_without_mmu_regs[0] = AMPP_FUNCTION(F1__clk1, Z1L1003, N1_data_out, Z1_A_stall); --FD1_sr[19] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[19] FD1_sr[19] = AMPP_FUNCTION(A1L333, FD1L137, D1_CLRN_SIGNAL, FD1L81); --FD1_sr[18] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[18] FD1_sr[18] = AMPP_FUNCTION(A1L333, FD1L139, D1_CLRN_SIGNAL, FD1L81); --VC1_break_readreg[20] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[20] VC1_break_readreg[20] = AMPP_FUNCTION(F1__clk1, VC1L37, D1_CLRN_SIGNAL, VC1L26); --ED1_MonDReg[20] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[20] ED1_MonDReg[20] = AMPP_FUNCTION(F1__clk1, ED1L67, D1_CLRN_SIGNAL, ED1L33); --FD1L128 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4775 FD1L128 = AMPP_FUNCTION(FD1L78, VC1_break_readreg[20], FD1L77, ED1_MonDReg[20]); --FD1L129 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4776 FD1L129 = AMPP_FUNCTION(FD1L7, FD1_ir[0], FD1L128, FD1_sr[22]); --ED1_MonDReg[19] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[19] ED1_MonDReg[19] = AMPP_FUNCTION(F1__clk1, ED1L68, D1_CLRN_SIGNAL, ED1L33); --FD1L130 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4777 FD1L130 = AMPP_FUNCTION(FD1L77, FD1_sr[21], FD1L78, ED1_MonDReg[19]); --VC1_break_readreg[19] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[19] VC1_break_readreg[19] = AMPP_FUNCTION(F1__clk1, VC1L38, D1_CLRN_SIGNAL, VC1L26); --FD1L131 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4778 FD1L131 = AMPP_FUNCTION(FD1L75, FD1L76, FD1L130, VC1_break_readreg[19]); --JE1_stage_4 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|stage_4 JE1_stage_4 = DFFEAS(JE1L31, F1__clk1, , , HE1L16, , , , ); --JE1L30 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|p3_stage_3~10 JE1L30 = JE1_full_4 & JE1_stage_4 # !JE1_full_4 & (JB1L16); --G6L3 is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:2:S_IRF|Q[0]~58 G6L3 = AMPP_FUNCTION(G3_Q[0], G6_Q[0], G8_Q[1], D1L15); --M1_w_anode28w[3] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|w_anode28w[3] M1_w_anode28w[3] = AMPP_FUNCTION(G3_Q[2], D1L39, G3_Q[3], G3_Q[1]); --H1_WORD_SR[3] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3] H1_WORD_SR[3] = AMPP_FUNCTION(A1L333, H1L38, H1L26); --H1L34 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~1842 H1L34 = AMPP_FUNCTION(H1_word_counter[4], H1_word_counter[0], H1_word_counter[2], H1_word_counter[3]); --H1L35 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~1843 H1L35 = AMPP_FUNCTION(H1_word_counter[1], H1_word_counter[2], H1L34); --H1L36 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~1844 H1L36 = AMPP_FUNCTION(H1_WORD_SR[3], L1_state[4], H1_clear_signal, H1L35); --FD1L22Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[3]~reg0 FD1L22Q = AMPP_FUNCTION(A1L336, FD1_sr[3], FD1L104); --FD1L198 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|take_action_ocimem_b~27 FD1L198 = AMPP_FUNCTION(FD1L54Q, FD1_jxdr, FD1_ir[1], FD1_ir[0]); --ED1_MonAReg[10] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[10] ED1_MonAReg[10] = AMPP_FUNCTION(F1__clk1, ED1L29, FD1L36Q, D1_CLRN_SIGNAL, FD1L196, ED1L15); --ED1L65 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3244 ED1L65 = AMPP_FUNCTION(FD1L22Q, FD1L198, RD1_q_b[0], ED1_MonAReg[10]); --FD1L197 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|take_action_ocimem_a~46 FD1L197 = AMPP_FUNCTION(FD1_jxdr, FD1L54Q, FD1_ir[1], FD1_ir[0]); --ED1_MonRd1 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonRd1 ED1_MonRd1 = AMPP_FUNCTION(F1__clk1, ED1_MonRd, D1_CLRN_SIGNAL); --ED1L33 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[0]~3245 ED1L33 = AMPP_FUNCTION(FD1L197, FD1L198, ED1_MonRd1); --FD1L19Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[0]~reg0 FD1L19Q = AMPP_FUNCTION(A1L336, FD1_sr[0], FD1L104); --FD1L55Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[36]~reg0 FD1L55Q = AMPP_FUNCTION(A1L336, FD1_sr[36], FD1L104); --FD1L56Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[37]~reg0 FD1L56Q = AMPP_FUNCTION(A1L336, FD1_sr[37], FD1L104); --VC1L26 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[23]~2161 VC1L26 = AMPP_FUNCTION(FD1_jxdr, FD1_ir[1], FD1_ir[0]); --VC1L35 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2162 VC1L35 = AMPP_FUNCTION(FD1L19Q, FD1L55Q, FD1L56Q, VC1L26); --ED1_MonDReg[1] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[1] ED1_MonDReg[1] = AMPP_FUNCTION(F1__clk1, ED1L69, D1_CLRN_SIGNAL, ED1L33); --VC1_break_readreg[1] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[1] VC1_break_readreg[1] = AMPP_FUNCTION(F1__clk1, VC1L39, D1_CLRN_SIGNAL, VC1L26); --FD1L132 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4779 FD1L132 = AMPP_FUNCTION(ED1_MonDReg[1], FD1_ir[0], FD1_ir[1], VC1_break_readreg[1]); --FD1_sr[3] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[3] FD1_sr[3] = AMPP_FUNCTION(A1L333, FD1L141, D1_CLRN_SIGNAL, FD1L118); --FD1L133 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4780 FD1L133 = AMPP_FUNCTION(FD1L132, FD1_sr[3], FD1L7); --FD1_sr[25] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[25] FD1_sr[25] = AMPP_FUNCTION(A1L333, FD1L143, D1_CLRN_SIGNAL, FD1L81); --L1_state[14] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14] L1_state[14] = AMPP_FUNCTION(A1L333, L1L28); --L1L29 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~29 L1L29 = AMPP_FUNCTION(L1_state[12], L1_state[14]); --M1_w_anode18w[3] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|w_anode18w[3] M1_w_anode18w[3] = AMPP_FUNCTION(G3_Q[1], D1L39, G3_Q[3], G3_Q[2]); --VD1_td_shift[3] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[3] VD1_td_shift[3] = AMPP_FUNCTION(A1L333, VD1L85, D1_CLRN_SIGNAL, VD1L57); --VD1_rdata[0] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[0] VD1_rdata[0] = AMPP_FUNCTION(F1__clk1, FE1_q_b[0], N1_data_out, VD1L28); --VD1L64 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[2]~686 VD1L64 = AMPP_FUNCTION(VD1_td_shift[3], VD1_rdata[0], VD1_count[9]); --VD1L104 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|write_stalled~59 VD1L104 = AMPP_FUNCTION(VD1_td_shift[10], VD1_write_stalled, FB1_t_dav, altera_internal_jtag); --VD1L94 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[0]~7 VD1L94 = AMPP_FUNCTION(VD1_count[1], VD1L90); --FB1_r_val is system_0:u0|jtag_uart_0:the_jtag_uart_0|r_val FB1_r_val = DFFEAS(FB1_rd_wfifo, F1__clk1, N1_data_out, , , , , , ); --VD1_r_ena1 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|r_ena1 VD1_r_ena1 = AMPP_FUNCTION(F1__clk1, VD1L29, N1_data_out); --VD1L29 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|r_ena~1 VD1L29 = AMPP_FUNCTION(VD1_rvalid0, FB1_r_val, VD1_r_ena1); --VD1_read_write1 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write1 VD1_read_write1 = AMPP_FUNCTION(F1__clk1, VD1_read_write, N1_data_out); --VD1_read_write2 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write2 VD1_read_write2 = AMPP_FUNCTION(F1__clk1, VD1_read_write1, N1_data_out); --VD1L2 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always2~2 VD1L2 = AMPP_FUNCTION(VD1_read_write1, VD1_read_write2); --VD1_read_req is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_req VD1_read_req = AMPP_FUNCTION(A1L333, VD1_td_shift[9], D1_CLRN_SIGNAL, VD1L94); --VD1L46 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rvalid0~73 VD1L46 = AMPP_FUNCTION(VD1L29, VD1_user_saw_rvalid, VD1L2, VD1_read_req); --VD1_count[7] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[7] VD1_count[7] = AMPP_FUNCTION(A1L333, VD1L17, D1_CLRN_SIGNAL, VD1L57); --VD1L15 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count~216 VD1L15 = AMPP_FUNCTION(L1_state[4], VD1_count[7]); --VD1L16 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count~217 VD1L16 = AMPP_FUNCTION(L1_state[4], VD1_count[9]); --FE1_q_b[7] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2|q_b[7] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1 --Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered FE1_q_b[7]_PORT_A_data_in = Z1_d_writedata[7]; FE1_q_b[7]_PORT_A_data_in_reg = DFFE(FE1_q_b[7]_PORT_A_data_in, FE1_q_b[7]_clock_0, , , FE1_q_b[7]_clock_enable_0); FE1_q_b[7]_PORT_A_address = BUS(DE2_safe_q[0], DE2_safe_q[1], DE2_safe_q[2], DE2_safe_q[3], DE2_safe_q[4], DE2_safe_q[5]); FE1_q_b[7]_PORT_A_address_reg = DFFE(FE1_q_b[7]_PORT_A_address, FE1_q_b[7]_clock_0, , , FE1_q_b[7]_clock_enable_0); FE1_q_b[7]_PORT_B_address = BUS(DE1_safe_q[0], DE1_safe_q[1], DE1_safe_q[2], DE1_safe_q[3], DE1_safe_q[4], DE1_safe_q[5]); FE1_q_b[7]_PORT_B_address_reg = DFFE(FE1_q_b[7]_PORT_B_address, FE1_q_b[7]_clock_1, , , FE1_q_b[7]_clock_enable_1); FE1_q_b[7]_PORT_A_write_enable = VCC; FE1_q_b[7]_PORT_A_write_enable_reg = DFFE(FE1_q_b[7]_PORT_A_write_enable, FE1_q_b[7]_clock_0, , , FE1_q_b[7]_clock_enable_0); FE1_q_b[7]_PORT_B_read_enable = VCC; FE1_q_b[7]_PORT_B_read_enable_reg = DFFE(FE1_q_b[7]_PORT_B_read_enable, FE1_q_b[7]_clock_1, , , FE1_q_b[7]_clock_enable_1); FE1_q_b[7]_clock_0 = F1__clk1; FE1_q_b[7]_clock_1 = F1__clk1; FE1_q_b[7]_clock_enable_0 = FB1_fifo_wr; FE1_q_b[7]_clock_enable_1 = FB1_rd_wfifo; FE1_q_b[7]_PORT_B_data_out = MEMORY(FE1_q_b[7]_PORT_A_data_in_reg, , FE1_q_b[7]_PORT_A_address_reg, FE1_q_b[7]_PORT_B_address_reg, FE1_q_b[7]_PORT_A_write_enable_reg, FE1_q_b[7]_PORT_B_read_enable_reg, , , FE1_q_b[7]_clock_0, FE1_q_b[7]_clock_1, FE1_q_b[7]_clock_enable_0, FE1_q_b[7]_clock_enable_1, , ); FE1_q_b[7] = FE1_q_b[7]_PORT_B_data_out[0]; --VD1L28 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|r_ena~0 VD1L28 = AMPP_FUNCTION(FB1_r_val, VD1_r_ena1); --BE2L4 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|b_full~79 BE2L4 = EE2_safe_q[2] & EE2_safe_q[3] & EE2_safe_q[5] & EE2_safe_q[4]; --VD1L51Q is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|t_ena~reg0 VD1L51Q = AMPP_FUNCTION(F1__clk1, VD1L50, N1_data_out); --BE2L5 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|b_full~80 BE2L5 = EE2_safe_q[0] & EE2_safe_q[1] & BE2_b_non_empty & VD1L51Q; --FB1L45 is system_0:u0|jtag_uart_0:the_jtag_uart_0|fifo_rd~33 FB1L45 = Z1_d_read & GB1L8 & !Z1_d_address[2] & !AB1_cpu_0_data_master_waitrequest; --FB1L57 is system_0:u0|jtag_uart_0:the_jtag_uart_0|rvalid~16 FB1L57 = BE2_b_non_empty & FB1L45; --BE2L6 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|b_full~81 BE2L6 = !FB1L57 & (BE2_b_full # BE2L4 & BE2L5); --L1L26 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~22 L1L26 = AMPP_FUNCTION(L1_state[11], L1_state[10], L1_state[14]); --D1L44 is sld_hub:sld_hub_inst|process0~0 D1L44 = AMPP_FUNCTION(A1L335, L1_state[2]); --L1L40 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt~4 L1L40 = AMPP_FUNCTION(L1_tms_cnt[2], L1_tms_cnt[0], L1_tms_cnt[1]); --L1L38 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt~0 L1L38 = AMPP_FUNCTION(A1L335, L1_tms_cnt[0]); --L1L39 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt~1 L1L39 = AMPP_FUNCTION(L1_tms_cnt[0], L1_tms_cnt[1]); --L1L25 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~21 L1L25 = AMPP_FUNCTION(L1_state[9], A1L335); --L1L22 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~15 L1L22 = AMPP_FUNCTION(L1_state[5], L1_state[6]); --Z1_E_src2_reg[16] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[16] Z1_E_src2_reg[16] = AMPP_FUNCTION(F1__clk1, Z1L1791, N1_data_out, Z1_A_stall); --Z1L1879 is system_0:u0|cpu_0:the_cpu_0|E_st_data[16]~784 Z1L1879 = AMPP_FUNCTION(Z1_E_src2_reg[16], Z1_E_src2_reg[0], Z1_E_iw[4]); --Z1_dc_data_wr_byte_2 is system_0:u0|cpu_0:the_cpu_0|dc_data_wr_byte_2 Z1_dc_data_wr_byte_2 = AMPP_FUNCTION(Z1L3198, Z1L3163); --Z1L71 is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_valid_byte_2~24 Z1L71 = AMPP_FUNCTION(Z1_A_stall, Z1L3198, Z1L3163, Z1_A_dc_latest_data_valid_byte_2); --Z1_E_src2_reg[17] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[17] Z1_E_src2_reg[17] = AMPP_FUNCTION(F1__clk1, Z1L1794, N1_data_out, Z1_A_stall); --Z1L1880 is system_0:u0|cpu_0:the_cpu_0|E_st_data[17]~785 Z1L1880 = AMPP_FUNCTION(Z1_E_src2_reg[17], Z1_E_src2_reg[1], Z1_E_iw[4]); --Z1_E_src2_reg[18] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[18] Z1_E_src2_reg[18] = AMPP_FUNCTION(F1__clk1, Z1L1797, N1_data_out, Z1_A_stall); --Z1L1881 is system_0:u0|cpu_0:the_cpu_0|E_st_data[18]~786 Z1L1881 = AMPP_FUNCTION(Z1_E_src2_reg[18], Z1_E_src2_reg[2], Z1_E_iw[4]); --Z1_E_src2_reg[19] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[19] Z1_E_src2_reg[19] = AMPP_FUNCTION(F1__clk1, Z1L1800, N1_data_out, Z1_A_stall); --Z1L1882 is system_0:u0|cpu_0:the_cpu_0|E_st_data[19]~787 Z1L1882 = AMPP_FUNCTION(Z1_E_src2_reg[19], Z1_E_src2_reg[3], Z1_E_iw[4]); --Z1_E_src2_reg[20] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[20] Z1_E_src2_reg[20] = AMPP_FUNCTION(F1__clk1, Z1L1803, N1_data_out, Z1_A_stall); --Z1L1883 is system_0:u0|cpu_0:the_cpu_0|E_st_data[20]~788 Z1L1883 = AMPP_FUNCTION(Z1_E_src2_reg[20], Z1_E_src2_reg[4], Z1_E_iw[4]); --Z1_E_src2_reg[21] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[21] Z1_E_src2_reg[21] = AMPP_FUNCTION(F1__clk1, Z1L1806, N1_data_out, Z1_A_stall); --Z1L1884 is system_0:u0|cpu_0:the_cpu_0|E_st_data[21]~789 Z1L1884 = AMPP_FUNCTION(Z1_E_src2_reg[21], Z1_E_src2_reg[5], Z1_E_iw[4]); --Z1_E_src2_reg[22] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[22] Z1_E_src2_reg[22] = AMPP_FUNCTION(F1__clk1, Z1L1809, N1_data_out, Z1_A_stall); --Z1L1885 is system_0:u0|cpu_0:the_cpu_0|E_st_data[22]~790 Z1L1885 = AMPP_FUNCTION(Z1_E_src2_reg[22], Z1_E_src2_reg[6], Z1_E_iw[4]); --Z1_E_src2_reg[23] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[23] Z1_E_src2_reg[23] = AMPP_FUNCTION(F1__clk1, Z1L1812, N1_data_out, Z1_A_stall); --Z1L1886 is system_0:u0|cpu_0:the_cpu_0|E_st_data[23]~791 Z1L1886 = AMPP_FUNCTION(Z1_E_src2_reg[23], Z1_E_src2_reg[7], Z1_E_iw[4]); --Z1L2645 is system_0:u0|cpu_0:the_cpu_0|M_st_data[24]~100 Z1L2645 = AMPP_FUNCTION(Z1_E_src2_reg[0], Z1_E_src2_reg[8], Z1_E_iw[3]); --Z1_E_src2_reg[24] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[24] Z1_E_src2_reg[24] = AMPP_FUNCTION(F1__clk1, Z1L1815, N1_data_out, Z1_A_stall); --Z1_dc_data_wr_byte_3 is system_0:u0|cpu_0:the_cpu_0|dc_data_wr_byte_3 Z1_dc_data_wr_byte_3 = AMPP_FUNCTION(Z1L3198, Z1L3164); --Z1L73 is system_0:u0|cpu_0:the_cpu_0|A_dc_latest_data_valid_byte_3~24 Z1L73 = AMPP_FUNCTION(Z1_A_stall, Z1L3198, Z1L3164, Z1_A_dc_latest_data_valid_byte_3); --Z1L2648 is system_0:u0|cpu_0:the_cpu_0|M_st_data[25]~101 Z1L2648 = AMPP_FUNCTION(Z1_E_src2_reg[1], Z1_E_src2_reg[9], Z1_E_iw[3]); --Z1_E_src2_reg[25] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[25] Z1_E_src2_reg[25] = AMPP_FUNCTION(F1__clk1, Z1L1818, N1_data_out, Z1_A_stall); --Z1L2651 is system_0:u0|cpu_0:the_cpu_0|M_st_data[26]~102 Z1L2651 = AMPP_FUNCTION(Z1_E_src2_reg[2], Z1_E_src2_reg[10], Z1_E_iw[3]); --Z1_E_src2_reg[26] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[26] Z1_E_src2_reg[26] = AMPP_FUNCTION(F1__clk1, Z1L1821, N1_data_out, Z1_A_stall); --Z1L2654 is system_0:u0|cpu_0:the_cpu_0|M_st_data[27]~103 Z1L2654 = AMPP_FUNCTION(Z1_E_src2_reg[3], Z1_E_src2_reg[11], Z1_E_iw[3]); --Z1_E_src2_reg[27] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[27] Z1_E_src2_reg[27] = AMPP_FUNCTION(F1__clk1, Z1L1824, N1_data_out, Z1_A_stall); --Z1L2657 is system_0:u0|cpu_0:the_cpu_0|M_st_data[28]~104 Z1L2657 = AMPP_FUNCTION(Z1_E_src2_reg[4], Z1_E_src2_reg[12], Z1_E_iw[3]); --Z1_E_src2_reg[28] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[28] Z1_E_src2_reg[28] = AMPP_FUNCTION(F1__clk1, Z1L1827, N1_data_out, Z1_A_stall); --Z1L2660 is system_0:u0|cpu_0:the_cpu_0|M_st_data[29]~105 Z1L2660 = AMPP_FUNCTION(Z1_E_src2_reg[5], Z1_E_src2_reg[13], Z1_E_iw[3]); --Z1_E_src2_reg[29] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[29] Z1_E_src2_reg[29] = AMPP_FUNCTION(F1__clk1, Z1L1830, N1_data_out, Z1_A_stall); --Z1L2663 is system_0:u0|cpu_0:the_cpu_0|M_st_data[30]~106 Z1L2663 = AMPP_FUNCTION(Z1_E_src2_reg[6], Z1_E_src2_reg[14], Z1_E_iw[3]); --Z1_E_src2_reg[30] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[30] Z1_E_src2_reg[30] = AMPP_FUNCTION(F1__clk1, Z1L1833, N1_data_out, Z1_A_stall); --Z1L2666 is system_0:u0|cpu_0:the_cpu_0|M_st_data[31]~107 Z1L2666 = AMPP_FUNCTION(Z1_E_src2_reg[7], Z1_E_src2_reg[15], Z1_E_iw[3]); --Z1_E_src2_reg[31] is system_0:u0|cpu_0:the_cpu_0|E_src2_reg[31] Z1_E_src2_reg[31] = AMPP_FUNCTION(F1__clk1, Z1L1836, N1_data_out, Z1_A_stall); --XC1L6 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_error~108 XC1L6 = AMPP_FUNCTION(Z1_d_writedata[1], XC1L11, XC1_monitor_error, XC1L12); --ED1_MonWr is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonWr ED1_MonWr = AMPP_FUNCTION(F1__clk1, ED1L106, GND, D1_CLRN_SIGNAL, FD1L198, FD1L197); --CB1L24 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_byteenable[0]~16 CB1L24 = Z1_d_byteenable[0] # !CB1L30; --ED1_MonAReg[2] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[2] ED1_MonAReg[2] = AMPP_FUNCTION(F1__clk1, ED1L4, FD1L45Q, D1_CLRN_SIGNAL, FD1L196, ED1L15); --ED1_MonAReg[3] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[3] ED1_MonAReg[3] = AMPP_FUNCTION(F1__clk1, ED1L7, FD1L46Q, D1_CLRN_SIGNAL, FD1L196, ED1L15); --ED1_MonAReg[4] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[4] ED1_MonAReg[4] = AMPP_FUNCTION(F1__clk1, ED1L10, FD1L47Q, D1_CLRN_SIGNAL, FD1L196, ED1L15); --ED1_MonAReg[5] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[5] ED1_MonAReg[5] = AMPP_FUNCTION(F1__clk1, ED1L13, FD1L48Q, D1_CLRN_SIGNAL, FD1L196, ED1L15); --ED1_MonAReg[6] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[6] ED1_MonAReg[6] = AMPP_FUNCTION(F1__clk1, ED1L17, FD1L49Q, D1_CLRN_SIGNAL, FD1L196, ED1L15); --ED1_MonAReg[7] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[7] ED1_MonAReg[7] = AMPP_FUNCTION(F1__clk1, ED1L20, FD1L50Q, D1_CLRN_SIGNAL, FD1L196, ED1L15); --ED1_MonAReg[8] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[8] ED1_MonAReg[8] = AMPP_FUNCTION(F1__clk1, ED1L23, FD1L51Q, D1_CLRN_SIGNAL, FD1L196, ED1L15); --ED1_MonAReg[9] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[9] ED1_MonAReg[9] = AMPP_FUNCTION(F1__clk1, ED1L26, FD1L52Q, D1_CLRN_SIGNAL, FD1L196, ED1L15); --AB1L291 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_dbs_16_reg_segment_0[0]~1008 AB1L291 = JB1_cpu_0_data_master_requests_sdram_0_s1 & HB1_za_data[0] # !JB1_cpu_0_data_master_requests_sdram_0_s1 & (KE1_oDATA[0]); --AB1L2 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always3~9 AB1L2 = AB1L287 & !AB1_cpu_0_data_master_dbs_address[1]; --FE2_q_b[0] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2|q_b[0] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1 --Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered FE2_q_b[0]_PORT_A_data_in = VD1_wdata[0]; FE2_q_b[0]_PORT_A_data_in_reg = DFFE(FE2_q_b[0]_PORT_A_data_in, FE2_q_b[0]_clock_0, , , FE2_q_b[0]_clock_enable_0); FE2_q_b[0]_PORT_A_address = BUS(DE4_safe_q[0], DE4_safe_q[1], DE4_safe_q[2], DE4_safe_q[3], DE4_safe_q[4], DE4_safe_q[5]); FE2_q_b[0]_PORT_A_address_reg = DFFE(FE2_q_b[0]_PORT_A_address, FE2_q_b[0]_clock_0, , , FE2_q_b[0]_clock_enable_0); FE2_q_b[0]_PORT_B_address = BUS(DE3_safe_q[0], DE3_safe_q[1], DE3_safe_q[2], DE3_safe_q[3], DE3_safe_q[4], DE3_safe_q[5]); FE2_q_b[0]_PORT_B_address_reg = DFFE(FE2_q_b[0]_PORT_B_address, FE2_q_b[0]_clock_1, , , FE2_q_b[0]_clock_enable_1); FE2_q_b[0]_PORT_A_write_enable = VCC; FE2_q_b[0]_PORT_A_write_enable_reg = DFFE(FE2_q_b[0]_PORT_A_write_enable, FE2_q_b[0]_clock_0, , , FE2_q_b[0]_clock_enable_0); FE2_q_b[0]_PORT_B_read_enable = VCC; FE2_q_b[0]_PORT_B_read_enable_reg = DFFE(FE2_q_b[0]_PORT_B_read_enable, FE2_q_b[0]_clock_1, , , FE2_q_b[0]_clock_enable_1); FE2_q_b[0]_clock_0 = F1__clk1; FE2_q_b[0]_clock_1 = F1__clk1; FE2_q_b[0]_clock_enable_0 = FB1_wr_rfifo; FE2_q_b[0]_clock_enable_1 = FB1L57; FE2_q_b[0]_PORT_B_data_out = MEMORY(FE2_q_b[0]_PORT_A_data_in_reg, , FE2_q_b[0]_PORT_A_address_reg, FE2_q_b[0]_PORT_B_address_reg, FE2_q_b[0]_PORT_A_write_enable_reg, FE2_q_b[0]_PORT_B_read_enable_reg, , , FE2_q_b[0]_clock_0, FE2_q_b[0]_clock_1, FE2_q_b[0]_clock_enable_0, FE2_q_b[0]_clock_enable_1, , ); FE2_q_b[0] = FE2_q_b[0]_PORT_B_data_out[0]; --AB1L307 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[0]~1304 AB1L307 = FB1_read_0 & FE2_q_b[0] # !FB1_read_0 & (FB1_ien_AF); --AB1L308 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[0]~1305 AB1L308 = AB1L307 & (AB1_dbs_16_reg_segment_0[0] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !AB1L307 & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (AB1_dbs_16_reg_segment_0[0] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --AB1L3 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always5~9 AB1L3 = AB1L287 & !AB1_cpu_0_data_master_dbs_address[1] & !AB1_cpu_0_data_master_dbs_address[0]; --LE1_control_reg[0] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|control_reg[0] LE1_control_reg[0] = DFFEAS(Z1_d_writedata[0], F1__clk1, N1_data_out, , LE1L15, , , , ); --ME1_rx_data[0] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|rx_data[0] ME1_rx_data[0] = DFFEAS(ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1], F1__clk1, N1_data_out, , ME1_got_new_char, , , , ); --LE1L34 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data[0]~675 LE1L34 = Z1_d_address[2] & LE1_tx_data[0] # !Z1_d_address[2] & (ME1_rx_data[0]); --LE1L35 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data[0]~676 LE1L35 = Z1_d_address[3] & Z1_d_address[2] & LE1_control_reg[0] # !Z1_d_address[3] & (LE1L34); --X1_read_mux_out[0] is system_0:u0|Switch:the_Switch|read_mux_out[0] X1_read_mux_out[0] = SW[0] & !Z1_d_address[2] & !Z1_d_address[3]; --P1L34 is system_0:u0|KEY:the_KEY|readdata[0]~8 P1L34 = Z1_d_address[3] & (P1_irq_mask[0]) # !Z1_d_address[3] & KEY[0]; --P1L28 is system_0:u0|KEY:the_KEY|read_mux_out[0]~56 P1L28 = Z1_d_address[3] & P1_edge_capture[0]; --EB1L9 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[0]~96 EB1L9 = EB1L26 & Z1_d_address[2] # !EB1L26 & (Z1_ic_fill_ap_offset[0]); --EB1L10 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[1]~97 EB1L10 = EB1L26 & Z1_d_address[3] # !EB1L26 & (Z1_ic_fill_ap_offset[1]); --EB1L11 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[2]~98 EB1L11 = EB1L26 & Z1_d_address[4] # !EB1L26 & (Z1_ic_fill_ap_offset[2]); --EB1L12 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[3]~99 EB1L12 = EB1L26 & Z1_d_address[5] # !EB1L26 & (Z1_ic_fill_line[0]); --EB1L13 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[4]~100 EB1L13 = EB1L26 & Z1_d_address[6] # !EB1L26 & (Z1_ic_fill_line[1]); --EB1L14 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[5]~101 EB1L14 = EB1L26 & Z1_d_address[7] # !EB1L26 & (Z1_ic_fill_line[2]); --EB1L15 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[6]~102 EB1L15 = EB1L26 & Z1_d_address[8] # !EB1L26 & (Z1_ic_fill_line[3]); --SD1_endofpacketvalue_reg[0] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[0] SD1_endofpacketvalue_reg[0] = DFFEAS(Z1_d_writedata[0], F1__clk1, N1_data_out, , SD1_endofpacketvalue_wr_strobe, , , , ); --SD1_rx_holding_reg[0] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[0] SD1_rx_holding_reg[0] = DFFEAS(SD1_shift_reg[0], F1__clk1, N1_data_out, , SD1L26, , , , ); --SD1L18 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal~763 SD1L18 = EB1L9 & EB1L11 & !EB1L10; --SD1_epcs_slave_select_reg[0] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[0] SD1_epcs_slave_select_reg[0] = DFFEAS(SD1_epcs_slave_select_holding_reg[0], F1__clk1, N1_data_out, , SD1L50, , , , ); --SD1L140 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[0]~1345 SD1L140 = SD1L18 & (!SD1_epcs_slave_select_reg[0]) # !SD1L18 & SD1_rx_holding_reg[0]; --SD1L19 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal~764 SD1L19 = EB1L10 & EB1L11 & !EB1L9; --SD1L141 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[0]~1346 SD1L141 = !SD1L56 & (SD1L19 & SD1_endofpacketvalue_reg[0] # !SD1L19 & (SD1L140)); --Z1L1531 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_ld_initd_flushd_flushda~15 Z1L1531 = AMPP_FUNCTION(Z1L1542, Z1L1522, Z1_E_iw[5], Z1_E_iw[3]); --VC1_break_readreg[22] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[22] VC1_break_readreg[22] = AMPP_FUNCTION(F1__clk1, VC1L40, D1_CLRN_SIGNAL, VC1L26); --ED1_MonDReg[22] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[22] ED1_MonDReg[22] = AMPP_FUNCTION(F1__clk1, ED1L70, D1_CLRN_SIGNAL, ED1L33); --FD1L134 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4781 FD1L134 = AMPP_FUNCTION(FD1L78, VC1_break_readreg[22], FD1L77, ED1_MonDReg[22]); --FD1_sr[24] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[24] FD1_sr[24] = AMPP_FUNCTION(A1L333, FD1L145, D1_CLRN_SIGNAL, FD1L81); --FD1L135 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4782 FD1L135 = AMPP_FUNCTION(FD1L7, FD1_ir[0], FD1L134, FD1_sr[24]); --FD1L43Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[24]~reg0 FD1L43Q = AMPP_FUNCTION(A1L336, FD1_sr[24], FD1L104); --ED1L66 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3246 ED1L66 = AMPP_FUNCTION(FD1L43Q, FD1L198, RD1_q_b[21], ED1_MonAReg[10]); --VC1L36 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2163 VC1L36 = AMPP_FUNCTION(FD1L40Q, FD1L55Q, FD1L56Q, VC1L26); --M1_w_anode78w[3] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|w_anode78w[3] M1_w_anode78w[3] = AMPP_FUNCTION(G3_Q[3], G3_Q[1], G3_Q[2], D1L39); --D1L14 is sld_hub:sld_hub_inst|GEN_SHADOW_IRF~1 D1L14 = AMPP_FUNCTION(G8_Q[0], D1_OK_TO_UPDATE_IR_Q, L1_state[5]); --FD1_sr[37] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[37] FD1_sr[37] = AMPP_FUNCTION(A1L333, ~GND, altera_internal_jtag, D1_CLRN_SIGNAL, FD1L7, FD1L119); --FD1L119 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[36]~4783 FD1L119 = AMPP_FUNCTION(FD1L7, FD1_ir[1], FD1_ir[0], FD1L118); --FD1L4 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|Decoder~29 FD1L4 = AMPP_FUNCTION(G5_Q[1], G5_Q[0]); --HB1_za_data[1] is system_0:u0|sdram_0:the_sdram_0|za_data[1] HB1_za_data[1] = DFFEAS(A1L37, F1__clk1, N1_data_out, , , , , , ); --AB1L292 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_dbs_16_reg_segment_0[1]~1009 AB1L292 = JB1_cpu_0_data_master_requests_sdram_0_s1 & HB1_za_data[1] # !JB1_cpu_0_data_master_requests_sdram_0_s1 & (KE1_oDATA[1]); --FE2_q_b[1] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2|q_b[1] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1 --Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered FE2_q_b[1]_PORT_A_data_in = VD1_wdata[1]; FE2_q_b[1]_PORT_A_data_in_reg = DFFE(FE2_q_b[1]_PORT_A_data_in, FE2_q_b[1]_clock_0, , , FE2_q_b[1]_clock_enable_0); FE2_q_b[1]_PORT_A_address = BUS(DE4_safe_q[0], DE4_safe_q[1], DE4_safe_q[2], DE4_safe_q[3], DE4_safe_q[4], DE4_safe_q[5]); FE2_q_b[1]_PORT_A_address_reg = DFFE(FE2_q_b[1]_PORT_A_address, FE2_q_b[1]_clock_0, , , FE2_q_b[1]_clock_enable_0); FE2_q_b[1]_PORT_B_address = BUS(DE3_safe_q[0], DE3_safe_q[1], DE3_safe_q[2], DE3_safe_q[3], DE3_safe_q[4], DE3_safe_q[5]); FE2_q_b[1]_PORT_B_address_reg = DFFE(FE2_q_b[1]_PORT_B_address, FE2_q_b[1]_clock_1, , , FE2_q_b[1]_clock_enable_1); FE2_q_b[1]_PORT_A_write_enable = VCC; FE2_q_b[1]_PORT_A_write_enable_reg = DFFE(FE2_q_b[1]_PORT_A_write_enable, FE2_q_b[1]_clock_0, , , FE2_q_b[1]_clock_enable_0); FE2_q_b[1]_PORT_B_read_enable = VCC; FE2_q_b[1]_PORT_B_read_enable_reg = DFFE(FE2_q_b[1]_PORT_B_read_enable, FE2_q_b[1]_clock_1, , , FE2_q_b[1]_clock_enable_1); FE2_q_b[1]_clock_0 = F1__clk1; FE2_q_b[1]_clock_1 = F1__clk1; FE2_q_b[1]_clock_enable_0 = FB1_wr_rfifo; FE2_q_b[1]_clock_enable_1 = FB1L57; FE2_q_b[1]_PORT_B_data_out = MEMORY(FE2_q_b[1]_PORT_A_data_in_reg, , FE2_q_b[1]_PORT_A_address_reg, FE2_q_b[1]_PORT_B_address_reg, FE2_q_b[1]_PORT_A_write_enable_reg, FE2_q_b[1]_PORT_B_read_enable_reg, , , FE2_q_b[1]_clock_0, FE2_q_b[1]_clock_1, FE2_q_b[1]_clock_enable_0, FE2_q_b[1]_clock_enable_1, , ); FE2_q_b[1] = FE2_q_b[1]_PORT_B_data_out[0]; --AB1L309 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[1]~1306 AB1L309 = FB1_read_0 & FE2_q_b[1] # !FB1_read_0 & (FB1_ien_AE); --AB1L310 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[1]~1307 AB1L310 = AB1L309 & (AB1_dbs_16_reg_segment_0[1] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !AB1L309 & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (AB1_dbs_16_reg_segment_0[1] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --LE1L51 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data~9 LE1L51 = Z1_d_address[2] & LE1_tx_data[1] & !Z1_d_address[3] & !Z1_d_address[4]; --ME1_rx_data[1] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|rx_data[1] ME1_rx_data[1] = DFFEAS(ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2], F1__clk1, N1_data_out, , ME1_got_new_char, , , , ); --LE1L3 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|Equal~93 LE1L3 = !Z1_d_address[2] & !Z1_d_address[3] & !Z1_d_address[4]; --LE1L36 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data[1]~677 LE1L36 = LE1L2 & (LE1_control_reg[1] # ME1_rx_data[1] & LE1L3) # !LE1L2 & ME1_rx_data[1] & LE1L3; --LE1L37 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data[1]~678 LE1L37 = LE1L51 # LE1L36 # LE1L1 & ME1_framing_error; --X1_read_mux_out[1] is system_0:u0|Switch:the_Switch|read_mux_out[1] X1_read_mux_out[1] = SW[1] & !Z1_d_address[2] & !Z1_d_address[3]; --P1L37 is system_0:u0|KEY:the_KEY|readdata[1]~9 P1L37 = Z1_d_address[3] & (P1_irq_mask[1]) # !Z1_d_address[3] & KEY[1]; --P1L29 is system_0:u0|KEY:the_KEY|read_mux_out[1]~57 P1L29 = Z1_d_address[3] & P1_edge_capture[1]; --SD1_endofpacketvalue_reg[1] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[1] SD1_endofpacketvalue_reg[1] = DFFEAS(Z1_d_writedata[1], F1__clk1, N1_data_out, , SD1_endofpacketvalue_wr_strobe, , , , ); --SD1_epcs_slave_select_reg[1] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[1] SD1_epcs_slave_select_reg[1] = DFFEAS(SD1_epcs_slave_select_holding_reg[1], F1__clk1, N1_data_out, , SD1L50, , , , ); --SD1_rx_holding_reg[1] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[1] SD1_rx_holding_reg[1] = DFFEAS(SD1_shift_reg[1], F1__clk1, N1_data_out, , SD1L26, , , , ); --SD1L142 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[1]~1347 SD1L142 = SD1L18 & SD1_epcs_slave_select_reg[1] # !SD1L18 & (SD1_rx_holding_reg[1]); --SD1L143 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[1]~1348 SD1L143 = !SD1L56 & (SD1L19 & SD1_endofpacketvalue_reg[1] # !SD1L19 & (SD1L142)); --XC1L8 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_go~96 XC1L8 = AMPP_FUNCTION(FD1L196, UC1L12, ED1L107, A1L331); --FD1L42Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[23]~reg0 FD1L42Q = AMPP_FUNCTION(A1L336, FD1_sr[23], FD1L104); --XC1L9 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_go~97 XC1L9 = AMPP_FUNCTION(FD1L196, XC1_monitor_go, XC1L8, FD1L42Q); --ED1_MonDReg[2] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[2] ED1_MonDReg[2] = AMPP_FUNCTION(F1__clk1, ED1L72, FD1L24Q, D1_CLRN_SIGNAL, FD1L198, ED1L33); --HB1_za_data[2] is system_0:u0|sdram_0:the_sdram_0|za_data[2] HB1_za_data[2] = DFFEAS(A1L39, F1__clk1, N1_data_out, , , , , , ); --AB1L293 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_dbs_16_reg_segment_0[2]~1010 AB1L293 = JB1_cpu_0_data_master_requests_sdram_0_s1 & HB1_za_data[2] # !JB1_cpu_0_data_master_requests_sdram_0_s1 & (KE1_oDATA[2]); --FE2_q_b[2] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2|q_b[2] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1 --Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered FE2_q_b[2]_PORT_A_data_in = VD1_wdata[2]; FE2_q_b[2]_PORT_A_data_in_reg = DFFE(FE2_q_b[2]_PORT_A_data_in, FE2_q_b[2]_clock_0, , , FE2_q_b[2]_clock_enable_0); FE2_q_b[2]_PORT_A_address = BUS(DE4_safe_q[0], DE4_safe_q[1], DE4_safe_q[2], DE4_safe_q[3], DE4_safe_q[4], DE4_safe_q[5]); FE2_q_b[2]_PORT_A_address_reg = DFFE(FE2_q_b[2]_PORT_A_address, FE2_q_b[2]_clock_0, , , FE2_q_b[2]_clock_enable_0); FE2_q_b[2]_PORT_B_address = BUS(DE3_safe_q[0], DE3_safe_q[1], DE3_safe_q[2], DE3_safe_q[3], DE3_safe_q[4], DE3_safe_q[5]); FE2_q_b[2]_PORT_B_address_reg = DFFE(FE2_q_b[2]_PORT_B_address, FE2_q_b[2]_clock_1, , , FE2_q_b[2]_clock_enable_1); FE2_q_b[2]_PORT_A_write_enable = VCC; FE2_q_b[2]_PORT_A_write_enable_reg = DFFE(FE2_q_b[2]_PORT_A_write_enable, FE2_q_b[2]_clock_0, , , FE2_q_b[2]_clock_enable_0); FE2_q_b[2]_PORT_B_read_enable = VCC; FE2_q_b[2]_PORT_B_read_enable_reg = DFFE(FE2_q_b[2]_PORT_B_read_enable, FE2_q_b[2]_clock_1, , , FE2_q_b[2]_clock_enable_1); FE2_q_b[2]_clock_0 = F1__clk1; FE2_q_b[2]_clock_1 = F1__clk1; FE2_q_b[2]_clock_enable_0 = FB1_wr_rfifo; FE2_q_b[2]_clock_enable_1 = FB1L57; FE2_q_b[2]_PORT_B_data_out = MEMORY(FE2_q_b[2]_PORT_A_data_in_reg, , FE2_q_b[2]_PORT_A_address_reg, FE2_q_b[2]_PORT_B_address_reg, FE2_q_b[2]_PORT_A_write_enable_reg, FE2_q_b[2]_PORT_B_read_enable_reg, , , FE2_q_b[2]_clock_0, FE2_q_b[2]_clock_1, FE2_q_b[2]_clock_enable_0, FE2_q_b[2]_clock_enable_1, , ); FE2_q_b[2] = FE2_q_b[2]_PORT_B_data_out[0]; --AB1L311 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[2]~1308 AB1L311 = FE2_q_b[2] & FB1_read_0; --AB1L312 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[2]~1309 AB1L312 = AB1L311 & (AB1_dbs_16_reg_segment_0[2] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !AB1L311 & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (AB1_dbs_16_reg_segment_0[2] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --LE1L52 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data~10 LE1L52 = Z1_d_address[2] & LE1_tx_data[2] & !Z1_d_address[3] & !Z1_d_address[4]; --ME1_rx_data[2] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|rx_data[2] ME1_rx_data[2] = DFFEAS(ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3], F1__clk1, N1_data_out, , ME1_got_new_char, , , , ); --LE1L38 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data[2]~679 LE1L38 = LE1L2 & (LE1_control_reg[2] # LE1L3 & ME1_rx_data[2]) # !LE1L2 & LE1L3 & ME1_rx_data[2]; --LE1L39 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data[2]~680 LE1L39 = LE1L52 # LE1L38 # LE1L1 & ME1_break_detect; --X1_read_mux_out[2] is system_0:u0|Switch:the_Switch|read_mux_out[2] X1_read_mux_out[2] = SW[2] & !Z1_d_address[2] & !Z1_d_address[3]; --P1L40 is system_0:u0|KEY:the_KEY|readdata[2]~10 P1L40 = Z1_d_address[3] & (P1_irq_mask[2]) # !Z1_d_address[3] & KEY[2]; --P1L30 is system_0:u0|KEY:the_KEY|read_mux_out[2]~58 P1L30 = Z1_d_address[3] & P1_edge_capture[2]; --SD1_endofpacketvalue_reg[2] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[2] SD1_endofpacketvalue_reg[2] = DFFEAS(Z1_d_writedata[2], F1__clk1, N1_data_out, , SD1_endofpacketvalue_wr_strobe, , , , ); --SD1_epcs_slave_select_reg[2] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[2] SD1_epcs_slave_select_reg[2] = DFFEAS(SD1_epcs_slave_select_holding_reg[2], F1__clk1, N1_data_out, , SD1L50, , , , ); --SD1_rx_holding_reg[2] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[2] SD1_rx_holding_reg[2] = DFFEAS(SD1_shift_reg[2], F1__clk1, N1_data_out, , SD1L26, , , , ); --SD1L144 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[2]~1349 SD1L144 = SD1L18 & SD1_epcs_slave_select_reg[2] # !SD1L18 & (SD1_rx_holding_reg[2]); --SD1L145 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[2]~1350 SD1L145 = !SD1L56 & (SD1L19 & SD1_endofpacketvalue_reg[2] # !SD1L19 & (SD1L144)); --ED1_MonDReg[3] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[3] ED1_MonDReg[3] = AMPP_FUNCTION(F1__clk1, ED1L74, FD1L25Q, D1_CLRN_SIGNAL, FD1L198, ED1L33); --HB1_za_data[3] is system_0:u0|sdram_0:the_sdram_0|za_data[3] HB1_za_data[3] = DFFEAS(A1L41, F1__clk1, N1_data_out, , , , , , ); --AB1L294 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_dbs_16_reg_segment_0[3]~1011 AB1L294 = JB1_cpu_0_data_master_requests_sdram_0_s1 & HB1_za_data[3] # !JB1_cpu_0_data_master_requests_sdram_0_s1 & (KE1_oDATA[3]); --FE2_q_b[3] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2|q_b[3] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1 --Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered FE2_q_b[3]_PORT_A_data_in = VD1_wdata[3]; FE2_q_b[3]_PORT_A_data_in_reg = DFFE(FE2_q_b[3]_PORT_A_data_in, FE2_q_b[3]_clock_0, , , FE2_q_b[3]_clock_enable_0); FE2_q_b[3]_PORT_A_address = BUS(DE4_safe_q[0], DE4_safe_q[1], DE4_safe_q[2], DE4_safe_q[3], DE4_safe_q[4], DE4_safe_q[5]); FE2_q_b[3]_PORT_A_address_reg = DFFE(FE2_q_b[3]_PORT_A_address, FE2_q_b[3]_clock_0, , , FE2_q_b[3]_clock_enable_0); FE2_q_b[3]_PORT_B_address = BUS(DE3_safe_q[0], DE3_safe_q[1], DE3_safe_q[2], DE3_safe_q[3], DE3_safe_q[4], DE3_safe_q[5]); FE2_q_b[3]_PORT_B_address_reg = DFFE(FE2_q_b[3]_PORT_B_address, FE2_q_b[3]_clock_1, , , FE2_q_b[3]_clock_enable_1); FE2_q_b[3]_PORT_A_write_enable = VCC; FE2_q_b[3]_PORT_A_write_enable_reg = DFFE(FE2_q_b[3]_PORT_A_write_enable, FE2_q_b[3]_clock_0, , , FE2_q_b[3]_clock_enable_0); FE2_q_b[3]_PORT_B_read_enable = VCC; FE2_q_b[3]_PORT_B_read_enable_reg = DFFE(FE2_q_b[3]_PORT_B_read_enable, FE2_q_b[3]_clock_1, , , FE2_q_b[3]_clock_enable_1); FE2_q_b[3]_clock_0 = F1__clk1; FE2_q_b[3]_clock_1 = F1__clk1; FE2_q_b[3]_clock_enable_0 = FB1_wr_rfifo; FE2_q_b[3]_clock_enable_1 = FB1L57; FE2_q_b[3]_PORT_B_data_out = MEMORY(FE2_q_b[3]_PORT_A_data_in_reg, , FE2_q_b[3]_PORT_A_address_reg, FE2_q_b[3]_PORT_B_address_reg, FE2_q_b[3]_PORT_A_write_enable_reg, FE2_q_b[3]_PORT_B_read_enable_reg, , , FE2_q_b[3]_clock_0, FE2_q_b[3]_clock_1, FE2_q_b[3]_clock_enable_0, FE2_q_b[3]_clock_enable_1, , ); FE2_q_b[3] = FE2_q_b[3]_PORT_B_data_out[0]; --AB1L313 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[3]~1310 AB1L313 = FE2_q_b[3] & FB1_read_0; --AB1L314 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[3]~1311 AB1L314 = AB1L313 & (AB1_dbs_16_reg_segment_0[3] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !AB1L313 & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (AB1_dbs_16_reg_segment_0[3] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --LE1L53 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data~11 LE1L53 = Z1_d_address[2] & LE1_tx_data[3] & !Z1_d_address[3] & !Z1_d_address[4]; --ME1_rx_data[3] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|rx_data[3] ME1_rx_data[3] = DFFEAS(ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4], F1__clk1, N1_data_out, , ME1_got_new_char, , , , ); --LE1L40 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data[3]~681 LE1L40 = LE1L2 & (LE1_control_reg[3] # LE1L3 & ME1_rx_data[3]) # !LE1L2 & LE1L3 & ME1_rx_data[3]; --LE1L41 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data[3]~682 LE1L41 = LE1L53 # LE1L40 # LE1L1 & ME1_rx_overrun; --X1_read_mux_out[3] is system_0:u0|Switch:the_Switch|read_mux_out[3] X1_read_mux_out[3] = SW[3] & !Z1_d_address[2] & !Z1_d_address[3]; --P1L43 is system_0:u0|KEY:the_KEY|readdata[3]~11 P1L43 = Z1_d_address[3] & (P1_irq_mask[3]) # !Z1_d_address[3] & KEY[3]; --P1L31 is system_0:u0|KEY:the_KEY|read_mux_out[3]~59 P1L31 = Z1_d_address[3] & P1_edge_capture[3]; --SD1_epcs_slave_select_reg[3] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[3] SD1_epcs_slave_select_reg[3] = DFFEAS(SD1_epcs_slave_select_holding_reg[3], F1__clk1, N1_data_out, , SD1L50, , , , ); --SD1L63 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[6]~214 SD1L63 = EB1L9 & (EB1L10 $ EB1L11); --SD1_endofpacketvalue_reg[3] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[3] SD1_endofpacketvalue_reg[3] = DFFEAS(Z1_d_writedata[3], F1__clk1, N1_data_out, , SD1_endofpacketvalue_wr_strobe, , , , ); --SD1L64 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[6]~215 SD1L64 = EB1L10 & (EB1L9 $ EB1L11); --SD1_rx_holding_reg[3] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[3] SD1_rx_holding_reg[3] = DFFEAS(SD1_shift_reg[3], F1__clk1, N1_data_out, , SD1L26, , , , ); --SD1L146 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[3]~1351 SD1L146 = SD1L63 & (SD1L64) # !SD1L63 & (SD1L64 & SD1_endofpacketvalue_reg[3] # !SD1L64 & (SD1_rx_holding_reg[3])); --SD1L147 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[3]~1352 SD1L147 = SD1L63 & (SD1L146 & (SD1_iROE_reg) # !SD1L146 & SD1_epcs_slave_select_reg[3]) # !SD1L63 & (SD1L146); --SD1L148 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[3]~1353 SD1L148 = SD1L56 & (EB1L9 & SD1L147 # !EB1L9 & (SD1_ROE)) # !SD1L56 & SD1L147; --FE2_q_b[4] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2|q_b[4] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1 --Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered FE2_q_b[4]_PORT_A_data_in = VD1_wdata[4]; FE2_q_b[4]_PORT_A_data_in_reg = DFFE(FE2_q_b[4]_PORT_A_data_in, FE2_q_b[4]_clock_0, , , FE2_q_b[4]_clock_enable_0); FE2_q_b[4]_PORT_A_address = BUS(DE4_safe_q[0], DE4_safe_q[1], DE4_safe_q[2], DE4_safe_q[3], DE4_safe_q[4], DE4_safe_q[5]); FE2_q_b[4]_PORT_A_address_reg = DFFE(FE2_q_b[4]_PORT_A_address, FE2_q_b[4]_clock_0, , , FE2_q_b[4]_clock_enable_0); FE2_q_b[4]_PORT_B_address = BUS(DE3_safe_q[0], DE3_safe_q[1], DE3_safe_q[2], DE3_safe_q[3], DE3_safe_q[4], DE3_safe_q[5]); FE2_q_b[4]_PORT_B_address_reg = DFFE(FE2_q_b[4]_PORT_B_address, FE2_q_b[4]_clock_1, , , FE2_q_b[4]_clock_enable_1); FE2_q_b[4]_PORT_A_write_enable = VCC; FE2_q_b[4]_PORT_A_write_enable_reg = DFFE(FE2_q_b[4]_PORT_A_write_enable, FE2_q_b[4]_clock_0, , , FE2_q_b[4]_clock_enable_0); FE2_q_b[4]_PORT_B_read_enable = VCC; FE2_q_b[4]_PORT_B_read_enable_reg = DFFE(FE2_q_b[4]_PORT_B_read_enable, FE2_q_b[4]_clock_1, , , FE2_q_b[4]_clock_enable_1); FE2_q_b[4]_clock_0 = F1__clk1; FE2_q_b[4]_clock_1 = F1__clk1; FE2_q_b[4]_clock_enable_0 = FB1_wr_rfifo; FE2_q_b[4]_clock_enable_1 = FB1L57; FE2_q_b[4]_PORT_B_data_out = MEMORY(FE2_q_b[4]_PORT_A_data_in_reg, , FE2_q_b[4]_PORT_A_address_reg, FE2_q_b[4]_PORT_B_address_reg, FE2_q_b[4]_PORT_A_write_enable_reg, FE2_q_b[4]_PORT_B_read_enable_reg, , , FE2_q_b[4]_clock_0, FE2_q_b[4]_clock_1, FE2_q_b[4]_clock_enable_0, FE2_q_b[4]_clock_enable_1, , ); FE2_q_b[4] = FE2_q_b[4]_PORT_B_data_out[0]; --AB1L315 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[4]~1312 AB1L315 = FE2_q_b[4] & FB1_read_0; --AB1L316 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[4]~1313 AB1L316 = AB1L315 & (AB1_dbs_16_reg_segment_0[4] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !AB1L315 & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (AB1_dbs_16_reg_segment_0[4] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --HB1_za_data[4] is system_0:u0|sdram_0:the_sdram_0|za_data[4] HB1_za_data[4] = DFFEAS(A1L43, F1__clk1, N1_data_out, , , , , , ); --AB1L295 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_dbs_16_reg_segment_0[4]~1012 AB1L295 = JB1_cpu_0_data_master_requests_sdram_0_s1 & HB1_za_data[4] # !JB1_cpu_0_data_master_requests_sdram_0_s1 & (KE1_oDATA[4]); --X1_read_mux_out[4] is system_0:u0|Switch:the_Switch|read_mux_out[4] X1_read_mux_out[4] = SW[4] & !Z1_d_address[2] & !Z1_d_address[3]; --LE1L54 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data~12 LE1L54 = Z1_d_address[2] & LE1_tx_data[4] & !Z1_d_address[3] & !Z1_d_address[4]; --ME1_rx_data[4] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|rx_data[4] ME1_rx_data[4] = DFFEAS(ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5], F1__clk1, N1_data_out, , ME1_got_new_char, , , , ); --LE1L42 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data[4]~683 LE1L42 = LE1L2 & (LE1_control_reg[4] # LE1L3 & ME1_rx_data[4]) # !LE1L2 & LE1L3 & ME1_rx_data[4]; --LE1L43 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data[4]~684 LE1L43 = LE1L54 # LE1L42 # LE1L1 & NE1_tx_overrun; --SD1_endofpacketvalue_reg[4] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[4] SD1_endofpacketvalue_reg[4] = DFFEAS(Z1_d_writedata[4], F1__clk1, N1_data_out, , SD1_endofpacketvalue_wr_strobe, , , , ); --SD1_epcs_slave_select_reg[4] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[4] SD1_epcs_slave_select_reg[4] = DFFEAS(SD1_epcs_slave_select_holding_reg[4], F1__clk1, N1_data_out, , SD1L50, , , , ); --SD1_rx_holding_reg[4] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[4] SD1_rx_holding_reg[4] = DFFEAS(SD1_shift_reg[4], F1__clk1, N1_data_out, , SD1L26, , , , ); --SD1L149 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[4]~1354 SD1L149 = SD1L64 & (SD1L63) # !SD1L64 & (SD1L63 & SD1_epcs_slave_select_reg[4] # !SD1L63 & (SD1_rx_holding_reg[4])); --SD1L150 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[4]~1355 SD1L150 = SD1L64 & (SD1L149 & (SD1_iTOE_reg) # !SD1L149 & SD1_endofpacketvalue_reg[4]) # !SD1L64 & (SD1L149); --SD1L151 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[4]~1356 SD1L151 = SD1L56 & (EB1L9 & SD1L150 # !EB1L9 & (SD1_TOE)) # !SD1L56 & SD1L150; --ED1_MonDReg[4] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[4] ED1_MonDReg[4] = AMPP_FUNCTION(F1__clk1, ED1L76, FD1L26Q, D1_CLRN_SIGNAL, FD1L198, ED1L33); --FE2_q_b[5] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2|q_b[5] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1 --Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered FE2_q_b[5]_PORT_A_data_in = VD1_wdata[5]; FE2_q_b[5]_PORT_A_data_in_reg = DFFE(FE2_q_b[5]_PORT_A_data_in, FE2_q_b[5]_clock_0, , , FE2_q_b[5]_clock_enable_0); FE2_q_b[5]_PORT_A_address = BUS(DE4_safe_q[0], DE4_safe_q[1], DE4_safe_q[2], DE4_safe_q[3], DE4_safe_q[4], DE4_safe_q[5]); FE2_q_b[5]_PORT_A_address_reg = DFFE(FE2_q_b[5]_PORT_A_address, FE2_q_b[5]_clock_0, , , FE2_q_b[5]_clock_enable_0); FE2_q_b[5]_PORT_B_address = BUS(DE3_safe_q[0], DE3_safe_q[1], DE3_safe_q[2], DE3_safe_q[3], DE3_safe_q[4], DE3_safe_q[5]); FE2_q_b[5]_PORT_B_address_reg = DFFE(FE2_q_b[5]_PORT_B_address, FE2_q_b[5]_clock_1, , , FE2_q_b[5]_clock_enable_1); FE2_q_b[5]_PORT_A_write_enable = VCC; FE2_q_b[5]_PORT_A_write_enable_reg = DFFE(FE2_q_b[5]_PORT_A_write_enable, FE2_q_b[5]_clock_0, , , FE2_q_b[5]_clock_enable_0); FE2_q_b[5]_PORT_B_read_enable = VCC; FE2_q_b[5]_PORT_B_read_enable_reg = DFFE(FE2_q_b[5]_PORT_B_read_enable, FE2_q_b[5]_clock_1, , , FE2_q_b[5]_clock_enable_1); FE2_q_b[5]_clock_0 = F1__clk1; FE2_q_b[5]_clock_1 = F1__clk1; FE2_q_b[5]_clock_enable_0 = FB1_wr_rfifo; FE2_q_b[5]_clock_enable_1 = FB1L57; FE2_q_b[5]_PORT_B_data_out = MEMORY(FE2_q_b[5]_PORT_A_data_in_reg, , FE2_q_b[5]_PORT_A_address_reg, FE2_q_b[5]_PORT_B_address_reg, FE2_q_b[5]_PORT_A_write_enable_reg, FE2_q_b[5]_PORT_B_read_enable_reg, , , FE2_q_b[5]_clock_0, FE2_q_b[5]_clock_1, FE2_q_b[5]_clock_enable_0, FE2_q_b[5]_clock_enable_1, , ); FE2_q_b[5] = FE2_q_b[5]_PORT_B_data_out[0]; --AB1L317 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[5]~1314 AB1L317 = FE2_q_b[5] & FB1_read_0; --AB1L318 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[5]~1315 AB1L318 = AB1L317 & (AB1_dbs_16_reg_segment_0[5] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !AB1L317 & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (AB1_dbs_16_reg_segment_0[5] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --HB1_za_data[5] is system_0:u0|sdram_0:the_sdram_0|za_data[5] HB1_za_data[5] = DFFEAS(A1L45, F1__clk1, N1_data_out, , , , , , ); --AB1L296 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_dbs_16_reg_segment_0[5]~1013 AB1L296 = JB1_cpu_0_data_master_requests_sdram_0_s1 & HB1_za_data[5] # !JB1_cpu_0_data_master_requests_sdram_0_s1 & (KE1_oDATA[5]); --X1_read_mux_out[5] is system_0:u0|Switch:the_Switch|read_mux_out[5] X1_read_mux_out[5] = SW[5] & !Z1_d_address[2] & !Z1_d_address[3]; --LE1L55 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data~13 LE1L55 = Z1_d_address[2] & LE1_tx_data[5] & !Z1_d_address[3] & !Z1_d_address[4]; --ME1_rx_data[5] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|rx_data[5] ME1_rx_data[5] = DFFEAS(ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6], F1__clk1, N1_data_out, , ME1_got_new_char, , , , ); --LE1L44 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data[5]~685 LE1L44 = LE1L2 & (LE1_control_reg[5] # LE1L3 & ME1_rx_data[5]) # !LE1L2 & LE1L3 & ME1_rx_data[5]; --LE1L45 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data[5]~686 LE1L45 = LE1L55 # LE1L44 # LE1L1 & !NE1_tx_shift_empty; --SD1_endofpacketvalue_reg[5] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[5] SD1_endofpacketvalue_reg[5] = DFFEAS(Z1_d_writedata[5], F1__clk1, N1_data_out, , SD1_endofpacketvalue_wr_strobe, , , , ); --SD1_epcs_slave_select_reg[5] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[5] SD1_epcs_slave_select_reg[5] = DFFEAS(SD1_epcs_slave_select_holding_reg[5], F1__clk1, N1_data_out, , SD1L50, , , , ); --SD1_rx_holding_reg[5] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[5] SD1_rx_holding_reg[5] = DFFEAS(SD1_shift_reg[5], F1__clk1, N1_data_out, , SD1L26, , , , ); --SD1L20 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal~765 SD1L20 = !EB1L10 & (EB1L26 & Z1_d_address[2] # !EB1L26 & (Z1_ic_fill_ap_offset[0])); --SD1L152 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[5]~1357 SD1L152 = EB1L11 & (SD1L20 & SD1_epcs_slave_select_reg[5] # !SD1L20 & (SD1_rx_holding_reg[5])) # !EB1L11 & (SD1_rx_holding_reg[5]); --SD1L153 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[5]~1358 SD1L153 = SD1L19 & SD1_endofpacketvalue_reg[5] # !SD1L19 & (SD1L152); --SD1L154 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[5]~1359 SD1L154 = !SD1_tx_holding_primed & !SD1_transmitting; --SD1L155 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[5]~1360 SD1L155 = SD1L56 & (SD1L154 & !EB1L9) # !SD1L56 & SD1L153; --ED1_MonDReg[5] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[5] ED1_MonDReg[5] = AMPP_FUNCTION(F1__clk1, ED1L77, FD1L27Q, D1_CLRN_SIGNAL, FD1L198, ED1L33); --FE2_q_b[6] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2|q_b[6] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1 --Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered FE2_q_b[6]_PORT_A_data_in = VD1_wdata[6]; FE2_q_b[6]_PORT_A_data_in_reg = DFFE(FE2_q_b[6]_PORT_A_data_in, FE2_q_b[6]_clock_0, , , FE2_q_b[6]_clock_enable_0); FE2_q_b[6]_PORT_A_address = BUS(DE4_safe_q[0], DE4_safe_q[1], DE4_safe_q[2], DE4_safe_q[3], DE4_safe_q[4], DE4_safe_q[5]); FE2_q_b[6]_PORT_A_address_reg = DFFE(FE2_q_b[6]_PORT_A_address, FE2_q_b[6]_clock_0, , , FE2_q_b[6]_clock_enable_0); FE2_q_b[6]_PORT_B_address = BUS(DE3_safe_q[0], DE3_safe_q[1], DE3_safe_q[2], DE3_safe_q[3], DE3_safe_q[4], DE3_safe_q[5]); FE2_q_b[6]_PORT_B_address_reg = DFFE(FE2_q_b[6]_PORT_B_address, FE2_q_b[6]_clock_1, , , FE2_q_b[6]_clock_enable_1); FE2_q_b[6]_PORT_A_write_enable = VCC; FE2_q_b[6]_PORT_A_write_enable_reg = DFFE(FE2_q_b[6]_PORT_A_write_enable, FE2_q_b[6]_clock_0, , , FE2_q_b[6]_clock_enable_0); FE2_q_b[6]_PORT_B_read_enable = VCC; FE2_q_b[6]_PORT_B_read_enable_reg = DFFE(FE2_q_b[6]_PORT_B_read_enable, FE2_q_b[6]_clock_1, , , FE2_q_b[6]_clock_enable_1); FE2_q_b[6]_clock_0 = F1__clk1; FE2_q_b[6]_clock_1 = F1__clk1; FE2_q_b[6]_clock_enable_0 = FB1_wr_rfifo; FE2_q_b[6]_clock_enable_1 = FB1L57; FE2_q_b[6]_PORT_B_data_out = MEMORY(FE2_q_b[6]_PORT_A_data_in_reg, , FE2_q_b[6]_PORT_A_address_reg, FE2_q_b[6]_PORT_B_address_reg, FE2_q_b[6]_PORT_A_write_enable_reg, FE2_q_b[6]_PORT_B_read_enable_reg, , , FE2_q_b[6]_clock_0, FE2_q_b[6]_clock_1, FE2_q_b[6]_clock_enable_0, FE2_q_b[6]_clock_enable_1, , ); FE2_q_b[6] = FE2_q_b[6]_PORT_B_data_out[0]; --AB1L319 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[6]~1316 AB1L319 = FE2_q_b[6] & FB1_read_0; --AB1L320 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[6]~1317 AB1L320 = AB1L319 & (AB1_dbs_16_reg_segment_0[6] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !AB1L319 & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (AB1_dbs_16_reg_segment_0[6] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --AB1L297 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_dbs_16_reg_segment_0[6]~1014 AB1L297 = JB1_cpu_0_data_master_requests_sdram_0_s1 & HB1_za_data[6] # !JB1_cpu_0_data_master_requests_sdram_0_s1 & (KE1_oDATA[6]); --X1_read_mux_out[6] is system_0:u0|Switch:the_Switch|read_mux_out[6] X1_read_mux_out[6] = SW[6] & !Z1_d_address[2] & !Z1_d_address[3]; --LE1L56 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data~14 LE1L56 = Z1_d_address[2] & LE1_tx_data[6] & !Z1_d_address[3] & !Z1_d_address[4]; --ME1_rx_data[6] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|rx_data[6] ME1_rx_data[6] = DFFEAS(ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7], F1__clk1, N1_data_out, , ME1_got_new_char, , , , ); --LE1L46 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data[6]~687 LE1L46 = LE1L2 & (LE1_control_reg[6] # LE1L3 & ME1_rx_data[6]) # !LE1L2 & LE1L3 & ME1_rx_data[6]; --LE1L47 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data[6]~688 LE1L47 = LE1L56 # LE1L46 # LE1L1 & !NE1_tx_ready; --SD1_epcs_slave_select_reg[6] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[6] SD1_epcs_slave_select_reg[6] = DFFEAS(SD1_epcs_slave_select_holding_reg[6], F1__clk1, N1_data_out, , SD1L50, , , , ); --SD1_endofpacketvalue_reg[6] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[6] SD1_endofpacketvalue_reg[6] = DFFEAS(Z1_d_writedata[6], F1__clk1, N1_data_out, , SD1_endofpacketvalue_wr_strobe, , , , ); --SD1_rx_holding_reg[6] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[6] SD1_rx_holding_reg[6] = DFFEAS(SD1_shift_reg[6], F1__clk1, N1_data_out, , SD1L26, , , , ); --SD1L156 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[6]~1361 SD1L156 = SD1L63 & (SD1L64) # !SD1L63 & (SD1L64 & SD1_endofpacketvalue_reg[6] # !SD1L64 & (SD1_rx_holding_reg[6])); --SD1L157 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[6]~1362 SD1L157 = SD1L63 & (SD1L156 & (SD1_iTRDY_reg) # !SD1L156 & SD1_epcs_slave_select_reg[6]) # !SD1L63 & (SD1L156); --SD1L158 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[6]~1363 SD1L158 = SD1L56 & (EB1L9 & SD1L157 # !EB1L9 & (SD1L39)) # !SD1L56 & SD1L157; --ED1_MonDReg[6] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[6] ED1_MonDReg[6] = AMPP_FUNCTION(F1__clk1, ED1L78, D1_CLRN_SIGNAL, ED1L33); --FE2_q_b[7] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2|q_b[7] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1 --Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered FE2_q_b[7]_PORT_A_data_in = VD1_wdata[7]; FE2_q_b[7]_PORT_A_data_in_reg = DFFE(FE2_q_b[7]_PORT_A_data_in, FE2_q_b[7]_clock_0, , , FE2_q_b[7]_clock_enable_0); FE2_q_b[7]_PORT_A_address = BUS(DE4_safe_q[0], DE4_safe_q[1], DE4_safe_q[2], DE4_safe_q[3], DE4_safe_q[4], DE4_safe_q[5]); FE2_q_b[7]_PORT_A_address_reg = DFFE(FE2_q_b[7]_PORT_A_address, FE2_q_b[7]_clock_0, , , FE2_q_b[7]_clock_enable_0); FE2_q_b[7]_PORT_B_address = BUS(DE3_safe_q[0], DE3_safe_q[1], DE3_safe_q[2], DE3_safe_q[3], DE3_safe_q[4], DE3_safe_q[5]); FE2_q_b[7]_PORT_B_address_reg = DFFE(FE2_q_b[7]_PORT_B_address, FE2_q_b[7]_clock_1, , , FE2_q_b[7]_clock_enable_1); FE2_q_b[7]_PORT_A_write_enable = VCC; FE2_q_b[7]_PORT_A_write_enable_reg = DFFE(FE2_q_b[7]_PORT_A_write_enable, FE2_q_b[7]_clock_0, , , FE2_q_b[7]_clock_enable_0); FE2_q_b[7]_PORT_B_read_enable = VCC; FE2_q_b[7]_PORT_B_read_enable_reg = DFFE(FE2_q_b[7]_PORT_B_read_enable, FE2_q_b[7]_clock_1, , , FE2_q_b[7]_clock_enable_1); FE2_q_b[7]_clock_0 = F1__clk1; FE2_q_b[7]_clock_1 = F1__clk1; FE2_q_b[7]_clock_enable_0 = FB1_wr_rfifo; FE2_q_b[7]_clock_enable_1 = FB1L57; FE2_q_b[7]_PORT_B_data_out = MEMORY(FE2_q_b[7]_PORT_A_data_in_reg, , FE2_q_b[7]_PORT_A_address_reg, FE2_q_b[7]_PORT_B_address_reg, FE2_q_b[7]_PORT_A_write_enable_reg, FE2_q_b[7]_PORT_B_read_enable_reg, , , FE2_q_b[7]_clock_0, FE2_q_b[7]_clock_1, FE2_q_b[7]_clock_enable_0, FE2_q_b[7]_clock_enable_1, , ); FE2_q_b[7] = FE2_q_b[7]_PORT_B_data_out[0]; --AB1L321 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[7]~1318 AB1L321 = FE2_q_b[7] & FB1_read_0; --AB1L322 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[7]~1319 AB1L322 = AB1L321 & (AB1_dbs_16_reg_segment_0[7] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !AB1L321 & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (AB1_dbs_16_reg_segment_0[7] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --AB1L298 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_dbs_16_reg_segment_0[7]~1015 AB1L298 = JB1_cpu_0_data_master_requests_sdram_0_s1 & HB1_za_data[7] # !JB1_cpu_0_data_master_requests_sdram_0_s1 & (KE1_oDATA[7]); --X1_read_mux_out[7] is system_0:u0|Switch:the_Switch|read_mux_out[7] X1_read_mux_out[7] = SW[7] & !Z1_d_address[2] & !Z1_d_address[3]; --LE1L57 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data~15 LE1L57 = Z1_d_address[2] & LE1_tx_data[7] & !Z1_d_address[3] & !Z1_d_address[4]; --ME1_rx_data[7] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|rx_data[7] ME1_rx_data[7] = DFFEAS(ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8], F1__clk1, N1_data_out, , ME1_got_new_char, , , , ); --LE1L48 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data[7]~689 LE1L48 = LE1L2 & (LE1_control_reg[7] # LE1L3 & ME1_rx_data[7]) # !LE1L2 & LE1L3 & ME1_rx_data[7]; --LE1L49 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data[7]~690 LE1L49 = LE1L57 # LE1L48 # LE1L1 & ME1_rx_char_ready; --SD1_endofpacketvalue_reg[7] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[7] SD1_endofpacketvalue_reg[7] = DFFEAS(Z1_d_writedata[7], F1__clk1, N1_data_out, , SD1_endofpacketvalue_wr_strobe, , , , ); --SD1_epcs_slave_select_reg[7] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[7] SD1_epcs_slave_select_reg[7] = DFFEAS(SD1_epcs_slave_select_holding_reg[7], F1__clk1, N1_data_out, , SD1L50, , , , ); --SD1_rx_holding_reg[7] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[7] SD1_rx_holding_reg[7] = DFFEAS(SD1_shift_reg[7], F1__clk1, N1_data_out, , SD1L26, , , , ); --SD1L159 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[7]~1364 SD1L159 = SD1L64 & (SD1L63) # !SD1L64 & (SD1L63 & SD1_epcs_slave_select_reg[7] # !SD1L63 & (SD1_rx_holding_reg[7])); --SD1L160 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[7]~1365 SD1L160 = SD1L64 & (SD1L159 & (SD1_iRRDY_reg) # !SD1L159 & SD1_endofpacketvalue_reg[7]) # !SD1L64 & (SD1L159); --SD1L161 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[7]~1366 SD1L161 = SD1L56 & (EB1L9 & SD1L160 # !EB1L9 & (SD1_RRDY)) # !SD1L56 & SD1L160; --ED1_MonDReg[7] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[7] ED1_MonDReg[7] = AMPP_FUNCTION(F1__clk1, ED1L79, D1_CLRN_SIGNAL, ED1L33); --AB1L323 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[8]~1320 AB1L323 = FB1L40 & (AB1_dbs_16_reg_segment_0[8] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !FB1L40 & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (AB1_dbs_16_reg_segment_0[8] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --AB1L4 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always6~0 AB1L4 = AB1_cpu_0_data_master_dbs_address[0] & AB1L287 & !AB1_cpu_0_data_master_dbs_address[1]; --AB1L299 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_dbs_16_reg_segment_0[8]~1016 AB1L299 = JB1_cpu_0_data_master_requests_sdram_0_s1 & HB1_za_data[8] # !JB1_cpu_0_data_master_requests_sdram_0_s1 & (KE1_oDATA[8]); --X1_read_mux_out[8] is system_0:u0|Switch:the_Switch|read_mux_out[8] X1_read_mux_out[8] = SW[8] & !Z1_d_address[2] & !Z1_d_address[3]; --LE1_selected_read_data[8] is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data[8] LE1_selected_read_data[8] = LE1L1 & (LE1L59 # LE1L2 & LE1_control_reg[8]) # !LE1L1 & LE1L2 & LE1_control_reg[8]; --SD1_endofpacketvalue_reg[8] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[8] SD1_endofpacketvalue_reg[8] = DFFEAS(Z1_d_writedata[8], F1__clk1, N1_data_out, , SD1_endofpacketvalue_wr_strobe, , , , ); --SD1_epcs_slave_select_reg[8] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[8] SD1_epcs_slave_select_reg[8] = DFFEAS(SD1_epcs_slave_select_holding_reg[8], F1__clk1, N1_data_out, , SD1L50, , , , ); --SD1L162 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[8]~1367 SD1L162 = SD1L67 & (SD1L56) # !SD1L67 & (SD1L56 & SD1_iE_reg # !SD1L56 & (SD1_epcs_slave_select_reg[8])); --SD1_E is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|E SD1_E = SD1_ROE # SD1_TOE; --SD1L163 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[8]~1368 SD1L163 = SD1L67 & (SD1L162 & (SD1_E) # !SD1L162 & SD1_endofpacketvalue_reg[8]) # !SD1L67 & (SD1L162); --SD1L164 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[8]~1369 SD1L164 = SD1L163 & (EB1L10 $ (EB1L9 & EB1L11)); --CB1L25 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_byteenable[1]~17 CB1L25 = Z1_d_byteenable[1] # !CB1L30; --ED1_MonDReg[8] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[8] ED1_MonDReg[8] = AMPP_FUNCTION(F1__clk1, ED1L80, FD1L30Q, D1_CLRN_SIGNAL, FD1L198, ED1L33); --AB1L324 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[9]~1321 AB1L324 = Z1L178 & (AB1_dbs_16_reg_segment_0[9] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !Z1L178 & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (AB1_dbs_16_reg_segment_0[9] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --AB1L300 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_dbs_16_reg_segment_0[9]~1017 AB1L300 = JB1_cpu_0_data_master_requests_sdram_0_s1 & HB1_za_data[9] # !JB1_cpu_0_data_master_requests_sdram_0_s1 & (KE1_oDATA[9]); --X1_read_mux_out[9] is system_0:u0|Switch:the_Switch|read_mux_out[9] X1_read_mux_out[9] = SW[9] & !Z1_d_address[2] & !Z1_d_address[3]; --LE1L58 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|selected_read_data~50 LE1L58 = Z1_d_address[2] & Z1_d_address[3] & LE1_control_reg[9] & !Z1_d_address[4]; --SD1_endofpacketvalue_reg[9] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[9] SD1_endofpacketvalue_reg[9] = DFFEAS(Z1_d_writedata[9], F1__clk1, N1_data_out, , SD1_endofpacketvalue_wr_strobe, , , , ); --SD1_epcs_slave_select_reg[9] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[9] SD1_epcs_slave_select_reg[9] = DFFEAS(SD1_epcs_slave_select_holding_reg[9], F1__clk1, N1_data_out, , SD1L50, , , , ); --SD1L165 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[9]~1370 SD1L165 = SD1L67 & (SD1L56) # !SD1L67 & (SD1L56 & SD1_iEOP_reg # !SD1L56 & (SD1_epcs_slave_select_reg[9])); --SD1L166 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[9]~1371 SD1L166 = SD1L67 & (SD1L165 & (SD1_EOP) # !SD1L165 & SD1_endofpacketvalue_reg[9]) # !SD1L67 & (SD1L165); --SD1L167 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[9]~1372 SD1L167 = SD1L166 & (EB1L10 $ (EB1L9 & EB1L11)); --ED1_MonDReg[9] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[9] ED1_MonDReg[9] = AMPP_FUNCTION(F1__clk1, ED1L81, FD1L31Q, D1_CLRN_SIGNAL, FD1L198, ED1L33); --AB1L301 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_dbs_16_reg_segment_0[10]~1018 AB1L301 = JB1_cpu_0_data_master_requests_sdram_0_s1 & HB1_za_data[10] # !JB1_cpu_0_data_master_requests_sdram_0_s1 & (KE1_oDATA[10]); --FB1_ac is system_0:u0|jtag_uart_0:the_jtag_uart_0|ac FB1_ac = DFFEAS(FB1L8, F1__clk1, N1_data_out, , , , , , ); --AB1L325 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[10]~1322 AB1L325 = FB1_ac & (AB1_dbs_16_reg_segment_0[10] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !FB1_ac & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (AB1_dbs_16_reg_segment_0[10] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --SD1_SSO_reg is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|SSO_reg SD1_SSO_reg = DFFEAS(Z1_d_writedata[10], F1__clk1, N1_data_out, , SD1_control_wr_strobe, , , , ); --SD1_endofpacketvalue_reg[10] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[10] SD1_endofpacketvalue_reg[10] = DFFEAS(Z1_d_writedata[10], F1__clk1, N1_data_out, , SD1_endofpacketvalue_wr_strobe, , , , ); --SD1_epcs_slave_select_reg[10] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[10] SD1_epcs_slave_select_reg[10] = DFFEAS(SD1_epcs_slave_select_holding_reg[10], F1__clk1, N1_data_out, , SD1L50, , , , ); --SD1L174 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu~1373 SD1L174 = SD1L19 & SD1_endofpacketvalue_reg[10] # !SD1L19 & (SD1L18 & SD1_epcs_slave_select_reg[10]); --SD1L175 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu~1374 SD1L175 = EB1L9 & (SD1L56 & SD1_SSO_reg # !SD1L56 & (SD1L174)) # !EB1L9 & (SD1L174); --ED1_MonDReg[10] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[10] ED1_MonDReg[10] = AMPP_FUNCTION(F1__clk1, ED1L82, D1_CLRN_SIGNAL, ED1L33); --AB1L302 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_dbs_16_reg_segment_0[11]~1019 AB1L302 = JB1_cpu_0_data_master_requests_sdram_0_s1 & HB1_za_data[11] # !JB1_cpu_0_data_master_requests_sdram_0_s1 & (KE1_oDATA[11]); --AB1L326 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[11]~1323 AB1L326 = !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (AB1_dbs_16_reg_segment_0[11] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --SD1L168 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[11]~1375 SD1L168 = EB1L11 & (EB1L9 $ EB1L10); --SD1_endofpacketvalue_reg[11] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[11] SD1_endofpacketvalue_reg[11] = DFFEAS(Z1_d_writedata[11], F1__clk1, N1_data_out, , SD1_endofpacketvalue_wr_strobe, , , , ); --SD1_epcs_slave_select_reg[11] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[11] SD1_epcs_slave_select_reg[11] = DFFEAS(SD1_epcs_slave_select_holding_reg[11], F1__clk1, N1_data_out, , SD1L50, , , , ); --SD1L169 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[11]~1376 SD1L169 = SD1L168 & (SD1L19 & SD1_endofpacketvalue_reg[11] # !SD1L19 & (SD1_epcs_slave_select_reg[11])); --ED1_MonDReg[11] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[11] ED1_MonDReg[11] = AMPP_FUNCTION(F1__clk1, ED1L83, FD1L33Q, D1_CLRN_SIGNAL, FD1L198, ED1L33); --AB1L303 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_dbs_16_reg_segment_0[12]~1020 AB1L303 = JB1_cpu_0_data_master_requests_sdram_0_s1 & HB1_za_data[12] # !JB1_cpu_0_data_master_requests_sdram_0_s1 & (KE1_oDATA[12]); --AB1L327 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[12]~1324 AB1L327 = BE2_b_non_empty & (AB1_dbs_16_reg_segment_0[12] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !BE2_b_non_empty & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (AB1_dbs_16_reg_segment_0[12] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --SD1_endofpacketvalue_reg[12] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[12] SD1_endofpacketvalue_reg[12] = DFFEAS(Z1_d_writedata[12], F1__clk1, N1_data_out, , SD1_endofpacketvalue_wr_strobe, , , , ); --SD1_epcs_slave_select_reg[12] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[12] SD1_epcs_slave_select_reg[12] = DFFEAS(SD1_epcs_slave_select_holding_reg[12], F1__clk1, N1_data_out, , SD1L50, , , , ); --SD1L170 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[12]~1377 SD1L170 = SD1L168 & (SD1L19 & SD1_endofpacketvalue_reg[12] # !SD1L19 & (SD1_epcs_slave_select_reg[12])); --ED1_MonDReg[12] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[12] ED1_MonDReg[12] = AMPP_FUNCTION(F1__clk1, ED1L84, FD1L34Q, D1_CLRN_SIGNAL, FD1L198, ED1L33); --AB1L304 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_dbs_16_reg_segment_0[13]~1021 AB1L304 = JB1_cpu_0_data_master_requests_sdram_0_s1 & HB1_za_data[13] # !JB1_cpu_0_data_master_requests_sdram_0_s1 & (KE1_oDATA[13]); --AB1L328 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[13]~1325 AB1L328 = AB1_dbs_16_reg_segment_0[13] & (!BE1_b_full # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave) # !AB1_dbs_16_reg_segment_0[13] & !JB1_cpu_0_data_master_requests_sdram_0_s1 & (!BE1_b_full # !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave); --SD1_endofpacketvalue_reg[13] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[13] SD1_endofpacketvalue_reg[13] = DFFEAS(Z1_d_writedata[13], F1__clk1, N1_data_out, , SD1_endofpacketvalue_wr_strobe, , , , ); --SD1_epcs_slave_select_reg[13] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[13] SD1_epcs_slave_select_reg[13] = DFFEAS(SD1_epcs_slave_select_holding_reg[13], F1__clk1, N1_data_out, , SD1L50, , , , ); --SD1L171 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[13]~1378 SD1L171 = SD1L168 & (SD1L19 & SD1_endofpacketvalue_reg[13] # !SD1L19 & (SD1_epcs_slave_select_reg[13])); --ED1_MonDReg[13] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[13] ED1_MonDReg[13] = AMPP_FUNCTION(F1__clk1, ED1L85, D1_CLRN_SIGNAL, ED1L33); --AB1L305 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_dbs_16_reg_segment_0[14]~1022 AB1L305 = JB1_cpu_0_data_master_requests_sdram_0_s1 & HB1_za_data[14] # !JB1_cpu_0_data_master_requests_sdram_0_s1 & (KE1_oDATA[14]); --FB1_woverflow is system_0:u0|jtag_uart_0:the_jtag_uart_0|woverflow FB1_woverflow = DFFEAS(FB1L61, F1__clk1, N1_data_out, , , , , , ); --AB1L329 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[14]~1326 AB1L329 = FB1_woverflow & (AB1_dbs_16_reg_segment_0[14] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !FB1_woverflow & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (AB1_dbs_16_reg_segment_0[14] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --SD1_endofpacketvalue_reg[14] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[14] SD1_endofpacketvalue_reg[14] = DFFEAS(Z1_d_writedata[14], F1__clk1, N1_data_out, , SD1_endofpacketvalue_wr_strobe, , , , ); --SD1_epcs_slave_select_reg[14] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[14] SD1_epcs_slave_select_reg[14] = DFFEAS(SD1_epcs_slave_select_holding_reg[14], F1__clk1, N1_data_out, , SD1L50, , , , ); --SD1L172 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[14]~1379 SD1L172 = SD1L168 & (SD1L19 & SD1_endofpacketvalue_reg[14] # !SD1L19 & (SD1_epcs_slave_select_reg[14])); --ED1_MonDReg[14] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[14] ED1_MonDReg[14] = AMPP_FUNCTION(F1__clk1, ED1L86, D1_CLRN_SIGNAL, ED1L33); --AB1L306 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_dbs_16_reg_segment_0[15]~1023 AB1L306 = JB1_cpu_0_data_master_requests_sdram_0_s1 & HB1_za_data[15] # !JB1_cpu_0_data_master_requests_sdram_0_s1 & (KE1_oDATA[15]); --FB1_rvalid is system_0:u0|jtag_uart_0:the_jtag_uart_0|rvalid FB1_rvalid = DFFEAS(FB1L58, F1__clk1, N1_data_out, , , , , , ); --AB1L330 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[15]~1327 AB1L330 = FB1_rvalid & (AB1_dbs_16_reg_segment_0[15] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !FB1_rvalid & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (AB1_dbs_16_reg_segment_0[15] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --SD1_endofpacketvalue_reg[15] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[15] SD1_endofpacketvalue_reg[15] = DFFEAS(Z1_d_writedata[15], F1__clk1, N1_data_out, , SD1_endofpacketvalue_wr_strobe, , , , ); --SD1_epcs_slave_select_reg[15] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[15] SD1_epcs_slave_select_reg[15] = DFFEAS(SD1_epcs_slave_select_holding_reg[15], F1__clk1, N1_data_out, , SD1L50, , , , ); --SD1L173 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[15]~1380 SD1L173 = SD1L168 & (SD1L19 & SD1_endofpacketvalue_reg[15] # !SD1L19 & (SD1_epcs_slave_select_reg[15])); --ED1_MonDReg[15] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[15] ED1_MonDReg[15] = AMPP_FUNCTION(F1__clk1, ED1L87, D1_CLRN_SIGNAL, ED1L33); --PB1L4 is system_0:u0|uart_0_s1_arbitrator:the_uart_0_s1|uart_0_s1_end_xfer~3 PB1L4 = !Z1_d_address[6] & !PB1_d1_reasons_to_wait & LB1L10 & Q1L1; --HE1_stage_5 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|stage_5 HE1_stage_5 = DFFEAS(HE1L38, F1__clk1, , , HE1L15, , , , ); --JE1_full_5 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_5 JE1_full_5 = DFFEAS(HE1L37, F1__clk1, N1_data_out, , HE1L14, , , , ); --HE1L36 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|p4_stage_4~10 HE1L36 = JE1_full_5 & HE1_stage_5 # !JE1_full_5 & (JB1L7); --HE1L16 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|always4~1 HE1L16 = HB1_za_valid # JB1L5 & !JE1_full_4; --HE1L35 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|p4_full_4~9 HE1L35 = HB1_za_valid & (JB1L5 & JE1_full_3 # !JB1L5 & (JE1_full_5)) # !HB1_za_valid & JE1_full_3; --BB1_dbs_latent_8_reg_segment_2[5] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_2[5] BB1_dbs_latent_8_reg_segment_2[5] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[5], F1__clk1, N1_data_out, , BB1L8, , , , ); --BB1L94 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[21]~3041 BB1L94 = BB1_dbs_latent_8_reg_segment_2[5] & (HB1_za_data[5] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_2[5] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (HB1_za_data[5] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L95 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[21]~3042 BB1L95 = BB1L94 & (KE1_oDATA[5] # !LB1L14); --BB1L96 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[21]~3043 BB1L96 = BB1L95 & (UD1_q_a[21] & !DB1L1 # !EB1L29); --BB1L97 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[21]~3044 BB1L97 = BB1L96 & (RD1_q_a[21] & !CB1L14 # !BB1L176); --BB1_dbs_latent_8_reg_segment_2[4] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_2[4] BB1_dbs_latent_8_reg_segment_2[4] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[4], F1__clk1, N1_data_out, , BB1L8, , , , ); --BB1L90 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[20]~3045 BB1L90 = BB1_dbs_latent_8_reg_segment_2[4] & (HB1_za_data[4] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_2[4] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (HB1_za_data[4] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L91 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[20]~3046 BB1L91 = BB1L90 & (KE1_oDATA[4] # !LB1L14); --BB1L92 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[20]~3047 BB1L92 = BB1L91 & (UD1_q_a[20] & !DB1L1 # !EB1L29); --BB1L93 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[20]~3048 BB1L93 = BB1L92 & (RD1_q_a[20] & !CB1L14 # !BB1L176); --BB1_dbs_latent_8_reg_segment_2[3] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_2[3] BB1_dbs_latent_8_reg_segment_2[3] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[3], F1__clk1, N1_data_out, , BB1L8, , , , ); --BB1L86 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[19]~3049 BB1L86 = BB1_dbs_latent_8_reg_segment_2[3] & (HB1_za_data[3] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_2[3] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (HB1_za_data[3] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L87 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[19]~3050 BB1L87 = BB1L86 & (KE1_oDATA[3] # !LB1L14); --BB1L88 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[19]~3051 BB1L88 = BB1L87 & (UD1_q_a[19] & !DB1L1 # !EB1L29); --BB1L89 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[19]~3052 BB1L89 = BB1L88 & (RD1_q_a[19] & !CB1L14 # !BB1L176); --BB1_dbs_latent_8_reg_segment_2[2] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_2[2] BB1_dbs_latent_8_reg_segment_2[2] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[2], F1__clk1, N1_data_out, , BB1L8, , , , ); --BB1L82 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[18]~3053 BB1L82 = BB1_dbs_latent_8_reg_segment_2[2] & (HB1_za_data[2] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_2[2] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (HB1_za_data[2] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L83 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[18]~3054 BB1L83 = BB1L82 & (KE1_oDATA[2] # !LB1L14); --BB1L84 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[18]~3055 BB1L84 = BB1L83 & (UD1_q_a[18] & !DB1L1 # !EB1L29); --BB1L85 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[18]~3056 BB1L85 = BB1L84 & (RD1_q_a[18] & !CB1L14 # !BB1L176); --BB1_dbs_latent_8_reg_segment_2[1] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_2[1] BB1_dbs_latent_8_reg_segment_2[1] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[1], F1__clk1, N1_data_out, , BB1L8, , , , ); --BB1L78 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[17]~3057 BB1L78 = BB1_dbs_latent_8_reg_segment_2[1] & (HB1_za_data[1] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_2[1] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (HB1_za_data[1] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L79 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[17]~3058 BB1L79 = BB1L78 & (KE1_oDATA[1] # !LB1L14); --BB1L80 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[17]~3059 BB1L80 = BB1L79 & (UD1_q_a[17] & !DB1L1 # !EB1L29); --BB1L81 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[17]~3060 BB1L81 = BB1L80 & (RD1_q_a[17] & !CB1L14 # !BB1L176); --BB1_dbs_16_reg_segment_0[10] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[10] BB1_dbs_16_reg_segment_0[10] = DFFEAS(KE1_oDATA[10], F1__clk1, N1_data_out, , BB1L5, , , , ); --BB1L154 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~170 BB1L154 = BB1_dbs_16_reg_segment_0[10] # !LB1L14; --BB1_dbs_latent_8_reg_segment_1[2] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_1[2] BB1_dbs_latent_8_reg_segment_1[2] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[2], F1__clk1, N1_data_out, , BB1L7, , , , ); --BB1_dbs_latent_16_reg_segment_0[10] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_16_reg_segment_0[10] BB1_dbs_latent_16_reg_segment_0[10] = DFFEAS(HB1_za_data[10], F1__clk1, N1_data_out, , BB1L4, , , , ); --BB1L56 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[10]~3061 BB1L56 = BB1_dbs_latent_8_reg_segment_1[2] & (BB1_dbs_latent_16_reg_segment_0[10] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_1[2] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (BB1_dbs_latent_16_reg_segment_0[10] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L57 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[10]~3062 BB1L57 = BB1L154 & BB1L56 & (!BB1L170 # !EB1L29); --BB1L58 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[10]~3063 BB1L58 = BB1L57 & (RD1_q_a[10] & !CB1L14 # !BB1L176); --BB1_dbs_16_reg_segment_0[9] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[9] BB1_dbs_16_reg_segment_0[9] = DFFEAS(KE1_oDATA[9], F1__clk1, N1_data_out, , BB1L5, , , , ); --BB1L153 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~169 BB1L153 = BB1_dbs_16_reg_segment_0[9] # !LB1L14; --BB1_dbs_latent_8_reg_segment_1[1] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_1[1] BB1_dbs_latent_8_reg_segment_1[1] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[1], F1__clk1, N1_data_out, , BB1L7, , , , ); --BB1_dbs_latent_16_reg_segment_0[9] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_16_reg_segment_0[9] BB1_dbs_latent_16_reg_segment_0[9] = DFFEAS(HB1_za_data[9], F1__clk1, N1_data_out, , BB1L4, , , , ); --BB1L53 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[9]~3064 BB1L53 = BB1_dbs_latent_8_reg_segment_1[1] & (BB1_dbs_latent_16_reg_segment_0[9] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_1[1] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (BB1_dbs_latent_16_reg_segment_0[9] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L54 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[9]~3065 BB1L54 = BB1L153 & BB1L53 & (!BB1L169 # !EB1L29); --BB1L55 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[9]~3066 BB1L55 = BB1L54 & (RD1_q_a[9] & !CB1L14 # !BB1L176); --BB1_dbs_16_reg_segment_0[8] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[8] BB1_dbs_16_reg_segment_0[8] = DFFEAS(KE1_oDATA[8], F1__clk1, N1_data_out, , BB1L5, , , , ); --BB1L152 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~168 BB1L152 = BB1_dbs_16_reg_segment_0[8] # !LB1L14; --BB1_dbs_latent_8_reg_segment_1[0] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_1[0] BB1_dbs_latent_8_reg_segment_1[0] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[0], F1__clk1, N1_data_out, , BB1L7, , , , ); --BB1_dbs_latent_16_reg_segment_0[8] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_16_reg_segment_0[8] BB1_dbs_latent_16_reg_segment_0[8] = DFFEAS(HB1_za_data[8], F1__clk1, N1_data_out, , BB1L4, , , , ); --BB1L50 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[8]~3067 BB1L50 = BB1_dbs_latent_8_reg_segment_1[0] & (BB1_dbs_latent_16_reg_segment_0[8] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_1[0] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (BB1_dbs_latent_16_reg_segment_0[8] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L51 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[8]~3068 BB1L51 = BB1L152 & BB1L50 & (!BB1L168 # !EB1L29); --BB1L52 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[8]~3069 BB1L52 = BB1L51 & (RD1_q_a[8] & !CB1L14 # !BB1L176); --CB1L27 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_byteenable[3]~18 CB1L27 = Z1_d_byteenable[3] # !CB1L30; --ED1_MonDReg[27] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[27] ED1_MonDReg[27] = AMPP_FUNCTION(F1__clk1, ED1L88, FD1L49Q, D1_CLRN_SIGNAL, FD1L198, ED1L33); --ED1_MonDReg[31] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[31] ED1_MonDReg[31] = AMPP_FUNCTION(F1__clk1, ED1L89, D1_CLRN_SIGNAL, ED1L33); --ED1_MonDReg[28] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[28] ED1_MonDReg[28] = AMPP_FUNCTION(F1__clk1, ED1L90, D1_CLRN_SIGNAL, ED1L33); --ED1_MonDReg[30] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[30] ED1_MonDReg[30] = AMPP_FUNCTION(F1__clk1, ED1L91, D1_CLRN_SIGNAL, ED1L33); --ED1_MonDReg[29] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[29] ED1_MonDReg[29] = AMPP_FUNCTION(F1__clk1, ED1L92, FD1L51Q, D1_CLRN_SIGNAL, FD1L198, ED1L33); --BB1L6 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|always6~0 BB1L6 = BB1_dbs_rdv_count_enable & !BB1_cpu_0_instruction_master_dbs_rdv_counter[1] & !BB1_cpu_0_instruction_master_dbs_rdv_counter[0]; --BB1L4 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|always2~23 BB1L4 = BB1_dbs_rdv_count_enable & !BB1_cpu_0_instruction_master_dbs_rdv_counter[1]; --BB1L5 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|always5~0 BB1L5 = !BB1_cpu_0_instruction_master_dbs_address[1] & (BB1L254 # MB1L40 & BB1L252); --SD1_wr_strobe is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|wr_strobe SD1_wr_strobe = DFFEAS(SD1L180, F1__clk1, N1_data_out, , , , , , ); --SD1_control_wr_strobe is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|control_wr_strobe SD1_control_wr_strobe = EB1L9 & EB1L10 & SD1_wr_strobe & !EB1L11; --SD1_slowcount[1] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|slowcount[1] SD1_slowcount[1] = DFFEAS(SD1L179, F1__clk1, N1_data_out, , , , , , ); --SD1_slowcount[0] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|slowcount[0] SD1_slowcount[0] = DFFEAS(SD1L178, F1__clk1, N1_data_out, , , , , , ); --SD1L210 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|slowclock~27 SD1L210 = SD1_slowcount[1] & !SD1_slowcount[0]; --SD1_state[0] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|state[0] SD1_state[0] = DFFEAS(SD1L40, F1__clk1, N1_data_out, , SD1L51, , , , ); --SD1_state[4] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|state[4] SD1_state[4] = DFFEAS(SD1L221, F1__clk1, N1_data_out, , SD1L51, , , , ); --SD1_state[3] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|state[3] SD1_state[3] = DFFEAS(SD1L46, F1__clk1, N1_data_out, , SD1L51, , , , ); --SD1_state[2] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|state[2] SD1_state[2] = DFFEAS(SD1L44, F1__clk1, N1_data_out, , SD1L51, , , , ); --SD1_state[1] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|state[1] SD1_state[1] = DFFEAS(SD1L222, F1__clk1, N1_data_out, , SD1L51, , , , ); --SD1L21 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal~766 SD1L21 = !SD1_state[3] & !SD1_state[2] & !SD1_state[1]; --SD1L26 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|ROE~66 SD1L26 = SD1L210 & SD1_state[0] & SD1_state[4] & SD1L21; --SD1_status_wr_strobe is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|status_wr_strobe SD1_status_wr_strobe = EB1L10 & SD1_wr_strobe & !EB1L9 & !EB1L11; --SD1L27 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|ROE~67 SD1L27 = SD1_RRDY & (SD1L26 # SD1_ROE & !SD1_status_wr_strobe) # !SD1_RRDY & (SD1_ROE & !SD1_status_wr_strobe); --SD1_data_wr_strobe is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_wr_strobe SD1_data_wr_strobe = DFFEAS(SD1L176, F1__clk1, N1_data_out, , , , , , ); --SD1L38 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|TOE~39 SD1L38 = !SD1_status_wr_strobe & (SD1_TOE # SD1_data_wr_strobe & !SD1L39); --SD1_rd_strobe is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rd_strobe SD1_rd_strobe = DFFEAS(SD1_p1_rd_strobe, F1__clk1, N1_data_out, , , , , , ); --SD1_p1_rd_strobe is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_rd_strobe SD1_p1_rd_strobe = EB1_epcs_controller_epcs_control_port_in_a_read_cycle & DB1L1 & !SD1_rd_strobe; --SD1L139 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_rd_strobe~23 SD1L139 = SD1_p1_rd_strobe & !EB1L9 & !EB1L10 & !EB1L11; --SD1L180 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_wr_strobe~33 SD1L180 = Z1_d_write & EB1L26 & DB1L1 & !SD1_wr_strobe; --SD1L176 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_wr_strobe~20 SD1L176 = EB1L9 & SD1L180 & !EB1L10 & !EB1L11; --SD1L3 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~157 SD1L3 = Z1_d_writedata[2] & SD1_endofpacketvalue_reg[2] & (Z1_d_writedata[4] $ !SD1_endofpacketvalue_reg[4]) # !Z1_d_writedata[2] & !SD1_endofpacketvalue_reg[2] & (Z1_d_writedata[4] $ !SD1_endofpacketvalue_reg[4]); --SD1L4 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~158 SD1L4 = Z1_d_writedata[0] & SD1_endofpacketvalue_reg[0] & (Z1_d_writedata[7] $ !SD1_endofpacketvalue_reg[7]) # !Z1_d_writedata[0] & !SD1_endofpacketvalue_reg[0] & (Z1_d_writedata[7] $ !SD1_endofpacketvalue_reg[7]); --SD1L5 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~159 SD1L5 = Z1_d_writedata[3] & SD1_endofpacketvalue_reg[3] & (Z1_d_writedata[6] $ !SD1_endofpacketvalue_reg[6]) # !Z1_d_writedata[3] & !SD1_endofpacketvalue_reg[3] & (Z1_d_writedata[6] $ !SD1_endofpacketvalue_reg[6]); --SD1L6 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~160 SD1L6 = Z1_d_writedata[1] & SD1_endofpacketvalue_reg[1] & (Z1_d_writedata[5] $ !SD1_endofpacketvalue_reg[5]) # !Z1_d_writedata[1] & !SD1_endofpacketvalue_reg[1] & (Z1_d_writedata[5] $ !SD1_endofpacketvalue_reg[5]); --SD1L7 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~161 SD1L7 = SD1L3 & SD1L4 & SD1L5 & SD1L6; --SD1L8 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~162 SD1L8 = SD1_endofpacketvalue_reg[2] & SD1_rx_holding_reg[2] & (SD1_endofpacketvalue_reg[4] $ !SD1_rx_holding_reg[4]) # !SD1_endofpacketvalue_reg[2] & !SD1_rx_holding_reg[2] & (SD1_endofpacketvalue_reg[4] $ !SD1_rx_holding_reg[4]); --SD1L9 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~163 SD1L9 = SD1_endofpacketvalue_reg[0] & SD1_rx_holding_reg[0] & (SD1_endofpacketvalue_reg[7] $ !SD1_rx_holding_reg[7]) # !SD1_endofpacketvalue_reg[0] & !SD1_rx_holding_reg[0] & (SD1_endofpacketvalue_reg[7] $ !SD1_rx_holding_reg[7]); --SD1L10 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~164 SD1L10 = SD1_endofpacketvalue_reg[3] & SD1_rx_holding_reg[3] & (SD1_endofpacketvalue_reg[6] $ !SD1_rx_holding_reg[6]) # !SD1_endofpacketvalue_reg[3] & !SD1_rx_holding_reg[3] & (SD1_endofpacketvalue_reg[6] $ !SD1_rx_holding_reg[6]); --SD1L11 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~165 SD1L11 = SD1_endofpacketvalue_reg[1] & SD1_rx_holding_reg[1] & (SD1_endofpacketvalue_reg[5] $ !SD1_rx_holding_reg[5]) # !SD1_endofpacketvalue_reg[1] & !SD1_rx_holding_reg[1] & (SD1_endofpacketvalue_reg[5] $ !SD1_rx_holding_reg[5]); --SD1L12 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~166 SD1L12 = SD1L8 & SD1L9 & SD1L10 & SD1L11; --SD1L13 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~167 SD1L13 = SD1L139 & (SD1L12 # SD1L176 & SD1L7) # !SD1L139 & SD1L176 & SD1L7; --SD1L14 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~168 SD1L14 = !SD1_endofpacketvalue_reg[8] & !SD1_endofpacketvalue_reg[9]; --SD1L15 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~169 SD1L15 = !SD1_endofpacketvalue_reg[12] & !SD1_endofpacketvalue_reg[13] & !SD1_endofpacketvalue_reg[14] & !SD1_endofpacketvalue_reg[15]; --SD1L16 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~170 SD1L16 = SD1L14 & SD1L15 & !SD1_endofpacketvalue_reg[10] & !SD1_endofpacketvalue_reg[11]; --SD1L17 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~171 SD1L17 = !SD1_status_wr_strobe & (SD1_EOP # SD1L13 & SD1L16); --SD1_data_rd_strobe is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_rd_strobe SD1_data_rd_strobe = DFFEAS(SD1L139, F1__clk1, N1_data_out, , , , , , ); --SD1L29 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|RRDY~23 SD1L29 = SD1L26 # SD1_RRDY & !SD1_status_wr_strobe & !SD1_data_rd_strobe; --SD1L228 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_primed~30 SD1L228 = SD1_data_wr_strobe # SD1_tx_holding_primed & SD1_transmitting; --NE1L51 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|tx_wr_strobe_onset~11 NE1L51 = NE1L50 & !PB1_d1_reasons_to_wait; --LE1L60 is system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|status_wr_strobe~11 LE1L60 = Z1_d_write & LE1L1 & Q1L1 & !Z1_d_address[6]; --NE1L45 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|tx_overrun~39 NE1L45 = !LE1L60 & (NE1_tx_overrun # NE1_tx_ready & NE1L51); --NE1L49 is system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|tx_shift_empty~0 NE1L49 = NE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] # NE1_tx_ready # !NE1L42; --ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] = DFFEAS(ME1L85, F1__clk1, N1_data_out, , ME1L94, , , , ); --ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] = DFFEAS(ME1L76, F1__clk1, N1_data_out, , ME1L94, , , , ); --ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] = DFFEAS(ME1L84, F1__clk1, N1_data_out, , ME1L94, , , , ); --ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] = DFFEAS(ME1L83, F1__clk1, N1_data_out, , ME1L94, , , , ); --ME1L58 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|reduce_or~61 ME1L58 = ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] # ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] # ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] # ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7]; --ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] = DFFEAS(ME1L82, F1__clk1, N1_data_out, , ME1L94, , , , ); --ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] = DFFEAS(ME1L81, F1__clk1, N1_data_out, , ME1L94, , , , ); --ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] = DFFEAS(ME1L80, F1__clk1, N1_data_out, , ME1L94, , , , ); --ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] = DFFEAS(ME1L79, F1__clk1, N1_data_out, , ME1L94, , , , ); --ME1L59 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|reduce_or~62 ME1L59 = ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] # ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] # ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] # ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3]; --ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] = DFFEAS(ME1L78, F1__clk1, N1_data_out, , ME1L94, , , , ); --ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] = DFFEAS(ME1L77, F1__clk1, N1_data_out, , ME1L94, , , , ); --ME1L60 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|reduce_or~63 ME1L60 = ME1L58 # ME1L59 # ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] # ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1]; --ME1_delayed_unxrx_in_processxx3 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|delayed_unxrx_in_processxx3 ME1_delayed_unxrx_in_processxx3 = DFFEAS(ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0], F1__clk1, N1_data_out, , , , , , ); --ME1L55 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|framing_error~94 ME1L55 = ME1_delayed_unxrx_in_processxx3 & !ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] & !ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]; --ME1L56 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|framing_error~95 ME1L56 = !LE1L60 & (ME1_framing_error # ME1L60 & ME1L55); --ME1_got_new_char is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|got_new_char ME1_got_new_char = ME1_delayed_unxrx_in_processxx3 & !ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]; --ME1L49 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|break_detect~39 ME1L49 = !LE1L60 & (ME1_break_detect # ME1_got_new_char & !ME1L60); --ME1L74 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|rx_overrun~39 ME1L74 = !LE1L60 & (ME1_rx_overrun # ME1_rx_char_ready & ME1_got_new_char); --ME1L62 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|rx_char_ready~51 ME1L62 = PB1_d1_reasons_to_wait # !LE1L3 # !Z1_d_read; --ME1L63 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|rx_char_ready~52 ME1L63 = ME1L62 & (ME1_rx_char_ready # ME1_got_new_char) # !ME1L62 & !PB1L1 & (ME1_rx_char_ready # ME1_got_new_char); --FB1_wr_rfifo is system_0:u0|jtag_uart_0:the_jtag_uart_0|wr_rfifo FB1_wr_rfifo = VD1L51Q & !BE2_b_full; --EE2_counter_comb_bita0 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita0 EE2_counter_comb_bita0 = EE2_safe_q[0] $ (VCC # !FB1_wr_rfifo); --EE2L2 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita0~COUT EE2L2 = CARRY(EE2_safe_q[0] $ !FB1_wr_rfifo); --EE2_counter_comb_bita1 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita1 EE2_counter_comb_bita1 = EE2L2 & (EE2_safe_q[1] $ (FB1_wr_rfifo # VCC)) # !EE2L2 & (EE2_safe_q[1] # GND); --EE2L4 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita1~COUT EE2L4 = CARRY(EE2_safe_q[1] $ FB1_wr_rfifo # !EE2L2); --EE2_counter_comb_bita2 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita2 EE2_counter_comb_bita2 = EE2L4 & EE2_safe_q[2] & (VCC) # !EE2L4 & (EE2_safe_q[2] $ (VCC # !FB1_wr_rfifo)); --EE2L6 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita2~COUT EE2L6 = CARRY(!EE2L4 & (EE2_safe_q[2] $ !FB1_wr_rfifo)); --EE2_counter_comb_bita3 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita3 EE2_counter_comb_bita3 = EE2L6 & (EE2_safe_q[3] $ (FB1_wr_rfifo # VCC)) # !EE2L6 & (EE2_safe_q[3] # GND); --EE2L8 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita3~COUT EE2L8 = CARRY(EE2_safe_q[3] $ FB1_wr_rfifo # !EE2L6); --EE2_counter_comb_bita4 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita4 EE2_counter_comb_bita4 = EE2L8 & EE2_safe_q[4] & (VCC) # !EE2L8 & (EE2_safe_q[4] $ (VCC # !FB1_wr_rfifo)); --EE2L10 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita4~COUT EE2L10 = CARRY(!EE2L8 & (EE2_safe_q[4] $ !FB1_wr_rfifo)); --BE2L1 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|_~28 BE2L1 = BE2_b_non_empty & (FB1L45 $ (!BE2_b_full & VD1L51Q)) # !BE2_b_non_empty & (!BE2_b_full & VD1L51Q); --EE2_counter_comb_bita5 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita5 EE2_counter_comb_bita5 = EE2_safe_q[5] $ EE2L10; --BE2L2 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|_~83 BE2L2 = EE2_safe_q[2] # EE2_safe_q[1] # EE2_safe_q[3] # !EE2_safe_q[0]; --BE2L8 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~103 BE2L8 = !EE2_safe_q[5] & !EE2_safe_q[4] & !BE2L2 & FB1L45; --BE2L9 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~104 BE2L9 = VD1L51Q # BE2_b_full # BE2_b_non_empty & !BE2L8; --VD1_write_valid is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|write_valid VD1_write_valid = AMPP_FUNCTION(A1L333, VD1_td_shift[10], D1_CLRN_SIGNAL, VD1L94); --VD1L52 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|t_pause~70 VD1L52 = AMPP_FUNCTION(FB1_t_dav, VD1_write_stalled, VD1_write_valid); --VD1_jupdate1 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate1 VD1_jupdate1 = AMPP_FUNCTION(F1__clk1, VD1_jupdate, N1_data_out); --VD1_jupdate2 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate2 VD1_jupdate2 = AMPP_FUNCTION(F1__clk1, VD1_jupdate1, N1_data_out); --VD1L53 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|t_pause~71 VD1L53 = AMPP_FUNCTION(VD1L2, VD1L52, VD1_jupdate1, VD1_jupdate2); --FB1_fifo_wr is system_0:u0|jtag_uart_0:the_jtag_uart_0|fifo_wr FB1_fifo_wr = DFFEAS(FB1L47, F1__clk1, N1_data_out, , , , , , ); --EE1_counter_comb_bita0 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita0 EE1_counter_comb_bita0 = EE1_safe_q[0] $ (VCC # !FB1_fifo_wr); --EE1L2 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita0~COUT EE1L2 = CARRY(EE1_safe_q[0] $ !FB1_fifo_wr); --EE1_counter_comb_bita1 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita1 EE1_counter_comb_bita1 = EE1L2 & (EE1_safe_q[1] $ (FB1_fifo_wr # VCC)) # !EE1L2 & (EE1_safe_q[1] # GND); --EE1L4 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita1~COUT EE1L4 = CARRY(EE1_safe_q[1] $ FB1_fifo_wr # !EE1L2); --EE1_counter_comb_bita2 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita2 EE1_counter_comb_bita2 = EE1L4 & EE1_safe_q[2] & (VCC) # !EE1L4 & (EE1_safe_q[2] $ (VCC # !FB1_fifo_wr)); --EE1L6 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita2~COUT EE1L6 = CARRY(!EE1L4 & (EE1_safe_q[2] $ !FB1_fifo_wr)); --EE1_counter_comb_bita3 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita3 EE1_counter_comb_bita3 = EE1L6 & (EE1_safe_q[3] $ (FB1_fifo_wr # VCC)) # !EE1L6 & (EE1_safe_q[3] # GND); --EE1L8 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita3~COUT EE1L8 = CARRY(EE1_safe_q[3] $ FB1_fifo_wr # !EE1L6); --BE1_b_non_empty is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty BE1_b_non_empty = DFFEAS(BE1L9, F1__clk1, , , , , , , ); --FB1_rd_wfifo is system_0:u0|jtag_uart_0:the_jtag_uart_0|rd_wfifo FB1_rd_wfifo = BE1_b_non_empty & !VD1_rvalid0 & (!VD1_r_ena1 # !FB1_r_val); --BE1L1 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|_~28 BE1L1 = FB1_fifo_wr $ FB1_rd_wfifo; --BE1L3 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|b_full~120 BE1L3 = EE1_safe_q[3] & EE1_safe_q[0] & EE1_safe_q[2] & EE1_safe_q[1]; --BE1L4 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|b_full~121 BE1L4 = EE1_safe_q[5] & EE1_safe_q[4] & FB1_fifo_wr & BE1_b_non_empty; --BE1L5 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|b_full~122 BE1L5 = !FB1_rd_wfifo & (BE1_b_full # BE1L3 & BE1L4); --EE1_counter_comb_bita4 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita4 EE1_counter_comb_bita4 = EE1L8 & EE1_safe_q[4] & (VCC) # !EE1L8 & (EE1_safe_q[4] $ (VCC # !FB1_fifo_wr)); --EE1L10 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita4~COUT EE1L10 = CARRY(!EE1L8 & (EE1_safe_q[4] $ !FB1_fifo_wr)); --EE1_counter_comb_bita5 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw|counter_comb_bita5 EE1_counter_comb_bita5 = EE1_safe_q[5] $ EE1L10; --BB1L8 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|always8~0 BB1L8 = BB1_cpu_0_instruction_master_dbs_rdv_counter[1] & BB1_dbs_rdv_count_enable & !BB1_cpu_0_instruction_master_dbs_rdv_counter[0]; --CB1L26 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_byteenable[2]~19 CB1L26 = Z1_d_byteenable[2] # !CB1L30; --ED1_MonDReg[26] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[26] ED1_MonDReg[26] = AMPP_FUNCTION(F1__clk1, ED1L93, D1_CLRN_SIGNAL, ED1L33); --ED1_MonDReg[23] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[23] ED1_MonDReg[23] = AMPP_FUNCTION(F1__clk1, ED1L94, FD1L45Q, D1_CLRN_SIGNAL, FD1L198, ED1L33); --ED1_MonDReg[25] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[25] ED1_MonDReg[25] = AMPP_FUNCTION(F1__clk1, ED1L95, D1_CLRN_SIGNAL, ED1L33); --ED1_MonDReg[24] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[24] ED1_MonDReg[24] = AMPP_FUNCTION(F1__clk1, ED1L96, D1_CLRN_SIGNAL, ED1L33); --Z1_D_bht_data[0] is system_0:u0|cpu_0:the_cpu_0|D_bht_data[0] Z1_D_bht_data[0] = AMPP_FUNCTION(F1__clk1, EC1_q_a[0], N1_data_out, Z1_F_stall); --Z1_D_bht_ptr[0] is system_0:u0|cpu_0:the_cpu_0|D_bht_ptr[0] Z1_D_bht_ptr[0] = AMPP_FUNCTION(F1__clk1, Z1_F_bht_ptr[0], N1_data_out, Z1_F_stall); --Z1_D_bht_ptr[1] is system_0:u0|cpu_0:the_cpu_0|D_bht_ptr[1] Z1_D_bht_ptr[1] = AMPP_FUNCTION(F1__clk1, Z1_F_bht_ptr[1], N1_data_out, Z1_F_stall); --Z1_D_bht_ptr[2] is system_0:u0|cpu_0:the_cpu_0|D_bht_ptr[2] Z1_D_bht_ptr[2] = AMPP_FUNCTION(F1__clk1, Z1_F_bht_ptr[2], N1_data_out, Z1_F_stall); --Z1_D_bht_ptr[3] is system_0:u0|cpu_0:the_cpu_0|D_bht_ptr[3] Z1_D_bht_ptr[3] = AMPP_FUNCTION(F1__clk1, Z1_F_bht_ptr[3], N1_data_out, Z1_F_stall); --Z1_D_bht_ptr[4] is system_0:u0|cpu_0:the_cpu_0|D_bht_ptr[4] Z1_D_bht_ptr[4] = AMPP_FUNCTION(F1__clk1, Z1_F_bht_ptr[4], N1_data_out, Z1_F_stall); --Z1_D_bht_ptr[5] is system_0:u0|cpu_0:the_cpu_0|D_bht_ptr[5] Z1_D_bht_ptr[5] = AMPP_FUNCTION(F1__clk1, Z1_F_bht_ptr[5], N1_data_out, Z1_F_stall); --Z1_D_bht_ptr[6] is system_0:u0|cpu_0:the_cpu_0|D_bht_ptr[6] Z1_D_bht_ptr[6] = AMPP_FUNCTION(F1__clk1, Z1_F_bht_ptr[6], N1_data_out, Z1_F_stall); --Z1_D_bht_ptr[7] is system_0:u0|cpu_0:the_cpu_0|D_bht_ptr[7] Z1_D_bht_ptr[7] = AMPP_FUNCTION(F1__clk1, Z1_F_bht_ptr[7], N1_data_out, Z1_F_stall); --BB1L7 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|always7~0 BB1L7 = BB1_cpu_0_instruction_master_dbs_rdv_counter[0] & BB1_dbs_rdv_count_enable & !BB1_cpu_0_instruction_master_dbs_rdv_counter[1]; --ED1_MonDReg[16] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[16] ED1_MonDReg[16] = AMPP_FUNCTION(F1__clk1, ED1L97, D1_CLRN_SIGNAL, ED1L33); --BB1_dbs_16_reg_segment_0[6] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[6] BB1_dbs_16_reg_segment_0[6] = DFFEAS(KE1_oDATA[6], F1__clk1, N1_data_out, , BB1L5, , , , ); --BB1L150 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~166 BB1L150 = BB1_dbs_16_reg_segment_0[6] # !LB1L14; --BB1_dbs_latent_8_reg_segment_0[6] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_0[6] BB1_dbs_latent_8_reg_segment_0[6] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[6], F1__clk1, N1_data_out, , BB1L6, , , , ); --BB1_dbs_latent_16_reg_segment_0[6] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_16_reg_segment_0[6] BB1_dbs_latent_16_reg_segment_0[6] = DFFEAS(HB1_za_data[6], F1__clk1, N1_data_out, , BB1L4, , , , ); --BB1L44 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[6]~3070 BB1L44 = BB1_dbs_latent_8_reg_segment_0[6] & (BB1_dbs_latent_16_reg_segment_0[6] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_0[6] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (BB1_dbs_latent_16_reg_segment_0[6] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L45 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[6]~3071 BB1L45 = BB1L150 & BB1L44 & (!BB1L166 # !EB1L29); --BB1L46 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[6]~3072 BB1L46 = BB1L45 & (RD1_q_a[6] & !CB1L14 # !BB1L176); --BB1_dbs_16_reg_segment_0[7] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[7] BB1_dbs_16_reg_segment_0[7] = DFFEAS(KE1_oDATA[7], F1__clk1, N1_data_out, , BB1L5, , , , ); --BB1L151 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~167 BB1L151 = BB1_dbs_16_reg_segment_0[7] # !LB1L14; --BB1_dbs_latent_8_reg_segment_0[7] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_8_reg_segment_0[7] BB1_dbs_latent_8_reg_segment_0[7] = DFFEAS(MB1_incoming_tri_state_bridge_0_data[7], F1__clk1, N1_data_out, , BB1L6, , , , ); --BB1_dbs_latent_16_reg_segment_0[7] is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_latent_16_reg_segment_0[7] BB1_dbs_latent_16_reg_segment_0[7] = DFFEAS(HB1_za_data[7], F1__clk1, N1_data_out, , BB1L4, , , , ); --BB1L47 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[7]~3073 BB1L47 = BB1_dbs_latent_8_reg_segment_0[7] & (BB1_dbs_latent_16_reg_segment_0[7] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1) # !BB1_dbs_latent_8_reg_segment_0[7] & !MB1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (BB1_dbs_latent_16_reg_segment_0[7] # !JB1_cpu_0_instruction_master_read_data_valid_sdram_0_s1); --BB1L48 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[7]~3074 BB1L48 = BB1L151 & BB1L47 & (!BB1L167 # !EB1L29); --BB1L49 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata[7]~3075 BB1L49 = BB1L48 & (RD1_q_a[7] & !CB1L14 # !BB1L176); --QC2_mac_mult2 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 --DSP Block Multiplier Base Width: 18-bits QC2_mac_mult2 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L2 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT1 QC2L2 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L3 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT2 QC2L3 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L4 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT3 QC2L4 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L5 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT4 QC2L5 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L6 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT5 QC2L6 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L7 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT6 QC2L7 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L8 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT7 QC2L8 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L9 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT8 QC2L9 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L10 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT9 QC2L10 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L11 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT10 QC2L11 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L12 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT11 QC2L12 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L13 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT12 QC2L13 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L14 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT13 QC2L14 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L15 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT14 QC2L15 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L16 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT15 QC2L16 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L17 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT16 QC2L17 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L18 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT17 QC2L18 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L19 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT18 QC2L19 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L20 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT19 QC2L20 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L21 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT20 QC2L21 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L22 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT21 QC2L22 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L23 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT22 QC2L23 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L24 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT23 QC2L24 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L25 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT24 QC2L25 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L26 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT25 QC2L26 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L27 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT26 QC2L27 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L28 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT27 QC2L28 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L29 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT28 QC2L29 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L30 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT29 QC2L30 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L31 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT30 QC2L31 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC2L32 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT31 QC2L32 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[16], Z1_A_mul_src1[17], Z1_A_mul_src1[18], Z1_A_mul_src1[19], Z1_A_mul_src1[20], Z1_A_mul_src1[21], Z1_A_mul_src1[22], Z1_A_mul_src1[23], Z1_A_mul_src1[24], Z1_A_mul_src1[25], Z1_A_mul_src1[26], Z1_A_mul_src1[27], Z1_A_mul_src1[28], Z1_A_mul_src1[29], Z1_A_mul_src1[30], Z1_A_mul_src1[31], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1_mac_mult2 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 --DSP Block Multiplier Base Width: 18-bits QC1_mac_mult2 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L2 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT1 QC1L2 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L3 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT2 QC1L3 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L4 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT3 QC1L4 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L5 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT4 QC1L5 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L6 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT5 QC1L6 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L7 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT6 QC1L7 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L8 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT7 QC1L8 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L9 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT8 QC1L9 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L10 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT9 QC1L10 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L11 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT10 QC1L11 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L12 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT11 QC1L12 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L13 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT12 QC1L13 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L14 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT13 QC1L14 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L15 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT14 QC1L15 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L16 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT15 QC1L16 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L17 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT16 QC1L17 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L18 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT17 QC1L18 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L19 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT18 QC1L19 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L20 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT19 QC1L20 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L21 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT20 QC1L21 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L22 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT21 QC1L22 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L23 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT22 QC1L23 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L24 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT23 QC1L24 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L25 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT24 QC1L25 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L26 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT25 QC1L26 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L27 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT26 QC1L27 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L28 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT27 QC1L28 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L29 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT28 QC1L29 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L30 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT29 QC1L30 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L31 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT30 QC1L31 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --QC1L32 is system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2~DATAOUT31 QC1L32 = AMPP_FUNCTION(~GND, ~GND, Z1_A_mul_src1[0], Z1_A_mul_src1[1], Z1_A_mul_src1[2], Z1_A_mul_src1[3], Z1_A_mul_src1[4], Z1_A_mul_src1[5], Z1_A_mul_src1[6], Z1_A_mul_src1[7], Z1_A_mul_src1[8], Z1_A_mul_src1[9], Z1_A_mul_src1[10], Z1_A_mul_src1[11], Z1_A_mul_src1[12], Z1_A_mul_src1[13], Z1_A_mul_src1[14], Z1_A_mul_src1[15], Z1_A_mul_src2[0], Z1_A_mul_src2[1], Z1_A_mul_src2[2], Z1_A_mul_src2[3], Z1_A_mul_src2[4], Z1_A_mul_src2[5], Z1_A_mul_src2[6], Z1_A_mul_src2[7], Z1_A_mul_src2[8], Z1_A_mul_src2[9], Z1_A_mul_src2[10], Z1_A_mul_src2[11], Z1_A_mul_src2[12], Z1_A_mul_src2[13], Z1_A_mul_src2[14], Z1_A_mul_src2[15]); --Z1_A_mul_stall_d1 is system_0:u0|cpu_0:the_cpu_0|A_mul_stall_d1 Z1_A_mul_stall_d1 = AMPP_FUNCTION(F1__clk1, Z1_A_mul_stall, N1_data_out); --AB1L345 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[23]~1328 AB1L345 = !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (HB1_za_data[7] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --AB1L5 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always7~18 AB1L5 = AB1_cpu_0_data_master_dbs_address[1] & AB1L287 & !AB1_cpu_0_data_master_dbs_address[0]; --AB1L353 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[31]~1329 AB1L353 = !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (HB1_za_data[15] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --Z1_M_rot_step1[15] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[15] Z1_M_rot_step1[15] = AMPP_FUNCTION(F1__clk1, Z1L2502, Z1L2496, N1_data_out, Z1L3012, Z1_A_stall); --Z1_M_rot_step1[11] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[11] Z1_M_rot_step1[11] = AMPP_FUNCTION(F1__clk1, Z1L2490, Z1L2484, N1_data_out, Z1L3012, Z1_A_stall); --Z1_M_rot_rn[2] is system_0:u0|cpu_0:the_cpu_0|M_rot_rn[2] Z1_M_rot_rn[2] = AMPP_FUNCTION(F1__clk1, Z1L3014, N1_data_out, Z1_A_stall); --Z1L2719 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[15]~318 Z1L2719 = AMPP_FUNCTION(Z1_M_rot_step1[15], Z1_M_rot_step1[11], Z1_M_rot_rn[2]); --Z1_M_rot_step1[7] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[7] Z1_M_rot_step1[7] = AMPP_FUNCTION(F1__clk1, Z1L2478, Z1L2472, N1_data_out, Z1L3012, Z1_A_stall); --Z1_M_rot_step1[3] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[3] Z1_M_rot_step1[3] = AMPP_FUNCTION(F1__clk1, Z1L2466, Z1L2460, N1_data_out, Z1L3012, Z1_A_stall); --Z1L2695 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[7]~302 Z1L2695 = AMPP_FUNCTION(Z1_M_rot_step1[7], Z1_M_rot_step1[3], Z1_M_rot_rn[2]); --Z1_M_rot_rn[3] is system_0:u0|cpu_0:the_cpu_0|M_rot_rn[3] Z1_M_rot_rn[3] = AMPP_FUNCTION(F1__clk1, Z1L3016, N1_data_out, Z1_A_stall); --Z1_M_rot_step1[31] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[31] Z1_M_rot_step1[31] = AMPP_FUNCTION(F1__clk1, Z1L2550, Z1L2544, N1_data_out, Z1L3012, Z1_A_stall); --Z1_M_rot_step1[27] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[27] Z1_M_rot_step1[27] = AMPP_FUNCTION(F1__clk1, Z1L2538, Z1L2532, N1_data_out, Z1L3012, Z1_A_stall); --Z1L2767 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[31]~319 Z1L2767 = AMPP_FUNCTION(Z1_M_rot_step1[31], Z1_M_rot_step1[27], Z1_M_rot_rn[2]); --Z1_M_rot_step1[23] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[23] Z1_M_rot_step1[23] = AMPP_FUNCTION(F1__clk1, Z1L2526, Z1L2520, N1_data_out, Z1L3012, Z1_A_stall); --Z1_M_rot_step1[19] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[19] Z1_M_rot_step1[19] = AMPP_FUNCTION(F1__clk1, Z1L2514, Z1L2508, N1_data_out, Z1L3012, Z1_A_stall); --Z1L2743 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[23]~303 Z1L2743 = AMPP_FUNCTION(Z1_M_rot_step1[23], Z1_M_rot_step1[19], Z1_M_rot_rn[2]); --Z1_E_ctrl_shift_rot_right is system_0:u0|cpu_0:the_cpu_0|E_ctrl_shift_rot_right Z1_E_ctrl_shift_rot_right = AMPP_FUNCTION(F1__clk1, Z1L1060, N1_data_out, Z1_A_stall); --Z1L3009 is system_0:u0|cpu_0:the_cpu_0|add~3146 Z1L3009 = AMPP_FUNCTION(Z1_E_src2[0], Z1_E_ctrl_shift_rot_right); --Z1L3010 is system_0:u0|cpu_0:the_cpu_0|add~3147 Z1L3010 = AMPP_FUNCTION(Z1L3009, Z1_E_ctrl_shift_rot_right, GND); --Z1L3011 is system_0:u0|cpu_0:the_cpu_0|add~3148 Z1L3011 = AMPP_FUNCTION(Z1L3009, Z1_E_ctrl_shift_rot_right); --Z1L3012 is system_0:u0|cpu_0:the_cpu_0|add~3149 Z1L3012 = AMPP_FUNCTION(Z1_E_src2[1], Z1_E_ctrl_shift_rot_right, GND, Z1L3011); --Z1L3013 is system_0:u0|cpu_0:the_cpu_0|add~3150 Z1L3013 = AMPP_FUNCTION(Z1_E_src2[1], Z1_E_ctrl_shift_rot_right, Z1L3011); --Z1L3014 is system_0:u0|cpu_0:the_cpu_0|add~3151 Z1L3014 = AMPP_FUNCTION(Z1_E_src2[2], Z1_E_ctrl_shift_rot_right, GND, Z1L3013); --Z1L3015 is system_0:u0|cpu_0:the_cpu_0|add~3152 Z1L3015 = AMPP_FUNCTION(Z1_E_src2[2], Z1_E_ctrl_shift_rot_right, Z1L3013); --Z1L3016 is system_0:u0|cpu_0:the_cpu_0|add~3153 Z1L3016 = AMPP_FUNCTION(Z1_E_src2[3], Z1_E_ctrl_shift_rot_right, GND, Z1L3015); --Z1L3017 is system_0:u0|cpu_0:the_cpu_0|add~3154 Z1L3017 = AMPP_FUNCTION(Z1_E_src2[3], Z1_E_ctrl_shift_rot_right, Z1L3015); --Z1L3018 is system_0:u0|cpu_0:the_cpu_0|add~3155 Z1L3018 = AMPP_FUNCTION(Z1_E_src2[4], Z1_E_ctrl_shift_rot_right, Z1L3017); --Z1_E_ctrl_shift_right_arith is system_0:u0|cpu_0:the_cpu_0|E_ctrl_shift_right_arith Z1_E_ctrl_shift_right_arith = AMPP_FUNCTION(F1__clk1, Z1L1058, N1_data_out, Z1_A_stall); --Z1L1685 is system_0:u0|cpu_0:the_cpu_0|E_rot_fill_bit~8 Z1L1685 = AMPP_FUNCTION(Z1_E_src1[31], Z1_E_ctrl_shift_right_arith); --Z1L1691 is system_0:u0|cpu_0:the_cpu_0|E_rot_mask[5]~486 Z1L1691 = AMPP_FUNCTION(Z1_E_ctrl_shift_rot_right, Z1_E_src2[1], Z1_E_src2[2], Z1_E_src2[0]); --Z1L1703 is system_0:u0|cpu_0:the_cpu_0|E_rot_sel_fill3~14 Z1L1703 = AMPP_FUNCTION(Z1_E_ctrl_shift_rot_right, Z1_E_src2[4], Z1_E_src2[3]); --Z1_E_ctrl_rot is system_0:u0|cpu_0:the_cpu_0|E_ctrl_rot Z1_E_ctrl_rot = AMPP_FUNCTION(F1__clk1, Z1L1057, N1_data_out, Z1_A_stall); --Z1_E_ctrl_shift_rot_left is system_0:u0|cpu_0:the_cpu_0|E_ctrl_shift_rot_left Z1_E_ctrl_shift_rot_left = AMPP_FUNCTION(F1__clk1, Z1L1059, N1_data_out, Z1_A_stall); --Z1L1699 is system_0:u0|cpu_0:the_cpu_0|E_rot_pass3~12 Z1L1699 = AMPP_FUNCTION(Z1_E_ctrl_rot, Z1_E_ctrl_shift_rot_left, Z1_E_src2[4], Z1_E_src2[3]); --AB1L352 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[30]~1330 AB1L352 = !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (HB1_za_data[14] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --Z1_M_rot_step1[14] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[14] Z1_M_rot_step1[14] = AMPP_FUNCTION(F1__clk1, Z1L2499, Z1L2493, N1_data_out, Z1L3012, Z1_A_stall); --Z1_M_rot_step1[10] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[10] Z1_M_rot_step1[10] = AMPP_FUNCTION(F1__clk1, Z1L2487, Z1L2481, N1_data_out, Z1L3012, Z1_A_stall); --Z1L2716 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[14]~316 Z1L2716 = AMPP_FUNCTION(Z1_M_rot_step1[14], Z1_M_rot_step1[10], Z1_M_rot_rn[2]); --Z1_M_rot_step1[6] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[6] Z1_M_rot_step1[6] = AMPP_FUNCTION(F1__clk1, Z1L2475, Z1L2469, N1_data_out, Z1L3012, Z1_A_stall); --Z1_M_rot_step1[2] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[2] Z1_M_rot_step1[2] = AMPP_FUNCTION(F1__clk1, Z1L2463, Z1L2457, N1_data_out, Z1L3012, Z1_A_stall); --Z1L2692 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[6]~300 Z1L2692 = AMPP_FUNCTION(Z1_M_rot_step1[6], Z1_M_rot_step1[2], Z1_M_rot_rn[2]); --Z1_M_rot_step1[30] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[30] Z1_M_rot_step1[30] = AMPP_FUNCTION(F1__clk1, Z1L2547, Z1L2541, N1_data_out, Z1L3012, Z1_A_stall); --Z1_M_rot_step1[26] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[26] Z1_M_rot_step1[26] = AMPP_FUNCTION(F1__clk1, Z1L2535, Z1L2529, N1_data_out, Z1L3012, Z1_A_stall); --Z1L2764 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[30]~317 Z1L2764 = AMPP_FUNCTION(Z1_M_rot_step1[30], Z1_M_rot_step1[26], Z1_M_rot_rn[2]); --Z1_M_rot_step1[22] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[22] Z1_M_rot_step1[22] = AMPP_FUNCTION(F1__clk1, Z1L2523, Z1L2517, N1_data_out, Z1L3012, Z1_A_stall); --Z1_M_rot_step1[18] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[18] Z1_M_rot_step1[18] = AMPP_FUNCTION(F1__clk1, Z1L2511, Z1L2505, N1_data_out, Z1L3012, Z1_A_stall); --Z1L2740 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[22]~301 Z1L2740 = AMPP_FUNCTION(Z1_M_rot_step1[22], Z1_M_rot_step1[18], Z1_M_rot_rn[2]); --Z1L1693 is system_0:u0|cpu_0:the_cpu_0|E_rot_mask[6]~487 Z1L1693 = AMPP_FUNCTION(Z1_E_ctrl_shift_rot_right, Z1_E_src2[1], Z1_E_src2[2], Z1_E_src2[0]); --AB1L351 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[29]~1331 AB1L351 = !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (HB1_za_data[13] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --Z1_M_rot_step1[13] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[13] Z1_M_rot_step1[13] = AMPP_FUNCTION(F1__clk1, Z1L2496, Z1L2490, N1_data_out, Z1L3012, Z1_A_stall); --Z1_M_rot_step1[9] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[9] Z1_M_rot_step1[9] = AMPP_FUNCTION(F1__clk1, Z1L2484, Z1L2478, N1_data_out, Z1L3012, Z1_A_stall); --Z1L2713 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[13]~314 Z1L2713 = AMPP_FUNCTION(Z1_M_rot_step1[13], Z1_M_rot_step1[9], Z1_M_rot_rn[2]); --Z1_M_rot_step1[5] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[5] Z1_M_rot_step1[5] = AMPP_FUNCTION(F1__clk1, Z1L2472, Z1L2466, N1_data_out, Z1L3012, Z1_A_stall); --Z1_M_rot_step1[1] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[1] Z1_M_rot_step1[1] = AMPP_FUNCTION(F1__clk1, Z1L2460, Z1L2550, N1_data_out, Z1L3012, Z1_A_stall); --Z1L2689 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[5]~298 Z1L2689 = AMPP_FUNCTION(Z1_M_rot_step1[5], Z1_M_rot_step1[1], Z1_M_rot_rn[2]); --Z1_M_rot_step1[29] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[29] Z1_M_rot_step1[29] = AMPP_FUNCTION(F1__clk1, Z1L2544, Z1L2538, N1_data_out, Z1L3012, Z1_A_stall); --Z1_M_rot_step1[25] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[25] Z1_M_rot_step1[25] = AMPP_FUNCTION(F1__clk1, Z1L2532, Z1L2526, N1_data_out, Z1L3012, Z1_A_stall); --Z1L2761 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[29]~315 Z1L2761 = AMPP_FUNCTION(Z1_M_rot_step1[29], Z1_M_rot_step1[25], Z1_M_rot_rn[2]); --Z1_M_rot_step1[21] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[21] Z1_M_rot_step1[21] = AMPP_FUNCTION(F1__clk1, Z1L2520, Z1L2514, N1_data_out, Z1L3012, Z1_A_stall); --Z1_M_rot_step1[17] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[17] Z1_M_rot_step1[17] = AMPP_FUNCTION(F1__clk1, Z1L2508, Z1L2502, N1_data_out, Z1L3012, Z1_A_stall); --Z1L2737 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[21]~299 Z1L2737 = AMPP_FUNCTION(Z1_M_rot_step1[21], Z1_M_rot_step1[17], Z1_M_rot_rn[2]); --Z1L1692 is system_0:u0|cpu_0:the_cpu_0|E_rot_mask[5]~488 Z1L1692 = AMPP_FUNCTION(Z1_E_src2[2], Z1_E_src2[1], Z1_E_ctrl_shift_rot_right, Z1_E_src2[0]); --AB1L350 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[28]~1332 AB1L350 = !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (HB1_za_data[12] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --Z1_M_rot_step1[12] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[12] Z1_M_rot_step1[12] = AMPP_FUNCTION(F1__clk1, Z1L2493, Z1L2487, N1_data_out, Z1L3012, Z1_A_stall); --Z1_M_rot_step1[8] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[8] Z1_M_rot_step1[8] = AMPP_FUNCTION(F1__clk1, Z1L2481, Z1L2475, N1_data_out, Z1L3012, Z1_A_stall); --Z1L2710 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[12]~312 Z1L2710 = AMPP_FUNCTION(Z1_M_rot_step1[12], Z1_M_rot_step1[8], Z1_M_rot_rn[2]); --Z1_M_rot_step1[4] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[4] Z1_M_rot_step1[4] = AMPP_FUNCTION(F1__clk1, Z1L2469, Z1L2463, N1_data_out, Z1L3012, Z1_A_stall); --Z1_M_rot_step1[0] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[0] Z1_M_rot_step1[0] = AMPP_FUNCTION(F1__clk1, Z1L2457, Z1L2547, N1_data_out, Z1L3012, Z1_A_stall); --Z1L2686 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[4]~296 Z1L2686 = AMPP_FUNCTION(Z1_M_rot_step1[4], Z1_M_rot_step1[0], Z1_M_rot_rn[2]); --Z1_M_rot_step1[28] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[28] Z1_M_rot_step1[28] = AMPP_FUNCTION(F1__clk1, Z1L2541, Z1L2535, N1_data_out, Z1L3012, Z1_A_stall); --Z1_M_rot_step1[24] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[24] Z1_M_rot_step1[24] = AMPP_FUNCTION(F1__clk1, Z1L2529, Z1L2523, N1_data_out, Z1L3012, Z1_A_stall); --Z1L2758 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[28]~313 Z1L2758 = AMPP_FUNCTION(Z1_M_rot_step1[28], Z1_M_rot_step1[24], Z1_M_rot_rn[2]); --Z1_M_rot_step1[20] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[20] Z1_M_rot_step1[20] = AMPP_FUNCTION(F1__clk1, Z1L2517, Z1L2511, N1_data_out, Z1L3012, Z1_A_stall); --Z1_M_rot_step1[16] is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[16] Z1_M_rot_step1[16] = AMPP_FUNCTION(F1__clk1, Z1L2505, Z1L2499, N1_data_out, Z1L3012, Z1_A_stall); --Z1L2734 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[20]~297 Z1L2734 = AMPP_FUNCTION(Z1_M_rot_step1[20], Z1_M_rot_step1[16], Z1_M_rot_rn[2]); --Z1L1690 is system_0:u0|cpu_0:the_cpu_0|E_rot_mask[4]~489 Z1L1690 = AMPP_FUNCTION(Z1_E_src2[1], Z1_E_src2[0], Z1_E_ctrl_shift_rot_right, Z1_E_src2[2]); --AB1L349 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[27]~1333 AB1L349 = !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (HB1_za_data[11] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --Z1L2707 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[11]~310 Z1L2707 = AMPP_FUNCTION(Z1_M_rot_step1[11], Z1_M_rot_step1[7], Z1_M_rot_rn[2]); --Z1L2683 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[3]~294 Z1L2683 = AMPP_FUNCTION(Z1_M_rot_step1[3], Z1_M_rot_step1[31], Z1_M_rot_rn[2]); --Z1L2755 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[27]~311 Z1L2755 = AMPP_FUNCTION(Z1_M_rot_step1[27], Z1_M_rot_step1[23], Z1_M_rot_rn[2]); --Z1L2731 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[19]~295 Z1L2731 = AMPP_FUNCTION(Z1_M_rot_step1[19], Z1_M_rot_step1[15], Z1_M_rot_rn[2]); --Z1L1689 is system_0:u0|cpu_0:the_cpu_0|E_rot_mask[3]~490 Z1L1689 = AMPP_FUNCTION(Z1_E_ctrl_shift_rot_right, Z1_E_src2[1], Z1_E_src2[0], Z1_E_src2[2]); --AB1L348 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[26]~1334 AB1L348 = !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (HB1_za_data[10] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --Z1L2704 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[10]~308 Z1L2704 = AMPP_FUNCTION(Z1_M_rot_step1[10], Z1_M_rot_step1[6], Z1_M_rot_rn[2]); --Z1L2680 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[2]~292 Z1L2680 = AMPP_FUNCTION(Z1_M_rot_step1[2], Z1_M_rot_step1[30], Z1_M_rot_rn[2]); --Z1L2752 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[26]~309 Z1L2752 = AMPP_FUNCTION(Z1_M_rot_step1[26], Z1_M_rot_step1[22], Z1_M_rot_rn[2]); --Z1L2728 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[18]~293 Z1L2728 = AMPP_FUNCTION(Z1_M_rot_step1[18], Z1_M_rot_step1[14], Z1_M_rot_rn[2]); --Z1L1687 is system_0:u0|cpu_0:the_cpu_0|E_rot_mask[2]~491 Z1L1687 = AMPP_FUNCTION(Z1_E_src2[2], Z1_E_src2[1], Z1_E_src2[0], Z1_E_ctrl_shift_rot_right); --AB1L347 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[25]~1335 AB1L347 = !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (HB1_za_data[9] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --Z1L2701 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[9]~306 Z1L2701 = AMPP_FUNCTION(Z1_M_rot_step1[9], Z1_M_rot_step1[5], Z1_M_rot_rn[2]); --Z1L2677 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[1]~290 Z1L2677 = AMPP_FUNCTION(Z1_M_rot_step1[1], Z1_M_rot_step1[29], Z1_M_rot_rn[2]); --Z1L2749 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[25]~307 Z1L2749 = AMPP_FUNCTION(Z1_M_rot_step1[25], Z1_M_rot_step1[21], Z1_M_rot_rn[2]); --Z1L2725 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[17]~291 Z1L2725 = AMPP_FUNCTION(Z1_M_rot_step1[17], Z1_M_rot_step1[13], Z1_M_rot_rn[2]); --Z1L1686 is system_0:u0|cpu_0:the_cpu_0|E_rot_mask[1]~492 Z1L1686 = AMPP_FUNCTION(Z1_E_src2[1], Z1_E_src2[2], Z1_E_src2[0], Z1_E_ctrl_shift_rot_right); --AB1L346 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[24]~1336 AB1L346 = !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (HB1_za_data[8] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --Z1L2698 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[8]~304 Z1L2698 = AMPP_FUNCTION(Z1_M_rot_step1[8], Z1_M_rot_step1[4], Z1_M_rot_rn[2]); --Z1L2674 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[0]~288 Z1L2674 = AMPP_FUNCTION(Z1_M_rot_step1[0], Z1_M_rot_step1[28], Z1_M_rot_rn[2]); --Z1L2746 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[24]~305 Z1L2746 = AMPP_FUNCTION(Z1_M_rot_step1[24], Z1_M_rot_step1[20], Z1_M_rot_rn[2]); --Z1L2722 is system_0:u0|cpu_0:the_cpu_0|Mn_rot_step2[16]~289 Z1L2722 = AMPP_FUNCTION(Z1_M_rot_step1[16], Z1_M_rot_step1[12], Z1_M_rot_rn[2]); --Z1L1688 is system_0:u0|cpu_0:the_cpu_0|E_rot_mask[2]~493 Z1L1688 = AMPP_FUNCTION(Z1_E_src2[1], Z1_E_src2[2], Z1_E_src2[0], Z1_E_ctrl_shift_rot_right); --Z1L1702 is system_0:u0|cpu_0:the_cpu_0|E_rot_sel_fill2~13 Z1L1702 = AMPP_FUNCTION(Z1_E_src2[4], Z1_E_ctrl_shift_rot_right, Z1_E_src2[3], Z1_E_ctrl_shift_rot_left); --Z1L1697 is system_0:u0|cpu_0:the_cpu_0|E_rot_pass2~14 Z1L1697 = AMPP_FUNCTION(Z1_E_ctrl_shift_rot_right, Z1_E_src2[3]); --Z1L1698 is system_0:u0|cpu_0:the_cpu_0|E_rot_pass2~15 Z1L1698 = AMPP_FUNCTION(Z1_E_ctrl_rot, Z1_E_ctrl_shift_rot_left, Z1L1697, Z1_E_src2[4]); --FB1L26 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~419 FB1L26 = CARRY(!EE1_safe_q[0]); --FB1L27 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~420 FB1L27 = EE1_safe_q[1] & (FB1L26 # GND) # !EE1_safe_q[1] & !FB1L26; --FB1L28 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~421 FB1L28 = CARRY(EE1_safe_q[1] # !FB1L26); --FB1L29 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~422 FB1L29 = EE1_safe_q[2] & !FB1L28 & VCC # !EE1_safe_q[2] & (FB1L28 $ GND); --FB1L30 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~423 FB1L30 = CARRY(!EE1_safe_q[2] & !FB1L28); --FB1L31 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~424 FB1L31 = EE1_safe_q[3] & (FB1L30 # GND) # !EE1_safe_q[3] & !FB1L30; --FB1L32 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~425 FB1L32 = CARRY(EE1_safe_q[3] # !FB1L30); --FB1L33 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~426 FB1L33 = EE1_safe_q[4] & !FB1L32 & VCC # !EE1_safe_q[4] & (FB1L32 $ GND); --FB1L34 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~427 FB1L34 = CARRY(!EE1_safe_q[4] & !FB1L32); --FB1L35 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~428 FB1L35 = EE1_safe_q[5] & (FB1L34 # GND) # !EE1_safe_q[5] & !FB1L34; --FB1L36 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~429 FB1L36 = CARRY(EE1_safe_q[5] # !FB1L34); --FB1L37 is system_0:u0|jtag_uart_0:the_jtag_uart_0|add~430 FB1L37 = BE1_b_full $ !FB1L36; --AB1L343 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[22]~1337 AB1L343 = FB1_read_0 & BE2_b_full # !FB1_read_0 & (FB1L37); --AB1L344 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[22]~1338 AB1L344 = AB1L343 & (HB1_za_data[6] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !AB1L343 & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (HB1_za_data[6] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --AB1L341 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[21]~1339 AB1L341 = FB1_read_0 & EE2_safe_q[5] # !FB1_read_0 & (FB1L35); --AB1L342 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[21]~1340 AB1L342 = AB1L341 & (HB1_za_data[5] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !AB1L341 & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (HB1_za_data[5] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --AB1L339 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[20]~1341 AB1L339 = FB1_read_0 & EE2_safe_q[4] # !FB1_read_0 & (FB1L33); --AB1L340 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[20]~1342 AB1L340 = AB1L339 & (HB1_za_data[4] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !AB1L339 & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (HB1_za_data[4] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --AB1L337 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[19]~1343 AB1L337 = FB1_read_0 & EE2_safe_q[3] # !FB1_read_0 & (FB1L31); --AB1L338 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[19]~1344 AB1L338 = AB1L337 & (HB1_za_data[3] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !AB1L337 & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (HB1_za_data[3] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --AB1L335 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[18]~1345 AB1L335 = FB1_read_0 & EE2_safe_q[2] # !FB1_read_0 & (FB1L29); --AB1L336 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[18]~1346 AB1L336 = AB1L335 & (HB1_za_data[2] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !AB1L335 & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (HB1_za_data[2] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --ED1_MonDReg[18] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[18] ED1_MonDReg[18] = AMPP_FUNCTION(F1__clk1, ED1L99, FD1L40Q, D1_CLRN_SIGNAL, FD1L198, FD1L197); --AB1L333 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[17]~1347 AB1L333 = FB1_read_0 & EE2_safe_q[1] # !FB1_read_0 & (FB1L27); --AB1L334 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[17]~1348 AB1L334 = AB1L333 & (HB1_za_data[1] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !AB1L333 & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (HB1_za_data[1] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --ED1_MonDReg[17] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[17] ED1_MonDReg[17] = AMPP_FUNCTION(F1__clk1, ED1L100, D1_CLRN_SIGNAL, ED1L33); --AB1L331 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[16]~1349 AB1L331 = FB1_read_0 & EE2_safe_q[0] # !FB1_read_0 & (EE1_safe_q[0]); --AB1L332 is system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[16]~1350 AB1L332 = AB1L331 & (HB1_za_data[0] # !JB1_cpu_0_data_master_requests_sdram_0_s1) # !AB1L331 & !GB1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & (HB1_za_data[0] # !JB1_cpu_0_data_master_requests_sdram_0_s1); --Z1L1701 is system_0:u0|cpu_0:the_cpu_0|E_rot_sel_fill1~13 Z1L1701 = AMPP_FUNCTION(Z1_E_src2[4], Z1_E_ctrl_shift_rot_left, Z1_E_src2[3], Z1_E_ctrl_shift_rot_right); --Z1L1695 is system_0:u0|cpu_0:the_cpu_0|E_rot_pass1~14 Z1L1695 = AMPP_FUNCTION(Z1_E_ctrl_shift_rot_left, Z1_E_src2[3]); --Z1L1696 is system_0:u0|cpu_0:the_cpu_0|E_rot_pass1~15 Z1L1696 = AMPP_FUNCTION(Z1_E_ctrl_rot, Z1_E_ctrl_shift_rot_right, Z1L1695, Z1_E_src2[4]); --Z1L1700 is system_0:u0|cpu_0:the_cpu_0|E_rot_sel_fill0~14 Z1L1700 = AMPP_FUNCTION(Z1_E_ctrl_shift_rot_left, Z1_E_src2[4], Z1_E_src2[3]); --Z1L1694 is system_0:u0|cpu_0:the_cpu_0|E_rot_pass0~12 Z1L1694 = AMPP_FUNCTION(Z1_E_ctrl_rot, Z1_E_ctrl_shift_rot_right, Z1_E_src2[4], Z1_E_src2[3]); --Z1L1910 is system_0:u0|cpu_0:the_cpu_0|Equal~6231 Z1L1910 = AMPP_FUNCTION(Z1_D_iw[6], Z1_D_iw[7], Z1_D_iw[8]); --Z1L1511 is system_0:u0|cpu_0:the_cpu_0|E_control_rd_data_without_mmu_regs[3]~120 Z1L1511 = AMPP_FUNCTION(Z1_D_iw[8], Z1_D_iw[6], Z1_D_iw[7]); --Z1L1006 is system_0:u0|cpu_0:the_cpu_0|D_control_rd_data_without_mmu_regs[3]~353 Z1L1006 = AMPP_FUNCTION(Z1_A_ienable_reg[3], Z1_A_ipending_reg[3], Z1L1910, Z1L1511); --Z1L1005 is system_0:u0|cpu_0:the_cpu_0|D_control_rd_data_without_mmu_regs[2]~354 Z1L1005 = AMPP_FUNCTION(Z1_A_ienable_reg[2], Z1_A_ipending_reg[2], Z1L1910, Z1L1511); --Z1L1004 is system_0:u0|cpu_0:the_cpu_0|D_control_rd_data_without_mmu_regs[1]~355 Z1L1004 = AMPP_FUNCTION(Z1_A_ienable_reg[1], Z1_A_ipending_reg[1], Z1L1910, Z1L1511); --Z1L1001 is system_0:u0|cpu_0:the_cpu_0|D_control_rd_data_without_mmu_regs[0]~356 Z1L1001 = AMPP_FUNCTION(Z1_D_iw[6], Z1_A_bstatus_reg, Z1_D_iw[7], Z1_A_ienable_reg[0]); --Z1L1002 is system_0:u0|cpu_0:the_cpu_0|D_control_rd_data_without_mmu_regs[0]~357 Z1L1002 = AMPP_FUNCTION(Z1_A_status_reg_pie, Z1_A_ipending_reg[0], Z1_D_iw[8], Z1L1001); --Z1L1003 is system_0:u0|cpu_0:the_cpu_0|D_control_rd_data_without_mmu_regs[0]~358 Z1L1003 = AMPP_FUNCTION(Z1_A_estatus_reg, Z1_D_iw[7], Z1L1001, Z1L1002); --VC1_break_readreg[18] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[18] VC1_break_readreg[18] = AMPP_FUNCTION(F1__clk1, VC1L41, D1_CLRN_SIGNAL, VC1L26); --FD1L136 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4784 FD1L136 = AMPP_FUNCTION(FD1L78, VC1_break_readreg[18], FD1L77, ED1_MonDReg[18]); --FD1L137 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4785 FD1L137 = AMPP_FUNCTION(FD1L7, FD1_ir[0], FD1L136, FD1_sr[20]); --FD1L138 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4786 FD1L138 = AMPP_FUNCTION(FD1L77, FD1_sr[19], FD1L78, ED1_MonDReg[17]); --VC1_break_readreg[17] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[17] VC1_break_readreg[17] = AMPP_FUNCTION(F1__clk1, VC1L42, D1_CLRN_SIGNAL, VC1L26); --FD1L139 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4787 FD1L139 = AMPP_FUNCTION(FD1L75, FD1L76, FD1L138, VC1_break_readreg[17]); --VC1L37 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2164 VC1L37 = AMPP_FUNCTION(FD1L39Q, FD1L55Q, FD1L56Q, VC1L26); --ED1L67 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3247 ED1L67 = AMPP_FUNCTION(FD1L42Q, FD1L198, RD1_q_b[20], ED1_MonAReg[10]); --ED1L68 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3248 ED1L68 = AMPP_FUNCTION(FD1L41Q, FD1L198, RD1_q_b[19], ED1_MonAReg[10]); --VC1L38 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2165 VC1L38 = AMPP_FUNCTION(FD1L38Q, FD1L55Q, FD1L56Q, VC1L26); --JE1_stage_5 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|stage_5 JE1_stage_5 = DFFEAS(JE1L32, F1__clk1, , , HE1L15, , , , ); --JE1L31 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|p4_stage_4~10 JE1L31 = JE1_full_5 & JE1_stage_5 # !JE1_full_5 & (JB1L16); --H1L37 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~1845 H1L37 = AMPP_FUNCTION(H1_word_counter[2], H1_word_counter[4], H1_word_counter[3], H1_word_counter[0]); --H1L38 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~1846 H1L38 = AMPP_FUNCTION(altera_internal_jtag, H1L30, H1L37, H1L25); --ED1L4 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[2]~829 ED1L4 = AMPP_FUNCTION(ED1_MonAReg[2], GND); --ED1L5 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[2]~830 ED1L5 = AMPP_FUNCTION(ED1_MonAReg[2]); --ED1L7 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[3]~831 ED1L7 = AMPP_FUNCTION(ED1_MonAReg[3], GND, ED1L5); --ED1L8 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[3]~832 ED1L8 = AMPP_FUNCTION(ED1_MonAReg[3], ED1L5); --ED1L10 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[4]~833 ED1L10 = AMPP_FUNCTION(ED1_MonAReg[4], GND, ED1L8); --ED1L11 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[4]~834 ED1L11 = AMPP_FUNCTION(ED1_MonAReg[4], ED1L8); --ED1L13 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[5]~835 ED1L13 = AMPP_FUNCTION(ED1_MonAReg[5], GND, ED1L11); --ED1L14 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[5]~836 ED1L14 = AMPP_FUNCTION(ED1_MonAReg[5], ED1L11); --ED1L17 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[6]~837 ED1L17 = AMPP_FUNCTION(ED1_MonAReg[6], GND, ED1L14); --ED1L18 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[6]~838 ED1L18 = AMPP_FUNCTION(ED1_MonAReg[6], ED1L14); --ED1L20 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[7]~839 ED1L20 = AMPP_FUNCTION(ED1_MonAReg[7], GND, ED1L18); --ED1L21 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[7]~840 ED1L21 = AMPP_FUNCTION(ED1_MonAReg[7], ED1L18); --ED1L23 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[8]~841 ED1L23 = AMPP_FUNCTION(ED1_MonAReg[8], GND, ED1L21); --ED1L24 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[8]~842 ED1L24 = AMPP_FUNCTION(ED1_MonAReg[8], ED1L21); --ED1L26 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[9]~843 ED1L26 = AMPP_FUNCTION(ED1_MonAReg[9], GND, ED1L24); --ED1L27 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[9]~844 ED1L27 = AMPP_FUNCTION(ED1_MonAReg[9], ED1L24); --ED1L29 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[10]~845 ED1L29 = AMPP_FUNCTION(ED1_MonAReg[10], ED1L27); --FD1L36Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[17]~reg0 FD1L36Q = AMPP_FUNCTION(A1L336, FD1_sr[17], FD1L104); --ED1L15 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[5]~847 ED1L15 = AMPP_FUNCTION(FD1_jxdr, FD1_ir[1], FD1_ir[0]); --ED1_MonRd is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonRd ED1_MonRd = AMPP_FUNCTION(F1__clk1, ED1L103, D1_CLRN_SIGNAL); --FD1L23Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[4]~reg0 FD1L23Q = AMPP_FUNCTION(A1L336, FD1_sr[4], FD1L104); --ED1L69 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3249 ED1L69 = AMPP_FUNCTION(FD1L23Q, FD1L198, RD1_q_b[1], ED1_MonAReg[10]); --FD1L20Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[1]~reg0 FD1L20Q = AMPP_FUNCTION(A1L336, FD1_sr[1], FD1L104); --VC1L39 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2166 VC1L39 = AMPP_FUNCTION(FD1L20Q, FD1L55Q, FD1L56Q, VC1L26); --VC1_break_readreg[2] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[2] VC1_break_readreg[2] = AMPP_FUNCTION(F1__clk1, VC1L43, D1_CLRN_SIGNAL, VC1L26); --FD1L140 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4788 FD1L140 = AMPP_FUNCTION(ED1_MonDReg[2], FD1_ir[1], VC1_break_readreg[2], FD1_ir[0]); --FD1_sr[4] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[4] FD1_sr[4] = AMPP_FUNCTION(A1L333, FD1L147, D1_CLRN_SIGNAL, FD1L118); --FD1L141 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4789 FD1L141 = AMPP_FUNCTION(FD1L140, FD1_sr[4], FD1L7); --VC1_break_readreg[24] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[24] VC1_break_readreg[24] = AMPP_FUNCTION(F1__clk1, VC1L44, D1_CLRN_SIGNAL, VC1L26); --FD1L142 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4790 FD1L142 = AMPP_FUNCTION(FD1L78, VC1_break_readreg[24], FD1L77, ED1_MonDReg[24]); --FD1_sr[26] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[26] FD1_sr[26] = AMPP_FUNCTION(A1L333, FD1L149, D1_CLRN_SIGNAL, FD1L81); --FD1L143 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4791 FD1L143 = AMPP_FUNCTION(FD1L7, FD1_ir[0], FD1L142, FD1_sr[26]); --L1_state[13] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[13] L1_state[13] = AMPP_FUNCTION(A1L333, L1L27, A1L335); --L1L28 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~28 L1L28 = AMPP_FUNCTION(A1L335, L1_state[13]); --VD1L69 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[4]~1338 VD1L69 = AMPP_FUNCTION(L1_state[4], G4_Q[0], VD1L81); --VD1_td_shift[4] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[4] VD1_td_shift[4] = AMPP_FUNCTION(A1L333, VD1L86, D1_CLRN_SIGNAL, VD1L57); --VD1_rdata[1] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[1] VD1_rdata[1] = AMPP_FUNCTION(F1__clk1, FE1_q_b[1], N1_data_out, VD1L28); --VD1L85 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1339 VD1L85 = AMPP_FUNCTION(VD1L69, VD1_td_shift[4], VD1_rdata[1], VD1_count[9]); --FE1_q_b[0] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2|q_b[0] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1 --Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered FE1_q_b[0]_PORT_A_data_in = Z1_d_writedata[0]; FE1_q_b[0]_PORT_A_data_in_reg = DFFE(FE1_q_b[0]_PORT_A_data_in, FE1_q_b[0]_clock_0, , , FE1_q_b[0]_clock_enable_0); FE1_q_b[0]_PORT_A_address = BUS(DE2_safe_q[0], DE2_safe_q[1], DE2_safe_q[2], DE2_safe_q[3], DE2_safe_q[4], DE2_safe_q[5]); FE1_q_b[0]_PORT_A_address_reg = DFFE(FE1_q_b[0]_PORT_A_address, FE1_q_b[0]_clock_0, , , FE1_q_b[0]_clock_enable_0); FE1_q_b[0]_PORT_B_address = BUS(DE1_safe_q[0], DE1_safe_q[1], DE1_safe_q[2], DE1_safe_q[3], DE1_safe_q[4], DE1_safe_q[5]); FE1_q_b[0]_PORT_B_address_reg = DFFE(FE1_q_b[0]_PORT_B_address, FE1_q_b[0]_clock_1, , , FE1_q_b[0]_clock_enable_1); FE1_q_b[0]_PORT_A_write_enable = VCC; FE1_q_b[0]_PORT_A_write_enable_reg = DFFE(FE1_q_b[0]_PORT_A_write_enable, FE1_q_b[0]_clock_0, , , FE1_q_b[0]_clock_enable_0); FE1_q_b[0]_PORT_B_read_enable = VCC; FE1_q_b[0]_PORT_B_read_enable_reg = DFFE(FE1_q_b[0]_PORT_B_read_enable, FE1_q_b[0]_clock_1, , , FE1_q_b[0]_clock_enable_1); FE1_q_b[0]_clock_0 = F1__clk1; FE1_q_b[0]_clock_1 = F1__clk1; FE1_q_b[0]_clock_enable_0 = FB1_fifo_wr; FE1_q_b[0]_clock_enable_1 = FB1_rd_wfifo; FE1_q_b[0]_PORT_B_data_out = MEMORY(FE1_q_b[0]_PORT_A_data_in_reg, , FE1_q_b[0]_PORT_A_address_reg, FE1_q_b[0]_PORT_B_address_reg, FE1_q_b[0]_PORT_A_write_enable_reg, FE1_q_b[0]_PORT_B_read_enable_reg, , , FE1_q_b[0]_clock_0, FE1_q_b[0]_clock_1, FE1_q_b[0]_clock_enable_0, FE1_q_b[0]_clock_enable_1, , ); FE1_q_b[0] = FE1_q_b[0]_PORT_B_data_out[0]; --VD1_read_write is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write VD1_read_write = AMPP_FUNCTION(A1L333, VD1L43, D1_CLRN_SIGNAL, VD1L96); --VD1_count[6] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[6] VD1_count[6] = AMPP_FUNCTION(A1L333, VD1L18, D1_CLRN_SIGNAL, VD1L57); --VD1L17 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count~218 VD1L17 = AMPP_FUNCTION(L1_state[4], VD1_count[6]); --DE2_safe_q[0] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|safe_q[0] DE2_safe_q[0] = DFFEAS(DE2_counter_comb_bita0, F1__clk1, , , FB1_fifo_wr, , , , ); --DE2_safe_q[1] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|safe_q[1] DE2_safe_q[1] = DFFEAS(DE2_counter_comb_bita1, F1__clk1, , , FB1_fifo_wr, , , , ); --DE2_safe_q[2] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|safe_q[2] DE2_safe_q[2] = DFFEAS(DE2_counter_comb_bita2, F1__clk1, , , FB1_fifo_wr, , , , ); --DE2_safe_q[3] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|safe_q[3] DE2_safe_q[3] = DFFEAS(DE2_counter_comb_bita3, F1__clk1, , , FB1_fifo_wr, , , , ); --DE2_safe_q[4] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|safe_q[4] DE2_safe_q[4] = DFFEAS(DE2_counter_comb_bita4, F1__clk1, , , FB1_fifo_wr, , , , ); --DE2_safe_q[5] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|safe_q[5] DE2_safe_q[5] = DFFEAS(DE2_counter_comb_bita5, F1__clk1, , , FB1_fifo_wr, , , , ); --DE1_safe_q[0] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|safe_q[0] DE1_safe_q[0] = DFFEAS(DE1_counter_comb_bita0, F1__clk1, , , FB1_rd_wfifo, , , , ); --DE1_safe_q[1] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|safe_q[1] DE1_safe_q[1] = DFFEAS(DE1_counter_comb_bita1, F1__clk1, , , FB1_rd_wfifo, , , , ); --DE1_safe_q[2] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|safe_q[2] DE1_safe_q[2] = DFFEAS(DE1_counter_comb_bita2, F1__clk1, , , FB1_rd_wfifo, , , , ); --DE1_safe_q[3] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|safe_q[3] DE1_safe_q[3] = DFFEAS(DE1_counter_comb_bita3, F1__clk1, , , FB1_rd_wfifo, , , , ); --DE1_safe_q[4] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|safe_q[4] DE1_safe_q[4] = DFFEAS(DE1_counter_comb_bita4, F1__clk1, , , FB1_rd_wfifo, , , , ); --DE1_safe_q[5] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|safe_q[5] DE1_safe_q[5] = DFFEAS(DE1_counter_comb_bita5, F1__clk1, , , FB1_rd_wfifo, , , , ); --ED1L105 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonWr~43 ED1L105 = AMPP_FUNCTION(CB1L28, CB1_cpu_0_data_master_requests_cpu_0_jtag_debug_module, CB1_d1_reasons_to_wait, XC1_resetrequest); --ED1L106 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonWr~44 ED1L106 = AMPP_FUNCTION(ED1_MonWr, ED1L105); --FD1L45Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[26]~reg0 FD1L45Q = AMPP_FUNCTION(A1L336, FD1_sr[26], FD1L104); --FD1L46Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[27]~reg0 FD1L46Q = AMPP_FUNCTION(A1L336, FD1_sr[27], FD1L104); --FD1L47Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[28]~reg0 FD1L47Q = AMPP_FUNCTION(A1L336, FD1_sr[28], FD1L104); --FD1L48Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[29]~reg0 FD1L48Q = AMPP_FUNCTION(A1L336, FD1_sr[29], FD1L104); --FD1L49Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[30]~reg0 FD1L49Q = AMPP_FUNCTION(A1L336, FD1_sr[30], FD1L104); --FD1L50Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[31]~reg0 FD1L50Q = AMPP_FUNCTION(A1L336, FD1_sr[31], FD1L104); --FD1L51Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[32]~reg0 FD1L51Q = AMPP_FUNCTION(A1L336, FD1_sr[32], FD1L104); --FD1L52Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[33]~reg0 FD1L52Q = AMPP_FUNCTION(A1L336, FD1_sr[33], FD1L104); --VD1_wdata[0] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[0] VD1_wdata[0] = AMPP_FUNCTION(A1L333, altera_internal_jtag, D1_CLRN_SIGNAL, VD1L94); --DE4_safe_q[0] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|safe_q[0] DE4_safe_q[0] = DFFEAS(DE4_counter_comb_bita0, F1__clk1, , , FB1_wr_rfifo, , , , ); --DE4_safe_q[1] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|safe_q[1] DE4_safe_q[1] = DFFEAS(DE4_counter_comb_bita1, F1__clk1, , , FB1_wr_rfifo, , , , ); --DE4_safe_q[2] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|safe_q[2] DE4_safe_q[2] = DFFEAS(DE4_counter_comb_bita2, F1__clk1, , , FB1_wr_rfifo, , , , ); --DE4_safe_q[3] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|safe_q[3] DE4_safe_q[3] = DFFEAS(DE4_counter_comb_bita3, F1__clk1, , , FB1_wr_rfifo, , , , ); --DE4_safe_q[4] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|safe_q[4] DE4_safe_q[4] = DFFEAS(DE4_counter_comb_bita4, F1__clk1, , , FB1_wr_rfifo, , , , ); --DE4_safe_q[5] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|safe_q[5] DE4_safe_q[5] = DFFEAS(DE4_counter_comb_bita5, F1__clk1, , , FB1_wr_rfifo, , , , ); --DE3_safe_q[0] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|safe_q[0] DE3_safe_q[0] = DFFEAS(DE3_counter_comb_bita0, F1__clk1, , , FB1L57, , , , ); --DE3_safe_q[1] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|safe_q[1] DE3_safe_q[1] = DFFEAS(DE3_counter_comb_bita1, F1__clk1, , , FB1L57, , , , ); --DE3_safe_q[2] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|safe_q[2] DE3_safe_q[2] = DFFEAS(DE3_counter_comb_bita2, F1__clk1, , , FB1L57, , , , ); --DE3_safe_q[3] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|safe_q[3] DE3_safe_q[3] = DFFEAS(DE3_counter_comb_bita3, F1__clk1, , , FB1L57, , , , ); --DE3_safe_q[4] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|safe_q[4] DE3_safe_q[4] = DFFEAS(DE3_counter_comb_bita4, F1__clk1, , , FB1L57, , , , ); --DE3_safe_q[5] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|safe_q[5] DE3_safe_q[5] = DFFEAS(DE3_counter_comb_bita5, F1__clk1, , , FB1L57, , , , ); --SD1_endofpacketvalue_wr_strobe is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_wr_strobe SD1_endofpacketvalue_wr_strobe = EB1L10 & EB1L11 & SD1_wr_strobe & !EB1L9; --SD1_shift_reg[0] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[0] SD1_shift_reg[0] = DFFEAS(SD1L201, F1__clk1, N1_data_out, , SD1L194, , , , ); --SD1_epcs_slave_select_holding_reg[0] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[0] SD1_epcs_slave_select_holding_reg[0] = DFFEAS(UC1L3, F1__clk1, N1_data_out, , SD1_slaveselect_wr_strobe, , , , ); --SD1L225 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|transmitting~86 SD1L225 = SD1_tx_holding_primed & !SD1_transmitting; --SD1L50 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|always6~2 SD1L50 = SD1L225 # Z1_d_writedata[10] & SD1_control_wr_strobe & !SD1_SSO_reg; --VC1L40 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2167 VC1L40 = AMPP_FUNCTION(FD1L41Q, FD1L55Q, FD1L56Q, VC1L26); --ED1L70 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3250 ED1L70 = AMPP_FUNCTION(FD1L44Q, FD1L198, RD1_q_b[22], ED1_MonAReg[10]); --FD1L144 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4792 FD1L144 = AMPP_FUNCTION(FD1L77, FD1_sr[25], FD1L78, ED1_MonDReg[23]); --VC1_break_readreg[23] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[23] VC1_break_readreg[23] = AMPP_FUNCTION(F1__clk1, VC1L45, D1_CLRN_SIGNAL, VC1L26); --FD1L145 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4793 FD1L145 = AMPP_FUNCTION(FD1L75, FD1L76, FD1L144, VC1_break_readreg[23]); --VD1_wdata[1] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[1] VD1_wdata[1] = AMPP_FUNCTION(A1L333, VD1_td_shift[5], D1_CLRN_SIGNAL, VD1L96); --SD1_epcs_slave_select_holding_reg[1] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[1] SD1_epcs_slave_select_holding_reg[1] = DFFEAS(Z1_d_writedata[1], F1__clk1, N1_data_out, , SD1_slaveselect_wr_strobe, , , , ); --SD1_shift_reg[1] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[1] SD1_shift_reg[1] = DFFEAS(SD1L202, F1__clk1, N1_data_out, , SD1L194, , , , ); --ED1L71 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3251 ED1L71 = AMPP_FUNCTION(ED1_MonAReg[4], ED1_MonAReg[2]); --ED1L72 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3252 ED1L72 = AMPP_FUNCTION(RD1_q_b[2], ED1L71, ED1_MonAReg[10], ED1_MonAReg[3]); --FD1L24Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[5]~reg0 FD1L24Q = AMPP_FUNCTION(A1L336, FD1_sr[5], FD1L104); --VD1_wdata[2] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[2] VD1_wdata[2] = AMPP_FUNCTION(A1L333, VD1_td_shift[6], D1_CLRN_SIGNAL, VD1L96); --SD1_epcs_slave_select_holding_reg[2] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[2] SD1_epcs_slave_select_holding_reg[2] = DFFEAS(Z1_d_writedata[2], F1__clk1, N1_data_out, , SD1_slaveselect_wr_strobe, , , , ); --SD1_shift_reg[2] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[2] SD1_shift_reg[2] = DFFEAS(SD1L203, F1__clk1, N1_data_out, , SD1L194, , , , ); --ED1L73 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3253 ED1L73 = AMPP_FUNCTION(ED1_MonAReg[10], ED1_MonAReg[2], ED1_MonAReg[4], ED1_MonAReg[3]); --ED1L74 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3254 ED1L74 = AMPP_FUNCTION(ED1L73, RD1_q_b[3], ED1_MonAReg[10]); --FD1L25Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[6]~reg0 FD1L25Q = AMPP_FUNCTION(A1L336, FD1_sr[6], FD1L104); --VD1_wdata[3] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[3] VD1_wdata[3] = AMPP_FUNCTION(A1L333, VD1_td_shift[7], D1_CLRN_SIGNAL, VD1L96); --SD1_epcs_slave_select_holding_reg[3] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[3] SD1_epcs_slave_select_holding_reg[3] = DFFEAS(Z1_d_writedata[3], F1__clk1, N1_data_out, , SD1_slaveselect_wr_strobe, , , , ); --SD1_shift_reg[3] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[3] SD1_shift_reg[3] = DFFEAS(SD1L204, F1__clk1, N1_data_out, , SD1L194, , , , ); --VD1_wdata[4] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[4] VD1_wdata[4] = AMPP_FUNCTION(A1L333, VD1_td_shift[8], D1_CLRN_SIGNAL, VD1L96); --SD1_epcs_slave_select_holding_reg[4] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[4] SD1_epcs_slave_select_holding_reg[4] = DFFEAS(Z1_d_writedata[4], F1__clk1, N1_data_out, , SD1_slaveselect_wr_strobe, , , , ); --SD1_shift_reg[4] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[4] SD1_shift_reg[4] = DFFEAS(SD1L205, F1__clk1, N1_data_out, , SD1L194, , , , ); --ED1L75 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3255 ED1L75 = AMPP_FUNCTION(ED1_MonAReg[10], ED1_MonAReg[2], ED1_MonAReg[3], ED1_MonAReg[4]); --ED1L76 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3256 ED1L76 = AMPP_FUNCTION(ED1L75, RD1_q_b[4], ED1_MonAReg[10]); --FD1L26Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[7]~reg0 FD1L26Q = AMPP_FUNCTION(A1L336, FD1_sr[7], FD1L104); --VD1_wdata[5] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[5] VD1_wdata[5] = AMPP_FUNCTION(A1L333, VD1_td_shift[9], D1_CLRN_SIGNAL, VD1L96); --SD1_epcs_slave_select_holding_reg[5] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[5] SD1_epcs_slave_select_holding_reg[5] = DFFEAS(Z1_d_writedata[5], F1__clk1, N1_data_out, , SD1_slaveselect_wr_strobe, , , , ); --SD1_shift_reg[5] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[5] SD1_shift_reg[5] = DFFEAS(SD1L206, F1__clk1, N1_data_out, , SD1L194, , , , ); --ED1L1 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|Equal~85 ED1L1 = AMPP_FUNCTION(ED1_MonAReg[2], ED1_MonAReg[4]); --ED1L77 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3257 ED1L77 = AMPP_FUNCTION(RD1_q_b[5], ED1L1, ED1_MonAReg[10], ED1_MonAReg[3]); --FD1L27Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[8]~reg0 FD1L27Q = AMPP_FUNCTION(A1L336, FD1_sr[8], FD1L104); --VD1_wdata[6] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[6] VD1_wdata[6] = AMPP_FUNCTION(A1L333, VD1_td_shift[10], D1_CLRN_SIGNAL, VD1L96); --SD1_epcs_slave_select_holding_reg[6] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[6] SD1_epcs_slave_select_holding_reg[6] = DFFEAS(Z1_d_writedata[6], F1__clk1, N1_data_out, , SD1_slaveselect_wr_strobe, , , , ); --SD1_shift_reg[6] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[6] SD1_shift_reg[6] = DFFEAS(SD1L207, F1__clk1, N1_data_out, , SD1L194, , , , ); --FD1L28Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[9]~reg0 FD1L28Q = AMPP_FUNCTION(A1L336, FD1_sr[9], FD1L104); --ED1L78 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3258 ED1L78 = AMPP_FUNCTION(FD1L28Q, FD1L198, RD1_q_b[6], ED1_MonAReg[10]); --VD1_wdata[7] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[7] VD1_wdata[7] = AMPP_FUNCTION(A1L333, altera_internal_jtag, D1_CLRN_SIGNAL, VD1L96); --SD1_epcs_slave_select_holding_reg[7] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[7] SD1_epcs_slave_select_holding_reg[7] = DFFEAS(Z1_d_writedata[7], F1__clk1, N1_data_out, , SD1_slaveselect_wr_strobe, , , , ); --SD1_shift_reg[7] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[7] SD1_shift_reg[7] = DFFEAS(SD1L208, F1__clk1, N1_data_out, , SD1L194, , , , ); --FD1L29Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[10]~reg0 FD1L29Q = AMPP_FUNCTION(A1L336, FD1_sr[10], FD1L104); --ED1L79 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3259 ED1L79 = AMPP_FUNCTION(FD1L29Q, FD1L198, RD1_q_b[7], ED1_MonAReg[10]); --SD1_epcs_slave_select_holding_reg[8] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[8] SD1_epcs_slave_select_holding_reg[8] = DFFEAS(Z1_d_writedata[8], F1__clk1, N1_data_out, , SD1_slaveselect_wr_strobe, , , , ); --ED1L80 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3260 ED1L80 = AMPP_FUNCTION(RD1_q_b[8], ED1L71, ED1_MonAReg[10], ED1_MonAReg[3]); --FD1L30Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[11]~reg0 FD1L30Q = AMPP_FUNCTION(A1L336, FD1_sr[11], FD1L104); --SD1_epcs_slave_select_holding_reg[9] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[9] SD1_epcs_slave_select_holding_reg[9] = DFFEAS(Z1_d_writedata[9], F1__clk1, N1_data_out, , SD1_slaveselect_wr_strobe, , , , ); --ED1L81 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3261 ED1L81 = AMPP_FUNCTION(RD1_q_b[9], ED1L71, ED1_MonAReg[10], ED1_MonAReg[3]); --FD1L31Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[12]~reg0 FD1L31Q = AMPP_FUNCTION(A1L336, FD1_sr[12], FD1L104); --FB1L7 is system_0:u0|jtag_uart_0:the_jtag_uart_0|ac~71 FB1L7 = VD1L54Q # VD1L51Q; --FB1L8 is system_0:u0|jtag_uart_0:the_jtag_uart_0|ac~72 FB1L8 = FB1L7 # FB1_ac & (!FB1L49 # !Z1_d_writedata[10]); --SD1_epcs_slave_select_holding_reg[10] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[10] SD1_epcs_slave_select_holding_reg[10] = DFFEAS(Z1_d_writedata[10], F1__clk1, N1_data_out, , SD1_slaveselect_wr_strobe, , , , ); --FD1L32Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[13]~reg0 FD1L32Q = AMPP_FUNCTION(A1L336, FD1_sr[13], FD1L104); --ED1L82 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3262 ED1L82 = AMPP_FUNCTION(FD1L32Q, FD1L198, RD1_q_b[10], ED1_MonAReg[10]); --SD1_epcs_slave_select_holding_reg[11] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[11] SD1_epcs_slave_select_holding_reg[11] = DFFEAS(Z1_d_writedata[11], F1__clk1, N1_data_out, , SD1_slaveselect_wr_strobe, , , , ); --ED1L83 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3263 ED1L83 = AMPP_FUNCTION(ED1L73, RD1_q_b[11], ED1_MonAReg[10]); --FD1L33Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[14]~reg0 FD1L33Q = AMPP_FUNCTION(A1L336, FD1_sr[14], FD1L104); --SD1_epcs_slave_select_holding_reg[12] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[12] SD1_epcs_slave_select_holding_reg[12] = DFFEAS(Z1_d_writedata[12], F1__clk1, N1_data_out, , SD1_slaveselect_wr_strobe, , , , ); --ED1L84 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3264 ED1L84 = AMPP_FUNCTION(ED1L75, RD1_q_b[12], ED1_MonAReg[10]); --FD1L34Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[15]~reg0 FD1L34Q = AMPP_FUNCTION(A1L336, FD1_sr[15], FD1L104); --SD1_epcs_slave_select_holding_reg[13] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[13] SD1_epcs_slave_select_holding_reg[13] = DFFEAS(Z1_d_writedata[13], F1__clk1, N1_data_out, , SD1_slaveselect_wr_strobe, , , , ); --FD1L35Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[16]~reg0 FD1L35Q = AMPP_FUNCTION(A1L336, FD1_sr[16], FD1L104); --ED1L85 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3265 ED1L85 = AMPP_FUNCTION(FD1L35Q, FD1L198, RD1_q_b[13], ED1_MonAReg[10]); --FB1L39 is system_0:u0|jtag_uart_0:the_jtag_uart_0|always2~32 FB1L39 = Z1_d_write & GB1L8 & !AB1_cpu_0_data_master_waitrequest; --FB1L61 is system_0:u0|jtag_uart_0:the_jtag_uart_0|woverflow~60 FB1L61 = FB1L39 & (Z1_d_address[2] & FB1_woverflow # !Z1_d_address[2] & (BE1_b_full)) # !FB1L39 & FB1_woverflow; --SD1_epcs_slave_select_holding_reg[14] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[14] SD1_epcs_slave_select_holding_reg[14] = DFFEAS(Z1_d_writedata[14], F1__clk1, N1_data_out, , SD1_slaveselect_wr_strobe, , , , ); --ED1L86 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3266 ED1L86 = AMPP_FUNCTION(FD1L36Q, FD1L198, RD1_q_b[14], ED1_MonAReg[10]); --FB1L58 is system_0:u0|jtag_uart_0:the_jtag_uart_0|rvalid~17 FB1L58 = FB1L45 & BE2_b_non_empty # !FB1L45 & (FB1_rvalid); --SD1_epcs_slave_select_holding_reg[15] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[15] SD1_epcs_slave_select_holding_reg[15] = DFFEAS(Z1_d_writedata[15], F1__clk1, N1_data_out, , SD1_slaveselect_wr_strobe, , , , ); --ED1L87 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3267 ED1L87 = AMPP_FUNCTION(FD1L37Q, FD1L198, RD1_q_b[15], ED1_MonAReg[10]); --HE1_stage_6 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|stage_6 HE1_stage_6 = DFFEAS(JB1L7, F1__clk1, , , HE1L13, , , , ); --JE1_full_6 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_6 JE1_full_6 = DFFEAS(HE1L39, F1__clk1, N1_data_out, , HE1L14, , , , ); --HE1L38 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|p5_stage_5~10 HE1L38 = JE1_full_6 & HE1_stage_6 # !JE1_full_6 & (JB1L7); --HE1L15 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|always2~1 HE1L15 = HB1_za_valid # JB1L5 & !JE1_full_5; --HE1L37 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|p5_full_5~9 HE1L37 = HB1_za_valid & (JB1L5 & JE1_full_4 # !JB1L5 & (JE1_full_6)) # !HB1_za_valid & JE1_full_4; --ED1L88 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3268 ED1L88 = AMPP_FUNCTION(RD1_q_b[27], ED1L71, ED1_MonAReg[10], ED1_MonAReg[3]); --ED1L89 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3269 ED1L89 = AMPP_FUNCTION(FD1L53Q, FD1L198, RD1_q_b[31], ED1_MonAReg[10]); --ED1L90 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3270 ED1L90 = AMPP_FUNCTION(FD1L50Q, FD1L198, RD1_q_b[28], ED1_MonAReg[10]); --ED1L91 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3271 ED1L91 = AMPP_FUNCTION(FD1L52Q, FD1L198, RD1_q_b[30], ED1_MonAReg[10]); --ED1L92 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3272 ED1L92 = AMPP_FUNCTION(RD1_q_b[29], ED1L71, ED1_MonAReg[10], ED1_MonAReg[3]); --SD1L179 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_slowcount[1]~43 SD1L179 = SD1_transmitting & SD1_slowcount[0] & !SD1_slowcount[1]; --SD1L178 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_slowcount[0]~44 SD1L178 = SD1_transmitting & !SD1_slowcount[1] & !SD1_slowcount[0]; --SD1L40 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|add~97 SD1L40 = SD1_state[0] $ VCC; --SD1L41 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|add~98 SD1L41 = CARRY(SD1_state[0]); --SD1L51 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|always11~0 SD1L51 = SD1_transmitting & SD1_slowcount[1] & !SD1_slowcount[0]; --SD1L42 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|add~99 SD1L42 = SD1_state[1] & !SD1L41 # !SD1_state[1] & (SD1L41 # GND); --SD1L43 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|add~100 SD1L43 = CARRY(!SD1L41 # !SD1_state[1]); --SD1L44 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|add~101 SD1L44 = SD1_state[2] & (SD1L43 $ GND) # !SD1_state[2] & !SD1L43 & VCC; --SD1L45 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|add~102 SD1L45 = CARRY(SD1_state[2] & !SD1L43); --SD1L46 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|add~103 SD1L46 = SD1_state[3] & !SD1L45 # !SD1_state[3] & (SD1L45 # GND); --SD1L47 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|add~104 SD1L47 = CARRY(!SD1L45 # !SD1_state[3]); --SD1L48 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|add~105 SD1L48 = SD1_state[4] $ !SD1L47; --SD1L221 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|state~8160 SD1L221 = SD1L48 & (!SD1L21 # !SD1_state[4] # !SD1_state[0]); --SD1L222 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|state~8161 SD1L222 = SD1L42 & (!SD1L21 # !SD1_state[4] # !SD1_state[0]); --ME1_do_start_rx is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|do_start_rx ME1_do_start_rx = DFFEAS(ME1L21, F1__clk1, N1_data_out, , , , , , ); --ME1_sync_rxd is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|sync_rxd ME1_sync_rxd = DFFEAS(ME1_d1_source_rxd, F1__clk1, N1_data_out, , , , , , ); --ME1L85 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in[9]~40 ME1L85 = ME1_do_start_rx # ME1_sync_rxd; --ME1_baud_clk_en is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_clk_en ME1_baud_clk_en = DFFEAS(ME1L23, F1__clk1, N1_data_out, , , , , , ); --ME1L94 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6]~971 ME1L94 = ME1_do_start_rx # ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] & ME1_baud_clk_en; --ME1L76 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in[0]~41 ME1L76 = ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] # ME1_do_start_rx; --ME1L84 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in[8]~42 ME1L84 = ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] # ME1_do_start_rx; --ME1L83 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in[7]~43 ME1L83 = ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] # ME1_do_start_rx; --ME1L82 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in[6]~44 ME1L82 = ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] # ME1_do_start_rx; --ME1L81 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in[5]~45 ME1L81 = ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] # ME1_do_start_rx; --ME1L80 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in[4]~46 ME1L80 = ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] # ME1_do_start_rx; --ME1L79 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in[3]~47 ME1L79 = ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] # ME1_do_start_rx; --ME1L78 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in[2]~48 ME1L78 = ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] # ME1_do_start_rx; --ME1L77 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in[1]~49 ME1L77 = ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] # ME1_do_start_rx; --VD1_jupdate is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate VD1_jupdate = AMPP_FUNCTION(!A1L333, VD1L26, D1_CLRN_SIGNAL); --FB1L47 is system_0:u0|jtag_uart_0:the_jtag_uart_0|fifo_wr~26 FB1L47 = !Z1_d_address[2] & !BE1_b_full & FB1L39; --BE1L7 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~141 BE1L7 = EE1_safe_q[2] # EE1_safe_q[1] # EE1_safe_q[5] # EE1_safe_q[4]; --BE1L8 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~142 BE1L8 = EE1_safe_q[3] # BE1L7 # !FB1_rd_wfifo # !EE1_safe_q[0]; --BE1L9 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~143 BE1L9 = BE1_b_full # FB1_fifo_wr # BE1_b_non_empty & BE1L8; --ED1L93 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3273 ED1L93 = AMPP_FUNCTION(FD1L48Q, FD1L198, RD1_q_b[26], ED1_MonAReg[10]); --ED1L94 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3274 ED1L94 = AMPP_FUNCTION(RD1_q_b[23], ED1L1, ED1_MonAReg[10], ED1_MonAReg[3]); --ED1L95 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3275 ED1L95 = AMPP_FUNCTION(FD1L47Q, FD1L198, RD1_q_b[25], ED1_MonAReg[10]); --ED1L96 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3276 ED1L96 = AMPP_FUNCTION(FD1L46Q, FD1L198, RD1_q_b[24], ED1_MonAReg[10]); --EC1_q_a[0] is system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_kk61:auto_generated|altsyncram_u5e1:altsyncram1|q_a[0] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1 --Port A Logical Depth: 256, Port A Logical Width: 2, Port B Logical Depth: 256, Port B Logical Width: 2 --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered EC1_q_a[0] = AMPP_FUNCTION(VCC, Z1_M_bht_wr_en, F1__clk1, F1__clk1, Z1_F_stall, Z1_M_bht_wr_en, GND, Z1_F_bht_ptr_nxt[0], Z1_F_bht_ptr_nxt[1], Z1_F_bht_ptr_nxt[2], Z1_F_bht_ptr_nxt[3], Z1_F_bht_ptr_nxt[4], Z1_F_bht_ptr_nxt[5], Z1_F_bht_ptr_nxt[6], Z1_F_bht_ptr_nxt[7], Z1L2152, Z1_M_bht_ptr[0], Z1_M_bht_ptr[1], Z1_M_bht_ptr[2], Z1_M_bht_ptr[3], Z1_M_bht_ptr[4], Z1_M_bht_ptr[5], Z1_M_bht_ptr[6], Z1_M_bht_ptr[7]); --Z1_F_bht_ptr[0] is system_0:u0|cpu_0:the_cpu_0|F_bht_ptr[0] Z1_F_bht_ptr[0] = AMPP_FUNCTION(F1__clk1, Z1_F_bht_ptr_nxt[0], N1_data_out, Z1_F_stall); --Z1_F_bht_ptr[1] is system_0:u0|cpu_0:the_cpu_0|F_bht_ptr[1] Z1_F_bht_ptr[1] = AMPP_FUNCTION(F1__clk1, Z1_F_bht_ptr_nxt[1], N1_data_out, Z1_F_stall); --Z1_F_bht_ptr[2] is system_0:u0|cpu_0:the_cpu_0|F_bht_ptr[2] Z1_F_bht_ptr[2] = AMPP_FUNCTION(F1__clk1, Z1_F_bht_ptr_nxt[2], N1_data_out, Z1_F_stall); --Z1_F_bht_ptr[3] is system_0:u0|cpu_0:the_cpu_0|F_bht_ptr[3] Z1_F_bht_ptr[3] = AMPP_FUNCTION(F1__clk1, Z1_F_bht_ptr_nxt[3], N1_data_out, Z1_F_stall); --Z1_F_bht_ptr[4] is system_0:u0|cpu_0:the_cpu_0|F_bht_ptr[4] Z1_F_bht_ptr[4] = AMPP_FUNCTION(F1__clk1, Z1_F_bht_ptr_nxt[4], N1_data_out, Z1_F_stall); --Z1_F_bht_ptr[5] is system_0:u0|cpu_0:the_cpu_0|F_bht_ptr[5] Z1_F_bht_ptr[5] = AMPP_FUNCTION(F1__clk1, Z1_F_bht_ptr_nxt[5], N1_data_out, Z1_F_stall); --Z1_F_bht_ptr[6] is system_0:u0|cpu_0:the_cpu_0|F_bht_ptr[6] Z1_F_bht_ptr[6] = AMPP_FUNCTION(F1__clk1, Z1_F_bht_ptr_nxt[6], N1_data_out, Z1_F_stall); --Z1_F_bht_ptr[7] is system_0:u0|cpu_0:the_cpu_0|F_bht_ptr[7] Z1_F_bht_ptr[7] = AMPP_FUNCTION(F1__clk1, Z1_F_bht_ptr_nxt[7], N1_data_out, Z1_F_stall); --ED1L97 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3277 ED1L97 = AMPP_FUNCTION(FD1L38Q, FD1L198, RD1_q_b[16], ED1_MonAReg[10]); --Z1_A_mul_src1[16] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[16] Z1_A_mul_src1[16] = AMPP_FUNCTION(F1__clk1, Z1L435, N1_data_out); --Z1_A_mul_src1[17] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[17] Z1_A_mul_src1[17] = AMPP_FUNCTION(F1__clk1, Z1L436, N1_data_out); --Z1_A_mul_src1[18] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[18] Z1_A_mul_src1[18] = AMPP_FUNCTION(F1__clk1, Z1L437, N1_data_out); --Z1_A_mul_src1[19] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[19] Z1_A_mul_src1[19] = AMPP_FUNCTION(F1__clk1, Z1L438, N1_data_out); --Z1_A_mul_src1[20] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[20] Z1_A_mul_src1[20] = AMPP_FUNCTION(F1__clk1, Z1L439, N1_data_out); --Z1_A_mul_src1[21] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[21] Z1_A_mul_src1[21] = AMPP_FUNCTION(F1__clk1, Z1L440, N1_data_out); --Z1_A_mul_src1[22] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[22] Z1_A_mul_src1[22] = AMPP_FUNCTION(F1__clk1, Z1L441, N1_data_out); --Z1_A_mul_src1[23] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[23] Z1_A_mul_src1[23] = AMPP_FUNCTION(F1__clk1, Z1L442, N1_data_out); --Z1_A_mul_src1[24] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[24] Z1_A_mul_src1[24] = AMPP_FUNCTION(F1__clk1, Z1L443, N1_data_out); --Z1_A_mul_src1[25] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[25] Z1_A_mul_src1[25] = AMPP_FUNCTION(F1__clk1, Z1L444, N1_data_out); --Z1_A_mul_src1[26] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[26] Z1_A_mul_src1[26] = AMPP_FUNCTION(F1__clk1, Z1L445, N1_data_out); --Z1_A_mul_src1[27] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[27] Z1_A_mul_src1[27] = AMPP_FUNCTION(F1__clk1, Z1L446, N1_data_out); --Z1_A_mul_src1[28] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[28] Z1_A_mul_src1[28] = AMPP_FUNCTION(F1__clk1, Z1L447, N1_data_out); --Z1_A_mul_src1[29] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[29] Z1_A_mul_src1[29] = AMPP_FUNCTION(F1__clk1, Z1L448, N1_data_out); --Z1_A_mul_src1[30] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[30] Z1_A_mul_src1[30] = AMPP_FUNCTION(F1__clk1, Z1L449, N1_data_out); --Z1_A_mul_src1[31] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[31] Z1_A_mul_src1[31] = AMPP_FUNCTION(F1__clk1, Z1L450, N1_data_out); --Z1_A_mul_src2[0] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[0] Z1_A_mul_src2[0] = AMPP_FUNCTION(F1__clk1, Z1L484, N1_data_out); --Z1_A_mul_src2[1] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[1] Z1_A_mul_src2[1] = AMPP_FUNCTION(F1__clk1, Z1L485, N1_data_out); --Z1_A_mul_src2[2] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[2] Z1_A_mul_src2[2] = AMPP_FUNCTION(F1__clk1, Z1L486, N1_data_out); --Z1_A_mul_src2[3] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[3] Z1_A_mul_src2[3] = AMPP_FUNCTION(F1__clk1, Z1L487, N1_data_out); --Z1_A_mul_src2[4] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[4] Z1_A_mul_src2[4] = AMPP_FUNCTION(F1__clk1, Z1L488, N1_data_out); --Z1_A_mul_src2[5] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[5] Z1_A_mul_src2[5] = AMPP_FUNCTION(F1__clk1, Z1L489, N1_data_out); --Z1_A_mul_src2[6] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[6] Z1_A_mul_src2[6] = AMPP_FUNCTION(F1__clk1, Z1L490, N1_data_out); --Z1_A_mul_src2[7] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[7] Z1_A_mul_src2[7] = AMPP_FUNCTION(F1__clk1, Z1L491, N1_data_out); --Z1_A_mul_src2[8] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[8] Z1_A_mul_src2[8] = AMPP_FUNCTION(F1__clk1, Z1L492, N1_data_out); --Z1_A_mul_src2[9] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[9] Z1_A_mul_src2[9] = AMPP_FUNCTION(F1__clk1, Z1L493, N1_data_out); --Z1_A_mul_src2[10] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[10] Z1_A_mul_src2[10] = AMPP_FUNCTION(F1__clk1, Z1L494, N1_data_out); --Z1_A_mul_src2[11] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[11] Z1_A_mul_src2[11] = AMPP_FUNCTION(F1__clk1, Z1L495, N1_data_out); --Z1_A_mul_src2[12] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[12] Z1_A_mul_src2[12] = AMPP_FUNCTION(F1__clk1, Z1L496, N1_data_out); --Z1_A_mul_src2[13] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[13] Z1_A_mul_src2[13] = AMPP_FUNCTION(F1__clk1, Z1L497, N1_data_out); --Z1_A_mul_src2[14] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[14] Z1_A_mul_src2[14] = AMPP_FUNCTION(F1__clk1, Z1L498, N1_data_out); --Z1_A_mul_src2[15] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[15] Z1_A_mul_src2[15] = AMPP_FUNCTION(F1__clk1, Z1L499, N1_data_out); --Z1_A_mul_src1[0] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[0] Z1_A_mul_src1[0] = AMPP_FUNCTION(F1__clk1, Z1L419, N1_data_out); --Z1_A_mul_src1[1] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[1] Z1_A_mul_src1[1] = AMPP_FUNCTION(F1__clk1, Z1L420, N1_data_out); --Z1_A_mul_src1[2] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[2] Z1_A_mul_src1[2] = AMPP_FUNCTION(F1__clk1, Z1L421, N1_data_out); --Z1_A_mul_src1[3] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[3] Z1_A_mul_src1[3] = AMPP_FUNCTION(F1__clk1, Z1L422, N1_data_out); --Z1_A_mul_src1[4] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[4] Z1_A_mul_src1[4] = AMPP_FUNCTION(F1__clk1, Z1L423, N1_data_out); --Z1_A_mul_src1[5] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[5] Z1_A_mul_src1[5] = AMPP_FUNCTION(F1__clk1, Z1L424, N1_data_out); --Z1_A_mul_src1[6] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[6] Z1_A_mul_src1[6] = AMPP_FUNCTION(F1__clk1, Z1L425, N1_data_out); --Z1_A_mul_src1[7] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[7] Z1_A_mul_src1[7] = AMPP_FUNCTION(F1__clk1, Z1L426, N1_data_out); --Z1_A_mul_src1[8] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[8] Z1_A_mul_src1[8] = AMPP_FUNCTION(F1__clk1, Z1L427, N1_data_out); --Z1_A_mul_src1[9] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[9] Z1_A_mul_src1[9] = AMPP_FUNCTION(F1__clk1, Z1L428, N1_data_out); --Z1_A_mul_src1[10] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[10] Z1_A_mul_src1[10] = AMPP_FUNCTION(F1__clk1, Z1L429, N1_data_out); --Z1_A_mul_src1[11] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[11] Z1_A_mul_src1[11] = AMPP_FUNCTION(F1__clk1, Z1L430, N1_data_out); --Z1_A_mul_src1[12] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[12] Z1_A_mul_src1[12] = AMPP_FUNCTION(F1__clk1, Z1L431, N1_data_out); --Z1_A_mul_src1[13] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[13] Z1_A_mul_src1[13] = AMPP_FUNCTION(F1__clk1, Z1L432, N1_data_out); --Z1_A_mul_src1[14] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[14] Z1_A_mul_src1[14] = AMPP_FUNCTION(F1__clk1, Z1L433, N1_data_out); --Z1_A_mul_src1[15] is system_0:u0|cpu_0:the_cpu_0|A_mul_src1[15] Z1_A_mul_src1[15] = AMPP_FUNCTION(F1__clk1, Z1L434, N1_data_out); --Z1L2502 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[15]~349 Z1L2502 = AMPP_FUNCTION(Z1_E_src1[15], Z1_E_src1[14], Z1L3010); --Z1L2496 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[13]~333 Z1L2496 = AMPP_FUNCTION(Z1_E_src1[13], Z1_E_src1[12], Z1L3010); --Z1L2490 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[11]~350 Z1L2490 = AMPP_FUNCTION(Z1_E_src1[11], Z1_E_src1[10], Z1L3010); --Z1L2484 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[9]~334 Z1L2484 = AMPP_FUNCTION(Z1_E_src1[9], Z1_E_src1[8], Z1L3010); --Z1L2478 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[7]~351 Z1L2478 = AMPP_FUNCTION(Z1_E_src1[7], Z1_E_src1[6], Z1L3010); --Z1L2472 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[5]~335 Z1L2472 = AMPP_FUNCTION(Z1_E_src1[5], Z1_E_src1[4], Z1L3010); --Z1L2466 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[3]~344 Z1L2466 = AMPP_FUNCTION(Z1_E_src1[3], Z1_E_src1[2], Z1L3010); --Z1L2460 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[1]~328 Z1L2460 = AMPP_FUNCTION(Z1_E_src1[1], Z1_E_src1[0], Z1L3010); --Z1L2550 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[31]~345 Z1L2550 = AMPP_FUNCTION(Z1_E_src1[31], Z1_E_src1[30], Z1L3010); --Z1L2544 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[29]~329 Z1L2544 = AMPP_FUNCTION(Z1_E_src1[29], Z1_E_src1[28], Z1L3010); --Z1L2538 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[27]~346 Z1L2538 = AMPP_FUNCTION(Z1_E_src1[27], Z1_E_src1[26], Z1L3010); --Z1L2532 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[25]~330 Z1L2532 = AMPP_FUNCTION(Z1_E_src1[25], Z1_E_src1[24], Z1L3010); --Z1L2526 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[23]~347 Z1L2526 = AMPP_FUNCTION(Z1_E_src1[23], Z1_E_src1[22], Z1L3010); --Z1L2520 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[21]~331 Z1L2520 = AMPP_FUNCTION(Z1_E_src1[21], Z1_E_src1[20], Z1L3010); --Z1L2514 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[19]~348 Z1L2514 = AMPP_FUNCTION(Z1_E_src1[19], Z1_E_src1[18], Z1L3010); --Z1L2508 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[17]~332 Z1L2508 = AMPP_FUNCTION(Z1_E_src1[17], Z1_E_src1[16], Z1L3010); --Z1L1060 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_shift_rot_right~31 Z1L1060 = AMPP_FUNCTION(Z1_D_iw[14], Z1L1052, Z1_D_iw[13]); --Z1L1058 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_shift_right_arith~23 Z1L1058 = AMPP_FUNCTION(Z1L1894, Z1_D_iw[16], Z1L1052, Z1_D_iw[13]); --Z1L1057 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_rot~34 Z1L1057 = AMPP_FUNCTION(Z1L1052, Z1_D_iw[15], Z1_D_iw[13]); --Z1L1059 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_shift_rot_left~20 Z1L1059 = AMPP_FUNCTION(Z1L1052, Z1_D_iw[13], Z1_D_iw[14]); --Z1L2499 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[14]~341 Z1L2499 = AMPP_FUNCTION(Z1_E_src1[14], Z1_E_src1[13], Z1L3010); --Z1L2493 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[12]~325 Z1L2493 = AMPP_FUNCTION(Z1_E_src1[12], Z1_E_src1[11], Z1L3010); --Z1L2487 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[10]~342 Z1L2487 = AMPP_FUNCTION(Z1_E_src1[10], Z1_E_src1[9], Z1L3010); --Z1L2481 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[8]~326 Z1L2481 = AMPP_FUNCTION(Z1_E_src1[8], Z1_E_src1[7], Z1L3010); --Z1L2475 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[6]~343 Z1L2475 = AMPP_FUNCTION(Z1_E_src1[6], Z1_E_src1[5], Z1L3010); --Z1L2469 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[4]~327 Z1L2469 = AMPP_FUNCTION(Z1_E_src1[4], Z1_E_src1[3], Z1L3010); --Z1L2463 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[2]~336 Z1L2463 = AMPP_FUNCTION(Z1_E_src1[2], Z1_E_src1[1], Z1L3010); --Z1L2457 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[0]~320 Z1L2457 = AMPP_FUNCTION(Z1_E_src1[0], Z1_E_src1[31], Z1L3010); --Z1L2547 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[30]~337 Z1L2547 = AMPP_FUNCTION(Z1_E_src1[30], Z1_E_src1[29], Z1L3010); --Z1L2541 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[28]~321 Z1L2541 = AMPP_FUNCTION(Z1_E_src1[28], Z1_E_src1[27], Z1L3010); --Z1L2535 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[26]~338 Z1L2535 = AMPP_FUNCTION(Z1_E_src1[26], Z1_E_src1[25], Z1L3010); --Z1L2529 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[24]~322 Z1L2529 = AMPP_FUNCTION(Z1_E_src1[24], Z1_E_src1[23], Z1L3010); --Z1L2523 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[22]~339 Z1L2523 = AMPP_FUNCTION(Z1_E_src1[22], Z1_E_src1[21], Z1L3010); --Z1L2517 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[20]~323 Z1L2517 = AMPP_FUNCTION(Z1_E_src1[20], Z1_E_src1[19], Z1L3010); --Z1L2511 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[18]~340 Z1L2511 = AMPP_FUNCTION(Z1_E_src1[18], Z1_E_src1[17], Z1L3010); --Z1L2505 is system_0:u0|cpu_0:the_cpu_0|M_rot_step1[16]~324 Z1L2505 = AMPP_FUNCTION(Z1_E_src1[16], Z1_E_src1[15], Z1L3010); --ED1L98 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3278 ED1L98 = AMPP_FUNCTION(ED1_MonAReg[3], ED1L1, RD1_q_b[18], ED1_MonAReg[10]); --ED1L99 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3279 ED1L99 = AMPP_FUNCTION(ED1L98, ED1_MonDReg[18], ED1_MonRd1); --ED1L100 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg~3280 ED1L100 = AMPP_FUNCTION(FD1L39Q, FD1L198, RD1_q_b[17], ED1_MonAReg[10]); --VC1L41 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2168 VC1L41 = AMPP_FUNCTION(FD1L37Q, FD1L55Q, FD1L56Q, VC1L26); --VC1L42 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2169 VC1L42 = AMPP_FUNCTION(FD1L36Q, FD1L55Q, FD1L56Q, VC1L26); --JE1_stage_6 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|stage_6 JE1_stage_6 = DFFEAS(JB1L16, F1__clk1, , , HE1L13, , , , ); --JE1L32 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|p5_stage_5~10 JE1L32 = JE1_full_6 & JE1_stage_6 # !JE1_full_6 & (JB1L16); --FD1_sr[17] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[17] FD1_sr[17] = AMPP_FUNCTION(A1L333, FD1L151, D1_CLRN_SIGNAL, FD1L81); --ED1L103 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonRd~141 ED1L103 = AMPP_FUNCTION(FD1L197, ED1_MonRd, FD1L198, ED1L105); --FD1L21Q is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|jdo[2]~reg0 FD1L21Q = AMPP_FUNCTION(A1L336, FD1_sr[2], FD1L104); --VC1L43 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2170 VC1L43 = AMPP_FUNCTION(FD1L21Q, FD1L55Q, FD1L56Q, VC1L26); --VC1_break_readreg[3] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[3] VC1_break_readreg[3] = AMPP_FUNCTION(F1__clk1, VC1L46, D1_CLRN_SIGNAL, VC1L26); --FD1L146 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4794 FD1L146 = AMPP_FUNCTION(ED1_MonDReg[3], FD1_ir[0], FD1_ir[1], VC1_break_readreg[3]); --FD1_sr[5] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[5] FD1_sr[5] = AMPP_FUNCTION(A1L333, FD1L153, D1_CLRN_SIGNAL, FD1L118); --FD1L147 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4795 FD1L147 = AMPP_FUNCTION(FD1L146, FD1_sr[5], FD1L7); --VC1L44 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2171 VC1L44 = AMPP_FUNCTION(FD1L43Q, FD1L55Q, FD1L56Q, VC1L26); --FD1_sr[27] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[27] FD1_sr[27] = AMPP_FUNCTION(A1L333, FD1L155, D1_CLRN_SIGNAL, FD1L81); --FD1L148 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4796 FD1L148 = AMPP_FUNCTION(FD1L77, FD1_sr[27], FD1L78, ED1_MonDReg[25]); --VC1_break_readreg[25] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[25] VC1_break_readreg[25] = AMPP_FUNCTION(F1__clk1, VC1L47, D1_CLRN_SIGNAL, VC1L26); --FD1L149 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4797 FD1L149 = AMPP_FUNCTION(FD1L75, FD1L76, FD1L148, VC1_break_readreg[25]); --L1L27 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~26 L1L27 = AMPP_FUNCTION(L1_state[12], L1_state[13]); --VD1_td_shift[5] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[5] VD1_td_shift[5] = AMPP_FUNCTION(A1L333, VD1L71, G4_Q[0], D1_CLRN_SIGNAL, VD1L66, !L1_state[4], VD1L57); --VD1_rdata[2] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[2] VD1_rdata[2] = AMPP_FUNCTION(F1__clk1, FE1_q_b[2], N1_data_out, VD1L28); --VD1L86 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1340 VD1L86 = AMPP_FUNCTION(VD1L69, VD1_td_shift[5], VD1_rdata[2], VD1_count[9]); --FE1_q_b[1] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2|q_b[1] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1 --Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered FE1_q_b[1]_PORT_A_data_in = Z1_d_writedata[1]; FE1_q_b[1]_PORT_A_data_in_reg = DFFE(FE1_q_b[1]_PORT_A_data_in, FE1_q_b[1]_clock_0, , , FE1_q_b[1]_clock_enable_0); FE1_q_b[1]_PORT_A_address = BUS(DE2_safe_q[0], DE2_safe_q[1], DE2_safe_q[2], DE2_safe_q[3], DE2_safe_q[4], DE2_safe_q[5]); FE1_q_b[1]_PORT_A_address_reg = DFFE(FE1_q_b[1]_PORT_A_address, FE1_q_b[1]_clock_0, , , FE1_q_b[1]_clock_enable_0); FE1_q_b[1]_PORT_B_address = BUS(DE1_safe_q[0], DE1_safe_q[1], DE1_safe_q[2], DE1_safe_q[3], DE1_safe_q[4], DE1_safe_q[5]); FE1_q_b[1]_PORT_B_address_reg = DFFE(FE1_q_b[1]_PORT_B_address, FE1_q_b[1]_clock_1, , , FE1_q_b[1]_clock_enable_1); FE1_q_b[1]_PORT_A_write_enable = VCC; FE1_q_b[1]_PORT_A_write_enable_reg = DFFE(FE1_q_b[1]_PORT_A_write_enable, FE1_q_b[1]_clock_0, , , FE1_q_b[1]_clock_enable_0); FE1_q_b[1]_PORT_B_read_enable = VCC; FE1_q_b[1]_PORT_B_read_enable_reg = DFFE(FE1_q_b[1]_PORT_B_read_enable, FE1_q_b[1]_clock_1, , , FE1_q_b[1]_clock_enable_1); FE1_q_b[1]_clock_0 = F1__clk1; FE1_q_b[1]_clock_1 = F1__clk1; FE1_q_b[1]_clock_enable_0 = FB1_fifo_wr; FE1_q_b[1]_clock_enable_1 = FB1_rd_wfifo; FE1_q_b[1]_PORT_B_data_out = MEMORY(FE1_q_b[1]_PORT_A_data_in_reg, , FE1_q_b[1]_PORT_A_address_reg, FE1_q_b[1]_PORT_B_address_reg, FE1_q_b[1]_PORT_A_write_enable_reg, FE1_q_b[1]_PORT_B_read_enable_reg, , , FE1_q_b[1]_clock_0, FE1_q_b[1]_clock_1, FE1_q_b[1]_clock_enable_0, FE1_q_b[1]_clock_enable_1, , ); FE1_q_b[1] = FE1_q_b[1]_PORT_B_data_out[0]; --VD1L96 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[1]~6 VD1L96 = AMPP_FUNCTION(VD1L90, VD1_count[8]); --VD1_count[5] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[5] VD1_count[5] = AMPP_FUNCTION(A1L333, VD1L19, D1_CLRN_SIGNAL, VD1L57); --VD1L18 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count~219 VD1L18 = AMPP_FUNCTION(L1_state[4], VD1_count[5]); --DE2_counter_comb_bita0 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita0 DE2_counter_comb_bita0 = DE2_safe_q[0] $ VCC; --DE2L2 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita0~COUT DE2L2 = CARRY(DE2_safe_q[0]); --DE2_counter_comb_bita1 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita1 DE2_counter_comb_bita1 = DE2_safe_q[1] & !DE2L2 # !DE2_safe_q[1] & (DE2L2 # GND); --DE2L4 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita1~COUT DE2L4 = CARRY(!DE2L2 # !DE2_safe_q[1]); --DE2_counter_comb_bita2 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita2 DE2_counter_comb_bita2 = DE2_safe_q[2] & (DE2L4 $ GND) # !DE2_safe_q[2] & !DE2L4 & VCC; --DE2L6 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita2~COUT DE2L6 = CARRY(DE2_safe_q[2] & !DE2L4); --DE2_counter_comb_bita3 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita3 DE2_counter_comb_bita3 = DE2_safe_q[3] & !DE2L6 # !DE2_safe_q[3] & (DE2L6 # GND); --DE2L8 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita3~COUT DE2L8 = CARRY(!DE2L6 # !DE2_safe_q[3]); --DE2_counter_comb_bita4 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita4 DE2_counter_comb_bita4 = DE2_safe_q[4] & (DE2L8 $ GND) # !DE2_safe_q[4] & !DE2L8 & VCC; --DE2L10 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita4~COUT DE2L10 = CARRY(DE2_safe_q[4] & !DE2L8); --DE2_counter_comb_bita5 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita5 DE2_counter_comb_bita5 = DE2_safe_q[5] $ DE2L10; --DE1_counter_comb_bita0 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita0 DE1_counter_comb_bita0 = DE1_safe_q[0] $ VCC; --DE1L2 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita0~COUT DE1L2 = CARRY(DE1_safe_q[0]); --DE1_counter_comb_bita1 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita1 DE1_counter_comb_bita1 = DE1_safe_q[1] & !DE1L2 # !DE1_safe_q[1] & (DE1L2 # GND); --DE1L4 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita1~COUT DE1L4 = CARRY(!DE1L2 # !DE1_safe_q[1]); --DE1_counter_comb_bita2 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita2 DE1_counter_comb_bita2 = DE1_safe_q[2] & (DE1L4 $ GND) # !DE1_safe_q[2] & !DE1L4 & VCC; --DE1L6 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita2~COUT DE1L6 = CARRY(DE1_safe_q[2] & !DE1L4); --DE1_counter_comb_bita3 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita3 DE1_counter_comb_bita3 = DE1_safe_q[3] & !DE1L6 # !DE1_safe_q[3] & (DE1L6 # GND); --DE1L8 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita3~COUT DE1L8 = CARRY(!DE1L6 # !DE1_safe_q[3]); --DE1_counter_comb_bita4 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita4 DE1_counter_comb_bita4 = DE1_safe_q[4] & (DE1L8 $ GND) # !DE1_safe_q[4] & !DE1L8 & VCC; --DE1L10 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita4~COUT DE1L10 = CARRY(DE1_safe_q[4] & !DE1L8); --DE1_counter_comb_bita5 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita5 DE1_counter_comb_bita5 = DE1_safe_q[5] $ DE1L10; --FD1_sr[28] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[28] FD1_sr[28] = AMPP_FUNCTION(A1L333, FD1L157, D1_CLRN_SIGNAL, FD1L81); --FD1_sr[29] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[29] FD1_sr[29] = AMPP_FUNCTION(A1L333, FD1L159, D1_CLRN_SIGNAL, FD1L81); --FD1_sr[30] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[30] FD1_sr[30] = AMPP_FUNCTION(A1L333, FD1L161, D1_CLRN_SIGNAL, FD1L81); --FD1_sr[31] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[31] FD1_sr[31] = AMPP_FUNCTION(A1L333, FD1L112, D1_CLRN_SIGNAL, FD1L110); --FD1_sr[32] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[32] FD1_sr[32] = AMPP_FUNCTION(A1L333, FD1L163, D1_CLRN_SIGNAL, FD1L81); --FD1_sr[33] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[33] FD1_sr[33] = AMPP_FUNCTION(A1L333, FD1L164, D1_CLRN_SIGNAL, FD1L81); --DE4_counter_comb_bita0 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita0 DE4_counter_comb_bita0 = DE4_safe_q[0] $ VCC; --DE4L2 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita0~COUT DE4L2 = CARRY(DE4_safe_q[0]); --DE4_counter_comb_bita1 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita1 DE4_counter_comb_bita1 = DE4_safe_q[1] & !DE4L2 # !DE4_safe_q[1] & (DE4L2 # GND); --DE4L4 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita1~COUT DE4L4 = CARRY(!DE4L2 # !DE4_safe_q[1]); --DE4_counter_comb_bita2 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita2 DE4_counter_comb_bita2 = DE4_safe_q[2] & (DE4L4 $ GND) # !DE4_safe_q[2] & !DE4L4 & VCC; --DE4L6 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita2~COUT DE4L6 = CARRY(DE4_safe_q[2] & !DE4L4); --DE4_counter_comb_bita3 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita3 DE4_counter_comb_bita3 = DE4_safe_q[3] & !DE4L6 # !DE4_safe_q[3] & (DE4L6 # GND); --DE4L8 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita3~COUT DE4L8 = CARRY(!DE4L6 # !DE4_safe_q[3]); --DE4_counter_comb_bita4 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita4 DE4_counter_comb_bita4 = DE4_safe_q[4] & (DE4L8 $ GND) # !DE4_safe_q[4] & !DE4L8 & VCC; --DE4L10 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita4~COUT DE4L10 = CARRY(DE4_safe_q[4] & !DE4L8); --DE4_counter_comb_bita5 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr|counter_comb_bita5 DE4_counter_comb_bita5 = DE4_safe_q[5] $ DE4L10; --DE3_counter_comb_bita0 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita0 DE3_counter_comb_bita0 = DE3_safe_q[0] $ VCC; --DE3L2 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita0~COUT DE3L2 = CARRY(DE3_safe_q[0]); --DE3_counter_comb_bita1 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita1 DE3_counter_comb_bita1 = DE3_safe_q[1] & !DE3L2 # !DE3_safe_q[1] & (DE3L2 # GND); --DE3L4 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita1~COUT DE3L4 = CARRY(!DE3L2 # !DE3_safe_q[1]); --DE3_counter_comb_bita2 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita2 DE3_counter_comb_bita2 = DE3_safe_q[2] & (DE3L4 $ GND) # !DE3_safe_q[2] & !DE3L4 & VCC; --DE3L6 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita2~COUT DE3L6 = CARRY(DE3_safe_q[2] & !DE3L4); --DE3_counter_comb_bita3 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita3 DE3_counter_comb_bita3 = DE3_safe_q[3] & !DE3L6 # !DE3_safe_q[3] & (DE3L6 # GND); --DE3L8 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita3~COUT DE3L8 = CARRY(!DE3L6 # !DE3_safe_q[3]); --DE3_counter_comb_bita4 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita4 DE3_counter_comb_bita4 = DE3_safe_q[4] & (DE3L8 $ GND) # !DE3_safe_q[4] & !DE3L8 & VCC; --DE3L10 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita4~COUT DE3L10 = CARRY(DE3_safe_q[4] & !DE3L8); --DE3_counter_comb_bita5 is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count|counter_comb_bita5 DE3_counter_comb_bita5 = DE3_safe_q[5] $ DE3L10; --SD1_MISO_reg is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|MISO_reg SD1_MISO_reg = DFFEAS(SD1L24, F1__clk1, N1_data_out, , , , , , ); --SD1_tx_holding_reg[0] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[0] SD1_tx_holding_reg[0] = DFFEAS(Z1_d_writedata[0], F1__clk1, N1_data_out, , SD1_write_tx_holding, , , , ); --SD1_SCLK_reg is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|SCLK_reg SD1_SCLK_reg = DFFEAS(SD1L34, F1__clk1, N1_data_out, , , , , , ); --SD1L201 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~1225 SD1L201 = SD1L210 & (SD1_SCLK_reg & SD1_MISO_reg # !SD1_SCLK_reg & (SD1_tx_holding_reg[0])) # !SD1L210 & (SD1_tx_holding_reg[0]); --SD1_slaveselect_wr_strobe is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|slaveselect_wr_strobe SD1_slaveselect_wr_strobe = EB1L9 & EB1L11 & SD1_wr_strobe & !EB1L10; --VC1L45 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2172 VC1L45 = AMPP_FUNCTION(FD1L42Q, FD1L55Q, FD1L56Q, VC1L26); --SD1_tx_holding_reg[1] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[1] SD1_tx_holding_reg[1] = DFFEAS(Z1_d_writedata[1], F1__clk1, N1_data_out, , SD1_write_tx_holding, , , , ); --SD1L202 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~1226 SD1L202 = SD1L210 & (SD1_SCLK_reg & SD1_shift_reg[0] # !SD1_SCLK_reg & (SD1_tx_holding_reg[1])) # !SD1L210 & (SD1_tx_holding_reg[1]); --VD1_td_shift[6] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[6] VD1_td_shift[6] = AMPP_FUNCTION(A1L333, VD1L74, G4_Q[0], D1_CLRN_SIGNAL, VD1L66, !L1_state[4], VD1L57); --SD1_tx_holding_reg[2] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[2] SD1_tx_holding_reg[2] = DFFEAS(Z1_d_writedata[2], F1__clk1, N1_data_out, , SD1_write_tx_holding, , , , ); --SD1L203 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~1227 SD1L203 = SD1L210 & (SD1_SCLK_reg & SD1_shift_reg[1] # !SD1_SCLK_reg & (SD1_tx_holding_reg[2])) # !SD1L210 & (SD1_tx_holding_reg[2]); --FD1_sr[6] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[6] FD1_sr[6] = AMPP_FUNCTION(A1L333, FD1L166, D1_CLRN_SIGNAL, FD1L118); --VD1_td_shift[7] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[7] VD1_td_shift[7] = AMPP_FUNCTION(A1L333, VD1L87, D1_CLRN_SIGNAL, VD1L57); --SD1_tx_holding_reg[3] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[3] SD1_tx_holding_reg[3] = DFFEAS(Z1_d_writedata[3], F1__clk1, N1_data_out, , SD1_write_tx_holding, , , , ); --SD1L204 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~1228 SD1L204 = SD1L210 & (SD1_SCLK_reg & SD1_shift_reg[2] # !SD1_SCLK_reg & (SD1_tx_holding_reg[3])) # !SD1L210 & (SD1_tx_holding_reg[3]); --VD1_td_shift[8] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[8] VD1_td_shift[8] = AMPP_FUNCTION(A1L333, VD1L88, D1_CLRN_SIGNAL, !L1_state[4], VD1L57); --SD1_tx_holding_reg[4] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[4] SD1_tx_holding_reg[4] = DFFEAS(Z1_d_writedata[4], F1__clk1, N1_data_out, , SD1_write_tx_holding, , , , ); --SD1L205 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~1229 SD1L205 = SD1L210 & (SD1_SCLK_reg & SD1_shift_reg[3] # !SD1_SCLK_reg & (SD1_tx_holding_reg[4])) # !SD1L210 & (SD1_tx_holding_reg[4]); --FD1_sr[7] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[7] FD1_sr[7] = AMPP_FUNCTION(A1L333, FD1L113, D1_CLRN_SIGNAL, FD1L118); --SD1_tx_holding_reg[5] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[5] SD1_tx_holding_reg[5] = DFFEAS(Z1_d_writedata[5], F1__clk1, N1_data_out, , SD1_write_tx_holding, , , , ); --SD1L206 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~1230 SD1L206 = SD1L210 & (SD1_SCLK_reg & SD1_shift_reg[4] # !SD1_SCLK_reg & (SD1_tx_holding_reg[5])) # !SD1L210 & (SD1_tx_holding_reg[5]); --FD1_sr[8] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[8] FD1_sr[8] = AMPP_FUNCTION(A1L333, FD1L168, D1_CLRN_SIGNAL, FD1L118); --SD1_tx_holding_reg[6] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[6] SD1_tx_holding_reg[6] = DFFEAS(Z1_d_writedata[6], F1__clk1, N1_data_out, , SD1_write_tx_holding, , , , ); --SD1L207 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~1231 SD1L207 = SD1L210 & (SD1_SCLK_reg & SD1_shift_reg[5] # !SD1_SCLK_reg & (SD1_tx_holding_reg[6])) # !SD1L210 & (SD1_tx_holding_reg[6]); --FD1_sr[9] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[9] FD1_sr[9] = AMPP_FUNCTION(A1L333, FD1L171, D1_CLRN_SIGNAL, FD1L118); --SD1_tx_holding_reg[7] is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[7] SD1_tx_holding_reg[7] = DFFEAS(Z1_d_writedata[7], F1__clk1, N1_data_out, , SD1_write_tx_holding, , , , ); --SD1L208 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~1232 SD1L208 = SD1L210 & (SD1_SCLK_reg & SD1_shift_reg[6] # !SD1_SCLK_reg & (SD1_tx_holding_reg[7])) # !SD1L210 & (SD1_tx_holding_reg[7]); --FD1_sr[10] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[10] FD1_sr[10] = AMPP_FUNCTION(A1L333, FD1L174, D1_CLRN_SIGNAL, FD1L118); --FD1_sr[11] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[11] FD1_sr[11] = AMPP_FUNCTION(A1L333, FD1L177, D1_CLRN_SIGNAL, FD1L118); --FD1_sr[12] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[12] FD1_sr[12] = AMPP_FUNCTION(A1L333, FD1L180, D1_CLRN_SIGNAL, FD1L118); --FD1_sr[13] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[13] FD1_sr[13] = AMPP_FUNCTION(A1L333, FD1L183, D1_CLRN_SIGNAL, FD1L118); --FD1_sr[14] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[14] FD1_sr[14] = AMPP_FUNCTION(A1L333, FD1L186, D1_CLRN_SIGNAL, FD1L118); --FD1_sr[15] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[15] FD1_sr[15] = AMPP_FUNCTION(A1L333, FD1L116, D1_CLRN_SIGNAL, FD1L118); --FD1_sr[16] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[16] FD1_sr[16] = AMPP_FUNCTION(A1L333, FD1L188, D1_CLRN_SIGNAL, FD1L81); --HE1L13 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|always0~1 HE1L13 = HB1_za_valid # JB1L5 & !JE1_full_6; --HE1L39 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|p6_full_6~23 HE1L39 = JE1_full_5 & (JB1L5 # !HB1_za_valid); --ME1_delayed_unxsync_rxdxx1 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|delayed_unxsync_rxdxx1 ME1_delayed_unxsync_rxdxx1 = DFFEAS(ME1_sync_rxd, F1__clk1, N1_data_out, , , , , , ); --ME1L21 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|always5~21 ME1L21 = ME1_delayed_unxsync_rxdxx1 & !ME1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] & !ME1_sync_rxd; --ME1_d1_source_rxd is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|d1_source_rxd ME1_d1_source_rxd = DFFEAS(UART_RXD, F1__clk1, N1_data_out, , , , , , ); --ME1_baud_rate_counter[9] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter[9] ME1_baud_rate_counter[9] = DFFEAS(ME1L38, F1__clk1, N1_data_out, , , , , , ); --ME1_baud_rate_counter[8] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter[8] ME1_baud_rate_counter[8] = DFFEAS(ME1L39, F1__clk1, N1_data_out, , , , , , ); --ME1_baud_rate_counter[7] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter[7] ME1_baud_rate_counter[7] = DFFEAS(ME1L40, F1__clk1, N1_data_out, , , , , , ); --ME1_baud_rate_counter[6] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter[6] ME1_baud_rate_counter[6] = DFFEAS(ME1L41, F1__clk1, N1_data_out, , , , , , ); --ME1L35 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter_is_zero~139 ME1L35 = !ME1_baud_rate_counter[9] & !ME1_baud_rate_counter[8] & !ME1_baud_rate_counter[7] & !ME1_baud_rate_counter[6]; --ME1_baud_rate_counter[5] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter[5] ME1_baud_rate_counter[5] = DFFEAS(ME1L42, F1__clk1, N1_data_out, , , , , , ); --ME1_baud_rate_counter[4] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter[4] ME1_baud_rate_counter[4] = DFFEAS(ME1L43, F1__clk1, N1_data_out, , , , , , ); --ME1_baud_rate_counter[3] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter[3] ME1_baud_rate_counter[3] = DFFEAS(ME1L44, F1__clk1, N1_data_out, , , , , , ); --ME1_baud_rate_counter[2] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter[2] ME1_baud_rate_counter[2] = DFFEAS(ME1L45, F1__clk1, N1_data_out, , , , , , ); --ME1L36 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter_is_zero~140 ME1L36 = !ME1_baud_rate_counter[5] & !ME1_baud_rate_counter[4] & !ME1_baud_rate_counter[3] & !ME1_baud_rate_counter[2]; --ME1_baud_rate_counter[1] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter[1] ME1_baud_rate_counter[1] = DFFEAS(ME1L46, F1__clk1, N1_data_out, , , , , , ); --ME1_baud_rate_counter[0] is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter[0] ME1_baud_rate_counter[0] = DFFEAS(ME1L47, F1__clk1, N1_data_out, , , , , , ); --ME1L37 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter_is_zero~141 ME1L37 = ME1L35 & ME1L36 & !ME1_baud_rate_counter[1] & !ME1_baud_rate_counter[0]; --ME1L23 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_clk_en~30 ME1L23 = ME1L37 & (ME1_sync_rxd $ !ME1_delayed_unxsync_rxdxx1); --VD1L26 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~41 VD1L26 = AMPP_FUNCTION(VD1_jupdate, G4_Q[0], L1_state[8], VD1L1); --Z1L2152 is system_0:u0|cpu_0:the_cpu_0|M_bht_wr_data~5 Z1L2152 = AMPP_FUNCTION(Z1_M_valid_from_E, Z1_M_br_mispredict); --Z1_M_src1[16] is system_0:u0|cpu_0:the_cpu_0|M_src1[16] Z1_M_src1[16] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[16], N1_data_out, Z1_A_stall); --Z1L435 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[16]~304 Z1L435 = AMPP_FUNCTION(Z1_A_mul_src1[0], Z1_M_src1[16], Z1_A_mul_stall); --Z1_M_src1[17] is system_0:u0|cpu_0:the_cpu_0|M_src1[17] Z1_M_src1[17] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[17], N1_data_out, Z1_A_stall); --Z1L436 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[17]~305 Z1L436 = AMPP_FUNCTION(Z1_A_mul_src1[1], Z1_M_src1[17], Z1_A_mul_stall); --Z1_M_src1[18] is system_0:u0|cpu_0:the_cpu_0|M_src1[18] Z1_M_src1[18] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[18], N1_data_out, Z1_A_stall); --Z1L437 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[18]~306 Z1L437 = AMPP_FUNCTION(Z1_A_mul_src1[2], Z1_M_src1[18], Z1_A_mul_stall); --Z1_M_src1[19] is system_0:u0|cpu_0:the_cpu_0|M_src1[19] Z1_M_src1[19] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[19], N1_data_out, Z1_A_stall); --Z1L438 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[19]~307 Z1L438 = AMPP_FUNCTION(Z1_A_mul_src1[3], Z1_M_src1[19], Z1_A_mul_stall); --Z1_M_src1[20] is system_0:u0|cpu_0:the_cpu_0|M_src1[20] Z1_M_src1[20] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[20], N1_data_out, Z1_A_stall); --Z1L439 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[20]~308 Z1L439 = AMPP_FUNCTION(Z1_A_mul_src1[4], Z1_M_src1[20], Z1_A_mul_stall); --Z1_M_src1[21] is system_0:u0|cpu_0:the_cpu_0|M_src1[21] Z1_M_src1[21] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[21], N1_data_out, Z1_A_stall); --Z1L440 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[21]~309 Z1L440 = AMPP_FUNCTION(Z1_A_mul_src1[5], Z1_M_src1[21], Z1_A_mul_stall); --Z1_M_src1[22] is system_0:u0|cpu_0:the_cpu_0|M_src1[22] Z1_M_src1[22] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[22], N1_data_out, Z1_A_stall); --Z1L441 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[22]~310 Z1L441 = AMPP_FUNCTION(Z1_A_mul_src1[6], Z1_M_src1[22], Z1_A_mul_stall); --Z1_M_src1[23] is system_0:u0|cpu_0:the_cpu_0|M_src1[23] Z1_M_src1[23] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[23], N1_data_out, Z1_A_stall); --Z1L442 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[23]~311 Z1L442 = AMPP_FUNCTION(Z1_A_mul_src1[7], Z1_M_src1[23], Z1_A_mul_stall); --Z1_M_src1[24] is system_0:u0|cpu_0:the_cpu_0|M_src1[24] Z1_M_src1[24] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[24], N1_data_out, Z1_A_stall); --Z1L443 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[24]~312 Z1L443 = AMPP_FUNCTION(Z1_A_mul_src1[8], Z1_M_src1[24], Z1_A_mul_stall); --Z1_M_src1[25] is system_0:u0|cpu_0:the_cpu_0|M_src1[25] Z1_M_src1[25] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[25], N1_data_out, Z1_A_stall); --Z1L444 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[25]~313 Z1L444 = AMPP_FUNCTION(Z1_A_mul_src1[9], Z1_M_src1[25], Z1_A_mul_stall); --Z1_M_src1[26] is system_0:u0|cpu_0:the_cpu_0|M_src1[26] Z1_M_src1[26] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[26], N1_data_out, Z1_A_stall); --Z1L445 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[26]~314 Z1L445 = AMPP_FUNCTION(Z1_A_mul_src1[10], Z1_M_src1[26], Z1_A_mul_stall); --Z1_M_src1[27] is system_0:u0|cpu_0:the_cpu_0|M_src1[27] Z1_M_src1[27] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[27], N1_data_out, Z1_A_stall); --Z1L446 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[27]~315 Z1L446 = AMPP_FUNCTION(Z1_A_mul_src1[11], Z1_M_src1[27], Z1_A_mul_stall); --Z1_M_src1[28] is system_0:u0|cpu_0:the_cpu_0|M_src1[28] Z1_M_src1[28] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[28], N1_data_out, Z1_A_stall); --Z1L447 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[28]~316 Z1L447 = AMPP_FUNCTION(Z1_A_mul_src1[12], Z1_M_src1[28], Z1_A_mul_stall); --Z1_M_src1[29] is system_0:u0|cpu_0:the_cpu_0|M_src1[29] Z1_M_src1[29] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[29], N1_data_out, Z1_A_stall); --Z1L448 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[29]~317 Z1L448 = AMPP_FUNCTION(Z1_A_mul_src1[13], Z1_M_src1[29], Z1_A_mul_stall); --Z1_M_src1[30] is system_0:u0|cpu_0:the_cpu_0|M_src1[30] Z1_M_src1[30] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[30], N1_data_out, Z1_A_stall); --Z1L449 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[30]~318 Z1L449 = AMPP_FUNCTION(Z1_A_mul_src1[14], Z1_M_src1[30], Z1_A_mul_stall); --Z1_M_src1[31] is system_0:u0|cpu_0:the_cpu_0|M_src1[31] Z1_M_src1[31] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[31], N1_data_out, Z1_A_stall); --Z1L450 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[31]~319 Z1L450 = AMPP_FUNCTION(Z1_A_mul_src1[15], Z1_M_src1[31], Z1_A_mul_stall); --Z1_A_mul_src2[16] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[16] Z1_A_mul_src2[16] = AMPP_FUNCTION(F1__clk1, Z1L500, N1_data_out); --Z1_M_src2[0] is system_0:u0|cpu_0:the_cpu_0|M_src2[0] Z1_M_src2[0] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[0], N1_data_out, Z1_A_stall); --Z1L484 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[0]~304 Z1L484 = AMPP_FUNCTION(Z1_A_mul_src2[16], Z1_M_src2[0], Z1_A_mul_stall); --Z1_A_mul_src2[17] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[17] Z1_A_mul_src2[17] = AMPP_FUNCTION(F1__clk1, Z1L501, N1_data_out); --Z1_M_src2[1] is system_0:u0|cpu_0:the_cpu_0|M_src2[1] Z1_M_src2[1] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[1], N1_data_out, Z1_A_stall); --Z1L485 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[1]~305 Z1L485 = AMPP_FUNCTION(Z1_A_mul_src2[17], Z1_M_src2[1], Z1_A_mul_stall); --Z1_A_mul_src2[18] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[18] Z1_A_mul_src2[18] = AMPP_FUNCTION(F1__clk1, Z1L502, N1_data_out); --Z1_M_src2[2] is system_0:u0|cpu_0:the_cpu_0|M_src2[2] Z1_M_src2[2] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[2], N1_data_out, Z1_A_stall); --Z1L486 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[2]~306 Z1L486 = AMPP_FUNCTION(Z1_A_mul_src2[18], Z1_M_src2[2], Z1_A_mul_stall); --Z1_A_mul_src2[19] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[19] Z1_A_mul_src2[19] = AMPP_FUNCTION(F1__clk1, Z1L503, N1_data_out); --Z1_M_src2[3] is system_0:u0|cpu_0:the_cpu_0|M_src2[3] Z1_M_src2[3] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[3], N1_data_out, Z1_A_stall); --Z1L487 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[3]~307 Z1L487 = AMPP_FUNCTION(Z1_A_mul_src2[19], Z1_M_src2[3], Z1_A_mul_stall); --Z1_A_mul_src2[20] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[20] Z1_A_mul_src2[20] = AMPP_FUNCTION(F1__clk1, Z1L504, N1_data_out); --Z1_M_src2[4] is system_0:u0|cpu_0:the_cpu_0|M_src2[4] Z1_M_src2[4] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[4], N1_data_out, Z1_A_stall); --Z1L488 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[4]~308 Z1L488 = AMPP_FUNCTION(Z1_A_mul_src2[20], Z1_M_src2[4], Z1_A_mul_stall); --Z1_A_mul_src2[21] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[21] Z1_A_mul_src2[21] = AMPP_FUNCTION(F1__clk1, Z1L505, N1_data_out); --Z1_M_src2[5] is system_0:u0|cpu_0:the_cpu_0|M_src2[5] Z1_M_src2[5] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[5], N1_data_out, Z1_A_stall); --Z1L489 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[5]~309 Z1L489 = AMPP_FUNCTION(Z1_A_mul_src2[21], Z1_M_src2[5], Z1_A_mul_stall); --Z1_A_mul_src2[22] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[22] Z1_A_mul_src2[22] = AMPP_FUNCTION(F1__clk1, Z1L506, N1_data_out); --Z1_M_src2[6] is system_0:u0|cpu_0:the_cpu_0|M_src2[6] Z1_M_src2[6] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[6], N1_data_out, Z1_A_stall); --Z1L490 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[6]~310 Z1L490 = AMPP_FUNCTION(Z1_A_mul_src2[22], Z1_M_src2[6], Z1_A_mul_stall); --Z1_A_mul_src2[23] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[23] Z1_A_mul_src2[23] = AMPP_FUNCTION(F1__clk1, Z1L507, N1_data_out); --Z1_M_src2[7] is system_0:u0|cpu_0:the_cpu_0|M_src2[7] Z1_M_src2[7] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[7], N1_data_out, Z1_A_stall); --Z1L491 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[7]~311 Z1L491 = AMPP_FUNCTION(Z1_A_mul_src2[23], Z1_M_src2[7], Z1_A_mul_stall); --Z1_A_mul_src2[24] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[24] Z1_A_mul_src2[24] = AMPP_FUNCTION(F1__clk1, Z1L508, N1_data_out); --Z1_M_src2[8] is system_0:u0|cpu_0:the_cpu_0|M_src2[8] Z1_M_src2[8] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[8], N1_data_out, Z1_A_stall); --Z1L492 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[8]~312 Z1L492 = AMPP_FUNCTION(Z1_A_mul_src2[24], Z1_M_src2[8], Z1_A_mul_stall); --Z1_A_mul_src2[25] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[25] Z1_A_mul_src2[25] = AMPP_FUNCTION(F1__clk1, Z1L509, N1_data_out); --Z1_M_src2[9] is system_0:u0|cpu_0:the_cpu_0|M_src2[9] Z1_M_src2[9] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[9], N1_data_out, Z1_A_stall); --Z1L493 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[9]~313 Z1L493 = AMPP_FUNCTION(Z1_A_mul_src2[25], Z1_M_src2[9], Z1_A_mul_stall); --Z1_A_mul_src2[26] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[26] Z1_A_mul_src2[26] = AMPP_FUNCTION(F1__clk1, Z1L510, N1_data_out); --Z1_M_src2[10] is system_0:u0|cpu_0:the_cpu_0|M_src2[10] Z1_M_src2[10] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[10], N1_data_out, Z1_A_stall); --Z1L494 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[10]~314 Z1L494 = AMPP_FUNCTION(Z1_A_mul_src2[26], Z1_M_src2[10], Z1_A_mul_stall); --Z1_A_mul_src2[27] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[27] Z1_A_mul_src2[27] = AMPP_FUNCTION(F1__clk1, Z1L511, N1_data_out); --Z1_M_src2[11] is system_0:u0|cpu_0:the_cpu_0|M_src2[11] Z1_M_src2[11] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[11], N1_data_out, Z1_A_stall); --Z1L495 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[11]~315 Z1L495 = AMPP_FUNCTION(Z1_A_mul_src2[27], Z1_M_src2[11], Z1_A_mul_stall); --Z1_A_mul_src2[28] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[28] Z1_A_mul_src2[28] = AMPP_FUNCTION(F1__clk1, Z1L512, N1_data_out); --Z1_M_src2[12] is system_0:u0|cpu_0:the_cpu_0|M_src2[12] Z1_M_src2[12] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[12], N1_data_out, Z1_A_stall); --Z1L496 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[12]~316 Z1L496 = AMPP_FUNCTION(Z1_A_mul_src2[28], Z1_M_src2[12], Z1_A_mul_stall); --Z1_A_mul_src2[29] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[29] Z1_A_mul_src2[29] = AMPP_FUNCTION(F1__clk1, Z1L513, N1_data_out); --Z1_M_src2[13] is system_0:u0|cpu_0:the_cpu_0|M_src2[13] Z1_M_src2[13] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[13], N1_data_out, Z1_A_stall); --Z1L497 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[13]~317 Z1L497 = AMPP_FUNCTION(Z1_A_mul_src2[29], Z1_M_src2[13], Z1_A_mul_stall); --Z1_A_mul_src2[30] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[30] Z1_A_mul_src2[30] = AMPP_FUNCTION(F1__clk1, Z1L514, N1_data_out); --Z1_M_src2[14] is system_0:u0|cpu_0:the_cpu_0|M_src2[14] Z1_M_src2[14] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[14], N1_data_out, Z1_A_stall); --Z1L498 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[14]~318 Z1L498 = AMPP_FUNCTION(Z1_A_mul_src2[30], Z1_M_src2[14], Z1_A_mul_stall); --Z1_A_mul_src2[31] is system_0:u0|cpu_0:the_cpu_0|A_mul_src2[31] Z1_A_mul_src2[31] = AMPP_FUNCTION(F1__clk1, Z1L515, N1_data_out); --Z1_M_src2[15] is system_0:u0|cpu_0:the_cpu_0|M_src2[15] Z1_M_src2[15] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[15], N1_data_out, Z1_A_stall); --Z1L499 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[15]~319 Z1L499 = AMPP_FUNCTION(Z1_A_mul_src2[31], Z1_M_src2[15], Z1_A_mul_stall); --Z1_M_src1[0] is system_0:u0|cpu_0:the_cpu_0|M_src1[0] Z1_M_src1[0] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[0], N1_data_out, Z1_A_stall); --Z1L419 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[0]~320 Z1L419 = AMPP_FUNCTION(Z1_M_src1[0], Z1_A_mul_stall); --Z1_M_src1[1] is system_0:u0|cpu_0:the_cpu_0|M_src1[1] Z1_M_src1[1] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[1], N1_data_out, Z1_A_stall); --Z1L420 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[1]~321 Z1L420 = AMPP_FUNCTION(Z1_M_src1[1], Z1_A_mul_stall); --Z1_M_src1[2] is system_0:u0|cpu_0:the_cpu_0|M_src1[2] Z1_M_src1[2] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[2], N1_data_out, Z1_A_stall); --Z1L421 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[2]~322 Z1L421 = AMPP_FUNCTION(Z1_M_src1[2], Z1_A_mul_stall); --Z1_M_src1[3] is system_0:u0|cpu_0:the_cpu_0|M_src1[3] Z1_M_src1[3] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[3], N1_data_out, Z1_A_stall); --Z1L422 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[3]~323 Z1L422 = AMPP_FUNCTION(Z1_M_src1[3], Z1_A_mul_stall); --Z1_M_src1[4] is system_0:u0|cpu_0:the_cpu_0|M_src1[4] Z1_M_src1[4] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[4], N1_data_out, Z1_A_stall); --Z1L423 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[4]~324 Z1L423 = AMPP_FUNCTION(Z1_M_src1[4], Z1_A_mul_stall); --Z1_M_src1[5] is system_0:u0|cpu_0:the_cpu_0|M_src1[5] Z1_M_src1[5] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[5], N1_data_out, Z1_A_stall); --Z1L424 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[5]~325 Z1L424 = AMPP_FUNCTION(Z1_M_src1[5], Z1_A_mul_stall); --Z1_M_src1[6] is system_0:u0|cpu_0:the_cpu_0|M_src1[6] Z1_M_src1[6] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[6], N1_data_out, Z1_A_stall); --Z1L425 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[6]~326 Z1L425 = AMPP_FUNCTION(Z1_M_src1[6], Z1_A_mul_stall); --Z1_M_src1[7] is system_0:u0|cpu_0:the_cpu_0|M_src1[7] Z1_M_src1[7] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[7], N1_data_out, Z1_A_stall); --Z1L426 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[7]~327 Z1L426 = AMPP_FUNCTION(Z1_M_src1[7], Z1_A_mul_stall); --Z1_M_src1[8] is system_0:u0|cpu_0:the_cpu_0|M_src1[8] Z1_M_src1[8] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[8], N1_data_out, Z1_A_stall); --Z1L427 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[8]~328 Z1L427 = AMPP_FUNCTION(Z1_M_src1[8], Z1_A_mul_stall); --Z1_M_src1[9] is system_0:u0|cpu_0:the_cpu_0|M_src1[9] Z1_M_src1[9] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[9], N1_data_out, Z1_A_stall); --Z1L428 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[9]~329 Z1L428 = AMPP_FUNCTION(Z1_M_src1[9], Z1_A_mul_stall); --Z1_M_src1[10] is system_0:u0|cpu_0:the_cpu_0|M_src1[10] Z1_M_src1[10] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[10], N1_data_out, Z1_A_stall); --Z1L429 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[10]~330 Z1L429 = AMPP_FUNCTION(Z1_M_src1[10], Z1_A_mul_stall); --Z1_M_src1[11] is system_0:u0|cpu_0:the_cpu_0|M_src1[11] Z1_M_src1[11] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[11], N1_data_out, Z1_A_stall); --Z1L430 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[11]~331 Z1L430 = AMPP_FUNCTION(Z1_M_src1[11], Z1_A_mul_stall); --Z1_M_src1[12] is system_0:u0|cpu_0:the_cpu_0|M_src1[12] Z1_M_src1[12] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[12], N1_data_out, Z1_A_stall); --Z1L431 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[12]~332 Z1L431 = AMPP_FUNCTION(Z1_M_src1[12], Z1_A_mul_stall); --Z1_M_src1[13] is system_0:u0|cpu_0:the_cpu_0|M_src1[13] Z1_M_src1[13] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[13], N1_data_out, Z1_A_stall); --Z1L432 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[13]~333 Z1L432 = AMPP_FUNCTION(Z1_M_src1[13], Z1_A_mul_stall); --Z1_M_src1[14] is system_0:u0|cpu_0:the_cpu_0|M_src1[14] Z1_M_src1[14] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[14], N1_data_out, Z1_A_stall); --Z1L433 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[14]~334 Z1L433 = AMPP_FUNCTION(Z1_M_src1[14], Z1_A_mul_stall); --Z1_M_src1[15] is system_0:u0|cpu_0:the_cpu_0|M_src1[15] Z1_M_src1[15] = AMPP_FUNCTION(F1__clk1, Z1_E_src1[15], N1_data_out, Z1_A_stall); --Z1L434 is system_0:u0|cpu_0:the_cpu_0|A_mul_src1_nxt[15]~335 Z1L434 = AMPP_FUNCTION(Z1_M_src1[15], Z1_A_mul_stall); --VC1_break_readreg[16] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[16] VC1_break_readreg[16] = AMPP_FUNCTION(F1__clk1, VC1L48, D1_CLRN_SIGNAL, VC1L26); --FD1L150 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4798 FD1L150 = AMPP_FUNCTION(FD1L78, VC1_break_readreg[16], FD1L77, ED1_MonDReg[16]); --FD1L151 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4799 FD1L151 = AMPP_FUNCTION(FD1L7, FD1_ir[0], FD1L150, FD1_sr[18]); --VC1L46 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2173 VC1L46 = AMPP_FUNCTION(FD1L22Q, FD1L55Q, FD1L56Q, VC1L26); --VC1_break_readreg[4] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[4] VC1_break_readreg[4] = AMPP_FUNCTION(F1__clk1, VC1L49, D1_CLRN_SIGNAL, VC1L26); --FD1L152 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4800 FD1L152 = AMPP_FUNCTION(ED1_MonDReg[4], FD1_ir[1], VC1_break_readreg[4], FD1_ir[0]); --FD1L153 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4801 FD1L153 = AMPP_FUNCTION(FD1L152, FD1_sr[6], FD1L7); --VC1_break_readreg[26] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[26] VC1_break_readreg[26] = AMPP_FUNCTION(F1__clk1, VC1L50, D1_CLRN_SIGNAL, VC1L26); --FD1L154 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4802 FD1L154 = AMPP_FUNCTION(FD1L78, VC1_break_readreg[26], FD1L77, ED1_MonDReg[26]); --FD1L155 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4803 FD1L155 = AMPP_FUNCTION(FD1L7, FD1_ir[0], FD1L154, FD1_sr[28]); --VC1L47 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2174 VC1L47 = AMPP_FUNCTION(FD1L44Q, FD1L55Q, FD1L56Q, VC1L26); --VD1_rdata[3] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[3] VD1_rdata[3] = AMPP_FUNCTION(F1__clk1, FE1_q_b[3], N1_data_out, VD1L28); --VD1L71 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[5]~684 VD1L71 = AMPP_FUNCTION(VD1_td_shift[6], VD1_rdata[3], VD1_count[9]); --FE1_q_b[2] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2|q_b[2] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1 --Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered FE1_q_b[2]_PORT_A_data_in = Z1_d_writedata[2]; FE1_q_b[2]_PORT_A_data_in_reg = DFFE(FE1_q_b[2]_PORT_A_data_in, FE1_q_b[2]_clock_0, , , FE1_q_b[2]_clock_enable_0); FE1_q_b[2]_PORT_A_address = BUS(DE2_safe_q[0], DE2_safe_q[1], DE2_safe_q[2], DE2_safe_q[3], DE2_safe_q[4], DE2_safe_q[5]); FE1_q_b[2]_PORT_A_address_reg = DFFE(FE1_q_b[2]_PORT_A_address, FE1_q_b[2]_clock_0, , , FE1_q_b[2]_clock_enable_0); FE1_q_b[2]_PORT_B_address = BUS(DE1_safe_q[0], DE1_safe_q[1], DE1_safe_q[2], DE1_safe_q[3], DE1_safe_q[4], DE1_safe_q[5]); FE1_q_b[2]_PORT_B_address_reg = DFFE(FE1_q_b[2]_PORT_B_address, FE1_q_b[2]_clock_1, , , FE1_q_b[2]_clock_enable_1); FE1_q_b[2]_PORT_A_write_enable = VCC; FE1_q_b[2]_PORT_A_write_enable_reg = DFFE(FE1_q_b[2]_PORT_A_write_enable, FE1_q_b[2]_clock_0, , , FE1_q_b[2]_clock_enable_0); FE1_q_b[2]_PORT_B_read_enable = VCC; FE1_q_b[2]_PORT_B_read_enable_reg = DFFE(FE1_q_b[2]_PORT_B_read_enable, FE1_q_b[2]_clock_1, , , FE1_q_b[2]_clock_enable_1); FE1_q_b[2]_clock_0 = F1__clk1; FE1_q_b[2]_clock_1 = F1__clk1; FE1_q_b[2]_clock_enable_0 = FB1_fifo_wr; FE1_q_b[2]_clock_enable_1 = FB1_rd_wfifo; FE1_q_b[2]_PORT_B_data_out = MEMORY(FE1_q_b[2]_PORT_A_data_in_reg, , FE1_q_b[2]_PORT_A_address_reg, FE1_q_b[2]_PORT_B_address_reg, FE1_q_b[2]_PORT_A_write_enable_reg, FE1_q_b[2]_PORT_B_read_enable_reg, , , FE1_q_b[2]_clock_0, FE1_q_b[2]_clock_1, FE1_q_b[2]_clock_enable_0, FE1_q_b[2]_clock_enable_1, , ); FE1_q_b[2] = FE1_q_b[2]_PORT_B_data_out[0]; --VD1_count[4] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[4] VD1_count[4] = AMPP_FUNCTION(A1L333, VD1L20, D1_CLRN_SIGNAL, VD1L57); --VD1L19 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count~220 VD1L19 = AMPP_FUNCTION(L1_state[4], VD1_count[4]); --FD1L156 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4804 FD1L156 = AMPP_FUNCTION(FD1L77, FD1_sr[29], FD1L78, ED1_MonDReg[27]); --VC1_break_readreg[27] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[27] VC1_break_readreg[27] = AMPP_FUNCTION(F1__clk1, VC1L51, D1_CLRN_SIGNAL, VC1L26); --FD1L157 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4805 FD1L157 = AMPP_FUNCTION(FD1L75, FD1L76, FD1L156, VC1_break_readreg[27]); --VC1_break_readreg[28] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[28] VC1_break_readreg[28] = AMPP_FUNCTION(F1__clk1, VC1L52, D1_CLRN_SIGNAL, VC1L26); --FD1L158 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4806 FD1L158 = AMPP_FUNCTION(FD1L78, VC1_break_readreg[28], FD1L77, ED1_MonDReg[28]); --FD1L159 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4807 FD1L159 = AMPP_FUNCTION(FD1L7, FD1_ir[0], FD1L158, FD1_sr[30]); --FD1L160 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4808 FD1L160 = AMPP_FUNCTION(FD1L77, FD1_sr[31], FD1L78, ED1_MonDReg[29]); --VC1_break_readreg[29] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[29] VC1_break_readreg[29] = AMPP_FUNCTION(F1__clk1, VC1L53, D1_CLRN_SIGNAL, VC1L26); --FD1L161 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4809 FD1L161 = AMPP_FUNCTION(FD1L75, FD1L76, FD1L160, VC1_break_readreg[29]); --VC1_break_readreg[30] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[30] VC1_break_readreg[30] = AMPP_FUNCTION(F1__clk1, VC1L54, D1_CLRN_SIGNAL, VC1L26); --FD1L111 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4810 FD1L111 = AMPP_FUNCTION(VC1_break_readreg[30], ED1_MonDReg[30], FD1_ir[1], FD1L105); --FD1L112 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4811 FD1L112 = AMPP_FUNCTION(FD1L107, FD1_sr[32], FD1L111, FD1_ir[0]); --VC1_break_readreg[31] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[31] VC1_break_readreg[31] = AMPP_FUNCTION(F1__clk1, VC1L55, D1_CLRN_SIGNAL, VC1L26); --FD1L162 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4812 FD1L162 = AMPP_FUNCTION(FD1L78, VC1_break_readreg[31], FD1L77, ED1_MonDReg[31]); --FD1L163 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4813 FD1L163 = AMPP_FUNCTION(FD1L7, FD1_ir[0], FD1L162, FD1_sr[33]); --XC1_resetlatch is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetlatch XC1_resetlatch = AMPP_FUNCTION(F1__clk1, XC1L18); --FD1L164 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4814 FD1L164 = AMPP_FUNCTION(XC1_resetlatch, FD1L78, FD1_sr[34], FD1L77); --TD1_data0out is system_0:u0|epcs_controller:the_epcs_controller|tornado_epcs_controller_atom:the_tornado_epcs_controller_atom|data0out TD1_data0out = ASMIBLOCK(SD1_SCLK_reg, SD1L36, SD1_shift_reg[7], GND).DATA0OUT; --SD1L24 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|MISO_reg~101 SD1L24 = SD1L210 & (SD1_SCLK_reg & SD1_MISO_reg # !SD1_SCLK_reg & (TD1_data0out)) # !SD1L210 & SD1_MISO_reg; --SD1_write_tx_holding is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|write_tx_holding SD1_write_tx_holding = SD1_data_wr_strobe & (!SD1_transmitting # !SD1_tx_holding_primed); --SD1L31 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|SCLK_reg~310 SD1L31 = SD1_state[0] $ SD1_state[4] # !SD1L21; --SD1L32 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|SCLK_reg~311 SD1L32 = SD1_slowcount[1] & !SD1_slowcount[0] & (SD1_transmitting $ SD1_SCLK_reg); --SD1L33 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|SCLK_reg~312 SD1L33 = SD1L21 & !SD1_state[0] & !SD1_state[4] # !SD1L210; --SD1L34 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|SCLK_reg~313 SD1L34 = SD1_SCLK_reg & (SD1L33 # SD1L31 & SD1L32) # !SD1_SCLK_reg & SD1L31 & SD1L32; --VD1_rdata[4] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[4] VD1_rdata[4] = AMPP_FUNCTION(F1__clk1, FE1_q_b[4], N1_data_out, VD1L28); --VD1L74 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[6]~685 VD1L74 = AMPP_FUNCTION(VD1_td_shift[7], VD1_rdata[4], VD1_count[9]); --VC1_break_readreg[5] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[5] VC1_break_readreg[5] = AMPP_FUNCTION(F1__clk1, VC1L56, D1_CLRN_SIGNAL, VC1L26); --FD1L165 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4815 FD1L165 = AMPP_FUNCTION(ED1_MonDReg[5], FD1_ir[0], FD1_ir[1], VC1_break_readreg[5]); --FD1L166 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4816 FD1L166 = AMPP_FUNCTION(FD1L165, FD1_sr[7], FD1L7); --VD1_rdata[5] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[5] VD1_rdata[5] = AMPP_FUNCTION(F1__clk1, FE1_q_b[5], N1_data_out, VD1L28); --VD1L87 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1341 VD1L87 = AMPP_FUNCTION(VD1L69, VD1_td_shift[8], VD1_rdata[5], VD1_count[9]); --VD1_rdata[6] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[6] VD1_rdata[6] = AMPP_FUNCTION(F1__clk1, FE1_q_b[6], N1_data_out, VD1L28); --VD1L88 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1342 VD1L88 = AMPP_FUNCTION(VD1_td_shift[9], VD1_rdata[6], VD1_count[9]); --VC1_break_readreg[6] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[6] VC1_break_readreg[6] = AMPP_FUNCTION(F1__clk1, VC1L57, D1_CLRN_SIGNAL, VC1L26); --FD1L6 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|Select~305 FD1L6 = AMPP_FUNCTION(ED1_MonDReg[6], FD1_ir[0], FD1_ir[1], VC1_break_readreg[6]); --FD1L113 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4817 FD1L113 = AMPP_FUNCTION(FD1_sr[8], FD1L6, A1L332, FD1L104); --VC1_break_readreg[7] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[7] VC1_break_readreg[7] = AMPP_FUNCTION(F1__clk1, VC1L58, D1_CLRN_SIGNAL, VC1L26); --FD1L167 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4818 FD1L167 = AMPP_FUNCTION(ED1_MonDReg[7], FD1_ir[1], VC1_break_readreg[7], FD1_ir[0]); --FD1L168 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4819 FD1L168 = AMPP_FUNCTION(FD1L167, FD1_sr[9], FD1L7); --FD1L169 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4820 FD1L169 = AMPP_FUNCTION(FD1L77, FD1_sr[10], FD1L78, ED1_MonDReg[8]); --VC1_break_readreg[8] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[8] VC1_break_readreg[8] = AMPP_FUNCTION(F1__clk1, VC1L59, D1_CLRN_SIGNAL, VC1L26); --FD1L170 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4821 FD1L170 = AMPP_FUNCTION(FD1L75, FD1L76, FD1L169, VC1_break_readreg[8]); --FD1L171 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4822 FD1L171 = AMPP_FUNCTION(FD1L170, FD1_ir[1], FD1_ir[0], FD1L7); --VC1_break_readreg[9] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[9] VC1_break_readreg[9] = AMPP_FUNCTION(F1__clk1, VC1L60, D1_CLRN_SIGNAL, VC1L26); --FD1L172 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4823 FD1L172 = AMPP_FUNCTION(FD1L78, VC1_break_readreg[9], FD1L77, ED1_MonDReg[9]); --FD1L173 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4824 FD1L173 = AMPP_FUNCTION(FD1L7, FD1_ir[0], FD1L172, FD1_sr[11]); --FD1L174 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4825 FD1L174 = AMPP_FUNCTION(FD1L173, FD1_ir[1], FD1_ir[0], FD1L7); --FD1L175 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4826 FD1L175 = AMPP_FUNCTION(FD1L77, FD1_sr[12], FD1L78, ED1_MonDReg[10]); --VC1_break_readreg[10] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[10] VC1_break_readreg[10] = AMPP_FUNCTION(F1__clk1, VC1L61, D1_CLRN_SIGNAL, VC1L26); --FD1L176 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4827 FD1L176 = AMPP_FUNCTION(FD1L75, FD1L76, FD1L175, VC1_break_readreg[10]); --FD1L177 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4828 FD1L177 = AMPP_FUNCTION(FD1L176, FD1_ir[1], FD1_ir[0], FD1L7); --VC1_break_readreg[11] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[11] VC1_break_readreg[11] = AMPP_FUNCTION(F1__clk1, VC1L62, D1_CLRN_SIGNAL, VC1L26); --FD1L178 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4829 FD1L178 = AMPP_FUNCTION(FD1L78, VC1_break_readreg[11], FD1L77, ED1_MonDReg[11]); --FD1L179 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4830 FD1L179 = AMPP_FUNCTION(FD1L7, FD1_ir[0], FD1L178, FD1_sr[13]); --FD1L180 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4831 FD1L180 = AMPP_FUNCTION(FD1L179, FD1_ir[1], FD1_ir[0], FD1L7); --FD1L181 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4832 FD1L181 = AMPP_FUNCTION(FD1L77, FD1_sr[14], FD1L78, ED1_MonDReg[12]); --VC1_break_readreg[12] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[12] VC1_break_readreg[12] = AMPP_FUNCTION(F1__clk1, VC1L63, D1_CLRN_SIGNAL, VC1L26); --FD1L182 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4833 FD1L182 = AMPP_FUNCTION(FD1L75, FD1L76, FD1L181, VC1_break_readreg[12]); --FD1L183 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4834 FD1L183 = AMPP_FUNCTION(FD1L182, FD1_ir[1], FD1_ir[0], FD1L7); --VC1_break_readreg[13] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[13] VC1_break_readreg[13] = AMPP_FUNCTION(F1__clk1, VC1L64, D1_CLRN_SIGNAL, VC1L26); --FD1L184 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4835 FD1L184 = AMPP_FUNCTION(FD1L78, VC1_break_readreg[13], FD1L77, ED1_MonDReg[13]); --FD1L185 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4836 FD1L185 = AMPP_FUNCTION(FD1L7, FD1_ir[0], FD1L184, FD1_sr[15]); --FD1L186 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4837 FD1L186 = AMPP_FUNCTION(FD1L185, FD1_ir[1], FD1_ir[0], FD1L7); --FD1_DRsize.010 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.010 FD1_DRsize.010 = AMPP_FUNCTION(A1L333, FD1L5, D1_CLRN_SIGNAL, FD1L195); --FD1L114 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4838 FD1L114 = AMPP_FUNCTION(altera_internal_jtag, FD1_sr[16], FD1_DRsize.010); --VC1_break_readreg[14] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[14] VC1_break_readreg[14] = AMPP_FUNCTION(F1__clk1, VC1L65, D1_CLRN_SIGNAL, VC1L26); --FD1L115 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4839 FD1L115 = AMPP_FUNCTION(VC1_break_readreg[14], ED1_MonDReg[14], FD1_ir[1], FD1_ir[0]); --FD1L116 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4840 FD1L116 = AMPP_FUNCTION(FD1L114, FD1L115, A1L332, FD1L104); --FD1L187 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4841 FD1L187 = AMPP_FUNCTION(FD1L77, FD1_sr[17], FD1L78, ED1_MonDReg[15]); --VC1_break_readreg[15] is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[15] VC1_break_readreg[15] = AMPP_FUNCTION(F1__clk1, VC1L66, D1_CLRN_SIGNAL, VC1L26); --FD1L188 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4842 FD1L188 = AMPP_FUNCTION(FD1L75, FD1L76, FD1L187, VC1_break_readreg[15]); --ME1L1 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~180 ME1L1 = ME1_baud_rate_counter[0] $ VCC; --ME1L2 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~181 ME1L2 = CARRY(ME1_baud_rate_counter[0]); --ME1L3 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~182 ME1L3 = ME1_baud_rate_counter[1] & ME1L2 & VCC # !ME1_baud_rate_counter[1] & !ME1L2; --ME1L4 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~183 ME1L4 = CARRY(!ME1_baud_rate_counter[1] & !ME1L2); --ME1L5 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~184 ME1L5 = ME1_baud_rate_counter[2] & (GND # !ME1L4) # !ME1_baud_rate_counter[2] & (ME1L4 $ GND); --ME1L6 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~185 ME1L6 = CARRY(ME1_baud_rate_counter[2] # !ME1L4); --ME1L7 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~186 ME1L7 = ME1_baud_rate_counter[3] & ME1L6 & VCC # !ME1_baud_rate_counter[3] & !ME1L6; --ME1L8 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~187 ME1L8 = CARRY(!ME1_baud_rate_counter[3] & !ME1L6); --ME1L9 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~188 ME1L9 = ME1_baud_rate_counter[4] & (GND # !ME1L8) # !ME1_baud_rate_counter[4] & (ME1L8 $ GND); --ME1L10 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~189 ME1L10 = CARRY(ME1_baud_rate_counter[4] # !ME1L8); --ME1L11 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~190 ME1L11 = ME1_baud_rate_counter[5] & ME1L10 & VCC # !ME1_baud_rate_counter[5] & !ME1L10; --ME1L12 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~191 ME1L12 = CARRY(!ME1_baud_rate_counter[5] & !ME1L10); --ME1L13 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~192 ME1L13 = ME1_baud_rate_counter[6] & (GND # !ME1L12) # !ME1_baud_rate_counter[6] & (ME1L12 $ GND); --ME1L14 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~193 ME1L14 = CARRY(ME1_baud_rate_counter[6] # !ME1L12); --ME1L15 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~194 ME1L15 = ME1_baud_rate_counter[7] & ME1L14 & VCC # !ME1_baud_rate_counter[7] & !ME1L14; --ME1L16 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~195 ME1L16 = CARRY(!ME1_baud_rate_counter[7] & !ME1L14); --ME1L17 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~196 ME1L17 = ME1_baud_rate_counter[8] & (GND # !ME1L16) # !ME1_baud_rate_counter[8] & (ME1L16 $ GND); --ME1L18 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~197 ME1L18 = CARRY(ME1_baud_rate_counter[8] # !ME1L16); --ME1L19 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|add~198 ME1L19 = ME1_baud_rate_counter[9] $ !ME1L18; --ME1L38 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter~603 ME1L38 = ME1L19 & (ME1_sync_rxd $ !ME1_delayed_unxsync_rxdxx1) # !ME1L19 & ME1L37 & (ME1_sync_rxd $ !ME1_delayed_unxsync_rxdxx1); --ME1L39 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter~604 ME1L39 = ME1L37 # ME1L17 # ME1_sync_rxd $ ME1_delayed_unxsync_rxdxx1; --ME1L40 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter~605 ME1L40 = ME1L15 & (ME1_sync_rxd $ ME1_delayed_unxsync_rxdxx1 # !ME1L37) # !ME1L15 & (ME1_sync_rxd $ ME1_delayed_unxsync_rxdxx1); --ME1L41 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter~606 ME1L41 = ME1L37 & (ME1_sync_rxd $ !ME1_delayed_unxsync_rxdxx1) # !ME1L37 & ME1L13 & (ME1_sync_rxd $ !ME1_delayed_unxsync_rxdxx1); --ME1L42 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter~607 ME1L42 = ME1L37 # ME1L11 # ME1_sync_rxd $ ME1_delayed_unxsync_rxdxx1; --ME1L43 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter~608 ME1L43 = ME1L9 & (ME1_sync_rxd $ ME1_delayed_unxsync_rxdxx1 # !ME1L37) # !ME1L9 & (ME1_sync_rxd $ ME1_delayed_unxsync_rxdxx1); --ME1L44 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter~609 ME1L44 = ME1L7 & !ME1L37 & (ME1_sync_rxd $ !ME1_delayed_unxsync_rxdxx1); --ME1L45 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter~610 ME1L45 = ME1L37 & (ME1_sync_rxd $ !ME1_delayed_unxsync_rxdxx1) # !ME1L37 & ME1L5 & (ME1_sync_rxd $ !ME1_delayed_unxsync_rxdxx1); --ME1L46 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter~611 ME1L46 = ME1L3 & (ME1_sync_rxd $ ME1_delayed_unxsync_rxdxx1 # !ME1L37) # !ME1L3 & (ME1_sync_rxd $ ME1_delayed_unxsync_rxdxx1); --ME1L47 is system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|baud_rate_counter~612 ME1L47 = ME1L1 & !ME1L37 & (ME1_sync_rxd $ !ME1_delayed_unxsync_rxdxx1); --Z1_M_src2[16] is system_0:u0|cpu_0:the_cpu_0|M_src2[16] Z1_M_src2[16] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[16], N1_data_out, Z1_A_stall); --Z1L500 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[16]~320 Z1L500 = AMPP_FUNCTION(Z1_M_src2[16], Z1_A_mul_stall); --Z1_M_src2[17] is system_0:u0|cpu_0:the_cpu_0|M_src2[17] Z1_M_src2[17] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[17], N1_data_out, Z1_A_stall); --Z1L501 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[17]~321 Z1L501 = AMPP_FUNCTION(Z1_M_src2[17], Z1_A_mul_stall); --Z1_M_src2[18] is system_0:u0|cpu_0:the_cpu_0|M_src2[18] Z1_M_src2[18] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[18], N1_data_out, Z1_A_stall); --Z1L502 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[18]~322 Z1L502 = AMPP_FUNCTION(Z1_M_src2[18], Z1_A_mul_stall); --Z1_M_src2[19] is system_0:u0|cpu_0:the_cpu_0|M_src2[19] Z1_M_src2[19] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[19], N1_data_out, Z1_A_stall); --Z1L503 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[19]~323 Z1L503 = AMPP_FUNCTION(Z1_M_src2[19], Z1_A_mul_stall); --Z1_M_src2[20] is system_0:u0|cpu_0:the_cpu_0|M_src2[20] Z1_M_src2[20] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[20], N1_data_out, Z1_A_stall); --Z1L504 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[20]~324 Z1L504 = AMPP_FUNCTION(Z1_M_src2[20], Z1_A_mul_stall); --Z1_M_src2[21] is system_0:u0|cpu_0:the_cpu_0|M_src2[21] Z1_M_src2[21] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[21], N1_data_out, Z1_A_stall); --Z1L505 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[21]~325 Z1L505 = AMPP_FUNCTION(Z1_M_src2[21], Z1_A_mul_stall); --Z1_M_src2[22] is system_0:u0|cpu_0:the_cpu_0|M_src2[22] Z1_M_src2[22] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[22], N1_data_out, Z1_A_stall); --Z1L506 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[22]~326 Z1L506 = AMPP_FUNCTION(Z1_M_src2[22], Z1_A_mul_stall); --Z1_M_src2[23] is system_0:u0|cpu_0:the_cpu_0|M_src2[23] Z1_M_src2[23] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[23], N1_data_out, Z1_A_stall); --Z1L507 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[23]~327 Z1L507 = AMPP_FUNCTION(Z1_M_src2[23], Z1_A_mul_stall); --Z1_M_src2[24] is system_0:u0|cpu_0:the_cpu_0|M_src2[24] Z1_M_src2[24] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[24], N1_data_out, Z1_A_stall); --Z1L508 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[24]~328 Z1L508 = AMPP_FUNCTION(Z1_M_src2[24], Z1_A_mul_stall); --Z1_M_src2[25] is system_0:u0|cpu_0:the_cpu_0|M_src2[25] Z1_M_src2[25] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[25], N1_data_out, Z1_A_stall); --Z1L509 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[25]~329 Z1L509 = AMPP_FUNCTION(Z1_M_src2[25], Z1_A_mul_stall); --Z1_M_src2[26] is system_0:u0|cpu_0:the_cpu_0|M_src2[26] Z1_M_src2[26] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[26], N1_data_out, Z1_A_stall); --Z1L510 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[26]~330 Z1L510 = AMPP_FUNCTION(Z1_M_src2[26], Z1_A_mul_stall); --Z1_M_src2[27] is system_0:u0|cpu_0:the_cpu_0|M_src2[27] Z1_M_src2[27] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[27], N1_data_out, Z1_A_stall); --Z1L511 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[27]~331 Z1L511 = AMPP_FUNCTION(Z1_M_src2[27], Z1_A_mul_stall); --Z1_M_src2[28] is system_0:u0|cpu_0:the_cpu_0|M_src2[28] Z1_M_src2[28] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[28], N1_data_out, Z1_A_stall); --Z1L512 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[28]~332 Z1L512 = AMPP_FUNCTION(Z1_M_src2[28], Z1_A_mul_stall); --Z1_M_src2[29] is system_0:u0|cpu_0:the_cpu_0|M_src2[29] Z1_M_src2[29] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[29], N1_data_out, Z1_A_stall); --Z1L513 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[29]~333 Z1L513 = AMPP_FUNCTION(Z1_M_src2[29], Z1_A_mul_stall); --Z1_M_src2[30] is system_0:u0|cpu_0:the_cpu_0|M_src2[30] Z1_M_src2[30] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[30], N1_data_out, Z1_A_stall); --Z1L514 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[30]~334 Z1L514 = AMPP_FUNCTION(Z1_M_src2[30], Z1_A_mul_stall); --Z1_M_src2[31] is system_0:u0|cpu_0:the_cpu_0|M_src2[31] Z1_M_src2[31] = AMPP_FUNCTION(F1__clk1, Z1_E_src2[31], N1_data_out, Z1_A_stall); --Z1L515 is system_0:u0|cpu_0:the_cpu_0|A_mul_src2_nxt[31]~335 Z1L515 = AMPP_FUNCTION(Z1_M_src2[31], Z1_A_mul_stall); --VC1L48 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2175 VC1L48 = AMPP_FUNCTION(FD1L35Q, FD1L55Q, FD1L56Q, VC1L26); --VC1L49 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2176 VC1L49 = AMPP_FUNCTION(FD1L23Q, FD1L55Q, FD1L56Q, VC1L26); --VC1L50 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2177 VC1L50 = AMPP_FUNCTION(FD1L45Q, FD1L55Q, FD1L56Q, VC1L26); --FE1_q_b[3] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2|q_b[3] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1 --Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered FE1_q_b[3]_PORT_A_data_in = Z1_d_writedata[3]; FE1_q_b[3]_PORT_A_data_in_reg = DFFE(FE1_q_b[3]_PORT_A_data_in, FE1_q_b[3]_clock_0, , , FE1_q_b[3]_clock_enable_0); FE1_q_b[3]_PORT_A_address = BUS(DE2_safe_q[0], DE2_safe_q[1], DE2_safe_q[2], DE2_safe_q[3], DE2_safe_q[4], DE2_safe_q[5]); FE1_q_b[3]_PORT_A_address_reg = DFFE(FE1_q_b[3]_PORT_A_address, FE1_q_b[3]_clock_0, , , FE1_q_b[3]_clock_enable_0); FE1_q_b[3]_PORT_B_address = BUS(DE1_safe_q[0], DE1_safe_q[1], DE1_safe_q[2], DE1_safe_q[3], DE1_safe_q[4], DE1_safe_q[5]); FE1_q_b[3]_PORT_B_address_reg = DFFE(FE1_q_b[3]_PORT_B_address, FE1_q_b[3]_clock_1, , , FE1_q_b[3]_clock_enable_1); FE1_q_b[3]_PORT_A_write_enable = VCC; FE1_q_b[3]_PORT_A_write_enable_reg = DFFE(FE1_q_b[3]_PORT_A_write_enable, FE1_q_b[3]_clock_0, , , FE1_q_b[3]_clock_enable_0); FE1_q_b[3]_PORT_B_read_enable = VCC; FE1_q_b[3]_PORT_B_read_enable_reg = DFFE(FE1_q_b[3]_PORT_B_read_enable, FE1_q_b[3]_clock_1, , , FE1_q_b[3]_clock_enable_1); FE1_q_b[3]_clock_0 = F1__clk1; FE1_q_b[3]_clock_1 = F1__clk1; FE1_q_b[3]_clock_enable_0 = FB1_fifo_wr; FE1_q_b[3]_clock_enable_1 = FB1_rd_wfifo; FE1_q_b[3]_PORT_B_data_out = MEMORY(FE1_q_b[3]_PORT_A_data_in_reg, , FE1_q_b[3]_PORT_A_address_reg, FE1_q_b[3]_PORT_B_address_reg, FE1_q_b[3]_PORT_A_write_enable_reg, FE1_q_b[3]_PORT_B_read_enable_reg, , , FE1_q_b[3]_clock_0, FE1_q_b[3]_clock_1, FE1_q_b[3]_clock_enable_0, FE1_q_b[3]_clock_enable_1, , ); FE1_q_b[3] = FE1_q_b[3]_PORT_B_data_out[0]; --VD1_count[3] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[3] VD1_count[3] = AMPP_FUNCTION(A1L333, VD1L21, D1_CLRN_SIGNAL, VD1L57); --VD1L20 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count~221 VD1L20 = AMPP_FUNCTION(L1_state[4], VD1_count[3]); --VC1L51 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2178 VC1L51 = AMPP_FUNCTION(FD1L46Q, FD1L55Q, FD1L56Q, VC1L26); --VC1L52 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2179 VC1L52 = AMPP_FUNCTION(FD1L47Q, FD1L55Q, FD1L56Q, VC1L26); --VC1L53 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2180 VC1L53 = AMPP_FUNCTION(FD1L48Q, FD1L55Q, FD1L56Q, VC1L26); --VC1L54 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2181 VC1L54 = AMPP_FUNCTION(FD1L49Q, FD1L55Q, FD1L56Q, VC1L26); --VC1L55 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2182 VC1L55 = AMPP_FUNCTION(FD1L50Q, FD1L55Q, FD1L56Q, VC1L26); --XC1L17 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetlatch~182 XC1L17 = AMPP_FUNCTION(XC1_resetlatch, D1_CLRN_SIGNAL, FD1L196, FD1L43Q); --XC1L18 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetlatch~183 XC1L18 = AMPP_FUNCTION(XC1L17, D1_CLRN_SIGNAL, N1_data_out, FD1L196); --SD1_stateZero is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|stateZero SD1_stateZero = DFFEAS(SD1L22, F1__clk1, N1_data_out, , SD1L51, , , , ); --SD1L36 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|SS_n~17 SD1L36 = SD1_epcs_slave_select_reg[0] # !SD1_SSO_reg & (!SD1_stateZero # !SD1_transmitting); --FE1_q_b[4] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2|q_b[4] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1 --Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered FE1_q_b[4]_PORT_A_data_in = Z1_d_writedata[4]; FE1_q_b[4]_PORT_A_data_in_reg = DFFE(FE1_q_b[4]_PORT_A_data_in, FE1_q_b[4]_clock_0, , , FE1_q_b[4]_clock_enable_0); FE1_q_b[4]_PORT_A_address = BUS(DE2_safe_q[0], DE2_safe_q[1], DE2_safe_q[2], DE2_safe_q[3], DE2_safe_q[4], DE2_safe_q[5]); FE1_q_b[4]_PORT_A_address_reg = DFFE(FE1_q_b[4]_PORT_A_address, FE1_q_b[4]_clock_0, , , FE1_q_b[4]_clock_enable_0); FE1_q_b[4]_PORT_B_address = BUS(DE1_safe_q[0], DE1_safe_q[1], DE1_safe_q[2], DE1_safe_q[3], DE1_safe_q[4], DE1_safe_q[5]); FE1_q_b[4]_PORT_B_address_reg = DFFE(FE1_q_b[4]_PORT_B_address, FE1_q_b[4]_clock_1, , , FE1_q_b[4]_clock_enable_1); FE1_q_b[4]_PORT_A_write_enable = VCC; FE1_q_b[4]_PORT_A_write_enable_reg = DFFE(FE1_q_b[4]_PORT_A_write_enable, FE1_q_b[4]_clock_0, , , FE1_q_b[4]_clock_enable_0); FE1_q_b[4]_PORT_B_read_enable = VCC; FE1_q_b[4]_PORT_B_read_enable_reg = DFFE(FE1_q_b[4]_PORT_B_read_enable, FE1_q_b[4]_clock_1, , , FE1_q_b[4]_clock_enable_1); FE1_q_b[4]_clock_0 = F1__clk1; FE1_q_b[4]_clock_1 = F1__clk1; FE1_q_b[4]_clock_enable_0 = FB1_fifo_wr; FE1_q_b[4]_clock_enable_1 = FB1_rd_wfifo; FE1_q_b[4]_PORT_B_data_out = MEMORY(FE1_q_b[4]_PORT_A_data_in_reg, , FE1_q_b[4]_PORT_A_address_reg, FE1_q_b[4]_PORT_B_address_reg, FE1_q_b[4]_PORT_A_write_enable_reg, FE1_q_b[4]_PORT_B_read_enable_reg, , , FE1_q_b[4]_clock_0, FE1_q_b[4]_clock_1, FE1_q_b[4]_clock_enable_0, FE1_q_b[4]_clock_enable_1, , ); FE1_q_b[4] = FE1_q_b[4]_PORT_B_data_out[0]; --VC1L56 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2183 VC1L56 = AMPP_FUNCTION(FD1L24Q, FD1L55Q, FD1L56Q, VC1L26); --FE1_q_b[5] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2|q_b[5] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1 --Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered FE1_q_b[5]_PORT_A_data_in = Z1_d_writedata[5]; FE1_q_b[5]_PORT_A_data_in_reg = DFFE(FE1_q_b[5]_PORT_A_data_in, FE1_q_b[5]_clock_0, , , FE1_q_b[5]_clock_enable_0); FE1_q_b[5]_PORT_A_address = BUS(DE2_safe_q[0], DE2_safe_q[1], DE2_safe_q[2], DE2_safe_q[3], DE2_safe_q[4], DE2_safe_q[5]); FE1_q_b[5]_PORT_A_address_reg = DFFE(FE1_q_b[5]_PORT_A_address, FE1_q_b[5]_clock_0, , , FE1_q_b[5]_clock_enable_0); FE1_q_b[5]_PORT_B_address = BUS(DE1_safe_q[0], DE1_safe_q[1], DE1_safe_q[2], DE1_safe_q[3], DE1_safe_q[4], DE1_safe_q[5]); FE1_q_b[5]_PORT_B_address_reg = DFFE(FE1_q_b[5]_PORT_B_address, FE1_q_b[5]_clock_1, , , FE1_q_b[5]_clock_enable_1); FE1_q_b[5]_PORT_A_write_enable = VCC; FE1_q_b[5]_PORT_A_write_enable_reg = DFFE(FE1_q_b[5]_PORT_A_write_enable, FE1_q_b[5]_clock_0, , , FE1_q_b[5]_clock_enable_0); FE1_q_b[5]_PORT_B_read_enable = VCC; FE1_q_b[5]_PORT_B_read_enable_reg = DFFE(FE1_q_b[5]_PORT_B_read_enable, FE1_q_b[5]_clock_1, , , FE1_q_b[5]_clock_enable_1); FE1_q_b[5]_clock_0 = F1__clk1; FE1_q_b[5]_clock_1 = F1__clk1; FE1_q_b[5]_clock_enable_0 = FB1_fifo_wr; FE1_q_b[5]_clock_enable_1 = FB1_rd_wfifo; FE1_q_b[5]_PORT_B_data_out = MEMORY(FE1_q_b[5]_PORT_A_data_in_reg, , FE1_q_b[5]_PORT_A_address_reg, FE1_q_b[5]_PORT_B_address_reg, FE1_q_b[5]_PORT_A_write_enable_reg, FE1_q_b[5]_PORT_B_read_enable_reg, , , FE1_q_b[5]_clock_0, FE1_q_b[5]_clock_1, FE1_q_b[5]_clock_enable_0, FE1_q_b[5]_clock_enable_1, , ); FE1_q_b[5] = FE1_q_b[5]_PORT_B_data_out[0]; --FE1_q_b[6] is system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2|q_b[6] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1 --Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8 --Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered FE1_q_b[6]_PORT_A_data_in = Z1_d_writedata[6]; FE1_q_b[6]_PORT_A_data_in_reg = DFFE(FE1_q_b[6]_PORT_A_data_in, FE1_q_b[6]_clock_0, , , FE1_q_b[6]_clock_enable_0); FE1_q_b[6]_PORT_A_address = BUS(DE2_safe_q[0], DE2_safe_q[1], DE2_safe_q[2], DE2_safe_q[3], DE2_safe_q[4], DE2_safe_q[5]); FE1_q_b[6]_PORT_A_address_reg = DFFE(FE1_q_b[6]_PORT_A_address, FE1_q_b[6]_clock_0, , , FE1_q_b[6]_clock_enable_0); FE1_q_b[6]_PORT_B_address = BUS(DE1_safe_q[0], DE1_safe_q[1], DE1_safe_q[2], DE1_safe_q[3], DE1_safe_q[4], DE1_safe_q[5]); FE1_q_b[6]_PORT_B_address_reg = DFFE(FE1_q_b[6]_PORT_B_address, FE1_q_b[6]_clock_1, , , FE1_q_b[6]_clock_enable_1); FE1_q_b[6]_PORT_A_write_enable = VCC; FE1_q_b[6]_PORT_A_write_enable_reg = DFFE(FE1_q_b[6]_PORT_A_write_enable, FE1_q_b[6]_clock_0, , , FE1_q_b[6]_clock_enable_0); FE1_q_b[6]_PORT_B_read_enable = VCC; FE1_q_b[6]_PORT_B_read_enable_reg = DFFE(FE1_q_b[6]_PORT_B_read_enable, FE1_q_b[6]_clock_1, , , FE1_q_b[6]_clock_enable_1); FE1_q_b[6]_clock_0 = F1__clk1; FE1_q_b[6]_clock_1 = F1__clk1; FE1_q_b[6]_clock_enable_0 = FB1_fifo_wr; FE1_q_b[6]_clock_enable_1 = FB1_rd_wfifo; FE1_q_b[6]_PORT_B_data_out = MEMORY(FE1_q_b[6]_PORT_A_data_in_reg, , FE1_q_b[6]_PORT_A_address_reg, FE1_q_b[6]_PORT_B_address_reg, FE1_q_b[6]_PORT_A_write_enable_reg, FE1_q_b[6]_PORT_B_read_enable_reg, , , FE1_q_b[6]_clock_0, FE1_q_b[6]_clock_1, FE1_q_b[6]_clock_enable_0, FE1_q_b[6]_clock_enable_1, , ); FE1_q_b[6] = FE1_q_b[6]_PORT_B_data_out[0]; --VC1L57 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2184 VC1L57 = AMPP_FUNCTION(FD1L25Q, FD1L55Q, FD1L56Q, VC1L26); --VC1L58 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2185 VC1L58 = AMPP_FUNCTION(FD1L26Q, FD1L55Q, FD1L56Q, VC1L26); --VC1L59 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2186 VC1L59 = AMPP_FUNCTION(FD1L27Q, FD1L55Q, FD1L56Q, VC1L26); --VC1L60 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2187 VC1L60 = AMPP_FUNCTION(FD1L28Q, FD1L55Q, FD1L56Q, VC1L26); --VC1L61 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2188 VC1L61 = AMPP_FUNCTION(FD1L29Q, FD1L55Q, FD1L56Q, VC1L26); --VC1L62 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2189 VC1L62 = AMPP_FUNCTION(FD1L30Q, FD1L55Q, FD1L56Q, VC1L26); --VC1L63 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2190 VC1L63 = AMPP_FUNCTION(FD1L31Q, FD1L55Q, FD1L56Q, VC1L26); --VC1L64 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2191 VC1L64 = AMPP_FUNCTION(FD1L32Q, FD1L55Q, FD1L56Q, VC1L26); --FD1L5 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|Decoder~30 FD1L5 = AMPP_FUNCTION(G5_Q[1], G5_Q[0]); --VC1L65 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2192 VC1L65 = AMPP_FUNCTION(FD1L33Q, FD1L55Q, FD1L56Q, VC1L26); --VC1L66 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg~2193 VC1L66 = AMPP_FUNCTION(FD1L34Q, FD1L55Q, FD1L56Q, VC1L26); --VD1_count[2] is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[2] VD1_count[2] = AMPP_FUNCTION(A1L333, VD1L22, D1_CLRN_SIGNAL, VD1L57); --VD1L21 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count~222 VD1L21 = AMPP_FUNCTION(L1_state[4], VD1_count[2]); --SD1L22 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal~767 SD1L22 = !SD1L21 # !SD1_state[4] # !SD1_state[0]; --VD1L22 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count~223 VD1L22 = AMPP_FUNCTION(L1_state[4], VD1_count[1]); --HB1L302 is system_0:u0|sdram_0:the_sdram_0|m_addr[0]~122 HB1L302 = !HB1_m_state.010000000 & HB1L301 & (HB1_m_state.000000001 # !HB1_init_done); --HB1L177 is system_0:u0|sdram_0:the_sdram_0|Select~8281 HB1L177 = HB1_m_state.001000000 # !HB1_m_state.000001000 & !HB1_m_state.000010000 & HB1L47; --HB1L178 is system_0:u0|sdram_0:the_sdram_0|Select~8282 HB1L178 = HB1_m_state.001000000 # !HB1_m_state.000001000 & !HB1_m_state.000010000 & HB1L48; --HB1L179 is system_0:u0|sdram_0:the_sdram_0|Select~8283 HB1L179 = HB1_m_state.001000000 # !HB1_m_state.000001000 & !HB1_m_state.000010000 & HB1L49; --HB1L180 is system_0:u0|sdram_0:the_sdram_0|Select~8284 HB1L180 = HB1_m_state.001000000 # !HB1_m_state.000001000 & !HB1_m_state.000010000 & HB1L50; --HB1_f_select is system_0:u0|sdram_0:the_sdram_0|f_select HB1_f_select = HB1_f_pop & HB1L385 & (GE1_entries[1] # GE1_entries[0]); --HB1L262 is system_0:u0|sdram_0:the_sdram_0|always5~0 HB1L262 = HB1L385 & (GE1_entries[1] # GE1_entries[0]) # !HB1_f_pop; --JE1L42 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|updated_one_count~132 JE1L42 = JB1L16 & (GE1_entries[0] # !GE1_entries[1]); --HB1L181 is system_0:u0|sdram_0:the_sdram_0|Select~8285 HB1L181 = HB1L300 & !HB1_refresh_request & (GE1_entries[1] # GE1_entries[0]); --GE1L90 is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[38]~2 GE1L90 = HB1L263 & GE1_wr_address & (GE1_entries[0] # !GE1_entries[1]); --GE1L47 is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[38]~2 GE1L47 = HB1L263 & !GE1_wr_address & (GE1_entries[0] # !GE1_entries[1]); --HB1L369 is system_0:u0|sdram_0:the_sdram_0|m_state.000001000~470 HB1L369 = !HB1_m_count[2] & !HB1_m_count[1] & HB1_m_state.000000100 & !HB1L73; --HB1L182 is system_0:u0|sdram_0:the_sdram_0|Select~8286 HB1L182 = HB1L70 # !HB1_m_count[2] & !HB1_m_count[1] & HB1_m_state.000100000; --HB1L183 is system_0:u0|sdram_0:the_sdram_0|Select~8287 HB1L183 = HB1_m_state.000000100 # HB1_m_state.000100000 # !HB1L91; --JB1L68 is system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_end_xfer~11 JB1L68 = GE1_entries[1] & !GE1_entries[0] & HB1L263; --EB1L24 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_begins_xfer~63 EB1L24 = !EB1_d1_reasons_to_wait & (EB1_cpu_0_data_master_requests_epcs_controller_epcs_control_port # EB1L28 & EB1L3); --EB1L22 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_addend[1]~736 EB1L22 = EB1L25 & (EB1L26) # !EB1L25 & (EB1L7 # EB1_epcs_controller_epcs_control_port_saved_chosen_master_vector[0] & !EB1L26); --EB1L19 is system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_addend[0]~737 EB1L19 = EB1L7 & (EB1L25) # !EB1L7 & !EB1L25 & (EB1L26 # !EB1_epcs_controller_epcs_control_port_saved_chosen_master_vector[0]); --CB1L23 is system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_begintransfer~58 CB1L23 = !CB1_d1_reasons_to_wait & (CB1_cpu_0_data_master_requests_cpu_0_jtag_debug_module # EB1L28 & CB1L1); --FB1L42 is system_0:u0|jtag_uart_0:the_jtag_uart_0|av_waitrequest~43 FB1L42 = GB1L8 & !AB1_cpu_0_data_master_waitrequest & (Z1_d_write # Z1_d_read); --GE1L97 is system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|wr_address~16 GE1L97 = GE1_wr_address $ (HB1L263 & (GE1_entries[0] # !GE1_entries[1])); --Z1L1891 is system_0:u0|cpu_0:the_cpu_0|E_valid~32 Z1L1891 = AMPP_FUNCTION(Z1_M_pipe_flush, Z1_E_valid_from_D, Z1L2334); --Z1L1540 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_ld_st_non_bypass~0 Z1L1540 = AMPP_FUNCTION(Z1L2868, Z1L2934, Z1_E_ctrl_alu_subtract, Z1L1541); --Z1L1550 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_st_bypass~1 Z1L1550 = AMPP_FUNCTION(Z1_E_iw[0], Z1_E_iw[1], Z1_E_iw[5], Z1L1483); --Z1L1977 is system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[4]~1091 Z1L1977 = AMPP_FUNCTION(Z1_D_kill, Z1_D_inst_ram_hit, Z1_D_issue, Z1L966); --Z1L1050 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_jmp_indirect~37 Z1L1050 = AMPP_FUNCTION(Z1_D_iw[11], Z1_D_iw[16], Z1L1049); --Z1L2007 is system_0:u0|cpu_0:the_cpu_0|F_iw[14]~1608 Z1L2007 = AMPP_FUNCTION(Z1_latched_oci_tb_hbreak_req, Z1_hbreak_enabled, JC1_q_a[14], Z1L1994); --Z1L1300 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[31]~3722 Z1L1300 = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src, Z1L1478, Z1L1299); --Z1L1297 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[30]~3723 Z1L1297 = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src, Z1L1476, Z1L1296); --Z1L1294 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[29]~3724 Z1L1294 = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src, Z1L1474, Z1L1293); --Z1L1291 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[28]~3725 Z1L1291 = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src, Z1L1472, Z1L1290); --Z1L1288 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[27]~3726 Z1L1288 = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src, Z1L1470, Z1L1287); --Z1L1285 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[26]~3727 Z1L1285 = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src, Z1L1468, Z1L1284); --Z1L1282 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[25]~3728 Z1L1282 = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src, Z1L1466, Z1L1281); --Z1L1279 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[24]~3729 Z1L1279 = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src, Z1L1464, Z1L1278); --Z1L1237 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[10]~3730 Z1L1237 = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src, Z1L1422, Z1L1236); --Z1L1234 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[9]~3731 Z1L1234 = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src, Z1L1420, Z1L1233); --Z1L1231 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[8]~3732 Z1L1231 = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src, Z1L1418, Z1L1230); --Z1L1228 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[7]~3733 Z1L1228 = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src, Z1L1416, Z1L1227); --Z1L1225 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[6]~3734 Z1L1225 = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src, Z1L1414, Z1L1224); --Z1L1222 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[5]~3735 Z1L1222 = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src, Z1L1412, Z1L1221); --Z1L1219 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[4]~3736 Z1L1219 = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src, Z1L1410, Z1L1218); --Z1L1216 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[3]~3737 Z1L1216 = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src, Z1L1408, Z1L1215); --Z1L1213 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[2]~3738 Z1L1213 = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src, Z1L1406, Z1L1212); --Z1L1210 is system_0:u0|cpu_0:the_cpu_0|D_src1_reg[1]~3739 Z1L1210 = AMPP_FUNCTION(Z1_E_regnum_a_cmp_D, Z1_D_ctrl_a_not_src, Z1L1404, Z1L1209); --Z1L1038 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_flush_pipe_always~323 Z1L1038 = AMPP_FUNCTION(Z1_D_iw[4], Z1_D_iw[5], Z1L1141, Z1L1037); --Z1L3382 is system_0:u0|cpu_0:the_cpu_0|wait_for_one_post_bret_inst~127 Z1L3382 = AMPP_FUNCTION(Z1_M_pipe_flush, Z1_E_valid_from_D, Z1_A_stall); --Z1L3290 is system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_cnt_nxt[2]~42 Z1L3290 = AMPP_FUNCTION(Z1_ic_fill_ap_cnt[1], Z1_ic_fill_ap_cnt[0], BB1L250, Z1_ic_fill_ap_cnt[2]); --Z1L1551 is system_0:u0|cpu_0:the_cpu_0|E_ctrl_st_non_bypass~26 Z1L1551 = AMPP_FUNCTION(Z1_E_iw[0], Z1_E_iw[1], Z1_E_iw[5], Z1L1483); --Z1L2011 is system_0:u0|cpu_0:the_cpu_0|F_iw[18]~1609 Z1L2011 = AMPP_FUNCTION(Z1_latched_oci_tb_hbreak_req, Z1_hbreak_enabled, JC1_q_a[18], Z1L1994); --Z1L2010 is system_0:u0|cpu_0:the_cpu_0|F_iw[17]~1610 Z1L2010 = AMPP_FUNCTION(Z1_latched_oci_tb_hbreak_req, Z1_hbreak_enabled, JC1_q_a[17], Z1L1994); --Z1_D_ctrl_mul_lsw is system_0:u0|cpu_0:the_cpu_0|D_ctrl_mul_lsw Z1_D_ctrl_mul_lsw = AMPP_FUNCTION(Z1_D_iw[5], Z1L1143, Z1L1908, Z1_D_iw[4]); --BB1L176 is system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_readdata~3076 BB1L176 = EB1L28 & CB1L1 & (!UC1L13 # !CB1L14); --MB1L47 is system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register_in~13 MB1L47 = !MB1_cfi_flash_0_s1_wait_counter[0] & AB1L355 & MB1L40 & !MB1L144; --ED1L108 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|comb~26 ED1L108 = AMPP_FUNCTION(Z1_d_write, Z1_hbreak_enabled, CB1L30, CB1L14); --SD1L56 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]~216 SD1L56 = !EB1L11 & (EB1L26 & Z1_d_address[3] # !EB1L26 & (Z1_ic_fill_ap_offset[1])); --SD1L67 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[8]~217 SD1L67 = !EB1L9 & (EB1L26 & Z1_d_address[3] # !EB1L26 & (Z1_ic_fill_ap_offset[1])); --SD1L226 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|transmitting~87 SD1L226 = !SD1L26 & (SD1_tx_holding_primed # SD1_transmitting); --VD1L50 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|t_ena~53 VD1L50 = AMPP_FUNCTION(VD1_read_write1, VD1_read_write2, VD1L51Q, VD1L52); --SD1L194 is system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[1]~1233 SD1L194 = SD1L225 # SD1_slowcount[1] & !SD1_slowcount[0] & SD1_SCLK_reg; --Z1L1929 is system_0:u0|cpu_0:the_cpu_0|F_ctrl_a_not_src~53 Z1L1929 = AMPP_FUNCTION(JC1_q_a[1], Z1L1994, JC1_q_a[2], Z1L1932); --Z1L1933 is system_0:u0|cpu_0:the_cpu_0|F_ctrl_br_uncond~76 Z1L1933 = AMPP_FUNCTION(JC1_q_a[0], Z1L1994, JC1_q_a[1], Z1L1932); --Z1L1152 is system_0:u0|cpu_0:the_cpu_0|D_op_call~834 Z1L1152 = AMPP_FUNCTION(Z1_D_iw[0], Z1_D_iw[1], Z1_D_iw[2], Z1_D_iw[3]); --Z1L1014 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_alu_signed_cmp~272 Z1L1014 = AMPP_FUNCTION(Z1_D_iw[1], Z1_D_iw[2], Z1_D_iw[3], Z1_D_iw[4]); --Z1L1017 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_alu_subtract~363 Z1L1017 = AMPP_FUNCTION(Z1_D_iw[1], Z1_D_iw[2], Z1_D_iw[3], Z1_D_iw[4]); --Z1L1008 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_alu_force_xor~277 Z1L1008 = AMPP_FUNCTION(Z1_D_iw[5], Z1_D_iw[1], Z1_D_iw[2], Z1_D_iw[3]); --Z1L1013 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_alu_force_xor~282 Z1L1013 = AMPP_FUNCTION(Z1L1008, Z1_D_iw[0]); --Z1L1039 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_flush_pipe_always~324 Z1L1039 = AMPP_FUNCTION(Z1_D_iw[14], Z1_D_iw[16], Z1_D_iw[11], Z1_D_iw[13]); --Z1L1040 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_flush_pipe_always~325 Z1L1040 = AMPP_FUNCTION(Z1L1039, Z1_D_iw[16], Z1_D_iw[15]); --Z1L1019 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_alu_subtract~367 Z1L1019 = AMPP_FUNCTION(Z1_D_iw[0], Z1L1017, Z1L1015); --Z1L1020 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_alu_subtract~368 Z1L1020 = AMPP_FUNCTION(Z1_D_iw[13], Z1L1019, Z1L1049, Z1L1018); --Z1L1016 is system_0:u0|cpu_0:the_cpu_0|D_ctrl_alu_signed_cmp~275 Z1L1016 = AMPP_FUNCTION(Z1_D_iw[0], Z1L1014, Z1L1015, Z1_D_iw[5]); --Z1L129 is system_0:u0|cpu_0:the_cpu_0|A_en_d1~9 Z1L129 = AMPP_FUNCTION(Z1_A_stall); --HB1L408 is system_0:u0|sdram_0:the_sdram_0|refresh_counter[10]~496 HB1L408 = !HB1L253; --HB1L406 is system_0:u0|sdram_0:the_sdram_0|refresh_counter[9]~497 HB1L406 = !HB1L251; --HB1L400 is system_0:u0|sdram_0:the_sdram_0|refresh_counter[4]~499 HB1L400 = !HB1L241; --UC1L9 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[3]~724 UC1L9 = AMPP_FUNCTION(Z1_d_writedata[3]); --UC1L7 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[2]~725 UC1L7 = AMPP_FUNCTION(Z1_d_writedata[2]); --UC1L5 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[1]~726 UC1L5 = AMPP_FUNCTION(Z1_d_writedata[1]); --UC1L3 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[0]~727 UC1L3 = AMPP_FUNCTION(Z1_d_writedata[0]); --Z1L952 is system_0:u0|cpu_0:the_cpu_0|A_wr_dst_reg_from_M~4 Z1L952 = AMPP_FUNCTION(Z1_M_wr_dst_reg_from_E); --VD1L43 is system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write~4 VD1L43 = AMPP_FUNCTION(VD1_read_write); --FD1L193 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updateir~7 FD1L193 = AMPP_FUNCTION(FD1L8, FD1L193, A1L336); --FD1L190 is system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updatedr~8 FD1L190 = AMPP_FUNCTION(FD1L104, FD1L190, A1L336); --~GND is ~GND ~GND = GND; --CLOCK_24[0] is CLOCK_24[0] --operation mode is input CLOCK_24[0] = INPUT(); --CLOCK_24[1] is CLOCK_24[1] --operation mode is input CLOCK_24[1] = INPUT(); --CLOCK_27[0] is CLOCK_27[0] --operation mode is input CLOCK_27[0] = INPUT(); --CLOCK_27[1] is CLOCK_27[1] --operation mode is input CLOCK_27[1] = INPUT(); --EXT_CLOCK is EXT_CLOCK --operation mode is input EXT_CLOCK = INPUT(); --TDI is TDI --operation mode is input TDI = INPUT(); --TCK is TCK --operation mode is input TCK = INPUT(); --TCS is TCS --operation mode is input TCS = INPUT(); --PS2_DAT is PS2_DAT --operation mode is input PS2_DAT = INPUT(); --PS2_CLK is PS2_CLK --operation mode is input PS2_CLK = INPUT(); --AUD_ADCDAT is AUD_ADCDAT --operation mode is input AUD_ADCDAT = INPUT(); --CLOCK_50 is CLOCK_50 --operation mode is input CLOCK_50 = INPUT(); --SW[0] is SW[0] --operation mode is input SW[0] = INPUT(); --KEY[0] is KEY[0] --operation mode is input KEY[0] = INPUT(); --SW[1] is SW[1] --operation mode is input SW[1] = INPUT(); --KEY[1] is KEY[1] --operation mode is input KEY[1] = INPUT(); --SW[2] is SW[2] --operation mode is input SW[2] = INPUT(); --KEY[2] is KEY[2] --operation mode is input KEY[2] = INPUT(); --SW[3] is SW[3] --operation mode is input SW[3] = INPUT(); --KEY[3] is KEY[3] --operation mode is input KEY[3] = INPUT(); --SW[4] is SW[4] --operation mode is input SW[4] = INPUT(); --SW[5] is SW[5] --operation mode is input SW[5] = INPUT(); --SW[6] is SW[6] --operation mode is input SW[6] = INPUT(); --SW[7] is SW[7] --operation mode is input SW[7] = INPUT(); --SW[8] is SW[8] --operation mode is input SW[8] = INPUT(); --SW[9] is SW[9] --operation mode is input SW[9] = INPUT(); --UART_RXD is UART_RXD --operation mode is input UART_RXD = INPUT(); --HEX0[0] is HEX0[0] --operation mode is output HEX0[0] = OUTPUT(RB1L1); --HEX0[1] is HEX0[1] --operation mode is output HEX0[1] = OUTPUT(RB1L2); --HEX0[2] is HEX0[2] --operation mode is output HEX0[2] = OUTPUT(RB1L3); --HEX0[3] is HEX0[3] --operation mode is output HEX0[3] = OUTPUT(RB1L4); --HEX0[4] is HEX0[4] --operation mode is output HEX0[4] = OUTPUT(RB1L5); --HEX0[5] is HEX0[5] --operation mode is output HEX0[5] = OUTPUT(RB1L6); --HEX0[6] is HEX0[6] --operation mode is output HEX0[6] = OUTPUT(!RB1L7); --HEX1[0] is HEX1[0] --operation mode is output HEX1[0] = OUTPUT(RB2L1); --HEX1[1] is HEX1[1] --operation mode is output HEX1[1] = OUTPUT(RB2L2); --HEX1[2] is HEX1[2] --operation mode is output HEX1[2] = OUTPUT(RB2L3); --HEX1[3] is HEX1[3] --operation mode is output HEX1[3] = OUTPUT(RB2L4); --HEX1[4] is HEX1[4] --operation mode is output HEX1[4] = OUTPUT(RB2L5); --HEX1[5] is HEX1[5] --operation mode is output HEX1[5] = OUTPUT(RB2L6); --HEX1[6] is HEX1[6] --operation mode is output HEX1[6] = OUTPUT(!RB2L7); --HEX2[0] is HEX2[0] --operation mode is output HEX2[0] = OUTPUT(RB3L1); --HEX2[1] is HEX2[1] --operation mode is output HEX2[1] = OUTPUT(RB3L2); --HEX2[2] is HEX2[2] --operation mode is output HEX2[2] = OUTPUT(RB3L3); --HEX2[3] is HEX2[3] --operation mode is output HEX2[3] = OUTPUT(RB3L4); --HEX2[4] is HEX2[4] --operation mode is output HEX2[4] = OUTPUT(RB3L5); --HEX2[5] is HEX2[5] --operation mode is output HEX2[5] = OUTPUT(RB3L6); --HEX2[6] is HEX2[6] --operation mode is output HEX2[6] = OUTPUT(!RB3L7); --HEX3[0] is HEX3[0] --operation mode is output HEX3[0] = OUTPUT(RB4L1); --HEX3[1] is HEX3[1] --operation mode is output HEX3[1] = OUTPUT(RB4L2); --HEX3[2] is HEX3[2] --operation mode is output HEX3[2] = OUTPUT(RB4L3); --HEX3[3] is HEX3[3] --operation mode is output HEX3[3] = OUTPUT(RB4L4); --HEX3[4] is HEX3[4] --operation mode is output HEX3[4] = OUTPUT(RB4L5); --HEX3[5] is HEX3[5] --operation mode is output HEX3[5] = OUTPUT(RB4L6); --HEX3[6] is HEX3[6] --operation mode is output HEX3[6] = OUTPUT(!RB4L7); --LEDG[0] is LEDG[0] --operation mode is output LEDG[0] = OUTPUT(R1_data_out[0]); --LEDG[1] is LEDG[1] --operation mode is output LEDG[1] = OUTPUT(R1_data_out[1]); --LEDG[2] is LEDG[2] --operation mode is output LEDG[2] = OUTPUT(R1_data_out[2]); --LEDG[3] is LEDG[3] --operation mode is output LEDG[3] = OUTPUT(R1_data_out[3]); --LEDG[4] is LEDG[4] --operation mode is output LEDG[4] = OUTPUT(R1_data_out[4]); --LEDG[5] is LEDG[5] --operation mode is output LEDG[5] = OUTPUT(R1_data_out[5]); --LEDG[6] is LEDG[6] --operation mode is output LEDG[6] = OUTPUT(R1_data_out[6]); --LEDG[7] is LEDG[7] --operation mode is output LEDG[7] = OUTPUT(R1_data_out[7]); --LEDR[0] is LEDR[0] --operation mode is output LEDR[0] = OUTPUT(T1_data_out[0]); --LEDR[1] is LEDR[1] --operation mode is output LEDR[1] = OUTPUT(T1_data_out[1]); --LEDR[2] is LEDR[2] --operation mode is output LEDR[2] = OUTPUT(T1_data_out[2]); --LEDR[3] is LEDR[3] --operation mode is output LEDR[3] = OUTPUT(T1_data_out[3]); --LEDR[4] is LEDR[4] --operation mode is output LEDR[4] = OUTPUT(T1_data_out[4]); --LEDR[5] is LEDR[5] --operation mode is output LEDR[5] = OUTPUT(T1_data_out[5]); --LEDR[6] is LEDR[6] --operation mode is output LEDR[6] = OUTPUT(T1_data_out[6]); --LEDR[7] is LEDR[7] --operation mode is output LEDR[7] = OUTPUT(T1_data_out[7]); --LEDR[8] is LEDR[8] --operation mode is output LEDR[8] = OUTPUT(T1_data_out[8]); --LEDR[9] is LEDR[9] --operation mode is output LEDR[9] = OUTPUT(T1_data_out[9]); --UART_TXD is UART_TXD --operation mode is output UART_TXD = OUTPUT(!NE1_txd); --DRAM_ADDR[0] is DRAM_ADDR[0] --operation mode is output DRAM_ADDR[0] = OUTPUT(HB1_m_addr[0]); --DRAM_ADDR[1] is DRAM_ADDR[1] --operation mode is output DRAM_ADDR[1] = OUTPUT(HB1_m_addr[1]); --DRAM_ADDR[2] is DRAM_ADDR[2] --operation mode is output DRAM_ADDR[2] = OUTPUT(HB1_m_addr[2]); --DRAM_ADDR[3] is DRAM_ADDR[3] --operation mode is output DRAM_ADDR[3] = OUTPUT(HB1_m_addr[3]); --DRAM_ADDR[4] is DRAM_ADDR[4] --operation mode is output DRAM_ADDR[4] = OUTPUT(HB1_m_addr[4]); --DRAM_ADDR[5] is DRAM_ADDR[5] --operation mode is output DRAM_ADDR[5] = OUTPUT(HB1_m_addr[5]); --DRAM_ADDR[6] is DRAM_ADDR[6] --operation mode is output DRAM_ADDR[6] = OUTPUT(HB1_m_addr[6]); --DRAM_ADDR[7] is DRAM_ADDR[7] --operation mode is output DRAM_ADDR[7] = OUTPUT(HB1_m_addr[7]); --DRAM_ADDR[8] is DRAM_ADDR[8] --operation mode is output DRAM_ADDR[8] = OUTPUT(HB1_m_addr[8]); --DRAM_ADDR[9] is DRAM_ADDR[9] --operation mode is output DRAM_ADDR[9] = OUTPUT(HB1_m_addr[9]); --DRAM_ADDR[10] is DRAM_ADDR[10] --operation mode is output DRAM_ADDR[10] = OUTPUT(HB1_m_addr[10]); --DRAM_ADDR[11] is DRAM_ADDR[11] --operation mode is output DRAM_ADDR[11] = OUTPUT(HB1_m_addr[11]); --DRAM_LDQM is DRAM_LDQM --operation mode is output DRAM_LDQM = OUTPUT(HB1_m_dqm[0]); --DRAM_UDQM is DRAM_UDQM --operation mode is output DRAM_UDQM = OUTPUT(HB1_m_dqm[1]); --DRAM_WE_N is DRAM_WE_N --operation mode is output DRAM_WE_N = OUTPUT(!HB1_m_cmd[0]); --DRAM_CAS_N is DRAM_CAS_N --operation mode is output DRAM_CAS_N = OUTPUT(!HB1_m_cmd[1]); --DRAM_RAS_N is DRAM_RAS_N --operation mode is output DRAM_RAS_N = OUTPUT(!HB1_m_cmd[2]); --DRAM_CS_N is DRAM_CS_N --operation mode is output DRAM_CS_N = OUTPUT(!HB1_m_cmd[3]); --DRAM_BA_0 is DRAM_BA_0 --operation mode is output DRAM_BA_0 = OUTPUT(HB1_m_bank[0]); --DRAM_BA_1 is DRAM_BA_1 --operation mode is output DRAM_BA_1 = OUTPUT(HB1_m_bank[1]); --DRAM_CLK is DRAM_CLK --operation mode is output DRAM_CLK = OUTPUT(F1__clk0); --DRAM_CKE is DRAM_CKE --operation mode is output DRAM_CKE = OUTPUT(VCC); --FL_ADDR[0] is FL_ADDR[0] --operation mode is output FL_ADDR[0] = OUTPUT(MB1_tri_state_bridge_0_address[0]); --FL_ADDR[1] is FL_ADDR[1] --operation mode is output FL_ADDR[1] = OUTPUT(MB1_tri_state_bridge_0_address[1]); --FL_ADDR[2] is FL_ADDR[2] --operation mode is output FL_ADDR[2] = OUTPUT(MB1_tri_state_bridge_0_address[2]); --FL_ADDR[3] is FL_ADDR[3] --operation mode is output FL_ADDR[3] = OUTPUT(MB1_tri_state_bridge_0_address[3]); --FL_ADDR[4] is FL_ADDR[4] --operation mode is output FL_ADDR[4] = OUTPUT(MB1_tri_state_bridge_0_address[4]); --FL_ADDR[5] is FL_ADDR[5] --operation mode is output FL_ADDR[5] = OUTPUT(MB1_tri_state_bridge_0_address[5]); --FL_ADDR[6] is FL_ADDR[6] --operation mode is output FL_ADDR[6] = OUTPUT(MB1_tri_state_bridge_0_address[6]); --FL_ADDR[7] is FL_ADDR[7] --operation mode is output FL_ADDR[7] = OUTPUT(MB1_tri_state_bridge_0_address[7]); --FL_ADDR[8] is FL_ADDR[8] --operation mode is output FL_ADDR[8] = OUTPUT(MB1_tri_state_bridge_0_address[8]); --FL_ADDR[9] is FL_ADDR[9] --operation mode is output FL_ADDR[9] = OUTPUT(MB1_tri_state_bridge_0_address[9]); --FL_ADDR[10] is FL_ADDR[10] --operation mode is output FL_ADDR[10] = OUTPUT(MB1_tri_state_bridge_0_address[10]); --FL_ADDR[11] is FL_ADDR[11] --operation mode is output FL_ADDR[11] = OUTPUT(MB1_tri_state_bridge_0_address[11]); --FL_ADDR[12] is FL_ADDR[12] --operation mode is output FL_ADDR[12] = OUTPUT(MB1_tri_state_bridge_0_address[12]); --FL_ADDR[13] is FL_ADDR[13] --operation mode is output FL_ADDR[13] = OUTPUT(MB1_tri_state_bridge_0_address[13]); --FL_ADDR[14] is FL_ADDR[14] --operation mode is output FL_ADDR[14] = OUTPUT(MB1_tri_state_bridge_0_address[14]); --FL_ADDR[15] is FL_ADDR[15] --operation mode is output FL_ADDR[15] = OUTPUT(MB1_tri_state_bridge_0_address[15]); --FL_ADDR[16] is FL_ADDR[16] --operation mode is output FL_ADDR[16] = OUTPUT(MB1_tri_state_bridge_0_address[16]); --FL_ADDR[17] is FL_ADDR[17] --operation mode is output FL_ADDR[17] = OUTPUT(MB1_tri_state_bridge_0_address[17]); --FL_ADDR[18] is FL_ADDR[18] --operation mode is output FL_ADDR[18] = OUTPUT(MB1_tri_state_bridge_0_address[18]); --FL_ADDR[19] is FL_ADDR[19] --operation mode is output FL_ADDR[19] = OUTPUT(MB1_tri_state_bridge_0_address[19]); --FL_ADDR[20] is FL_ADDR[20] --operation mode is output FL_ADDR[20] = OUTPUT(MB1_tri_state_bridge_0_address[20]); --FL_ADDR[21] is FL_ADDR[21] --operation mode is output FL_ADDR[21] = OUTPUT(MB1_tri_state_bridge_0_address[21]); --FL_WE_N is FL_WE_N --operation mode is output FL_WE_N = OUTPUT(!MB1_write_n_to_the_cfi_flash_0); --FL_RST_N is FL_RST_N --operation mode is output FL_RST_N = OUTPUT(GND); --FL_OE_N is FL_OE_N --operation mode is output FL_OE_N = OUTPUT(!MB1_tri_state_bridge_0_readn); --FL_CE_N is FL_CE_N --operation mode is output FL_CE_N = OUTPUT(!MB1_select_n_to_the_cfi_flash_0); --SRAM_ADDR[0] is SRAM_ADDR[0] --operation mode is output SRAM_ADDR[0] = OUTPUT(LB1L22); --SRAM_ADDR[1] is SRAM_ADDR[1] --operation mode is output SRAM_ADDR[1] = OUTPUT(LB1L23); --SRAM_ADDR[2] is SRAM_ADDR[2] --operation mode is output SRAM_ADDR[2] = OUTPUT(LB1L24); --SRAM_ADDR[3] is SRAM_ADDR[3] --operation mode is output SRAM_ADDR[3] = OUTPUT(LB1L25); --SRAM_ADDR[4] is SRAM_ADDR[4] --operation mode is output SRAM_ADDR[4] = OUTPUT(LB1L26); --SRAM_ADDR[5] is SRAM_ADDR[5] --operation mode is output SRAM_ADDR[5] = OUTPUT(LB1L27); --SRAM_ADDR[6] is SRAM_ADDR[6] --operation mode is output SRAM_ADDR[6] = OUTPUT(LB1L28); --SRAM_ADDR[7] is SRAM_ADDR[7] --operation mode is output SRAM_ADDR[7] = OUTPUT(LB1L29); --SRAM_ADDR[8] is SRAM_ADDR[8] --operation mode is output SRAM_ADDR[8] = OUTPUT(LB1L30); --SRAM_ADDR[9] is SRAM_ADDR[9] --operation mode is output SRAM_ADDR[9] = OUTPUT(LB1L31); --SRAM_ADDR[10] is SRAM_ADDR[10] --operation mode is output SRAM_ADDR[10] = OUTPUT(LB1L32); --SRAM_ADDR[11] is SRAM_ADDR[11] --operation mode is output SRAM_ADDR[11] = OUTPUT(LB1L33); --SRAM_ADDR[12] is SRAM_ADDR[12] --operation mode is output SRAM_ADDR[12] = OUTPUT(LB1L34); --SRAM_ADDR[13] is SRAM_ADDR[13] --operation mode is output SRAM_ADDR[13] = OUTPUT(LB1L35); --SRAM_ADDR[14] is SRAM_ADDR[14] --operation mode is output SRAM_ADDR[14] = OUTPUT(LB1L36); --SRAM_ADDR[15] is SRAM_ADDR[15] --operation mode is output SRAM_ADDR[15] = OUTPUT(LB1L37); --SRAM_ADDR[16] is SRAM_ADDR[16] --operation mode is output SRAM_ADDR[16] = OUTPUT(LB1L38); --SRAM_ADDR[17] is SRAM_ADDR[17] --operation mode is output SRAM_ADDR[17] = OUTPUT(LB1L39); --SRAM_UB_N is SRAM_UB_N --operation mode is output SRAM_UB_N = OUTPUT(GND); --SRAM_LB_N is SRAM_LB_N --operation mode is output SRAM_LB_N = OUTPUT(GND); --SRAM_WE_N is SRAM_WE_N --operation mode is output SRAM_WE_N = OUTPUT(!LB1L85); --SRAM_CE_N is SRAM_CE_N --operation mode is output SRAM_CE_N = OUTPUT(!LB1L59); --SRAM_OE_N is SRAM_OE_N --operation mode is output SRAM_OE_N = OUTPUT(!LB1_sram_0_avalonS_in_a_read_cycle); --SD_CLK is SD_CLK --operation mode is output SD_CLK = OUTPUT(GND); --TDO is TDO --operation mode is output TDO = OUTPUT(GND); --I2C_SCLK is I2C_SCLK --operation mode is output I2C_SCLK = OUTPUT(GND); --VGA_HS is VGA_HS --operation mode is output VGA_HS = OUTPUT(GND); --VGA_VS is VGA_VS --operation mode is output VGA_VS = OUTPUT(GND); --VGA_R[0] is VGA_R[0] --operation mode is output VGA_R[0] = OUTPUT(GND); --VGA_R[1] is VGA_R[1] --operation mode is output VGA_R[1] = OUTPUT(GND); --VGA_R[2] is VGA_R[2] --operation mode is output VGA_R[2] = OUTPUT(GND); --VGA_R[3] is VGA_R[3] --operation mode is output VGA_R[3] = OUTPUT(GND); --VGA_G[0] is VGA_G[0] --operation mode is output VGA_G[0] = OUTPUT(GND); --VGA_G[1] is VGA_G[1] --operation mode is output VGA_G[1] = OUTPUT(GND); --VGA_G[2] is VGA_G[2] --operation mode is output VGA_G[2] = OUTPUT(GND); --VGA_G[3] is VGA_G[3] --operation mode is output VGA_G[3] = OUTPUT(GND); --VGA_B[0] is VGA_B[0] --operation mode is output VGA_B[0] = OUTPUT(GND); --VGA_B[1] is VGA_B[1] --operation mode is output VGA_B[1] = OUTPUT(GND); --VGA_B[2] is VGA_B[2] --operation mode is output VGA_B[2] = OUTPUT(GND); --VGA_B[3] is VGA_B[3] --operation mode is output VGA_B[3] = OUTPUT(GND); --AUD_DACDAT is AUD_DACDAT --operation mode is output AUD_DACDAT = OUTPUT(GND); --AUD_XCK is AUD_XCK --operation mode is output AUD_XCK = OUTPUT(GND); --SD_DAT3 is SD_DAT3 --operation mode is bidir SD_DAT3 = BIDIR(OPNDRN(VCC)); --SD_CMD is SD_CMD --operation mode is bidir SD_CMD = BIDIR(OPNDRN(VCC)); --A1L35 is DRAM_DQ[0]~15 --operation mode is bidir A1L35 = DRAM_DQ[0]; --DRAM_DQ[0] is DRAM_DQ[0] --operation mode is bidir DRAM_DQ[0]_tri_out = TRI(HB1_m_data[0], HB1_oe); DRAM_DQ[0] = BIDIR(DRAM_DQ[0]_tri_out); --A1L37 is DRAM_DQ[1]~14 --operation mode is bidir A1L37 = DRAM_DQ[1]; --DRAM_DQ[1] is DRAM_DQ[1] --operation mode is bidir DRAM_DQ[1]_tri_out = TRI(HB1_m_data[1], HB1_oe); DRAM_DQ[1] = BIDIR(DRAM_DQ[1]_tri_out); --A1L39 is DRAM_DQ[2]~13 --operation mode is bidir A1L39 = DRAM_DQ[2]; --DRAM_DQ[2] is DRAM_DQ[2] --operation mode is bidir DRAM_DQ[2]_tri_out = TRI(HB1_m_data[2], HB1_oe); DRAM_DQ[2] = BIDIR(DRAM_DQ[2]_tri_out); --A1L41 is DRAM_DQ[3]~12 --operation mode is bidir A1L41 = DRAM_DQ[3]; --DRAM_DQ[3] is DRAM_DQ[3] --operation mode is bidir DRAM_DQ[3]_tri_out = TRI(HB1_m_data[3], HB1_oe); DRAM_DQ[3] = BIDIR(DRAM_DQ[3]_tri_out); --A1L43 is DRAM_DQ[4]~11 --operation mode is bidir A1L43 = DRAM_DQ[4]; --DRAM_DQ[4] is DRAM_DQ[4] --operation mode is bidir DRAM_DQ[4]_tri_out = TRI(HB1_m_data[4], HB1_oe); DRAM_DQ[4] = BIDIR(DRAM_DQ[4]_tri_out); --A1L45 is DRAM_DQ[5]~10 --operation mode is bidir A1L45 = DRAM_DQ[5]; --DRAM_DQ[5] is DRAM_DQ[5] --operation mode is bidir DRAM_DQ[5]_tri_out = TRI(HB1_m_data[5], HB1_oe); DRAM_DQ[5] = BIDIR(DRAM_DQ[5]_tri_out); --A1L47 is DRAM_DQ[6]~9 --operation mode is bidir A1L47 = DRAM_DQ[6]; --DRAM_DQ[6] is DRAM_DQ[6] --operation mode is bidir DRAM_DQ[6]_tri_out = TRI(HB1_m_data[6], HB1_oe); DRAM_DQ[6] = BIDIR(DRAM_DQ[6]_tri_out); --A1L49 is DRAM_DQ[7]~8 --operation mode is bidir A1L49 = DRAM_DQ[7]; --DRAM_DQ[7] is DRAM_DQ[7] --operation mode is bidir DRAM_DQ[7]_tri_out = TRI(HB1_m_data[7], HB1_oe); DRAM_DQ[7] = BIDIR(DRAM_DQ[7]_tri_out); --A1L51 is DRAM_DQ[8]~7 --operation mode is bidir A1L51 = DRAM_DQ[8]; --DRAM_DQ[8] is DRAM_DQ[8] --operation mode is bidir DRAM_DQ[8]_tri_out = TRI(HB1_m_data[8], HB1_oe); DRAM_DQ[8] = BIDIR(DRAM_DQ[8]_tri_out); --A1L53 is DRAM_DQ[9]~6 --operation mode is bidir A1L53 = DRAM_DQ[9]; --DRAM_DQ[9] is DRAM_DQ[9] --operation mode is bidir DRAM_DQ[9]_tri_out = TRI(HB1_m_data[9], HB1_oe); DRAM_DQ[9] = BIDIR(DRAM_DQ[9]_tri_out); --A1L55 is DRAM_DQ[10]~5 --operation mode is bidir A1L55 = DRAM_DQ[10]; --DRAM_DQ[10] is DRAM_DQ[10] --operation mode is bidir DRAM_DQ[10]_tri_out = TRI(HB1_m_data[10], HB1_oe); DRAM_DQ[10] = BIDIR(DRAM_DQ[10]_tri_out); --A1L57 is DRAM_DQ[11]~4 --operation mode is bidir A1L57 = DRAM_DQ[11]; --DRAM_DQ[11] is DRAM_DQ[11] --operation mode is bidir DRAM_DQ[11]_tri_out = TRI(HB1_m_data[11], HB1_oe); DRAM_DQ[11] = BIDIR(DRAM_DQ[11]_tri_out); --A1L59 is DRAM_DQ[12]~3 --operation mode is bidir A1L59 = DRAM_DQ[12]; --DRAM_DQ[12] is DRAM_DQ[12] --operation mode is bidir DRAM_DQ[12]_tri_out = TRI(HB1_m_data[12], HB1_oe); DRAM_DQ[12] = BIDIR(DRAM_DQ[12]_tri_out); --A1L61 is DRAM_DQ[13]~2 --operation mode is bidir A1L61 = DRAM_DQ[13]; --DRAM_DQ[13] is DRAM_DQ[13] --operation mode is bidir DRAM_DQ[13]_tri_out = TRI(HB1_m_data[13], HB1_oe); DRAM_DQ[13] = BIDIR(DRAM_DQ[13]_tri_out); --A1L63 is DRAM_DQ[14]~1 --operation mode is bidir A1L63 = DRAM_DQ[14]; --DRAM_DQ[14] is DRAM_DQ[14] --operation mode is bidir DRAM_DQ[14]_tri_out = TRI(HB1_m_data[14], HB1_oe); DRAM_DQ[14] = BIDIR(DRAM_DQ[14]_tri_out); --A1L65 is DRAM_DQ[15]~0 --operation mode is bidir A1L65 = DRAM_DQ[15]; --DRAM_DQ[15] is DRAM_DQ[15] --operation mode is bidir DRAM_DQ[15]_tri_out = TRI(HB1_m_data[15], HB1_oe); DRAM_DQ[15] = BIDIR(DRAM_DQ[15]_tri_out); --A1L97 is FL_DQ[0]~7 --operation mode is bidir A1L97 = FL_DQ[0]; --FL_DQ[0] is FL_DQ[0] --operation mode is bidir FL_DQ[0]_tri_out = TRI(MB1_d1_outgoing_tri_state_bridge_0_data[0], MB1_d1_in_a_write_cycle); FL_DQ[0] = BIDIR(FL_DQ[0]_tri_out); --A1L99 is FL_DQ[1]~6 --operation mode is bidir A1L99 = FL_DQ[1]; --FL_DQ[1] is FL_DQ[1] --operation mode is bidir FL_DQ[1]_tri_out = TRI(MB1_d1_outgoing_tri_state_bridge_0_data[1], MB1_d1_in_a_write_cycle); FL_DQ[1] = BIDIR(FL_DQ[1]_tri_out); --A1L101 is FL_DQ[2]~5 --operation mode is bidir A1L101 = FL_DQ[2]; --FL_DQ[2] is FL_DQ[2] --operation mode is bidir FL_DQ[2]_tri_out = TRI(MB1_d1_outgoing_tri_state_bridge_0_data[2], MB1_d1_in_a_write_cycle); FL_DQ[2] = BIDIR(FL_DQ[2]_tri_out); --A1L103 is FL_DQ[3]~4 --operation mode is bidir A1L103 = FL_DQ[3]; --FL_DQ[3] is FL_DQ[3] --operation mode is bidir FL_DQ[3]_tri_out = TRI(MB1_d1_outgoing_tri_state_bridge_0_data[3], MB1_d1_in_a_write_cycle); FL_DQ[3] = BIDIR(FL_DQ[3]_tri_out); --A1L105 is FL_DQ[4]~3 --operation mode is bidir A1L105 = FL_DQ[4]; --FL_DQ[4] is FL_DQ[4] --operation mode is bidir FL_DQ[4]_tri_out = TRI(MB1_d1_outgoing_tri_state_bridge_0_data[4], MB1_d1_in_a_write_cycle); FL_DQ[4] = BIDIR(FL_DQ[4]_tri_out); --A1L107 is FL_DQ[5]~2 --operation mode is bidir A1L107 = FL_DQ[5]; --FL_DQ[5] is FL_DQ[5] --operation mode is bidir FL_DQ[5]_tri_out = TRI(MB1_d1_outgoing_tri_state_bridge_0_data[5], MB1_d1_in_a_write_cycle); FL_DQ[5] = BIDIR(FL_DQ[5]_tri_out); --A1L109 is FL_DQ[6]~1 --operation mode is bidir A1L109 = FL_DQ[6]; --FL_DQ[6] is FL_DQ[6] --operation mode is bidir FL_DQ[6]_tri_out = TRI(MB1_d1_outgoing_tri_state_bridge_0_data[6], MB1_d1_in_a_write_cycle); FL_DQ[6] = BIDIR(FL_DQ[6]_tri_out); --A1L111 is FL_DQ[7]~0 --operation mode is bidir A1L111 = FL_DQ[7]; --FL_DQ[7] is FL_DQ[7] --operation mode is bidir FL_DQ[7]_tri_out = TRI(MB1_d1_outgoing_tri_state_bridge_0_data[7], MB1_d1_in_a_write_cycle); FL_DQ[7] = BIDIR(FL_DQ[7]_tri_out); --KE1_oDATA[0] is system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[0] --operation mode is bidir KE1_oDATA[0] = SRAM_DQ[0]; --SRAM_DQ[0] is SRAM_DQ[0] --operation mode is bidir SRAM_DQ[0]_tri_out = TRI(AB1L28, LB1L85); SRAM_DQ[0] = BIDIR(SRAM_DQ[0]_tri_out); --KE1_oDATA[1] is system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[1] --operation mode is bidir KE1_oDATA[1] = SRAM_DQ[1]; --SRAM_DQ[1] is SRAM_DQ[1] --operation mode is bidir SRAM_DQ[1]_tri_out = TRI(AB1L29, LB1L85); SRAM_DQ[1] = BIDIR(SRAM_DQ[1]_tri_out); --KE1_oDATA[2] is system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[2] --operation mode is bidir KE1_oDATA[2] = SRAM_DQ[2]; --SRAM_DQ[2] is SRAM_DQ[2] --operation mode is bidir SRAM_DQ[2]_tri_out = TRI(AB1L30, LB1L85); SRAM_DQ[2] = BIDIR(SRAM_DQ[2]_tri_out); --KE1_oDATA[3] is system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[3] --operation mode is bidir KE1_oDATA[3] = SRAM_DQ[3]; --SRAM_DQ[3] is SRAM_DQ[3] --operation mode is bidir SRAM_DQ[3]_tri_out = TRI(AB1L31, LB1L85); SRAM_DQ[3] = BIDIR(SRAM_DQ[3]_tri_out); --KE1_oDATA[4] is system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[4] --operation mode is bidir KE1_oDATA[4] = SRAM_DQ[4]; --SRAM_DQ[4] is SRAM_DQ[4] --operation mode is bidir SRAM_DQ[4]_tri_out = TRI(AB1L32, LB1L85); SRAM_DQ[4] = BIDIR(SRAM_DQ[4]_tri_out); --KE1_oDATA[5] is system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[5] --operation mode is bidir KE1_oDATA[5] = SRAM_DQ[5]; --SRAM_DQ[5] is SRAM_DQ[5] --operation mode is bidir SRAM_DQ[5]_tri_out = TRI(AB1L33, LB1L85); SRAM_DQ[5] = BIDIR(SRAM_DQ[5]_tri_out); --KE1_oDATA[6] is system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[6] --operation mode is bidir KE1_oDATA[6] = SRAM_DQ[6]; --SRAM_DQ[6] is SRAM_DQ[6] --operation mode is bidir SRAM_DQ[6]_tri_out = TRI(AB1L34, LB1L85); SRAM_DQ[6] = BIDIR(SRAM_DQ[6]_tri_out); --KE1_oDATA[7] is system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[7] --operation mode is bidir KE1_oDATA[7] = SRAM_DQ[7]; --SRAM_DQ[7] is SRAM_DQ[7] --operation mode is bidir SRAM_DQ[7]_tri_out = TRI(AB1L35, LB1L85); SRAM_DQ[7] = BIDIR(SRAM_DQ[7]_tri_out); --KE1_oDATA[8] is system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[8] --operation mode is bidir KE1_oDATA[8] = SRAM_DQ[8]; --SRAM_DQ[8] is SRAM_DQ[8] --operation mode is bidir SRAM_DQ[8]_tri_out = TRI(AB1L36, LB1L85); SRAM_DQ[8] = BIDIR(SRAM_DQ[8]_tri_out); --KE1_oDATA[9] is system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[9] --operation mode is bidir KE1_oDATA[9] = SRAM_DQ[9]; --SRAM_DQ[9] is SRAM_DQ[9] --operation mode is bidir SRAM_DQ[9]_tri_out = TRI(AB1L37, LB1L85); SRAM_DQ[9] = BIDIR(SRAM_DQ[9]_tri_out); --KE1_oDATA[10] is system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[10] --operation mode is bidir KE1_oDATA[10] = SRAM_DQ[10]; --SRAM_DQ[10] is SRAM_DQ[10] --operation mode is bidir SRAM_DQ[10]_tri_out = TRI(AB1L38, LB1L85); SRAM_DQ[10] = BIDIR(SRAM_DQ[10]_tri_out); --KE1_oDATA[11] is system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[11] --operation mode is bidir KE1_oDATA[11] = SRAM_DQ[11]; --SRAM_DQ[11] is SRAM_DQ[11] --operation mode is bidir SRAM_DQ[11]_tri_out = TRI(AB1L39, LB1L85); SRAM_DQ[11] = BIDIR(SRAM_DQ[11]_tri_out); --KE1_oDATA[12] is system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[12] --operation mode is bidir KE1_oDATA[12] = SRAM_DQ[12]; --SRAM_DQ[12] is SRAM_DQ[12] --operation mode is bidir SRAM_DQ[12]_tri_out = TRI(AB1L40, LB1L85); SRAM_DQ[12] = BIDIR(SRAM_DQ[12]_tri_out); --KE1_oDATA[13] is system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[13] --operation mode is bidir KE1_oDATA[13] = SRAM_DQ[13]; --SRAM_DQ[13] is SRAM_DQ[13] --operation mode is bidir SRAM_DQ[13]_tri_out = TRI(AB1L41, LB1L85); SRAM_DQ[13] = BIDIR(SRAM_DQ[13]_tri_out); --KE1_oDATA[14] is system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[14] --operation mode is bidir KE1_oDATA[14] = SRAM_DQ[14]; --SRAM_DQ[14] is SRAM_DQ[14] --operation mode is bidir SRAM_DQ[14]_tri_out = TRI(AB1L42, LB1L85); SRAM_DQ[14] = BIDIR(SRAM_DQ[14]_tri_out); --KE1_oDATA[15] is system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[15] --operation mode is bidir KE1_oDATA[15] = SRAM_DQ[15]; --SRAM_DQ[15] is SRAM_DQ[15] --operation mode is bidir SRAM_DQ[15]_tri_out = TRI(AB1L43, LB1L85); SRAM_DQ[15] = BIDIR(SRAM_DQ[15]_tri_out); --SD_DAT is SD_DAT --operation mode is bidir SD_DAT = BIDIR(OPNDRN(VCC)); --I2C_SDAT is I2C_SDAT --operation mode is bidir I2C_SDAT = BIDIR(OPNDRN(VCC)); --AUD_ADCLRCK is AUD_ADCLRCK --operation mode is bidir AUD_ADCLRCK = BIDIR(OPNDRN(VCC)); --AUD_DACLRCK is AUD_DACLRCK --operation mode is bidir AUD_DACLRCK = BIDIR(OPNDRN(VCC)); --AUD_BCLK is AUD_BCLK --operation mode is bidir AUD_BCLK = BIDIR(OPNDRN(VCC)); --GPIO_0[0] is GPIO_0[0] --operation mode is bidir GPIO_0[0] = BIDIR(OPNDRN(VCC)); --GPIO_0[1] is GPIO_0[1] --operation mode is bidir GPIO_0[1] = BIDIR(OPNDRN(VCC)); --GPIO_0[2] is GPIO_0[2] --operation mode is bidir GPIO_0[2] = BIDIR(OPNDRN(VCC)); --GPIO_0[3] is GPIO_0[3] --operation mode is bidir GPIO_0[3] = BIDIR(OPNDRN(VCC)); --GPIO_0[4] is GPIO_0[4] --operation mode is bidir GPIO_0[4] = BIDIR(OPNDRN(VCC)); --GPIO_0[5] is GPIO_0[5] --operation mode is bidir GPIO_0[5] = BIDIR(OPNDRN(VCC)); --GPIO_0[6] is GPIO_0[6] --operation mode is bidir GPIO_0[6] = BIDIR(OPNDRN(VCC)); --GPIO_0[7] is GPIO_0[7] --operation mode is bidir GPIO_0[7] = BIDIR(OPNDRN(VCC)); --GPIO_0[8] is GPIO_0[8] --operation mode is bidir GPIO_0[8] = BIDIR(OPNDRN(VCC)); --GPIO_0[9] is GPIO_0[9] --operation mode is bidir GPIO_0[9] = BIDIR(OPNDRN(VCC)); --GPIO_0[10] is GPIO_0[10] --operation mode is bidir GPIO_0[10] = BIDIR(OPNDRN(VCC)); --GPIO_0[11] is GPIO_0[11] --operation mode is bidir GPIO_0[11] = BIDIR(OPNDRN(VCC)); --GPIO_0[12] is GPIO_0[12] --operation mode is bidir GPIO_0[12] = BIDIR(OPNDRN(VCC)); --GPIO_0[13] is GPIO_0[13] --operation mode is bidir GPIO_0[13] = BIDIR(OPNDRN(VCC)); --GPIO_0[14] is GPIO_0[14] --operation mode is bidir GPIO_0[14] = BIDIR(OPNDRN(VCC)); --GPIO_0[15] is GPIO_0[15] --operation mode is bidir GPIO_0[15] = BIDIR(OPNDRN(VCC)); --GPIO_0[16] is GPIO_0[16] --operation mode is bidir GPIO_0[16] = BIDIR(OPNDRN(VCC)); --GPIO_0[17] is GPIO_0[17] --operation mode is bidir GPIO_0[17] = BIDIR(OPNDRN(VCC)); --GPIO_0[18] is GPIO_0[18] --operation mode is bidir GPIO_0[18] = BIDIR(OPNDRN(VCC)); --GPIO_0[19] is GPIO_0[19] --operation mode is bidir GPIO_0[19] = BIDIR(OPNDRN(VCC)); --GPIO_0[20] is GPIO_0[20] --operation mode is bidir GPIO_0[20] = BIDIR(OPNDRN(VCC)); --GPIO_0[21] is GPIO_0[21] --operation mode is bidir GPIO_0[21] = BIDIR(OPNDRN(VCC)); --GPIO_0[22] is GPIO_0[22] --operation mode is bidir GPIO_0[22] = BIDIR(OPNDRN(VCC)); --GPIO_0[23] is GPIO_0[23] --operation mode is bidir GPIO_0[23] = BIDIR(OPNDRN(VCC)); --GPIO_0[24] is GPIO_0[24] --operation mode is bidir GPIO_0[24] = BIDIR(OPNDRN(VCC)); --GPIO_0[25] is GPIO_0[25] --operation mode is bidir GPIO_0[25] = BIDIR(OPNDRN(VCC)); --GPIO_0[26] is GPIO_0[26] --operation mode is bidir GPIO_0[26] = BIDIR(OPNDRN(VCC)); --GPIO_0[27] is GPIO_0[27] --operation mode is bidir GPIO_0[27] = BIDIR(OPNDRN(VCC)); --GPIO_0[28] is GPIO_0[28] --operation mode is bidir GPIO_0[28] = BIDIR(OPNDRN(VCC)); --GPIO_0[29] is GPIO_0[29] --operation mode is bidir GPIO_0[29] = BIDIR(OPNDRN(VCC)); --GPIO_0[30] is GPIO_0[30] --operation mode is bidir GPIO_0[30] = BIDIR(OPNDRN(VCC)); --GPIO_0[31] is GPIO_0[31] --operation mode is bidir GPIO_0[31] = BIDIR(OPNDRN(VCC)); --GPIO_0[32] is GPIO_0[32] --operation mode is bidir GPIO_0[32] = BIDIR(OPNDRN(VCC)); --GPIO_0[33] is GPIO_0[33] --operation mode is bidir GPIO_0[33] = BIDIR(OPNDRN(VCC)); --GPIO_0[34] is GPIO_0[34] --operation mode is bidir GPIO_0[34] = BIDIR(OPNDRN(VCC)); --GPIO_0[35] is GPIO_0[35] --operation mode is bidir GPIO_0[35] = BIDIR(OPNDRN(VCC)); --GPIO_1[0] is GPIO_1[0] --operation mode is bidir GPIO_1[0] = BIDIR(OPNDRN(VCC)); --GPIO_1[1] is GPIO_1[1] --operation mode is bidir GPIO_1[1] = BIDIR(OPNDRN(VCC)); --GPIO_1[2] is GPIO_1[2] --operation mode is bidir GPIO_1[2] = BIDIR(OPNDRN(VCC)); --GPIO_1[3] is GPIO_1[3] --operation mode is bidir GPIO_1[3] = BIDIR(OPNDRN(VCC)); --GPIO_1[4] is GPIO_1[4] --operation mode is bidir GPIO_1[4] = BIDIR(OPNDRN(VCC)); --GPIO_1[5] is GPIO_1[5] --operation mode is bidir GPIO_1[5] = BIDIR(OPNDRN(VCC)); --GPIO_1[6] is GPIO_1[6] --operation mode is bidir GPIO_1[6] = BIDIR(OPNDRN(VCC)); --GPIO_1[7] is GPIO_1[7] --operation mode is bidir GPIO_1[7] = BIDIR(OPNDRN(VCC)); --GPIO_1[8] is GPIO_1[8] --operation mode is bidir GPIO_1[8] = BIDIR(OPNDRN(VCC)); --GPIO_1[9] is GPIO_1[9] --operation mode is bidir GPIO_1[9] = BIDIR(OPNDRN(VCC)); --GPIO_1[10] is GPIO_1[10] --operation mode is bidir GPIO_1[10] = BIDIR(OPNDRN(VCC)); --GPIO_1[11] is GPIO_1[11] --operation mode is bidir GPIO_1[11] = BIDIR(OPNDRN(VCC)); --GPIO_1[12] is GPIO_1[12] --operation mode is bidir GPIO_1[12] = BIDIR(OPNDRN(VCC)); --GPIO_1[13] is GPIO_1[13] --operation mode is bidir GPIO_1[13] = BIDIR(OPNDRN(VCC)); --GPIO_1[14] is GPIO_1[14] --operation mode is bidir GPIO_1[14] = BIDIR(OPNDRN(VCC)); --GPIO_1[15] is GPIO_1[15] --operation mode is bidir GPIO_1[15] = BIDIR(OPNDRN(VCC)); --GPIO_1[16] is GPIO_1[16] --operation mode is bidir GPIO_1[16] = BIDIR(OPNDRN(VCC)); --GPIO_1[17] is GPIO_1[17] --operation mode is bidir GPIO_1[17] = BIDIR(OPNDRN(VCC)); --GPIO_1[18] is GPIO_1[18] --operation mode is bidir GPIO_1[18] = BIDIR(OPNDRN(VCC)); --GPIO_1[19] is GPIO_1[19] --operation mode is bidir GPIO_1[19] = BIDIR(OPNDRN(VCC)); --GPIO_1[20] is GPIO_1[20] --operation mode is bidir GPIO_1[20] = BIDIR(OPNDRN(VCC)); --GPIO_1[21] is GPIO_1[21] --operation mode is bidir GPIO_1[21] = BIDIR(OPNDRN(VCC)); --GPIO_1[22] is GPIO_1[22] --operation mode is bidir GPIO_1[22] = BIDIR(OPNDRN(VCC)); --GPIO_1[23] is GPIO_1[23] --operation mode is bidir GPIO_1[23] = BIDIR(OPNDRN(VCC)); --GPIO_1[24] is GPIO_1[24] --operation mode is bidir GPIO_1[24] = BIDIR(OPNDRN(VCC)); --GPIO_1[25] is GPIO_1[25] --operation mode is bidir GPIO_1[25] = BIDIR(OPNDRN(VCC)); --GPIO_1[26] is GPIO_1[26] --operation mode is bidir GPIO_1[26] = BIDIR(OPNDRN(VCC)); --GPIO_1[27] is GPIO_1[27] --operation mode is bidir GPIO_1[27] = BIDIR(OPNDRN(VCC)); --GPIO_1[28] is GPIO_1[28] --operation mode is bidir GPIO_1[28] = BIDIR(OPNDRN(VCC)); --GPIO_1[29] is GPIO_1[29] --operation mode is bidir GPIO_1[29] = BIDIR(OPNDRN(VCC)); --GPIO_1[30] is GPIO_1[30] --operation mode is bidir GPIO_1[30] = BIDIR(OPNDRN(VCC)); --GPIO_1[31] is GPIO_1[31] --operation mode is bidir GPIO_1[31] = BIDIR(OPNDRN(VCC)); --GPIO_1[32] is GPIO_1[32] --operation mode is bidir GPIO_1[32] = BIDIR(OPNDRN(VCC)); --GPIO_1[33] is GPIO_1[33] --operation mode is bidir GPIO_1[33] = BIDIR(OPNDRN(VCC)); --GPIO_1[34] is GPIO_1[34] --operation mode is bidir GPIO_1[34] = BIDIR(OPNDRN(VCC)); --GPIO_1[35] is GPIO_1[35] --operation mode is bidir GPIO_1[35] = BIDIR(OPNDRN(VCC)); --C1L82 is Reset_Delay:delay1|Equal~249 C1L82 = !C1L81; --D1L23 is sld_hub:sld_hub_inst|hub_tdo~536 D1L23 = AMPP_FUNCTION(D1_hub_tdo);