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--Cont[24] is Cont[24]
Cont[24] = DFFEAS(A1L88, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[25] is Cont[25]
Cont[25] = DFFEAS(A1L91, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[26] is Cont[26]
Cont[26] = DFFEAS(A1L94, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[27] is Cont[27]
Cont[27] = DFFEAS(A1L97, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--L1L1 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[0]~70
L1L1 = Cont[26] & !Cont[25] & (Cont[24] $ !Cont[27]) # !Cont[26] & Cont[24] & (Cont[25] $ !Cont[27]);


--L1L2 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[1]~71
L1L2 = Cont[25] & (Cont[24] & (Cont[27]) # !Cont[24] & Cont[26]) # !Cont[25] & Cont[26] & (Cont[24] $ Cont[27]);


--L1L3 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[2]~72
L1L3 = Cont[26] & Cont[27] & (Cont[25] # !Cont[24]) # !Cont[26] & !Cont[24] & Cont[25] & !Cont[27];


--L1L4 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[3]~73
L1L4 = Cont[24] & (Cont[25] $ !Cont[26]) # !Cont[24] & (Cont[25] & !Cont[26] & Cont[27] # !Cont[25] & Cont[26] & !Cont[27]);


--L1L5 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[4]~74
L1L5 = Cont[25] & Cont[24] & (!Cont[27]) # !Cont[25] & (Cont[26] & (!Cont[27]) # !Cont[26] & Cont[24]);


--L1L6 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[5]~75
L1L6 = Cont[24] & (Cont[27] $ (Cont[25] # !Cont[26])) # !Cont[24] & Cont[25] & !Cont[26] & !Cont[27];


--L1L7 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[6]~76
L1L7 = Cont[24] & (Cont[27] # Cont[25] $ Cont[26]) # !Cont[24] & (Cont[25] # Cont[26] $ Cont[27]);


--D1_mLED[0] is LEDG_Driver:u2|mLED[0]
D1_mLED[0] = DFFEAS(D1L79, D1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--D1_mLED[1] is LEDG_Driver:u2|mLED[1]
D1_mLED[1] = DFFEAS(D1L80, D1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--D1_mLED[2] is LEDG_Driver:u2|mLED[2]
D1_mLED[2] = DFFEAS(D1L81, D1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--D1_mLED[3] is LEDG_Driver:u2|mLED[3]
D1_mLED[3] = DFFEAS(D1L82, D1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--D1_mLED[4] is LEDG_Driver:u2|mLED[4]
D1_mLED[4] = DFFEAS(D1L83, D1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--D1_mLED[5] is LEDG_Driver:u2|mLED[5]
D1_mLED[5] = DFFEAS(D1L84, D1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--D1_mLED[6] is LEDG_Driver:u2|mLED[6]
D1_mLED[6] = DFFEAS(D1L85, D1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--D1_mLED[7] is LEDG_Driver:u2|mLED[7]
D1_mLED[7] = DFFEAS(D1L86, D1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[0] is LEDR_Driver:u1|mLED[0]
C1_mLED[0] = DFFEAS(C1L81, C1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[1] is LEDR_Driver:u1|mLED[1]
C1_mLED[1] = DFFEAS(C1L82, C1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[2] is LEDR_Driver:u1|mLED[2]
C1_mLED[2] = DFFEAS(C1L83, C1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[3] is LEDR_Driver:u1|mLED[3]
C1_mLED[3] = DFFEAS(C1L84, C1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[4] is LEDR_Driver:u1|mLED[4]
C1_mLED[4] = DFFEAS(C1L85, C1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[5] is LEDR_Driver:u1|mLED[5]
C1_mLED[5] = DFFEAS(C1L86, C1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[6] is LEDR_Driver:u1|mLED[6]
C1_mLED[6] = DFFEAS(C1L87, C1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[7] is LEDR_Driver:u1|mLED[7]
C1_mLED[7] = DFFEAS(C1L88, C1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[8] is LEDR_Driver:u1|mLED[8]
C1_mLED[8] = DFFEAS(C1L89, C1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[9] is LEDR_Driver:u1|mLED[9]
C1_mLED[9] = DFFEAS(C1L90, C1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--V1L40Q is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[0]~reg0
V1L40Q = DFFEAS(V1L38, J1_mI2C_CTRL_CLK, KEY[0],  ,  , VCC,  ,  , !J1_mI2C_GO);


--V1L46Q is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[2]~reg0
V1L46Q = DFFEAS(V1L44, J1_mI2C_CTRL_CLK, KEY[0],  ,  , VCC,  ,  , !J1_mI2C_GO);


--V1L49Q is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[3]~reg0
V1L49Q = DFFEAS(V1L47, J1_mI2C_CTRL_CLK, KEY[0],  ,  , VCC,  ,  , !J1_mI2C_GO);


--V1L43Q is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[1]~reg0
V1L43Q = DFFEAS(V1L41, J1_mI2C_CTRL_CLK, KEY[0],  ,  , VCC,  ,  , !J1_mI2C_GO);


--V1L15 is I2C_AV_Config:u7|I2C_Controller:u0|I2C_SCLK~253
V1L15 = V1L40Q # V1L46Q # V1L49Q # V1L43Q;


--V1L52Q is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[4]~reg0
V1L52Q = DFFEAS(V1L50, J1_mI2C_CTRL_CLK, KEY[0],  ,  , VCC,  ,  , !J1_mI2C_GO);


--V1L16 is I2C_AV_Config:u7|I2C_Controller:u0|I2C_SCLK~254
V1L16 = V1L52Q & (!V1L49Q # !V1L46Q) # !V1L52Q & V1L15;


--V1L55Q is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[5]~reg0
V1L55Q = DFFEAS(V1L53, J1_mI2C_CTRL_CLK, KEY[0],  ,  , VCC,  ,  , !J1_mI2C_GO);


--J1_mI2C_CTRL_CLK is I2C_AV_Config:u7|mI2C_CTRL_CLK
J1_mI2C_CTRL_CLK = DFFEAS(J1L72, CLOCK_50, KEY[0],  ,  ,  ,  ,  ,  );


--V1_SCLK is I2C_AV_Config:u7|I2C_Controller:u0|SCLK
V1_SCLK = DFFEAS(V1L23, J1_mI2C_CTRL_CLK, KEY[0],  ,  ,  ,  ,  ,  );


--V1L17 is I2C_AV_Config:u7|I2C_Controller:u0|I2C_SCLK~255
V1L17 = V1L16 & V1L55Q & !J1_mI2C_CTRL_CLK # !V1_SCLK;


--F1_oVGA_H_SYNC is VGA_Controller:u4|oVGA_H_SYNC
F1_oVGA_H_SYNC = DFFEAS(F1L56, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--F1_oVGA_V_SYNC is VGA_Controller:u4|oVGA_V_SYNC
F1_oVGA_V_SYNC = DFFEAS(F1L265, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--F1_Cur_Color_R[7] is VGA_Controller:u4|Cur_Color_R[7]
F1_Cur_Color_R[7] = DFFEAS(A1L399, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--F1_H_Cont[5] is VGA_Controller:u4|H_Cont[5]
F1_H_Cont[5] = DFFEAS(F1L37, M1__clk0, KEY[0],  ,  ,  ,  , F1L57,  );


--F1_H_Cont[6] is VGA_Controller:u4|H_Cont[6]
F1_H_Cont[6] = DFFEAS(F1L40, M1__clk0, KEY[0],  ,  ,  ,  , F1L57,  );


--F1L15 is VGA_Controller:u4|Equal~110
F1L15 = !F1_H_Cont[5] & !F1_H_Cont[6];


--F1_H_Cont[0] is VGA_Controller:u4|H_Cont[0]
F1_H_Cont[0] = DFFEAS(F1L22, M1__clk0, KEY[0],  ,  ,  ,  , F1L57,  );


--F1_H_Cont[1] is VGA_Controller:u4|H_Cont[1]
F1_H_Cont[1] = DFFEAS(F1L25, M1__clk0, KEY[0],  ,  ,  ,  , F1L57,  );


--F1_H_Cont[2] is VGA_Controller:u4|H_Cont[2]
F1_H_Cont[2] = DFFEAS(F1L28, M1__clk0, KEY[0],  ,  ,  ,  , F1L57,  );


--F1_H_Cont[3] is VGA_Controller:u4|H_Cont[3]
F1_H_Cont[3] = DFFEAS(F1L31, M1__clk0, KEY[0],  ,  ,  ,  , F1L57,  );


--F1L51 is VGA_Controller:u4|LessThan~1165
F1L51 = !F1_H_Cont[0] & !F1_H_Cont[1] # !F1_H_Cont[3] # !F1_H_Cont[2];


--F1_H_Cont[4] is VGA_Controller:u4|H_Cont[4]
F1_H_Cont[4] = DFFEAS(F1L34, M1__clk0, KEY[0],  ,  ,  ,  , F1L57,  );


--F1_H_Cont[7] is VGA_Controller:u4|H_Cont[7]
F1_H_Cont[7] = DFFEAS(F1L43, M1__clk0, KEY[0],  ,  ,  ,  , F1L57,  );


--F1_H_Cont[8] is VGA_Controller:u4|H_Cont[8]
F1_H_Cont[8] = DFFEAS(F1L46, M1__clk0, KEY[0],  ,  ,  ,  , F1L57,  );


--F1_H_Cont[9] is VGA_Controller:u4|H_Cont[9]
F1_H_Cont[9] = DFFEAS(F1L49, M1__clk0, KEY[0],  ,  ,  ,  , F1L57,  );


--F1L262 is VGA_Controller:u4|oVGA_R~305
F1L262 = F1L61 & !F1_H_Cont[7] # !F1_H_Cont[9] # !F1_H_Cont[8];


--F1_V_Cont[6] is VGA_Controller:u4|V_Cont[6]
F1_V_Cont[6] = DFFEAS(F1L84, M1__clk0, KEY[0],  , F1L19,  ,  , F1L60,  );


--F1_V_Cont[7] is VGA_Controller:u4|V_Cont[7]
F1_V_Cont[7] = DFFEAS(F1L87, M1__clk0, KEY[0],  , F1L19,  ,  , F1L60,  );


--F1_V_Cont[8] is VGA_Controller:u4|V_Cont[8]
F1_V_Cont[8] = DFFEAS(F1L90, M1__clk0, KEY[0],  , F1L19,  ,  , F1L60,  );


--F1L52 is VGA_Controller:u4|LessThan~1166
F1L52 = !F1_V_Cont[6] & !F1_V_Cont[7] & !F1_V_Cont[8];


--F1_V_Cont[1] is VGA_Controller:u4|V_Cont[1]
F1_V_Cont[1] = DFFEAS(F1L69, M1__clk0, KEY[0],  , F1L19,  ,  , F1L60,  );


--F1_V_Cont[2] is VGA_Controller:u4|V_Cont[2]
F1_V_Cont[2] = DFFEAS(F1L72, M1__clk0, KEY[0],  , F1L19,  ,  , F1L60,  );


--F1_V_Cont[3] is VGA_Controller:u4|V_Cont[3]
F1_V_Cont[3] = DFFEAS(F1L75, M1__clk0, KEY[0],  , F1L19,  ,  , F1L60,  );


--F1L53 is VGA_Controller:u4|LessThan~1167
F1L53 = !F1_V_Cont[1] & !F1_V_Cont[2] & !F1_V_Cont[3];


--F1_V_Cont[4] is VGA_Controller:u4|V_Cont[4]
F1_V_Cont[4] = DFFEAS(F1L78, M1__clk0, KEY[0],  , F1L19,  ,  , F1L60,  );


--F1_V_Cont[5] is VGA_Controller:u4|V_Cont[5]
F1_V_Cont[5] = DFFEAS(F1L81, M1__clk0, KEY[0],  , F1L19,  ,  , F1L60,  );


--F1L54 is VGA_Controller:u4|LessThan~1168
F1L54 = F1L53 & !F1_V_Cont[4] # !F1_V_Cont[5];


--F1_V_Cont[9] is VGA_Controller:u4|V_Cont[9]
F1_V_Cont[9] = DFFEAS(F1L93, M1__clk0, KEY[0],  , F1L19,  ,  , F1L60,  );


--F1L55 is VGA_Controller:u4|LessThan~1169
F1L55 = F1_V_Cont[4] # F1_V_Cont[5] # !F1L53 # !F1L52;


--F1L263 is VGA_Controller:u4|oVGA_R~306
F1L263 = F1_V_Cont[9] & (!F1L55) # !F1_V_Cont[9] & (!F1L54 # !F1L52);


--F1L16 is VGA_Controller:u4|Equal~111
F1L16 = !F1_H_Cont[8] & !F1_H_Cont[9];


--F1L259 is VGA_Controller:u4|oVGA_R[6]~307
F1L259 = F1_Cur_Color_R[7] & F1L262 & F1L263 & !F1L62;


--F1_Cur_Color_R[8] is VGA_Controller:u4|Cur_Color_R[8]
F1_Cur_Color_R[8] = DFFEAS(A1L400, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--F1L260 is VGA_Controller:u4|oVGA_R[8]~308
F1L260 = F1L262 & F1L263 & F1_Cur_Color_R[8] & !F1L62;


--F1_Cur_Color_R[9] is VGA_Controller:u4|Cur_Color_R[9]
F1_Cur_Color_R[9] = DFFEAS(A1L401, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--F1L261 is VGA_Controller:u4|oVGA_R[9]~309
F1L261 = F1L262 & F1L263 & F1_Cur_Color_R[9] & !F1L62;


--F1_Cur_Color_G[6] is VGA_Controller:u4|Cur_Color_G[6]
F1_Cur_Color_G[6] = DFFEAS(A1L395, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--F1L254 is VGA_Controller:u4|oVGA_G[6]~60
F1L254 = F1L262 & F1L263 & F1_Cur_Color_G[6] & !F1L62;


--F1_Cur_Color_G[7] is VGA_Controller:u4|Cur_Color_G[7]
F1_Cur_Color_G[7] = DFFEAS(A1L396, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--F1L255 is VGA_Controller:u4|oVGA_G[7]~61
F1L255 = F1L262 & F1L263 & F1_Cur_Color_G[7] & !F1L62;


--F1_Cur_Color_G[8] is VGA_Controller:u4|Cur_Color_G[8]
F1_Cur_Color_G[8] = DFFEAS(A1L397, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--F1L256 is VGA_Controller:u4|oVGA_G[8]~62
F1L256 = F1L262 & F1L263 & F1_Cur_Color_G[8] & !F1L62;


--F1_Cur_Color_G[9] is VGA_Controller:u4|Cur_Color_G[9]
F1_Cur_Color_G[9] = DFFEAS(A1L398, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--F1L257 is VGA_Controller:u4|oVGA_G[9]~63
F1L257 = F1L262 & F1L263 & F1_Cur_Color_G[9] & !F1L62;


--F1_Cur_Color_B[6] is VGA_Controller:u4|Cur_Color_B[6]
F1_Cur_Color_B[6] = DFFEAS(A1L391, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--F1L250 is VGA_Controller:u4|oVGA_B[6]~60
F1L250 = F1L262 & F1L263 & F1_Cur_Color_B[6] & !F1L62;


--F1_Cur_Color_B[7] is VGA_Controller:u4|Cur_Color_B[7]
F1_Cur_Color_B[7] = DFFEAS(A1L392, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--F1L251 is VGA_Controller:u4|oVGA_B[7]~61
F1L251 = F1L262 & F1L263 & F1_Cur_Color_B[7] & !F1L62;


--F1_Cur_Color_B[8] is VGA_Controller:u4|Cur_Color_B[8]
F1_Cur_Color_B[8] = DFFEAS(A1L393, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--F1L252 is VGA_Controller:u4|oVGA_B[8]~62
F1L252 = F1L262 & F1L263 & F1_Cur_Color_B[8] & !F1L62;


--F1_Cur_Color_B[9] is VGA_Controller:u4|Cur_Color_B[9]
F1_Cur_Color_B[9] = DFFEAS(A1L394, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--F1L253 is VGA_Controller:u4|oVGA_B[9]~63
F1L253 = F1L262 & F1L263 & F1_Cur_Color_B[9] & !F1L62;


--K1_LRCK_1X is AUDIO_DAC:u8|LRCK_1X
K1_LRCK_1X = DFFEAS(K1L37, M1__clk1, KEY[0],  ,  ,  ,  ,  ,  );


--K1L131Q is AUDIO_DAC:u8|rom~47
K1L131Q = DFFEAS(K1L141, !K1_LRCK_1X, KEY[0],  ,  ,  ,  , K1L42,  );


--K1_SEL_Cont[1] is AUDIO_DAC:u8|SEL_Cont[1]
K1_SEL_Cont[1] = DFFEAS(K1L118, !K1_oAUD_BCK, KEY[0],  ,  ,  ,  ,  ,  );


--K1_SEL_Cont[3] is AUDIO_DAC:u8|SEL_Cont[3]
K1_SEL_Cont[3] = DFFEAS(K1L122, !K1_oAUD_BCK, KEY[0],  ,  ,  ,  ,  ,  );


--K1L129Q is AUDIO_DAC:u8|rom~45
K1L129Q = DFFEAS(K1L137, !K1_LRCK_1X, KEY[0],  ,  ,  ,  , K1L42,  );


--K1_SEL_Cont[0] is AUDIO_DAC:u8|SEL_Cont[0]
K1_SEL_Cont[0] = DFFEAS(K1L116, !K1_oAUD_BCK, KEY[0],  ,  ,  ,  ,  ,  );


--K1L43 is AUDIO_DAC:u8|Mux~1930
K1L43 = K1L129Q & (K1_SEL_Cont[3] & !K1_SEL_Cont[1] & !K1_SEL_Cont[0] # !K1_SEL_Cont[3] & (K1_SEL_Cont[0])) # !K1L129Q & K1_SEL_Cont[1] & (K1_SEL_Cont[3] $ !K1_SEL_Cont[0]);


--K1L128Q is AUDIO_DAC:u8|rom~44
K1L128Q = DFFEAS(K1L135, !K1_LRCK_1X, KEY[0],  ,  ,  ,  , K1L42,  );


--K1_SEL_Cont[2] is AUDIO_DAC:u8|SEL_Cont[2]
K1_SEL_Cont[2] = DFFEAS(K1L120, !K1_oAUD_BCK, KEY[0],  ,  ,  ,  ,  ,  );


--K1L44 is AUDIO_DAC:u8|Mux~1931
K1L44 = K1L129Q & (K1_SEL_Cont[1] & K1_SEL_Cont[3] & K1_SEL_Cont[2] # !K1_SEL_Cont[1] & !K1_SEL_Cont[3] & !K1_SEL_Cont[2]);


--K1L45 is AUDIO_DAC:u8|Mux~1932
K1L45 = K1L128Q & (K1_SEL_Cont[2]) # !K1L128Q & K1L44 & (K1_SEL_Cont[0] # !K1_SEL_Cont[2]);


--K1L46 is AUDIO_DAC:u8|Mux~1933
K1L46 = K1_SEL_Cont[3] & (K1_SEL_Cont[1] & K1_SEL_Cont[0] # !K1L129Q) # !K1_SEL_Cont[3] & (K1L129Q & (!K1_SEL_Cont[0]) # !K1L129Q & K1_SEL_Cont[1] & K1_SEL_Cont[0]);


--K1L47 is AUDIO_DAC:u8|Mux~1934
K1L47 = K1L128Q & (K1L45 & (!K1L46) # !K1L45 & !K1L43) # !K1L128Q & (K1L45);


--K1L130Q is AUDIO_DAC:u8|rom~46
K1L130Q = DFFEAS(K1L139, !K1_LRCK_1X, KEY[0],  ,  ,  ,  , K1L42,  );


--K1L48 is AUDIO_DAC:u8|Mux~1935
K1L48 = K1_SEL_Cont[1] & !K1_SEL_Cont[2] & (K1_SEL_Cont[0] # !K1L128Q);


--K1L49 is AUDIO_DAC:u8|Mux~1936
K1L49 = K1_SEL_Cont[1] & !K1_SEL_Cont[2] & (K1_SEL_Cont[0] # !K1L128Q) # !K1_SEL_Cont[1] & K1_SEL_Cont[0] & (K1_SEL_Cont[2] # !K1L128Q);


--K1L50 is AUDIO_DAC:u8|Mux~1937
K1L50 = K1_SEL_Cont[1] & (K1_SEL_Cont[2] & (K1_SEL_Cont[0]) # !K1_SEL_Cont[2] & !K1L128Q & !K1_SEL_Cont[0]) # !K1_SEL_Cont[1] & (K1_SEL_Cont[0] # K1L128Q & K1_SEL_Cont[2]);


--K1L51 is AUDIO_DAC:u8|Mux~1938
K1L51 = K1L129Q & (K1_SEL_Cont[3]) # !K1L129Q & (K1_SEL_Cont[3] & !K1L49 # !K1_SEL_Cont[3] & (K1L50));


--K1L52 is AUDIO_DAC:u8|Mux~1939
K1L52 = K1L128Q & (K1_SEL_Cont[2] $ (!K1_SEL_Cont[1] & K1_SEL_Cont[0])) # !K1L128Q & !K1_SEL_Cont[1] & K1_SEL_Cont[2] & K1_SEL_Cont[0];


--K1L53 is AUDIO_DAC:u8|Mux~1940
K1L53 = K1L129Q & (K1L51 & (!K1L52) # !K1L51 & K1L48) # !K1L129Q & (K1L51);


--K1L127Q is AUDIO_DAC:u8|rom~43
K1L127Q = DFFEAS(K1L133, !K1_LRCK_1X, KEY[0],  ,  ,  ,  , K1L42,  );


--K1L54 is AUDIO_DAC:u8|Mux~1941
K1L54 = !K1L129Q & (K1_SEL_Cont[2] & !K1_SEL_Cont[3] & !K1_SEL_Cont[0] # !K1_SEL_Cont[2] & (K1_SEL_Cont[3] $ K1_SEL_Cont[0]));


--K1L55 is AUDIO_DAC:u8|Mux~1942
K1L55 = K1L129Q # K1_SEL_Cont[0] $ !K1_SEL_Cont[3];


--K1L56 is AUDIO_DAC:u8|Mux~1943
K1L56 = K1_SEL_Cont[2] & (K1L129Q # !K1_SEL_Cont[0] # !K1_SEL_Cont[3]) # !K1_SEL_Cont[2] & (K1_SEL_Cont[3] # !K1L129Q & K1_SEL_Cont[0]);


--K1L57 is AUDIO_DAC:u8|Mux~1944
K1L57 = K1L128Q & (K1_SEL_Cont[1]) # !K1L128Q & (K1_SEL_Cont[1] & K1L55 # !K1_SEL_Cont[1] & (K1L56));


--K1L58 is AUDIO_DAC:u8|Mux~1945
K1L58 = K1_SEL_Cont[3] & (K1_SEL_Cont[2] & !K1L129Q & K1_SEL_Cont[0] # !K1_SEL_Cont[2] & K1L129Q & !K1_SEL_Cont[0]) # !K1_SEL_Cont[3] & (K1_SEL_Cont[2] $ K1L129Q $ K1_SEL_Cont[0]);


--K1L59 is AUDIO_DAC:u8|Mux~1946
K1L59 = K1L128Q & (K1L57 & (K1L58) # !K1L57 & K1L54) # !K1L128Q & (K1L57);


--K1L60 is AUDIO_DAC:u8|Mux~1947
K1L60 = K1L130Q & (K1L127Q) # !K1L130Q & (K1L127Q & K1L53 # !K1L127Q & (K1L59));


--K1L61 is AUDIO_DAC:u8|Mux~1948
K1L61 = K1_SEL_Cont[0] & (K1_SEL_Cont[1] $ (K1L128Q & K1_SEL_Cont[2])) # !K1_SEL_Cont[0] & K1_SEL_Cont[1] & (K1L128Q $ K1_SEL_Cont[2]);


--K1L62 is AUDIO_DAC:u8|Mux~1949
K1L62 = K1L128Q & !K1_SEL_Cont[1] & K1_SEL_Cont[0] # !K1L128Q & (K1_SEL_Cont[2]);


--K1L63 is AUDIO_DAC:u8|Mux~1950
K1L63 = K1L129Q & (K1L62 & K1_SEL_Cont[0] # !K1L62 & (K1L61)) # !K1L129Q & (K1L62 $ (K1_SEL_Cont[0] & !K1L61));


--K1L64 is AUDIO_DAC:u8|Mux~1951
K1L64 = K1L61 & (K1L62 $ (!K1_SEL_Cont[0] # !K1L129Q)) # !K1L61 & K1L129Q & (K1_SEL_Cont[0] # K1L62);


--K1L65 is AUDIO_DAC:u8|Mux~1952
K1L65 = K1_SEL_Cont[3] & K1L63 # !K1_SEL_Cont[3] & (!K1L64);


--K1L66 is AUDIO_DAC:u8|Mux~1953
K1L66 = K1L130Q & (K1L60 & (K1L65) # !K1L60 & K1L47) # !K1L130Q & (K1L60);


--K1L132Q is AUDIO_DAC:u8|rom~48
K1L132Q = DFFEAS(K1L143, !K1_LRCK_1X, KEY[0],  ,  ,  ,  , K1L42,  );


--K1L67 is AUDIO_DAC:u8|Mux~1954
K1L67 = K1_SEL_Cont[1] & (K1L130Q # !K1_SEL_Cont[3] # !K1_SEL_Cont[0]) # !K1_SEL_Cont[1] & (K1_SEL_Cont[3] # K1_SEL_Cont[0] & !K1L130Q);


--K1L68 is AUDIO_DAC:u8|Mux~1955
K1L68 = K1_SEL_Cont[3] & K1L130Q & (K1_SEL_Cont[1] # !K1_SEL_Cont[0]) # !K1_SEL_Cont[3] & (K1_SEL_Cont[0] $ (K1_SEL_Cont[1] & !K1L130Q));


--K1L69 is AUDIO_DAC:u8|Mux~1956
K1L69 = K1_SEL_Cont[1] & !K1_SEL_Cont[3] & (!K1L130Q # !K1_SEL_Cont[0]) # !K1_SEL_Cont[1] & (K1_SEL_Cont[0] $ (K1_SEL_Cont[3] & K1L130Q));


--K1L70 is AUDIO_DAC:u8|Mux~1957
K1L70 = K1L129Q & (K1_SEL_Cont[2]) # !K1L129Q & (K1_SEL_Cont[2] & !K1L68 # !K1_SEL_Cont[2] & (!K1L69));


--K1L71 is AUDIO_DAC:u8|Mux~1958
K1L71 = K1_SEL_Cont[0] & (K1_SEL_Cont[1] # K1L130Q) # !K1_SEL_Cont[0] & (K1_SEL_Cont[3] & !K1_SEL_Cont[1] & !K1L130Q # !K1_SEL_Cont[3] & (K1L130Q));


--K1L72 is AUDIO_DAC:u8|Mux~1959
K1L72 = K1L129Q & (K1L70 & (K1L71) # !K1L70 & !K1L67) # !K1L129Q & (K1L70);


--K1L73 is AUDIO_DAC:u8|Mux~1960
K1L73 = K1_SEL_Cont[3] & (K1L129Q & (K1_SEL_Cont[2]) # !K1L129Q & !K1_SEL_Cont[0] & !K1_SEL_Cont[2]) # !K1_SEL_Cont[3] & !K1L129Q & (K1_SEL_Cont[0] $ K1_SEL_Cont[2]);


--K1L74 is AUDIO_DAC:u8|Mux~1961
K1L74 = K1_SEL_Cont[0] & (K1_SEL_Cont[3] & (K1_SEL_Cont[1]) # !K1_SEL_Cont[3] & !K1_SEL_Cont[2] & !K1_SEL_Cont[1]) # !K1_SEL_Cont[0] & !K1_SEL_Cont[1] & (K1_SEL_Cont[3] $ K1_SEL_Cont[2]);


--K1L75 is AUDIO_DAC:u8|Mux~1962
K1L75 = K1_SEL_Cont[1] $ (!K1L130Q & !K1L74);


--K1L76 is AUDIO_DAC:u8|Mux~1963
K1L76 = K1_SEL_Cont[3] & (K1_SEL_Cont[0] & (K1L129Q # K1_SEL_Cont[2]) # !K1_SEL_Cont[0] & K1L129Q & K1_SEL_Cont[2]) # !K1_SEL_Cont[3] & (K1_SEL_Cont[0] $ K1L129Q $ K1_SEL_Cont[2]);


--K1L77 is AUDIO_DAC:u8|Mux~1964
K1L77 = K1L130Q & (K1L75 & (!K1L76) # !K1L75 & !K1L73) # !K1L130Q & (K1L75);


--K1L78 is AUDIO_DAC:u8|Mux~1965
K1L78 = K1_SEL_Cont[0] & (K1_SEL_Cont[3] & K1_SEL_Cont[2] # !K1_SEL_Cont[3] & (K1_SEL_Cont[1])) # !K1_SEL_Cont[0] & (K1_SEL_Cont[1] & (K1_SEL_Cont[3]) # !K1_SEL_Cont[1] & !K1_SEL_Cont[2] & !K1_SEL_Cont[3]);


--K1L79 is AUDIO_DAC:u8|Mux~1966
K1L79 = K1_SEL_Cont[2] # K1_SEL_Cont[3] # K1_SEL_Cont[0] & !K1L130Q;


--K1L80 is AUDIO_DAC:u8|Mux~1967
K1L80 = K1L129Q & (!K1_SEL_Cont[1] & !K1L79) # !K1L129Q & K1L78;


--K1L81 is AUDIO_DAC:u8|Mux~1968
K1L81 = K1L127Q & (K1L128Q) # !K1L127Q & (K1L128Q & K1L77 # !K1L128Q & (K1L80));


--K1L82 is AUDIO_DAC:u8|Mux~1969
K1L82 = K1L130Q & (K1_SEL_Cont[0] & K1_SEL_Cont[1] # !K1_SEL_Cont[0] & (K1_SEL_Cont[3])) # !K1L130Q & (K1_SEL_Cont[1] & (!K1_SEL_Cont[3]) # !K1_SEL_Cont[1] & K1_SEL_Cont[0]);


--K1L83 is AUDIO_DAC:u8|Mux~1970
K1L83 = K1_SEL_Cont[1] & (K1_SEL_Cont[0] $ (!K1_SEL_Cont[3] & K1L130Q)) # !K1_SEL_Cont[1] & K1_SEL_Cont[3] & (K1_SEL_Cont[0] $ !K1L130Q);


--K1L84 is AUDIO_DAC:u8|Mux~1971
K1L84 = K1_SEL_Cont[1] & (K1_SEL_Cont[3] & !K1_SEL_Cont[0] # !K1_SEL_Cont[3] & (!K1L130Q)) # !K1_SEL_Cont[1] & (K1_SEL_Cont[0] # K1_SEL_Cont[3]);


--K1L85 is AUDIO_DAC:u8|Mux~1972
K1L85 = K1L129Q & (K1_SEL_Cont[2]) # !K1L129Q & (K1_SEL_Cont[2] & K1L83 # !K1_SEL_Cont[2] & (!K1L84));


--K1L86 is AUDIO_DAC:u8|Mux~1973
K1L86 = K1_SEL_Cont[0] & !K1_SEL_Cont[1] & (K1_SEL_Cont[3] $ !K1L130Q) # !K1_SEL_Cont[0] & K1_SEL_Cont[1] & !K1_SEL_Cont[3] & !K1L130Q;


--K1L87 is AUDIO_DAC:u8|Mux~1974
K1L87 = K1L129Q & (K1L85 & (!K1L86) # !K1L85 & !K1L82) # !K1L129Q & (K1L85);


--K1L88 is AUDIO_DAC:u8|Mux~1975
K1L88 = K1L127Q & (K1L81 & (K1L87) # !K1L81 & K1L72) # !K1L127Q & (K1L81);


--K1L89 is AUDIO_DAC:u8|Mux~1976
K1L89 = K1_SEL_Cont[0] & (K1_SEL_Cont[1] $ (!K1L127Q & K1L128Q)) # !K1_SEL_Cont[0] & K1L127Q & !K1L128Q & !K1_SEL_Cont[1];


--K1L90 is AUDIO_DAC:u8|Mux~1977
K1L90 = K1_SEL_Cont[0] & (K1L127Q & (K1_SEL_Cont[1]) # !K1L127Q & K1L128Q) # !K1_SEL_Cont[0] & !K1L128Q & (K1L127Q # K1_SEL_Cont[1]);


--K1L91 is AUDIO_DAC:u8|Mux~1978
K1L91 = K1_SEL_Cont[1] & (K1L127Q # K1L128Q # !K1_SEL_Cont[0]) # !K1_SEL_Cont[1] & (K1_SEL_Cont[0]);


--K1L92 is AUDIO_DAC:u8|Mux~1979
K1L92 = K1_SEL_Cont[2] & (K1_SEL_Cont[3]) # !K1_SEL_Cont[2] & (K1_SEL_Cont[3] & !K1L90 # !K1_SEL_Cont[3] & (K1L91));


--K1L93 is AUDIO_DAC:u8|Mux~1980
K1L93 = K1L128Q & (K1_SEL_Cont[1] & (K1_SEL_Cont[0]) # !K1_SEL_Cont[1] & (!K1_SEL_Cont[0] # !K1L127Q)) # !K1L128Q & (K1L127Q # K1_SEL_Cont[1] $ K1_SEL_Cont[0]);


--K1L94 is AUDIO_DAC:u8|Mux~1981
K1L94 = K1_SEL_Cont[2] & (K1L92 & (!K1L93) # !K1L92 & !K1L89) # !K1_SEL_Cont[2] & (K1L92);


--K1L95 is AUDIO_DAC:u8|Mux~1982
K1L95 = K1_SEL_Cont[3] & (!K1_SEL_Cont[1] & !K1_SEL_Cont[0]) # !K1_SEL_Cont[3] & (K1_SEL_Cont[0] $ (K1L127Q & K1_SEL_Cont[1]));


--K1L96 is AUDIO_DAC:u8|Mux~1983
K1L96 = K1L127Q & (K1_SEL_Cont[3] & !K1_SEL_Cont[1] & K1_SEL_Cont[0] # !K1_SEL_Cont[3] & K1_SEL_Cont[1] & !K1_SEL_Cont[0]);


--K1L97 is AUDIO_DAC:u8|Mux~1984
K1L97 = K1L127Q & (K1_SEL_Cont[0] & (!K1_SEL_Cont[1]) # !K1_SEL_Cont[0] & K1_SEL_Cont[3]) # !K1L127Q & (K1_SEL_Cont[3] # K1_SEL_Cont[1]);


--K1L98 is AUDIO_DAC:u8|Mux~1985
K1L98 = K1L128Q & (K1_SEL_Cont[2]) # !K1L128Q & (K1_SEL_Cont[2] & !K1L96 # !K1_SEL_Cont[2] & (K1L97));


--K1L99 is AUDIO_DAC:u8|Mux~1986
K1L99 = K1_SEL_Cont[3] & (K1_SEL_Cont[0] & (!K1_SEL_Cont[1]) # !K1_SEL_Cont[0] & !K1L127Q) # !K1_SEL_Cont[3] & (K1L127Q $ (K1_SEL_Cont[0]));


--K1L100 is AUDIO_DAC:u8|Mux~1987
K1L100 = K1L128Q & (K1L98 & (!K1L99) # !K1L98 & K1L95) # !K1L128Q & (K1L98);


--K1L101 is AUDIO_DAC:u8|Mux~1988
K1L101 = K1L128Q & (K1_SEL_Cont[3] # K1_SEL_Cont[1]) # !K1L128Q & (K1_SEL_Cont[0] & (K1_SEL_Cont[1]) # !K1_SEL_Cont[0] & K1_SEL_Cont[3]);


--K1L102 is AUDIO_DAC:u8|Mux~1989
K1L102 = K1L128Q & (K1_SEL_Cont[0] & !K1_SEL_Cont[3] & K1_SEL_Cont[2] # !K1_SEL_Cont[0] & (!K1_SEL_Cont[2]));


--K1L103 is AUDIO_DAC:u8|Mux~1990
K1L103 = K1L127Q & (K1_SEL_Cont[2]) # !K1L127Q & K1_SEL_Cont[1] & (K1L102);


--K1L104 is AUDIO_DAC:u8|Mux~1991
K1L104 = K1_SEL_Cont[3] & (K1L128Q $ (!K1_SEL_Cont[1] & K1_SEL_Cont[0]));


--K1L105 is AUDIO_DAC:u8|Mux~1992
K1L105 = K1L127Q & (K1L103 & (K1L104) # !K1L103 & K1L101) # !K1L127Q & (K1L103);


--K1L106 is AUDIO_DAC:u8|Mux~1993
K1L106 = K1L130Q & (K1L129Q) # !K1L130Q & (K1L129Q & K1L100 # !K1L129Q & (K1L105));


--K1L107 is AUDIO_DAC:u8|Mux~1994
K1L107 = K1_SEL_Cont[1] & (!K1_SEL_Cont[0] # !K1_SEL_Cont[2] # !K1L127Q) # !K1_SEL_Cont[1] & (K1_SEL_Cont[0] $ (!K1L127Q & K1_SEL_Cont[2]));


--K1L108 is AUDIO_DAC:u8|Mux~1995
K1L108 = K1L127Q & (K1_SEL_Cont[1] & (K1_SEL_Cont[0]) # !K1_SEL_Cont[1] & K1_SEL_Cont[2] & !K1_SEL_Cont[0]);


--K1L109 is AUDIO_DAC:u8|Mux~1996
K1L109 = K1_SEL_Cont[2] & (!K1_SEL_Cont[0] # !K1_SEL_Cont[1] # !K1L127Q) # !K1_SEL_Cont[2] & (K1_SEL_Cont[1] # K1_SEL_Cont[0]);


--K1L110 is AUDIO_DAC:u8|Mux~1997
K1L110 = K1L128Q & (K1_SEL_Cont[3]) # !K1L128Q & (K1_SEL_Cont[3] & !K1L108 # !K1_SEL_Cont[3] & (K1L109));


--K1L111 is AUDIO_DAC:u8|Mux~1998
K1L111 = K1_SEL_Cont[1] & (K1L127Q # K1_SEL_Cont[0]) # !K1_SEL_Cont[1] & (K1_SEL_Cont[2] # K1L127Q $ K1_SEL_Cont[0]);


--K1L112 is AUDIO_DAC:u8|Mux~1999
K1L112 = K1L128Q & (K1L110 & (!K1L111) # !K1L110 & K1L107) # !K1L128Q & (K1L110);


--K1L113 is AUDIO_DAC:u8|Mux~2000
K1L113 = K1L130Q & (K1L106 & (K1L112) # !K1L106 & K1L94) # !K1L130Q & (K1L106);


--M1__clk0 is VGA_Audio_PLL:u3|altpll:altpll_component|_clk0
M1__clk0 = PLL.CLK0(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_27[0]), .INCLK());

--M1__clk1 is VGA_Audio_PLL:u3|altpll:altpll_component|_clk1
M1__clk1 = PLL.CLK1(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_27[0]), .INCLK());


--Cont[23] is Cont[23]
Cont[23] = DFFEAS(A1L85, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[22] is Cont[22]
Cont[22] = DFFEAS(A1L82, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[21] is Cont[21]
Cont[21] = DFFEAS(A1L79, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[20] is Cont[20]
Cont[20] = DFFEAS(A1L76, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[19] is Cont[19]
Cont[19] = DFFEAS(A1L73, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[18] is Cont[18]
Cont[18] = DFFEAS(A1L70, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[17] is Cont[17]
Cont[17] = DFFEAS(A1L67, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[16] is Cont[16]
Cont[16] = DFFEAS(A1L64, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[15] is Cont[15]
Cont[15] = DFFEAS(A1L61, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[14] is Cont[14]
Cont[14] = DFFEAS(A1L58, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[13] is Cont[13]
Cont[13] = DFFEAS(A1L55, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[12] is Cont[12]
Cont[12] = DFFEAS(A1L52, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[11] is Cont[11]
Cont[11] = DFFEAS(A1L49, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[10] is Cont[10]
Cont[10] = DFFEAS(A1L46, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[9] is Cont[9]
Cont[9] = DFFEAS(A1L43, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[8] is Cont[8]
Cont[8] = DFFEAS(A1L40, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[7] is Cont[7]
Cont[7] = DFFEAS(A1L37, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[6] is Cont[6]
Cont[6] = DFFEAS(A1L34, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[5] is Cont[5]
Cont[5] = DFFEAS(A1L31, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[4] is Cont[4]
Cont[4] = DFFEAS(A1L28, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[3] is Cont[3]
Cont[3] = DFFEAS(A1L25, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[2] is Cont[2]
Cont[2] = DFFEAS(A1L22, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[1] is Cont[1]
Cont[1] = DFFEAS(A1L19, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Cont[0] is Cont[0]
Cont[0] = DFFEAS(A1L16, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--A1L16 is Cont[0]~224
A1L16 = Cont[0] $ VCC;

--A1L17 is Cont[0]~225
A1L17 = CARRY(Cont[0]);


--A1L19 is Cont[1]~226
A1L19 = Cont[1] & !A1L17 # !Cont[1] & (A1L17 # GND);

--A1L20 is Cont[1]~227
A1L20 = CARRY(!A1L17 # !Cont[1]);


--A1L22 is Cont[2]~228
A1L22 = Cont[2] & (A1L20 $ GND) # !Cont[2] & !A1L20 & VCC;

--A1L23 is Cont[2]~229
A1L23 = CARRY(Cont[2] & !A1L20);


--A1L25 is Cont[3]~230
A1L25 = Cont[3] & !A1L23 # !Cont[3] & (A1L23 # GND);

--A1L26 is Cont[3]~231
A1L26 = CARRY(!A1L23 # !Cont[3]);


--A1L28 is Cont[4]~232
A1L28 = Cont[4] & (A1L26 $ GND) # !Cont[4] & !A1L26 & VCC;

--A1L29 is Cont[4]~233
A1L29 = CARRY(Cont[4] & !A1L26);


--A1L31 is Cont[5]~234
A1L31 = Cont[5] & !A1L29 # !Cont[5] & (A1L29 # GND);

--A1L32 is Cont[5]~235
A1L32 = CARRY(!A1L29 # !Cont[5]);


--A1L34 is Cont[6]~236
A1L34 = Cont[6] & (A1L32 $ GND) # !Cont[6] & !A1L32 & VCC;

--A1L35 is Cont[6]~237
A1L35 = CARRY(Cont[6] & !A1L32);


--A1L37 is Cont[7]~238
A1L37 = Cont[7] & !A1L35 # !Cont[7] & (A1L35 # GND);

--A1L38 is Cont[7]~239
A1L38 = CARRY(!A1L35 # !Cont[7]);


--A1L40 is Cont[8]~240
A1L40 = Cont[8] & (A1L38 $ GND) # !Cont[8] & !A1L38 & VCC;

--A1L41 is Cont[8]~241
A1L41 = CARRY(Cont[8] & !A1L38);


--A1L43 is Cont[9]~242
A1L43 = Cont[9] & !A1L41 # !Cont[9] & (A1L41 # GND);

--A1L44 is Cont[9]~243
A1L44 = CARRY(!A1L41 # !Cont[9]);


--A1L46 is Cont[10]~244
A1L46 = Cont[10] & (A1L44 $ GND) # !Cont[10] & !A1L44 & VCC;

--A1L47 is Cont[10]~245
A1L47 = CARRY(Cont[10] & !A1L44);


--A1L49 is Cont[11]~246
A1L49 = Cont[11] & !A1L47 # !Cont[11] & (A1L47 # GND);

--A1L50 is Cont[11]~247
A1L50 = CARRY(!A1L47 # !Cont[11]);


--A1L52 is Cont[12]~248
A1L52 = Cont[12] & (A1L50 $ GND) # !Cont[12] & !A1L50 & VCC;

--A1L53 is Cont[12]~249
A1L53 = CARRY(Cont[12] & !A1L50);


--A1L55 is Cont[13]~250
A1L55 = Cont[13] & !A1L53 # !Cont[13] & (A1L53 # GND);

--A1L56 is Cont[13]~251
A1L56 = CARRY(!A1L53 # !Cont[13]);


--A1L58 is Cont[14]~252
A1L58 = Cont[14] & (A1L56 $ GND) # !Cont[14] & !A1L56 & VCC;

--A1L59 is Cont[14]~253
A1L59 = CARRY(Cont[14] & !A1L56);


--A1L61 is Cont[15]~254
A1L61 = Cont[15] & !A1L59 # !Cont[15] & (A1L59 # GND);

--A1L62 is Cont[15]~255
A1L62 = CARRY(!A1L59 # !Cont[15]);


--A1L64 is Cont[16]~256
A1L64 = Cont[16] & (A1L62 $ GND) # !Cont[16] & !A1L62 & VCC;

--A1L65 is Cont[16]~257
A1L65 = CARRY(Cont[16] & !A1L62);


--A1L67 is Cont[17]~258
A1L67 = Cont[17] & !A1L65 # !Cont[17] & (A1L65 # GND);

--A1L68 is Cont[17]~259
A1L68 = CARRY(!A1L65 # !Cont[17]);


--A1L70 is Cont[18]~260
A1L70 = Cont[18] & (A1L68 $ GND) # !Cont[18] & !A1L68 & VCC;

--A1L71 is Cont[18]~261
A1L71 = CARRY(Cont[18] & !A1L68);


--A1L73 is Cont[19]~262
A1L73 = Cont[19] & !A1L71 # !Cont[19] & (A1L71 # GND);

--A1L74 is Cont[19]~263
A1L74 = CARRY(!A1L71 # !Cont[19]);


--A1L76 is Cont[20]~264
A1L76 = Cont[20] & (A1L74 $ GND) # !Cont[20] & !A1L74 & VCC;

--A1L77 is Cont[20]~265
A1L77 = CARRY(Cont[20] & !A1L74);


--A1L79 is Cont[21]~266
A1L79 = Cont[21] & !A1L77 # !Cont[21] & (A1L77 # GND);

--A1L80 is Cont[21]~267
A1L80 = CARRY(!A1L77 # !Cont[21]);


--A1L82 is Cont[22]~268
A1L82 = Cont[22] & (A1L80 $ GND) # !Cont[22] & !A1L80 & VCC;

--A1L83 is Cont[22]~269
A1L83 = CARRY(Cont[22] & !A1L80);


--A1L85 is Cont[23]~270
A1L85 = Cont[23] & !A1L83 # !Cont[23] & (A1L83 # GND);

--A1L86 is Cont[23]~271
A1L86 = CARRY(!A1L83 # !Cont[23]);


--A1L88 is Cont[24]~272
A1L88 = Cont[24] & (A1L86 $ GND) # !Cont[24] & !A1L86 & VCC;

--A1L89 is Cont[24]~273
A1L89 = CARRY(Cont[24] & !A1L86);


--A1L91 is Cont[25]~274
A1L91 = Cont[25] & !A1L89 # !Cont[25] & (A1L89 # GND);

--A1L92 is Cont[25]~275
A1L92 = CARRY(!A1L89 # !Cont[25]);


--A1L94 is Cont[26]~276
A1L94 = Cont[26] & (A1L92 $ GND) # !Cont[26] & !A1L92 & VCC;

--A1L95 is Cont[26]~277
A1L95 = CARRY(Cont[26] & !A1L92);


--A1L97 is Cont[27]~278
A1L97 = Cont[27] $ A1L95;


--D1_DIR is LEDG_Driver:u2|DIR
D1_DIR = DFFEAS(D1L69, D1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--D1L79 is LEDG_Driver:u2|mLED~96
D1L79 = D1_DIR & (D1_mLED[1]) # !D1_DIR & !D1_mLED[7];


--D1_Cont[20] is LEDG_Driver:u2|Cont[20]
D1_Cont[20] = DFFEAS(D1L63, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1L80 is LEDG_Driver:u2|mLED~97
D1L80 = D1_DIR & (D1_mLED[2]) # !D1_DIR & D1_mLED[0];


--D1L81 is LEDG_Driver:u2|mLED~98
D1L81 = D1_DIR & !D1_mLED[3] # !D1_DIR & (D1_mLED[1]);


--D1L82 is LEDG_Driver:u2|mLED~99
D1L82 = D1_DIR & D1_mLED[4] # !D1_DIR & (!D1_mLED[2]);


--D1L83 is LEDG_Driver:u2|mLED~100
D1L83 = D1_DIR & D1_mLED[5] # !D1_DIR & (D1_mLED[3]);


--D1L84 is LEDG_Driver:u2|mLED~101
D1L84 = D1_DIR & D1_mLED[6] # !D1_DIR & (D1_mLED[4]);


--D1L85 is LEDG_Driver:u2|mLED~102
D1L85 = D1_DIR & D1_mLED[7] # !D1_DIR & (D1_mLED[5]);


--D1L86 is LEDG_Driver:u2|mLED~103
D1L86 = D1_DIR & (!D1_mLED[0]) # !D1_DIR & D1_mLED[6];


--C1_DIR is LEDR_Driver:u1|DIR
C1_DIR = DFFEAS(C1L68, C1_Cont[20], KEY[0],  ,  ,  ,  ,  ,  );


--C1L81 is LEDR_Driver:u1|mLED~120
C1L81 = C1_DIR & (C1_mLED[1]) # !C1_DIR & !C1_mLED[9];


--C1_Cont[20] is LEDR_Driver:u1|Cont[20]
C1_Cont[20] = DFFEAS(C1L63, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1L82 is LEDR_Driver:u1|mLED~121
C1L82 = C1_DIR & (C1_mLED[2]) # !C1_DIR & C1_mLED[0];


--C1L83 is LEDR_Driver:u1|mLED~122
C1L83 = C1_DIR & !C1_mLED[3] # !C1_DIR & (C1_mLED[1]);


--C1L84 is LEDR_Driver:u1|mLED~123
C1L84 = C1_DIR & C1_mLED[4] # !C1_DIR & (!C1_mLED[2]);


--C1L85 is LEDR_Driver:u1|mLED~124
C1L85 = C1_DIR & C1_mLED[5] # !C1_DIR & (C1_mLED[3]);


--C1L86 is LEDR_Driver:u1|mLED~125
C1L86 = C1_DIR & C1_mLED[6] # !C1_DIR & (C1_mLED[4]);


--C1L87 is LEDR_Driver:u1|mLED~126
C1L87 = C1_DIR & C1_mLED[7] # !C1_DIR & (C1_mLED[5]);


--C1L88 is LEDR_Driver:u1|mLED~127
C1L88 = C1_DIR & C1_mLED[8] # !C1_DIR & (C1_mLED[6]);


--C1L89 is LEDR_Driver:u1|mLED~128
C1L89 = C1_DIR & C1_mLED[9] # !C1_DIR & (C1_mLED[7]);


--C1L90 is LEDR_Driver:u1|mLED~129
C1L90 = C1_DIR & (!C1_mLED[0]) # !C1_DIR & C1_mLED[8];


--V1L56 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1103
V1L56 = !V1L52Q & !V1L46Q & !V1L49Q & !V1L43Q;


--V1L18 is I2C_AV_Config:u7|I2C_Controller:u0|LessThan~163
V1L18 = V1L40Q # V1L55Q # !V1L56;


--V1L38 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[0]~280
V1L38 = V1L18 & !V1L40Q # !V1L18 & V1L40Q & VCC;

--V1L39 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[0]~281
V1L39 = CARRY(V1L18 & !V1L40Q);


--J1_mI2C_GO is I2C_AV_Config:u7|mI2C_GO
J1_mI2C_GO = DFFEAS(J1L19, J1_mI2C_CTRL_CLK, KEY[0],  ,  ,  ,  ,  ,  );


--V1L41 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[1]~282
V1L41 = V1L43Q & (GND # !V1L39) # !V1L43Q & (V1L39 $ GND);

--V1L42 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[1]~283
V1L42 = CARRY(V1L43Q # !V1L39);


--V1L44 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[2]~284
V1L44 = V1L46Q & V1L42 & VCC # !V1L46Q & !V1L42;

--V1L45 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[2]~285
V1L45 = CARRY(!V1L46Q & !V1L42);


--V1L47 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[3]~286
V1L47 = V1L49Q & (GND # !V1L45) # !V1L49Q & (V1L45 $ GND);

--V1L48 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[3]~287
V1L48 = CARRY(V1L49Q # !V1L45);


--V1L50 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[4]~288
V1L50 = V1L52Q & V1L48 & VCC # !V1L52Q & !V1L48;

--V1L51 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[4]~289
V1L51 = CARRY(!V1L52Q & !V1L48);


--V1L53 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[5]~290
V1L53 = V1L55Q $ V1L51;


--J1_mI2C_CLK_DIV[12] is I2C_AV_Config:u7|mI2C_CLK_DIV[12]
J1_mI2C_CLK_DIV[12] = DFFEAS(J1L60, CLOCK_50, KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[13] is I2C_AV_Config:u7|mI2C_CLK_DIV[13]
J1_mI2C_CLK_DIV[13] = DFFEAS(J1L63, CLOCK_50, KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[14] is I2C_AV_Config:u7|mI2C_CLK_DIV[14]
J1_mI2C_CLK_DIV[14] = DFFEAS(J1L66, CLOCK_50, KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[15] is I2C_AV_Config:u7|mI2C_CLK_DIV[15]
J1_mI2C_CLK_DIV[15] = DFFEAS(J1L69, CLOCK_50, KEY[0],  ,  ,  ,  , J1L18,  );


--J1L14 is I2C_AV_Config:u7|LessThan~226
J1L14 = !J1_mI2C_CLK_DIV[12] & !J1_mI2C_CLK_DIV[13] & !J1_mI2C_CLK_DIV[14] & !J1_mI2C_CLK_DIV[15];


--J1_mI2C_CLK_DIV[2] is I2C_AV_Config:u7|mI2C_CLK_DIV[2]
J1_mI2C_CLK_DIV[2] = DFFEAS(J1L30, CLOCK_50, KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[3] is I2C_AV_Config:u7|mI2C_CLK_DIV[3]
J1_mI2C_CLK_DIV[3] = DFFEAS(J1L33, CLOCK_50, KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[4] is I2C_AV_Config:u7|mI2C_CLK_DIV[4]
J1_mI2C_CLK_DIV[4] = DFFEAS(J1L36, CLOCK_50, KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[5] is I2C_AV_Config:u7|mI2C_CLK_DIV[5]
J1_mI2C_CLK_DIV[5] = DFFEAS(J1L39, CLOCK_50, KEY[0],  ,  ,  ,  , J1L18,  );


--J1L15 is I2C_AV_Config:u7|LessThan~227
J1L15 = !J1_mI2C_CLK_DIV[2] & !J1_mI2C_CLK_DIV[3] & !J1_mI2C_CLK_DIV[4] & !J1_mI2C_CLK_DIV[5];


--J1_mI2C_CLK_DIV[6] is I2C_AV_Config:u7|mI2C_CLK_DIV[6]
J1_mI2C_CLK_DIV[6] = DFFEAS(J1L42, CLOCK_50, KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[7] is I2C_AV_Config:u7|mI2C_CLK_DIV[7]
J1_mI2C_CLK_DIV[7] = DFFEAS(J1L45, CLOCK_50, KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[8] is I2C_AV_Config:u7|mI2C_CLK_DIV[8]
J1_mI2C_CLK_DIV[8] = DFFEAS(J1L48, CLOCK_50, KEY[0],  ,  ,  ,  , J1L18,  );


--J1L16 is I2C_AV_Config:u7|LessThan~228
J1L16 = J1L15 # !J1_mI2C_CLK_DIV[8] # !J1_mI2C_CLK_DIV[7] # !J1_mI2C_CLK_DIV[6];


--J1_mI2C_CLK_DIV[9] is I2C_AV_Config:u7|mI2C_CLK_DIV[9]
J1_mI2C_CLK_DIV[9] = DFFEAS(J1L51, CLOCK_50, KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[10] is I2C_AV_Config:u7|mI2C_CLK_DIV[10]
J1_mI2C_CLK_DIV[10] = DFFEAS(J1L54, CLOCK_50, KEY[0],  ,  ,  ,  , J1L18,  );


--J1L17 is I2C_AV_Config:u7|LessThan~229
J1L17 = !J1_mI2C_CLK_DIV[9] & !J1_mI2C_CLK_DIV[10];


--J1_mI2C_CLK_DIV[11] is I2C_AV_Config:u7|mI2C_CLK_DIV[11]
J1_mI2C_CLK_DIV[11] = DFFEAS(J1L57, CLOCK_50, KEY[0],  ,  ,  ,  , J1L18,  );


--J1L18 is I2C_AV_Config:u7|LessThan~230
J1L18 = J1_mI2C_CLK_DIV[11] & (!J1L17 # !J1L16) # !J1L14;


--J1L72 is I2C_AV_Config:u7|mI2C_CTRL_CLK~79
J1L72 = J1_mI2C_CTRL_CLK $ J1L18;


--V1L20 is I2C_AV_Config:u7|I2C_Controller:u0|SCLK~145
V1L20 = V1L43Q & !V1L49Q # !V1L43Q & (V1L46Q);


--V1L21 is I2C_AV_Config:u7|I2C_Controller:u0|SCLK~146
V1L21 = V1L52Q & (!V1L20 # !V1L49Q # !V1L40Q) # !V1L52Q & (V1L49Q # V1L20);


--V1L37 is I2C_AV_Config:u7|I2C_Controller:u0|SD[12]~381
V1L37 = V1L52Q & V1L46Q & V1L49Q & V1L43Q;


--V1L22 is I2C_AV_Config:u7|I2C_Controller:u0|SCLK~147
V1L22 = V1L40Q & (V1L37 $ !V1L21);


--V1L23 is I2C_AV_Config:u7|I2C_Controller:u0|SCLK~148
V1L23 = V1L55Q & (V1L21 & V1_SCLK & !V1L22 # !V1L21 & (V1L22)) # !V1L55Q & V1_SCLK;


--F1L56 is VGA_Controller:u4|LessThan~1170
F1L56 = F1_H_Cont[7] # F1_H_Cont[5] & F1_H_Cont[6] # !F1L16;


--F1L17 is VGA_Controller:u4|Equal~112
F1L17 = !F1_H_Cont[2] & !F1_H_Cont[3];


--F1L18 is VGA_Controller:u4|Equal~113
F1L18 = F1L15 & F1L17 & !F1_H_Cont[7] & !F1_H_Cont[4];


--F1L19 is VGA_Controller:u4|Equal~114
F1L19 = F1L16 & F1L18 & !F1_H_Cont[0] & !F1_H_Cont[1];


--F1L265 is VGA_Controller:u4|oVGA_V_SYNC~174
F1L265 = F1L19 & (F1_V_Cont[9] # F1L55) # !F1L19 & F1_oVGA_V_SYNC;


--G1_oRed[7] is VGA_Pattern:u5|oRed[7]
G1_oRed[7] = DFFEAS(G1L49, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--H1_oRed[8] is VGA_OSD_RAM:u6|oRed[8]
H1_oRed[8] = DFFEAS(H1L140, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--A1L399 is mVGA_R[7]~123
A1L399 = SW[0] & G1_oRed[7] # !SW[0] & (H1_oRed[8]);


--F1L22 is VGA_Controller:u4|H_Cont[0]~235
F1L22 = F1_H_Cont[0] $ VCC;

--F1L23 is VGA_Controller:u4|H_Cont[0]~236
F1L23 = CARRY(F1_H_Cont[0]);


--F1L25 is VGA_Controller:u4|H_Cont[1]~237
F1L25 = F1_H_Cont[1] & !F1L23 # !F1_H_Cont[1] & (F1L23 # GND);

--F1L26 is VGA_Controller:u4|H_Cont[1]~238
F1L26 = CARRY(!F1L23 # !F1_H_Cont[1]);


--F1L28 is VGA_Controller:u4|H_Cont[2]~239
F1L28 = F1_H_Cont[2] & (F1L26 $ GND) # !F1_H_Cont[2] & !F1L26 & VCC;

--F1L29 is VGA_Controller:u4|H_Cont[2]~240
F1L29 = CARRY(F1_H_Cont[2] & !F1L26);


--F1L31 is VGA_Controller:u4|H_Cont[3]~241
F1L31 = F1_H_Cont[3] & !F1L29 # !F1_H_Cont[3] & (F1L29 # GND);

--F1L32 is VGA_Controller:u4|H_Cont[3]~242
F1L32 = CARRY(!F1L29 # !F1_H_Cont[3]);


--F1L34 is VGA_Controller:u4|H_Cont[4]~243
F1L34 = F1_H_Cont[4] & (F1L32 $ GND) # !F1_H_Cont[4] & !F1L32 & VCC;

--F1L35 is VGA_Controller:u4|H_Cont[4]~244
F1L35 = CARRY(F1_H_Cont[4] & !F1L32);


--F1L37 is VGA_Controller:u4|H_Cont[5]~245
F1L37 = F1_H_Cont[5] & !F1L35 # !F1_H_Cont[5] & (F1L35 # GND);

--F1L38 is VGA_Controller:u4|H_Cont[5]~246
F1L38 = CARRY(!F1L35 # !F1_H_Cont[5]);


--F1L57 is VGA_Controller:u4|LessThan~1171
F1L57 = F1_H_Cont[8] & F1_H_Cont[9] & (F1_H_Cont[7] # !F1L15);


--F1L40 is VGA_Controller:u4|H_Cont[6]~247
F1L40 = F1_H_Cont[6] & (F1L38 $ GND) # !F1_H_Cont[6] & !F1L38 & VCC;

--F1L41 is VGA_Controller:u4|H_Cont[6]~248
F1L41 = CARRY(F1_H_Cont[6] & !F1L38);


--F1L43 is VGA_Controller:u4|H_Cont[7]~249
F1L43 = F1_H_Cont[7] & !F1L41 # !F1_H_Cont[7] & (F1L41 # GND);

--F1L44 is VGA_Controller:u4|H_Cont[7]~250
F1L44 = CARRY(!F1L41 # !F1_H_Cont[7]);


--F1L46 is VGA_Controller:u4|H_Cont[8]~251
F1L46 = F1_H_Cont[8] & (F1L44 $ GND) # !F1_H_Cont[8] & !F1L44 & VCC;

--F1L47 is VGA_Controller:u4|H_Cont[8]~252
F1L47 = CARRY(F1_H_Cont[8] & !F1L44);


--F1L49 is VGA_Controller:u4|H_Cont[9]~253
F1L49 = F1_H_Cont[9] $ F1L47;


--F1_V_Cont[0] is VGA_Controller:u4|V_Cont[0]
F1_V_Cont[0] = DFFEAS(F1L66, M1__clk0, KEY[0],  , F1L19,  ,  , F1L60,  );


--F1L66 is VGA_Controller:u4|V_Cont[0]~564
F1L66 = F1_V_Cont[0] $ VCC;

--F1L67 is VGA_Controller:u4|V_Cont[0]~565
F1L67 = CARRY(F1_V_Cont[0]);


--F1L69 is VGA_Controller:u4|V_Cont[1]~566
F1L69 = F1_V_Cont[1] & !F1L67 # !F1_V_Cont[1] & (F1L67 # GND);

--F1L70 is VGA_Controller:u4|V_Cont[1]~567
F1L70 = CARRY(!F1L67 # !F1_V_Cont[1]);


--F1L72 is VGA_Controller:u4|V_Cont[2]~568
F1L72 = F1_V_Cont[2] & (F1L70 $ GND) # !F1_V_Cont[2] & !F1L70 & VCC;

--F1L73 is VGA_Controller:u4|V_Cont[2]~569
F1L73 = CARRY(F1_V_Cont[2] & !F1L70);


--F1L75 is VGA_Controller:u4|V_Cont[3]~570
F1L75 = F1_V_Cont[3] & !F1L73 # !F1_V_Cont[3] & (F1L73 # GND);

--F1L76 is VGA_Controller:u4|V_Cont[3]~571
F1L76 = CARRY(!F1L73 # !F1_V_Cont[3]);


--F1L78 is VGA_Controller:u4|V_Cont[4]~572
F1L78 = F1_V_Cont[4] & (F1L76 $ GND) # !F1_V_Cont[4] & !F1L76 & VCC;

--F1L79 is VGA_Controller:u4|V_Cont[4]~573
F1L79 = CARRY(F1_V_Cont[4] & !F1L76);


--F1L81 is VGA_Controller:u4|V_Cont[5]~574
F1L81 = F1_V_Cont[5] & !F1L79 # !F1_V_Cont[5] & (F1L79 # GND);

--F1L82 is VGA_Controller:u4|V_Cont[5]~575
F1L82 = CARRY(!F1L79 # !F1_V_Cont[5]);


--F1L84 is VGA_Controller:u4|V_Cont[6]~576
F1L84 = F1_V_Cont[6] & (F1L82 $ GND) # !F1_V_Cont[6] & !F1L82 & VCC;

--F1L85 is VGA_Controller:u4|V_Cont[6]~577
F1L85 = CARRY(F1_V_Cont[6] & !F1L82);


--F1L58 is VGA_Controller:u4|LessThan~1172
F1L58 = F1L52 & !F1_V_Cont[4] & !F1_V_Cont[5];


--F1L59 is VGA_Controller:u4|LessThan~1173
F1L59 = !F1_V_Cont[1] & !F1_V_Cont[0] # !F1_V_Cont[3] # !F1_V_Cont[2];


--F1L60 is VGA_Controller:u4|LessThan~1174
F1L60 = F1_V_Cont[9] & (!F1L59 # !F1L58);


--F1L87 is VGA_Controller:u4|V_Cont[7]~578
F1L87 = F1_V_Cont[7] & !F1L85 # !F1_V_Cont[7] & (F1L85 # GND);

--F1L88 is VGA_Controller:u4|V_Cont[7]~579
F1L88 = CARRY(!F1L85 # !F1_V_Cont[7]);


--F1L90 is VGA_Controller:u4|V_Cont[8]~580
F1L90 = F1_V_Cont[8] & (F1L88 $ GND) # !F1_V_Cont[8] & !F1L88 & VCC;

--F1L91 is VGA_Controller:u4|V_Cont[8]~581
F1L91 = CARRY(F1_V_Cont[8] & !F1L88);


--F1L93 is VGA_Controller:u4|V_Cont[9]~582
F1L93 = F1_V_Cont[9] $ F1L91;


--G1_oRed[8] is VGA_Pattern:u5|oRed[8]
G1_oRed[8] = DFFEAS(G1L50, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--A1L400 is mVGA_R[8]~124
A1L400 = SW[0] & G1_oRed[8] # !SW[0] & (H1_oRed[8]);


--G1_oRed[9] is VGA_Pattern:u5|oRed[9]
G1_oRed[9] = DFFEAS(G1L5, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--A1L401 is mVGA_R[9]~125
A1L401 = SW[0] & G1_oRed[9] # !SW[0] & (H1_oRed[8]);


--G1_oGreen[6] is VGA_Pattern:u5|oGreen[6]
G1_oGreen[6] = DFFEAS(G1L41, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--A1L395 is mVGA_G[6]~58
A1L395 = SW[0] & G1_oGreen[6] # !SW[0] & (H1_oRed[8]);


--G1_oGreen[7] is VGA_Pattern:u5|oGreen[7]
G1_oGreen[7] = DFFEAS(G1L43, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--A1L396 is mVGA_G[7]~59
A1L396 = SW[0] & G1_oGreen[7] # !SW[0] & (H1_oRed[8]);


--G1_oGreen[8] is VGA_Pattern:u5|oGreen[8]
G1_oGreen[8] = DFFEAS(G1L44, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--A1L397 is mVGA_G[8]~60
A1L397 = SW[0] & G1_oGreen[8] # !SW[0] & (H1_oRed[8]);


--G1_oGreen[9] is VGA_Pattern:u5|oGreen[9]
G1_oGreen[9] = DFFEAS(G1L42, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--A1L398 is mVGA_G[9]~61
A1L398 = SW[0] & G1_oGreen[9] # !SW[0] & (H1_oRed[8]);


--G1_oBlue[6] is VGA_Pattern:u5|oBlue[6]
G1_oBlue[6] = DFFEAS(G1L8, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--A1L391 is mVGA_B[6]~55
A1L391 = SW[0] & G1_oBlue[6] # !SW[0] & (H1_oRed[8]);


--G1_oBlue[7] is VGA_Pattern:u5|oBlue[7]
G1_oBlue[7] = DFFEAS(G1L27, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--A1L392 is mVGA_B[7]~56
A1L392 = SW[0] & G1_oBlue[7] # !SW[0] & (H1_oRed[8]);


--G1_oBlue[8] is VGA_Pattern:u5|oBlue[8]
G1_oBlue[8] = DFFEAS(G1L29, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--A1L393 is mVGA_B[8]~57
A1L393 = SW[0] & G1_oBlue[8] # !SW[0] & (H1_oRed[8]);


--G1_oBlue[9] is VGA_Pattern:u5|oBlue[9]
G1_oBlue[9] = DFFEAS(G1L30, M1__clk0, KEY[0],  ,  ,  ,  , F1_oCoord_Y[9],  );


--H1_oBlue[9] is VGA_OSD_RAM:u6|oBlue[9]
H1_oBlue[9] = DFFEAS(VCC, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--A1L394 is mVGA_B[9]~58
A1L394 = SW[0] & G1_oBlue[9] # !SW[0] & (H1_oBlue[9]);


--K1_LRCK_1X_DIV[0] is AUDIO_DAC:u8|LRCK_1X_DIV[0]
K1_LRCK_1X_DIV[0] = DFFEAS(K1L11, M1__clk1, KEY[0],  ,  ,  ,  , K1L40,  );


--K1_LRCK_1X_DIV[1] is AUDIO_DAC:u8|LRCK_1X_DIV[1]
K1_LRCK_1X_DIV[1] = DFFEAS(K1L14, M1__clk1, KEY[0],  ,  ,  ,  , K1L40,  );


--K1_LRCK_1X_DIV[2] is AUDIO_DAC:u8|LRCK_1X_DIV[2]
K1_LRCK_1X_DIV[2] = DFFEAS(K1L17, M1__clk1, KEY[0],  ,  ,  ,  , K1L40,  );


--K1_LRCK_1X_DIV[3] is AUDIO_DAC:u8|LRCK_1X_DIV[3]
K1_LRCK_1X_DIV[3] = DFFEAS(K1L20, M1__clk1, KEY[0],  ,  ,  ,  , K1L40,  );


--K1L38 is AUDIO_DAC:u8|LessThan~297
K1L38 = !K1_LRCK_1X_DIV[3] # !K1_LRCK_1X_DIV[2] # !K1_LRCK_1X_DIV[1] # !K1_LRCK_1X_DIV[0];


--K1_LRCK_1X_DIV[4] is AUDIO_DAC:u8|LRCK_1X_DIV[4]
K1_LRCK_1X_DIV[4] = DFFEAS(K1L23, M1__clk1, KEY[0],  ,  ,  ,  , K1L40,  );


--K1_LRCK_1X_DIV[5] is AUDIO_DAC:u8|LRCK_1X_DIV[5]
K1_LRCK_1X_DIV[5] = DFFEAS(K1L26, M1__clk1, KEY[0],  ,  ,  ,  , K1L40,  );


--K1L39 is AUDIO_DAC:u8|LessThan~298
K1L39 = K1L38 # !K1_LRCK_1X_DIV[5] # !K1_LRCK_1X_DIV[4];


--K1_LRCK_1X_DIV[6] is AUDIO_DAC:u8|LRCK_1X_DIV[6]
K1_LRCK_1X_DIV[6] = DFFEAS(K1L29, M1__clk1, KEY[0],  ,  ,  ,  , K1L40,  );


--K1_LRCK_1X_DIV[7] is AUDIO_DAC:u8|LRCK_1X_DIV[7]
K1_LRCK_1X_DIV[7] = DFFEAS(K1L32, M1__clk1, KEY[0],  ,  ,  ,  , K1L40,  );


--K1_LRCK_1X_DIV[8] is AUDIO_DAC:u8|LRCK_1X_DIV[8]
K1_LRCK_1X_DIV[8] = DFFEAS(K1L35, M1__clk1, KEY[0],  ,  ,  ,  , K1L40,  );


--K1L40 is AUDIO_DAC:u8|LessThan~299
K1L40 = K1_LRCK_1X_DIV[8] # K1_LRCK_1X_DIV[7] & (K1_LRCK_1X_DIV[6] # !K1L39);


--K1L37 is AUDIO_DAC:u8|LRCK_1X~51
K1L37 = K1_LRCK_1X $ K1L40;


--K1L133 is AUDIO_DAC:u8|rom~141
K1L133 = K1L127Q $ VCC;

--K1L134 is AUDIO_DAC:u8|rom~142
K1L134 = CARRY(K1L127Q);


--K1L135 is AUDIO_DAC:u8|rom~143
K1L135 = K1L128Q & !K1L134 # !K1L128Q & (K1L134 # GND);

--K1L136 is AUDIO_DAC:u8|rom~144
K1L136 = CARRY(!K1L134 # !K1L128Q);


--K1L137 is AUDIO_DAC:u8|rom~145
K1L137 = K1L129Q & (K1L136 $ GND) # !K1L129Q & !K1L136 & VCC;

--K1L138 is AUDIO_DAC:u8|rom~146
K1L138 = CARRY(K1L129Q & !K1L136);


--K1L139 is AUDIO_DAC:u8|rom~147
K1L139 = K1L130Q & !K1L138 # !K1L130Q & (K1L138 # GND);

--K1L140 is AUDIO_DAC:u8|rom~148
K1L140 = CARRY(!K1L138 # !K1L130Q);


--K1L141 is AUDIO_DAC:u8|rom~149
K1L141 = K1L131Q & (K1L140 $ GND) # !K1L131Q & !K1L140 & VCC;

--K1L142 is AUDIO_DAC:u8|rom~150
K1L142 = CARRY(K1L131Q & !K1L140);


--K1L41 is AUDIO_DAC:u8|LessThan~300
K1L41 = !K1L129Q # !K1L130Q # !K1L128Q # !K1L127Q;


--K1L42 is AUDIO_DAC:u8|LessThan~301
K1L42 = K1L132Q & (K1L131Q # !K1L41);


--K1L118 is AUDIO_DAC:u8|SEL_Cont[1]~50
K1L118 = K1_SEL_Cont[1] $ K1_SEL_Cont[0];


--K1_oAUD_BCK is AUDIO_DAC:u8|oAUD_BCK
K1_oAUD_BCK = DFFEAS(K1L124, M1__clk1, KEY[0],  ,  ,  ,  ,  ,  );


--K1L122 is AUDIO_DAC:u8|SEL_Cont[3]~51
K1L122 = K1_SEL_Cont[3] $ (K1_SEL_Cont[1] & K1_SEL_Cont[0] & K1_SEL_Cont[2]);


--K1L120 is AUDIO_DAC:u8|SEL_Cont[2]~52
K1L120 = K1_SEL_Cont[2] $ (K1_SEL_Cont[1] & K1_SEL_Cont[0]);


--K1L143 is AUDIO_DAC:u8|rom~151
K1L143 = K1L132Q $ K1L142;


--D1L66 is LEDG_Driver:u2|DIR~102
D1L66 = D1_mLED[4] & D1_mLED[6] & D1_mLED[2] # !D1_mLED[4] & (D1_mLED[6] # D1_mLED[2]);


--D1L67 is LEDG_Driver:u2|DIR~103
D1L67 = D1_mLED[5] & !D1_mLED[3] & !D1_DIR & D1_mLED[4] # !D1_mLED[5] & D1_mLED[3] & D1_DIR & !D1_mLED[4];


--D1L68 is LEDG_Driver:u2|DIR~104
D1L68 = D1_mLED[0] & !D1_mLED[7] & D1L67;


--D1L69 is LEDG_Driver:u2|DIR~105
D1L69 = D1_mLED[1] & (D1_DIR # D1L66 & D1L68) # !D1_mLED[1] & D1_DIR & (D1L66 # !D1L68);


--D1_Cont[19] is LEDG_Driver:u2|Cont[19]
D1_Cont[19] = DFFEAS(D1L60, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[18] is LEDG_Driver:u2|Cont[18]
D1_Cont[18] = DFFEAS(D1L57, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[17] is LEDG_Driver:u2|Cont[17]
D1_Cont[17] = DFFEAS(D1L54, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[16] is LEDG_Driver:u2|Cont[16]
D1_Cont[16] = DFFEAS(D1L51, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[15] is LEDG_Driver:u2|Cont[15]
D1_Cont[15] = DFFEAS(D1L48, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[14] is LEDG_Driver:u2|Cont[14]
D1_Cont[14] = DFFEAS(D1L45, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[13] is LEDG_Driver:u2|Cont[13]
D1_Cont[13] = DFFEAS(D1L42, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[12] is LEDG_Driver:u2|Cont[12]
D1_Cont[12] = DFFEAS(D1L39, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[11] is LEDG_Driver:u2|Cont[11]
D1_Cont[11] = DFFEAS(D1L36, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[10] is LEDG_Driver:u2|Cont[10]
D1_Cont[10] = DFFEAS(D1L33, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[9] is LEDG_Driver:u2|Cont[9]
D1_Cont[9] = DFFEAS(D1L30, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[8] is LEDG_Driver:u2|Cont[8]
D1_Cont[8] = DFFEAS(D1L27, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[7] is LEDG_Driver:u2|Cont[7]
D1_Cont[7] = DFFEAS(D1L24, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[6] is LEDG_Driver:u2|Cont[6]
D1_Cont[6] = DFFEAS(D1L21, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[5] is LEDG_Driver:u2|Cont[5]
D1_Cont[5] = DFFEAS(D1L18, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[4] is LEDG_Driver:u2|Cont[4]
D1_Cont[4] = DFFEAS(D1L15, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[3] is LEDG_Driver:u2|Cont[3]
D1_Cont[3] = DFFEAS(D1L12, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[2] is LEDG_Driver:u2|Cont[2]
D1_Cont[2] = DFFEAS(D1L9, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[1] is LEDG_Driver:u2|Cont[1]
D1_Cont[1] = DFFEAS(D1L6, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1_Cont[0] is LEDG_Driver:u2|Cont[0]
D1_Cont[0] = DFFEAS(D1L3, CLOCK_24[0],  ,  ,  ,  ,  ,  ,  );


--D1L3 is LEDG_Driver:u2|Cont[0]~168
D1L3 = D1_Cont[0] $ VCC;

--D1L4 is LEDG_Driver:u2|Cont[0]~169
D1L4 = CARRY(D1_Cont[0]);


--D1L6 is LEDG_Driver:u2|Cont[1]~170
D1L6 = D1_Cont[1] & !D1L4 # !D1_Cont[1] & (D1L4 # GND);

--D1L7 is LEDG_Driver:u2|Cont[1]~171
D1L7 = CARRY(!D1L4 # !D1_Cont[1]);


--D1L9 is LEDG_Driver:u2|Cont[2]~172
D1L9 = D1_Cont[2] & (D1L7 $ GND) # !D1_Cont[2] & !D1L7 & VCC;

--D1L10 is LEDG_Driver:u2|Cont[2]~173
D1L10 = CARRY(D1_Cont[2] & !D1L7);


--D1L12 is LEDG_Driver:u2|Cont[3]~174
D1L12 = D1_Cont[3] & !D1L10 # !D1_Cont[3] & (D1L10 # GND);

--D1L13 is LEDG_Driver:u2|Cont[3]~175
D1L13 = CARRY(!D1L10 # !D1_Cont[3]);


--D1L15 is LEDG_Driver:u2|Cont[4]~176
D1L15 = D1_Cont[4] & (D1L13 $ GND) # !D1_Cont[4] & !D1L13 & VCC;

--D1L16 is LEDG_Driver:u2|Cont[4]~177
D1L16 = CARRY(D1_Cont[4] & !D1L13);


--D1L18 is LEDG_Driver:u2|Cont[5]~178
D1L18 = D1_Cont[5] & !D1L16 # !D1_Cont[5] & (D1L16 # GND);

--D1L19 is LEDG_Driver:u2|Cont[5]~179
D1L19 = CARRY(!D1L16 # !D1_Cont[5]);


--D1L21 is LEDG_Driver:u2|Cont[6]~180
D1L21 = D1_Cont[6] & (D1L19 $ GND) # !D1_Cont[6] & !D1L19 & VCC;

--D1L22 is LEDG_Driver:u2|Cont[6]~181
D1L22 = CARRY(D1_Cont[6] & !D1L19);


--D1L24 is LEDG_Driver:u2|Cont[7]~182
D1L24 = D1_Cont[7] & !D1L22 # !D1_Cont[7] & (D1L22 # GND);

--D1L25 is LEDG_Driver:u2|Cont[7]~183
D1L25 = CARRY(!D1L22 # !D1_Cont[7]);


--D1L27 is LEDG_Driver:u2|Cont[8]~184
D1L27 = D1_Cont[8] & (D1L25 $ GND) # !D1_Cont[8] & !D1L25 & VCC;

--D1L28 is LEDG_Driver:u2|Cont[8]~185
D1L28 = CARRY(D1_Cont[8] & !D1L25);


--D1L30 is LEDG_Driver:u2|Cont[9]~186
D1L30 = D1_Cont[9] & !D1L28 # !D1_Cont[9] & (D1L28 # GND);

--D1L31 is LEDG_Driver:u2|Cont[9]~187
D1L31 = CARRY(!D1L28 # !D1_Cont[9]);


--D1L33 is LEDG_Driver:u2|Cont[10]~188
D1L33 = D1_Cont[10] & (D1L31 $ GND) # !D1_Cont[10] & !D1L31 & VCC;

--D1L34 is LEDG_Driver:u2|Cont[10]~189
D1L34 = CARRY(D1_Cont[10] & !D1L31);


--D1L36 is LEDG_Driver:u2|Cont[11]~190
D1L36 = D1_Cont[11] & !D1L34 # !D1_Cont[11] & (D1L34 # GND);

--D1L37 is LEDG_Driver:u2|Cont[11]~191
D1L37 = CARRY(!D1L34 # !D1_Cont[11]);


--D1L39 is LEDG_Driver:u2|Cont[12]~192
D1L39 = D1_Cont[12] & (D1L37 $ GND) # !D1_Cont[12] & !D1L37 & VCC;

--D1L40 is LEDG_Driver:u2|Cont[12]~193
D1L40 = CARRY(D1_Cont[12] & !D1L37);


--D1L42 is LEDG_Driver:u2|Cont[13]~194
D1L42 = D1_Cont[13] & !D1L40 # !D1_Cont[13] & (D1L40 # GND);

--D1L43 is LEDG_Driver:u2|Cont[13]~195
D1L43 = CARRY(!D1L40 # !D1_Cont[13]);


--D1L45 is LEDG_Driver:u2|Cont[14]~196
D1L45 = D1_Cont[14] & (D1L43 $ GND) # !D1_Cont[14] & !D1L43 & VCC;

--D1L46 is LEDG_Driver:u2|Cont[14]~197
D1L46 = CARRY(D1_Cont[14] & !D1L43);


--D1L48 is LEDG_Driver:u2|Cont[15]~198
D1L48 = D1_Cont[15] & !D1L46 # !D1_Cont[15] & (D1L46 # GND);

--D1L49 is LEDG_Driver:u2|Cont[15]~199
D1L49 = CARRY(!D1L46 # !D1_Cont[15]);


--D1L51 is LEDG_Driver:u2|Cont[16]~200
D1L51 = D1_Cont[16] & (D1L49 $ GND) # !D1_Cont[16] & !D1L49 & VCC;

--D1L52 is LEDG_Driver:u2|Cont[16]~201
D1L52 = CARRY(D1_Cont[16] & !D1L49);


--D1L54 is LEDG_Driver:u2|Cont[17]~202
D1L54 = D1_Cont[17] & !D1L52 # !D1_Cont[17] & (D1L52 # GND);

--D1L55 is LEDG_Driver:u2|Cont[17]~203
D1L55 = CARRY(!D1L52 # !D1_Cont[17]);


--D1L57 is LEDG_Driver:u2|Cont[18]~204
D1L57 = D1_Cont[18] & (D1L55 $ GND) # !D1_Cont[18] & !D1L55 & VCC;

--D1L58 is LEDG_Driver:u2|Cont[18]~205
D1L58 = CARRY(D1_Cont[18] & !D1L55);


--D1L60 is LEDG_Driver:u2|Cont[19]~206
D1L60 = D1_Cont[19] & !D1L58 # !D1_Cont[19] & (D1L58 # GND);

--D1L61 is LEDG_Driver:u2|Cont[19]~207
D1L61 = CARRY(!D1L58 # !D1_Cont[19]);


--D1L63 is LEDG_Driver:u2|Cont[20]~208
D1L63 = D1_Cont[20] $ !D1L61;


--C1L69 is LEDR_Driver:u1|Equal~158
C1L69 = C1_mLED[0] & !C1_mLED[4] & !C1_mLED[5] & !C1_mLED[9];


--C1L66 is LEDR_Driver:u1|DIR~100
C1L66 = C1_mLED[6] & !C1_mLED[3] & C1_mLED[8] & !C1_DIR # !C1_mLED[6] & C1_mLED[3] & !C1_mLED[8] & C1_DIR;


--C1L67 is LEDR_Driver:u1|DIR~101
C1L67 = C1_mLED[1] & (C1_DIR # C1_mLED[2] & C1_mLED[7]) # !C1_mLED[1] & C1_DIR & (C1_mLED[2] # C1_mLED[7]);


--C1L68 is LEDR_Driver:u1|DIR~102
C1L68 = C1L69 & (C1L66 & (C1L67) # !C1L66 & C1_DIR) # !C1L69 & (C1_DIR);


--C1_Cont[19] is LEDR_Driver:u1|Cont[19]
C1_Cont[19] = DFFEAS(C1L60, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[18] is LEDR_Driver:u1|Cont[18]
C1_Cont[18] = DFFEAS(C1L57, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[17] is LEDR_Driver:u1|Cont[17]
C1_Cont[17] = DFFEAS(C1L54, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[16] is LEDR_Driver:u1|Cont[16]
C1_Cont[16] = DFFEAS(C1L51, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[15] is LEDR_Driver:u1|Cont[15]
C1_Cont[15] = DFFEAS(C1L48, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[14] is LEDR_Driver:u1|Cont[14]
C1_Cont[14] = DFFEAS(C1L45, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[13] is LEDR_Driver:u1|Cont[13]
C1_Cont[13] = DFFEAS(C1L42, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[12] is LEDR_Driver:u1|Cont[12]
C1_Cont[12] = DFFEAS(C1L39, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[11] is LEDR_Driver:u1|Cont[11]
C1_Cont[11] = DFFEAS(C1L36, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[10] is LEDR_Driver:u1|Cont[10]
C1_Cont[10] = DFFEAS(C1L33, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[9] is LEDR_Driver:u1|Cont[9]
C1_Cont[9] = DFFEAS(C1L30, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[8] is LEDR_Driver:u1|Cont[8]
C1_Cont[8] = DFFEAS(C1L27, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[7] is LEDR_Driver:u1|Cont[7]
C1_Cont[7] = DFFEAS(C1L24, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[6] is LEDR_Driver:u1|Cont[6]
C1_Cont[6] = DFFEAS(C1L21, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[5] is LEDR_Driver:u1|Cont[5]
C1_Cont[5] = DFFEAS(C1L18, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[4] is LEDR_Driver:u1|Cont[4]
C1_Cont[4] = DFFEAS(C1L15, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[3] is LEDR_Driver:u1|Cont[3]
C1_Cont[3] = DFFEAS(C1L12, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[2] is LEDR_Driver:u1|Cont[2]
C1_Cont[2] = DFFEAS(C1L9, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[1] is LEDR_Driver:u1|Cont[1]
C1_Cont[1] = DFFEAS(C1L6, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1_Cont[0] is LEDR_Driver:u1|Cont[0]
C1_Cont[0] = DFFEAS(C1L3, CLOCK_27[0],  ,  ,  ,  ,  ,  ,  );


--C1L3 is LEDR_Driver:u1|Cont[0]~168
C1L3 = C1_Cont[0] $ VCC;

--C1L4 is LEDR_Driver:u1|Cont[0]~169
C1L4 = CARRY(C1_Cont[0]);


--C1L6 is LEDR_Driver:u1|Cont[1]~170
C1L6 = C1_Cont[1] & !C1L4 # !C1_Cont[1] & (C1L4 # GND);

--C1L7 is LEDR_Driver:u1|Cont[1]~171
C1L7 = CARRY(!C1L4 # !C1_Cont[1]);


--C1L9 is LEDR_Driver:u1|Cont[2]~172
C1L9 = C1_Cont[2] & (C1L7 $ GND) # !C1_Cont[2] & !C1L7 & VCC;

--C1L10 is LEDR_Driver:u1|Cont[2]~173
C1L10 = CARRY(C1_Cont[2] & !C1L7);


--C1L12 is LEDR_Driver:u1|Cont[3]~174
C1L12 = C1_Cont[3] & !C1L10 # !C1_Cont[3] & (C1L10 # GND);

--C1L13 is LEDR_Driver:u1|Cont[3]~175
C1L13 = CARRY(!C1L10 # !C1_Cont[3]);


--C1L15 is LEDR_Driver:u1|Cont[4]~176
C1L15 = C1_Cont[4] & (C1L13 $ GND) # !C1_Cont[4] & !C1L13 & VCC;

--C1L16 is LEDR_Driver:u1|Cont[4]~177
C1L16 = CARRY(C1_Cont[4] & !C1L13);


--C1L18 is LEDR_Driver:u1|Cont[5]~178
C1L18 = C1_Cont[5] & !C1L16 # !C1_Cont[5] & (C1L16 # GND);

--C1L19 is LEDR_Driver:u1|Cont[5]~179
C1L19 = CARRY(!C1L16 # !C1_Cont[5]);


--C1L21 is LEDR_Driver:u1|Cont[6]~180
C1L21 = C1_Cont[6] & (C1L19 $ GND) # !C1_Cont[6] & !C1L19 & VCC;

--C1L22 is LEDR_Driver:u1|Cont[6]~181
C1L22 = CARRY(C1_Cont[6] & !C1L19);


--C1L24 is LEDR_Driver:u1|Cont[7]~182
C1L24 = C1_Cont[7] & !C1L22 # !C1_Cont[7] & (C1L22 # GND);

--C1L25 is LEDR_Driver:u1|Cont[7]~183
C1L25 = CARRY(!C1L22 # !C1_Cont[7]);


--C1L27 is LEDR_Driver:u1|Cont[8]~184
C1L27 = C1_Cont[8] & (C1L25 $ GND) # !C1_Cont[8] & !C1L25 & VCC;

--C1L28 is LEDR_Driver:u1|Cont[8]~185
C1L28 = CARRY(C1_Cont[8] & !C1L25);


--C1L30 is LEDR_Driver:u1|Cont[9]~186
C1L30 = C1_Cont[9] & !C1L28 # !C1_Cont[9] & (C1L28 # GND);

--C1L31 is LEDR_Driver:u1|Cont[9]~187
C1L31 = CARRY(!C1L28 # !C1_Cont[9]);


--C1L33 is LEDR_Driver:u1|Cont[10]~188
C1L33 = C1_Cont[10] & (C1L31 $ GND) # !C1_Cont[10] & !C1L31 & VCC;

--C1L34 is LEDR_Driver:u1|Cont[10]~189
C1L34 = CARRY(C1_Cont[10] & !C1L31);


--C1L36 is LEDR_Driver:u1|Cont[11]~190
C1L36 = C1_Cont[11] & !C1L34 # !C1_Cont[11] & (C1L34 # GND);

--C1L37 is LEDR_Driver:u1|Cont[11]~191
C1L37 = CARRY(!C1L34 # !C1_Cont[11]);


--C1L39 is LEDR_Driver:u1|Cont[12]~192
C1L39 = C1_Cont[12] & (C1L37 $ GND) # !C1_Cont[12] & !C1L37 & VCC;

--C1L40 is LEDR_Driver:u1|Cont[12]~193
C1L40 = CARRY(C1_Cont[12] & !C1L37);


--C1L42 is LEDR_Driver:u1|Cont[13]~194
C1L42 = C1_Cont[13] & !C1L40 # !C1_Cont[13] & (C1L40 # GND);

--C1L43 is LEDR_Driver:u1|Cont[13]~195
C1L43 = CARRY(!C1L40 # !C1_Cont[13]);


--C1L45 is LEDR_Driver:u1|Cont[14]~196
C1L45 = C1_Cont[14] & (C1L43 $ GND) # !C1_Cont[14] & !C1L43 & VCC;

--C1L46 is LEDR_Driver:u1|Cont[14]~197
C1L46 = CARRY(C1_Cont[14] & !C1L43);


--C1L48 is LEDR_Driver:u1|Cont[15]~198
C1L48 = C1_Cont[15] & !C1L46 # !C1_Cont[15] & (C1L46 # GND);

--C1L49 is LEDR_Driver:u1|Cont[15]~199
C1L49 = CARRY(!C1L46 # !C1_Cont[15]);


--C1L51 is LEDR_Driver:u1|Cont[16]~200
C1L51 = C1_Cont[16] & (C1L49 $ GND) # !C1_Cont[16] & !C1L49 & VCC;

--C1L52 is LEDR_Driver:u1|Cont[16]~201
C1L52 = CARRY(C1_Cont[16] & !C1L49);


--C1L54 is LEDR_Driver:u1|Cont[17]~202
C1L54 = C1_Cont[17] & !C1L52 # !C1_Cont[17] & (C1L52 # GND);

--C1L55 is LEDR_Driver:u1|Cont[17]~203
C1L55 = CARRY(!C1L52 # !C1_Cont[17]);


--C1L57 is LEDR_Driver:u1|Cont[18]~204
C1L57 = C1_Cont[18] & (C1L55 $ GND) # !C1_Cont[18] & !C1L55 & VCC;

--C1L58 is LEDR_Driver:u1|Cont[18]~205
C1L58 = CARRY(C1_Cont[18] & !C1L55);


--C1L60 is LEDR_Driver:u1|Cont[19]~206
C1L60 = C1_Cont[19] & !C1L58 # !C1_Cont[19] & (C1L58 # GND);

--C1L61 is LEDR_Driver:u1|Cont[19]~207
C1L61 = CARRY(!C1L58 # !C1_Cont[19]);


--C1L63 is LEDR_Driver:u1|Cont[20]~208
C1L63 = C1_Cont[20] $ !C1L61;


--V1_END is I2C_AV_Config:u7|I2C_Controller:u0|END
V1_END = DFFEAS(V1L14, J1_mI2C_CTRL_CLK, KEY[0],  ,  ,  ,  ,  ,  );


--J1_mSetup_ST.10 is I2C_AV_Config:u7|mSetup_ST.10
J1_mSetup_ST.10 = DFFEAS(J1L90, J1_mI2C_CTRL_CLK, KEY[0],  ,  ,  ,  ,  ,  );


--J1_mSetup_ST.01 is I2C_AV_Config:u7|mSetup_ST.01
J1_mSetup_ST.01 = DFFEAS(J1L20, J1_mI2C_CTRL_CLK, KEY[0],  ,  ,  ,  ,  ,  );


--J1L19 is I2C_AV_Config:u7|Select~135
J1L19 = J1_mI2C_GO & (V1_END # !J1_mSetup_ST.01) # !J1_mI2C_GO & (!J1_mSetup_ST.10 & !J1_mSetup_ST.01);


--J1_mI2C_CLK_DIV[1] is I2C_AV_Config:u7|mI2C_CLK_DIV[1]
J1_mI2C_CLK_DIV[1] = DFFEAS(J1L27, CLOCK_50, KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[0] is I2C_AV_Config:u7|mI2C_CLK_DIV[0]
J1_mI2C_CLK_DIV[0] = DFFEAS(J1L24, CLOCK_50, KEY[0],  ,  ,  ,  , J1L18,  );


--J1L24 is I2C_AV_Config:u7|mI2C_CLK_DIV[0]~239
J1L24 = J1_mI2C_CLK_DIV[0] $ VCC;

--J1L25 is I2C_AV_Config:u7|mI2C_CLK_DIV[0]~240
J1L25 = CARRY(J1_mI2C_CLK_DIV[0]);


--J1L27 is I2C_AV_Config:u7|mI2C_CLK_DIV[1]~241
J1L27 = J1_mI2C_CLK_DIV[1] & !J1L25 # !J1_mI2C_CLK_DIV[1] & (J1L25 # GND);

--J1L28 is I2C_AV_Config:u7|mI2C_CLK_DIV[1]~242
J1L28 = CARRY(!J1L25 # !J1_mI2C_CLK_DIV[1]);


--J1L30 is I2C_AV_Config:u7|mI2C_CLK_DIV[2]~243
J1L30 = J1_mI2C_CLK_DIV[2] & (J1L28 $ GND) # !J1_mI2C_CLK_DIV[2] & !J1L28 & VCC;

--J1L31 is I2C_AV_Config:u7|mI2C_CLK_DIV[2]~244
J1L31 = CARRY(J1_mI2C_CLK_DIV[2] & !J1L28);


--J1L33 is I2C_AV_Config:u7|mI2C_CLK_DIV[3]~245
J1L33 = J1_mI2C_CLK_DIV[3] & !J1L31 # !J1_mI2C_CLK_DIV[3] & (J1L31 # GND);

--J1L34 is I2C_AV_Config:u7|mI2C_CLK_DIV[3]~246
J1L34 = CARRY(!J1L31 # !J1_mI2C_CLK_DIV[3]);


--J1L36 is I2C_AV_Config:u7|mI2C_CLK_DIV[4]~247
J1L36 = J1_mI2C_CLK_DIV[4] & (J1L34 $ GND) # !J1_mI2C_CLK_DIV[4] & !J1L34 & VCC;

--J1L37 is I2C_AV_Config:u7|mI2C_CLK_DIV[4]~248
J1L37 = CARRY(J1_mI2C_CLK_DIV[4] & !J1L34);


--J1L39 is I2C_AV_Config:u7|mI2C_CLK_DIV[5]~249
J1L39 = J1_mI2C_CLK_DIV[5] & !J1L37 # !J1_mI2C_CLK_DIV[5] & (J1L37 # GND);

--J1L40 is I2C_AV_Config:u7|mI2C_CLK_DIV[5]~250
J1L40 = CARRY(!J1L37 # !J1_mI2C_CLK_DIV[5]);


--J1L42 is I2C_AV_Config:u7|mI2C_CLK_DIV[6]~251
J1L42 = J1_mI2C_CLK_DIV[6] & (J1L40 $ GND) # !J1_mI2C_CLK_DIV[6] & !J1L40 & VCC;

--J1L43 is I2C_AV_Config:u7|mI2C_CLK_DIV[6]~252
J1L43 = CARRY(J1_mI2C_CLK_DIV[6] & !J1L40);


--J1L45 is I2C_AV_Config:u7|mI2C_CLK_DIV[7]~253
J1L45 = J1_mI2C_CLK_DIV[7] & !J1L43 # !J1_mI2C_CLK_DIV[7] & (J1L43 # GND);

--J1L46 is I2C_AV_Config:u7|mI2C_CLK_DIV[7]~254
J1L46 = CARRY(!J1L43 # !J1_mI2C_CLK_DIV[7]);


--J1L48 is I2C_AV_Config:u7|mI2C_CLK_DIV[8]~255
J1L48 = J1_mI2C_CLK_DIV[8] & (J1L46 $ GND) # !J1_mI2C_CLK_DIV[8] & !J1L46 & VCC;

--J1L49 is I2C_AV_Config:u7|mI2C_CLK_DIV[8]~256
J1L49 = CARRY(J1_mI2C_CLK_DIV[8] & !J1L46);


--J1L51 is I2C_AV_Config:u7|mI2C_CLK_DIV[9]~257
J1L51 = J1_mI2C_CLK_DIV[9] & !J1L49 # !J1_mI2C_CLK_DIV[9] & (J1L49 # GND);

--J1L52 is I2C_AV_Config:u7|mI2C_CLK_DIV[9]~258
J1L52 = CARRY(!J1L49 # !J1_mI2C_CLK_DIV[9]);


--J1L54 is I2C_AV_Config:u7|mI2C_CLK_DIV[10]~259
J1L54 = J1_mI2C_CLK_DIV[10] & (J1L52 $ GND) # !J1_mI2C_CLK_DIV[10] & !J1L52 & VCC;

--J1L55 is I2C_AV_Config:u7|mI2C_CLK_DIV[10]~260
J1L55 = CARRY(J1_mI2C_CLK_DIV[10] & !J1L52);


--J1L57 is I2C_AV_Config:u7|mI2C_CLK_DIV[11]~261
J1L57 = J1_mI2C_CLK_DIV[11] & !J1L55 # !J1_mI2C_CLK_DIV[11] & (J1L55 # GND);

--J1L58 is I2C_AV_Config:u7|mI2C_CLK_DIV[11]~262
J1L58 = CARRY(!J1L55 # !J1_mI2C_CLK_DIV[11]);


--J1L60 is I2C_AV_Config:u7|mI2C_CLK_DIV[12]~263
J1L60 = J1_mI2C_CLK_DIV[12] & (J1L58 $ GND) # !J1_mI2C_CLK_DIV[12] & !J1L58 & VCC;

--J1L61 is I2C_AV_Config:u7|mI2C_CLK_DIV[12]~264
J1L61 = CARRY(J1_mI2C_CLK_DIV[12] & !J1L58);


--J1L63 is I2C_AV_Config:u7|mI2C_CLK_DIV[13]~265
J1L63 = J1_mI2C_CLK_DIV[13] & !J1L61 # !J1_mI2C_CLK_DIV[13] & (J1L61 # GND);

--J1L64 is I2C_AV_Config:u7|mI2C_CLK_DIV[13]~266
J1L64 = CARRY(!J1L61 # !J1_mI2C_CLK_DIV[13]);


--J1L66 is I2C_AV_Config:u7|mI2C_CLK_DIV[14]~267
J1L66 = J1_mI2C_CLK_DIV[14] & (J1L64 $ GND) # !J1_mI2C_CLK_DIV[14] & !J1L64 & VCC;

--J1L67 is I2C_AV_Config:u7|mI2C_CLK_DIV[14]~268
J1L67 = CARRY(J1_mI2C_CLK_DIV[14] & !J1L64);


--J1L69 is I2C_AV_Config:u7|mI2C_CLK_DIV[15]~269
J1L69 = J1_mI2C_CLK_DIV[15] $ J1L67;


--F1_oCoord_Y[9] is VGA_Controller:u4|oCoord_Y[9]
F1_oCoord_Y[9] = DFFEAS(F1L248, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_Y[8] is VGA_Controller:u4|oCoord_Y[8]
F1_oCoord_Y[8] = DFFEAS(F1L245, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_Y[7] is VGA_Controller:u4|oCoord_Y[7]
F1_oCoord_Y[7] = DFFEAS(F1L242, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_Y[4] is VGA_Controller:u4|oCoord_Y[4]
F1_oCoord_Y[4] = DFFEAS(F1L233, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_Y[3] is VGA_Controller:u4|oCoord_Y[3]
F1_oCoord_Y[3] = DFFEAS(F1L230, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_Y[6] is VGA_Controller:u4|oCoord_Y[6]
F1_oCoord_Y[6] = DFFEAS(F1L239, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_Y[5] is VGA_Controller:u4|oCoord_Y[5]
F1_oCoord_Y[5] = DFFEAS(F1L236, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--G1L1 is VGA_Pattern:u5|LessThan~2783
G1L1 = !F1_oCoord_Y[4] & !F1_oCoord_Y[3] # !F1_oCoord_Y[5] # !F1_oCoord_Y[6];


--G1L49 is VGA_Pattern:u5|oRed~94
G1L49 = F1_oCoord_Y[9] # F1_oCoord_Y[8] & (F1_oCoord_Y[7] # !G1L1);


--F1_oCoord_X[7] is VGA_Controller:u4|oCoord_X[7]
F1_oCoord_X[7] = DFFEAS(F1L211, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_X[8] is VGA_Controller:u4|oCoord_X[8]
F1_oCoord_X[8] = DFFEAS(F1L214, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--H1L12 is VGA_OSD_RAM:u6|LessThan~450
H1L12 = !F1_oCoord_X[7] & !F1_oCoord_X[8];


--F1_oCoord_X[4] is VGA_Controller:u4|oCoord_X[4]
F1_oCoord_X[4] = DFFEAS(F1L202, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_X[5] is VGA_Controller:u4|oCoord_X[5]
F1_oCoord_X[5] = DFFEAS(F1L205, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_X[2] is VGA_Controller:u4|oCoord_X[2]
F1_oCoord_X[2] = DFFEAS(F1L196, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_X[3] is VGA_Controller:u4|oCoord_X[3]
F1_oCoord_X[3] = DFFEAS(F1L199, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--H1L13 is VGA_OSD_RAM:u6|LessThan~451
H1L13 = !F1_oCoord_X[4] & !F1_oCoord_X[5] & !F1_oCoord_X[2] & !F1_oCoord_X[3];


--F1_oCoord_X[6] is VGA_Controller:u4|oCoord_X[6]
F1_oCoord_X[6] = DFFEAS(F1L208, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_X[9] is VGA_Controller:u4|oCoord_X[9]
F1_oCoord_X[9] = DFFEAS(F1L217, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--H1L14 is VGA_OSD_RAM:u6|LessThan~452
H1L14 = H1L12 & (H1L13 # !F1_oCoord_X[6]) # !F1_oCoord_X[9];


--F1_oCoord_Y[2] is VGA_Controller:u4|oCoord_Y[2]
F1_oCoord_Y[2] = DFFEAS(F1L227, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1L225 is VGA_Controller:u4|oCoord_Y[2]~475
F1L225 = !F1_oCoord_Y[3] & !F1_oCoord_Y[2];


--F1_oCoord_Y[1] is VGA_Controller:u4|oCoord_Y[1]
F1_oCoord_Y[1] = DFFEAS(F1L222, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--G1L2 is VGA_Pattern:u5|LessThan~2784
G1L2 = F1_oCoord_Y[4] & F1_oCoord_Y[5];


--H1L15 is VGA_OSD_RAM:u6|LessThan~453
H1L15 = !F1_oCoord_Y[7] & !F1_oCoord_Y[6];


--H1L138 is VGA_OSD_RAM:u6|oRed~81
H1L138 = !F1_oCoord_Y[9] & (F1_oCoord_Y[8] # !H1L15 # !H1L19);


--F1L226 is VGA_Controller:u4|oCoord_Y[2]~476
F1L226 = F1L225 & !F1_oCoord_Y[4] & !F1_oCoord_Y[5] & !F1_oCoord_Y[1];


--H1L16 is VGA_OSD_RAM:u6|LessThan~454
H1L16 = F1L226 # !F1_oCoord_Y[6] # !F1_oCoord_Y[7] # !F1_oCoord_Y[8];


--H1L17 is VGA_OSD_RAM:u6|LessThan~455
H1L17 = !F1_oCoord_X[9] & !F1_oCoord_X[7] & !F1_oCoord_X[8] & !F1_oCoord_X[6];


--G1L40 is VGA_Pattern:u5|oGreen~1204
G1L40 = F1_oCoord_X[4] & F1_oCoord_X[5];


--H1L18 is VGA_OSD_RAM:u6|LessThan~456
H1L18 = H1L17 & (!G1L40 # !F1_oCoord_X[3] # !F1_oCoord_X[2]);


--H1L139 is VGA_OSD_RAM:u6|oRed~82
H1L139 = H1L14 & H1L138 & H1L16 & !H1L18;


--R1_address_reg_a[9] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[9]
R1_address_reg_a[9] = DFFEAS(R1_address_reg_a[3], M1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1_address_reg_a[8] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[8]
R1_address_reg_a[8] = DFFEAS(R1_address_reg_a[2], M1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1_address_reg_a[7] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[7]
R1_address_reg_a[7] = DFFEAS(R1_address_reg_a[1], M1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1_ram_block2a50 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 400, Port A Width: 8, Port B Depth: 3200, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a50_PORT_A_data_in_reg = DFFE(R1_ram_block2a50_PORT_A_data_in, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_data_in = ~GND;
R1_ram_block2a50_PORT_B_data_in_reg = DFFE(R1_ram_block2a50_PORT_B_data_in, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a50_PORT_A_address_reg = DFFE(R1_ram_block2a50_PORT_A_address, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a50_PORT_B_address_reg = DFFE(R1_ram_block2a50_PORT_B_address, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_write_enable = GND;
R1_ram_block2a50_PORT_A_write_enable_reg = DFFE(R1_ram_block2a50_PORT_A_write_enable, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_write_enable = GND;
R1_ram_block2a50_PORT_B_write_enable_reg = DFFE(R1_ram_block2a50_PORT_B_write_enable, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_clock_0 = M1__clk0;
R1_ram_block2a50_clock_1 = GND;
R1_ram_block2a50_clock_enable_0 = S3L106;
R1_ram_block2a50_clock_enable_1 = GND;
R1_ram_block2a50_PORT_A_data_out = MEMORY(R1_ram_block2a50_PORT_A_data_in_reg, R1_ram_block2a50_PORT_B_data_in_reg, R1_ram_block2a50_PORT_A_address_reg, R1_ram_block2a50_PORT_B_address_reg, R1_ram_block2a50_PORT_A_write_enable_reg, R1_ram_block2a50_PORT_B_write_enable_reg, , , R1_ram_block2a50_clock_0, R1_ram_block2a50_clock_1, R1_ram_block2a50_clock_enable_0, R1_ram_block2a50_clock_enable_1, , );
R1_ram_block2a50_PORT_A_data_out_reg = DFFE(R1_ram_block2a50_PORT_A_data_out, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50 = R1_ram_block2a50_PORT_A_data_out_reg[0];

--R1M2542Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT1
R1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a50_PORT_A_data_in_reg = DFFE(R1_ram_block2a50_PORT_A_data_in, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_data_in = ~GND;
R1_ram_block2a50_PORT_B_data_in_reg = DFFE(R1_ram_block2a50_PORT_B_data_in, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a50_PORT_A_address_reg = DFFE(R1_ram_block2a50_PORT_A_address, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a50_PORT_B_address_reg = DFFE(R1_ram_block2a50_PORT_B_address, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_write_enable = GND;
R1_ram_block2a50_PORT_A_write_enable_reg = DFFE(R1_ram_block2a50_PORT_A_write_enable, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_write_enable = GND;
R1_ram_block2a50_PORT_B_write_enable_reg = DFFE(R1_ram_block2a50_PORT_B_write_enable, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_clock_0 = M1__clk0;
R1_ram_block2a50_clock_1 = GND;
R1_ram_block2a50_clock_enable_0 = S3L106;
R1_ram_block2a50_clock_enable_1 = GND;
R1_ram_block2a50_PORT_A_data_out = MEMORY(R1_ram_block2a50_PORT_A_data_in_reg, R1_ram_block2a50_PORT_B_data_in_reg, R1_ram_block2a50_PORT_A_address_reg, R1_ram_block2a50_PORT_B_address_reg, R1_ram_block2a50_PORT_A_write_enable_reg, R1_ram_block2a50_PORT_B_write_enable_reg, , , R1_ram_block2a50_clock_0, R1_ram_block2a50_clock_1, R1_ram_block2a50_clock_enable_0, R1_ram_block2a50_clock_enable_1, , );
R1_ram_block2a50_PORT_A_data_out_reg = DFFE(R1_ram_block2a50_PORT_A_data_out, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1M2542Q = R1_ram_block2a50_PORT_A_data_out_reg[1];

--R1M2543Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT2
R1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a50_PORT_A_data_in_reg = DFFE(R1_ram_block2a50_PORT_A_data_in, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_data_in = ~GND;
R1_ram_block2a50_PORT_B_data_in_reg = DFFE(R1_ram_block2a50_PORT_B_data_in, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a50_PORT_A_address_reg = DFFE(R1_ram_block2a50_PORT_A_address, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a50_PORT_B_address_reg = DFFE(R1_ram_block2a50_PORT_B_address, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_write_enable = GND;
R1_ram_block2a50_PORT_A_write_enable_reg = DFFE(R1_ram_block2a50_PORT_A_write_enable, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_write_enable = GND;
R1_ram_block2a50_PORT_B_write_enable_reg = DFFE(R1_ram_block2a50_PORT_B_write_enable, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_clock_0 = M1__clk0;
R1_ram_block2a50_clock_1 = GND;
R1_ram_block2a50_clock_enable_0 = S3L106;
R1_ram_block2a50_clock_enable_1 = GND;
R1_ram_block2a50_PORT_A_data_out = MEMORY(R1_ram_block2a50_PORT_A_data_in_reg, R1_ram_block2a50_PORT_B_data_in_reg, R1_ram_block2a50_PORT_A_address_reg, R1_ram_block2a50_PORT_B_address_reg, R1_ram_block2a50_PORT_A_write_enable_reg, R1_ram_block2a50_PORT_B_write_enable_reg, , , R1_ram_block2a50_clock_0, R1_ram_block2a50_clock_1, R1_ram_block2a50_clock_enable_0, R1_ram_block2a50_clock_enable_1, , );
R1_ram_block2a50_PORT_A_data_out_reg = DFFE(R1_ram_block2a50_PORT_A_data_out, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1M2543Q = R1_ram_block2a50_PORT_A_data_out_reg[2];

--R1M2544Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT3
R1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a50_PORT_A_data_in_reg = DFFE(R1_ram_block2a50_PORT_A_data_in, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_data_in = ~GND;
R1_ram_block2a50_PORT_B_data_in_reg = DFFE(R1_ram_block2a50_PORT_B_data_in, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a50_PORT_A_address_reg = DFFE(R1_ram_block2a50_PORT_A_address, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a50_PORT_B_address_reg = DFFE(R1_ram_block2a50_PORT_B_address, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_write_enable = GND;
R1_ram_block2a50_PORT_A_write_enable_reg = DFFE(R1_ram_block2a50_PORT_A_write_enable, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_write_enable = GND;
R1_ram_block2a50_PORT_B_write_enable_reg = DFFE(R1_ram_block2a50_PORT_B_write_enable, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_clock_0 = M1__clk0;
R1_ram_block2a50_clock_1 = GND;
R1_ram_block2a50_clock_enable_0 = S3L106;
R1_ram_block2a50_clock_enable_1 = GND;
R1_ram_block2a50_PORT_A_data_out = MEMORY(R1_ram_block2a50_PORT_A_data_in_reg, R1_ram_block2a50_PORT_B_data_in_reg, R1_ram_block2a50_PORT_A_address_reg, R1_ram_block2a50_PORT_B_address_reg, R1_ram_block2a50_PORT_A_write_enable_reg, R1_ram_block2a50_PORT_B_write_enable_reg, , , R1_ram_block2a50_clock_0, R1_ram_block2a50_clock_1, R1_ram_block2a50_clock_enable_0, R1_ram_block2a50_clock_enable_1, , );
R1_ram_block2a50_PORT_A_data_out_reg = DFFE(R1_ram_block2a50_PORT_A_data_out, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1M2544Q = R1_ram_block2a50_PORT_A_data_out_reg[3];

--R1M2545Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT4
R1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a50_PORT_A_data_in_reg = DFFE(R1_ram_block2a50_PORT_A_data_in, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_data_in = ~GND;
R1_ram_block2a50_PORT_B_data_in_reg = DFFE(R1_ram_block2a50_PORT_B_data_in, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a50_PORT_A_address_reg = DFFE(R1_ram_block2a50_PORT_A_address, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a50_PORT_B_address_reg = DFFE(R1_ram_block2a50_PORT_B_address, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_write_enable = GND;
R1_ram_block2a50_PORT_A_write_enable_reg = DFFE(R1_ram_block2a50_PORT_A_write_enable, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_write_enable = GND;
R1_ram_block2a50_PORT_B_write_enable_reg = DFFE(R1_ram_block2a50_PORT_B_write_enable, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_clock_0 = M1__clk0;
R1_ram_block2a50_clock_1 = GND;
R1_ram_block2a50_clock_enable_0 = S3L106;
R1_ram_block2a50_clock_enable_1 = GND;
R1_ram_block2a50_PORT_A_data_out = MEMORY(R1_ram_block2a50_PORT_A_data_in_reg, R1_ram_block2a50_PORT_B_data_in_reg, R1_ram_block2a50_PORT_A_address_reg, R1_ram_block2a50_PORT_B_address_reg, R1_ram_block2a50_PORT_A_write_enable_reg, R1_ram_block2a50_PORT_B_write_enable_reg, , , R1_ram_block2a50_clock_0, R1_ram_block2a50_clock_1, R1_ram_block2a50_clock_enable_0, R1_ram_block2a50_clock_enable_1, , );
R1_ram_block2a50_PORT_A_data_out_reg = DFFE(R1_ram_block2a50_PORT_A_data_out, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1M2545Q = R1_ram_block2a50_PORT_A_data_out_reg[4];

--R1M2546Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT5
R1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a50_PORT_A_data_in_reg = DFFE(R1_ram_block2a50_PORT_A_data_in, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_data_in = ~GND;
R1_ram_block2a50_PORT_B_data_in_reg = DFFE(R1_ram_block2a50_PORT_B_data_in, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a50_PORT_A_address_reg = DFFE(R1_ram_block2a50_PORT_A_address, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a50_PORT_B_address_reg = DFFE(R1_ram_block2a50_PORT_B_address, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_write_enable = GND;
R1_ram_block2a50_PORT_A_write_enable_reg = DFFE(R1_ram_block2a50_PORT_A_write_enable, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_write_enable = GND;
R1_ram_block2a50_PORT_B_write_enable_reg = DFFE(R1_ram_block2a50_PORT_B_write_enable, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_clock_0 = M1__clk0;
R1_ram_block2a50_clock_1 = GND;
R1_ram_block2a50_clock_enable_0 = S3L106;
R1_ram_block2a50_clock_enable_1 = GND;
R1_ram_block2a50_PORT_A_data_out = MEMORY(R1_ram_block2a50_PORT_A_data_in_reg, R1_ram_block2a50_PORT_B_data_in_reg, R1_ram_block2a50_PORT_A_address_reg, R1_ram_block2a50_PORT_B_address_reg, R1_ram_block2a50_PORT_A_write_enable_reg, R1_ram_block2a50_PORT_B_write_enable_reg, , , R1_ram_block2a50_clock_0, R1_ram_block2a50_clock_1, R1_ram_block2a50_clock_enable_0, R1_ram_block2a50_clock_enable_1, , );
R1_ram_block2a50_PORT_A_data_out_reg = DFFE(R1_ram_block2a50_PORT_A_data_out, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1M2546Q = R1_ram_block2a50_PORT_A_data_out_reg[5];

--R1M2547Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT6
R1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a50_PORT_A_data_in_reg = DFFE(R1_ram_block2a50_PORT_A_data_in, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_data_in = ~GND;
R1_ram_block2a50_PORT_B_data_in_reg = DFFE(R1_ram_block2a50_PORT_B_data_in, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a50_PORT_A_address_reg = DFFE(R1_ram_block2a50_PORT_A_address, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a50_PORT_B_address_reg = DFFE(R1_ram_block2a50_PORT_B_address, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_write_enable = GND;
R1_ram_block2a50_PORT_A_write_enable_reg = DFFE(R1_ram_block2a50_PORT_A_write_enable, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_write_enable = GND;
R1_ram_block2a50_PORT_B_write_enable_reg = DFFE(R1_ram_block2a50_PORT_B_write_enable, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_clock_0 = M1__clk0;
R1_ram_block2a50_clock_1 = GND;
R1_ram_block2a50_clock_enable_0 = S3L106;
R1_ram_block2a50_clock_enable_1 = GND;
R1_ram_block2a50_PORT_A_data_out = MEMORY(R1_ram_block2a50_PORT_A_data_in_reg, R1_ram_block2a50_PORT_B_data_in_reg, R1_ram_block2a50_PORT_A_address_reg, R1_ram_block2a50_PORT_B_address_reg, R1_ram_block2a50_PORT_A_write_enable_reg, R1_ram_block2a50_PORT_B_write_enable_reg, , , R1_ram_block2a50_clock_0, R1_ram_block2a50_clock_1, R1_ram_block2a50_clock_enable_0, R1_ram_block2a50_clock_enable_1, , );
R1_ram_block2a50_PORT_A_data_out_reg = DFFE(R1_ram_block2a50_PORT_A_data_out, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1M2547Q = R1_ram_block2a50_PORT_A_data_out_reg[6];

--R1M2548Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT7
R1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a50_PORT_A_data_in_reg = DFFE(R1_ram_block2a50_PORT_A_data_in, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_data_in = ~GND;
R1_ram_block2a50_PORT_B_data_in_reg = DFFE(R1_ram_block2a50_PORT_B_data_in, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a50_PORT_A_address_reg = DFFE(R1_ram_block2a50_PORT_A_address, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a50_PORT_B_address_reg = DFFE(R1_ram_block2a50_PORT_B_address, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_write_enable = GND;
R1_ram_block2a50_PORT_A_write_enable_reg = DFFE(R1_ram_block2a50_PORT_A_write_enable, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_write_enable = GND;
R1_ram_block2a50_PORT_B_write_enable_reg = DFFE(R1_ram_block2a50_PORT_B_write_enable, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_clock_0 = M1__clk0;
R1_ram_block2a50_clock_1 = GND;
R1_ram_block2a50_clock_enable_0 = S3L106;
R1_ram_block2a50_clock_enable_1 = GND;
R1_ram_block2a50_PORT_A_data_out = MEMORY(R1_ram_block2a50_PORT_A_data_in_reg, R1_ram_block2a50_PORT_B_data_in_reg, R1_ram_block2a50_PORT_A_address_reg, R1_ram_block2a50_PORT_B_address_reg, R1_ram_block2a50_PORT_A_write_enable_reg, R1_ram_block2a50_PORT_B_write_enable_reg, , , R1_ram_block2a50_clock_0, R1_ram_block2a50_clock_1, R1_ram_block2a50_clock_enable_0, R1_ram_block2a50_clock_enable_1, , );
R1_ram_block2a50_PORT_A_data_out_reg = DFFE(R1_ram_block2a50_PORT_A_data_out, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1M2548Q = R1_ram_block2a50_PORT_A_data_out_reg[7];


--T1L46 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5031
T1L46 = R1_address_reg_a[8] & !R1_address_reg_a[7] # !R1_address_reg_a[8] & R1_address_reg_a[7] & R1M2546Q;


--R1_ram_block2a49 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a49_PORT_A_data_in_reg = DFFE(R1_ram_block2a49_PORT_A_data_in, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_data_in = ~GND;
R1_ram_block2a49_PORT_B_data_in_reg = DFFE(R1_ram_block2a49_PORT_B_data_in, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a49_PORT_A_address_reg = DFFE(R1_ram_block2a49_PORT_A_address, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a49_PORT_B_address_reg = DFFE(R1_ram_block2a49_PORT_B_address, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_write_enable = GND;
R1_ram_block2a49_PORT_A_write_enable_reg = DFFE(R1_ram_block2a49_PORT_A_write_enable, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_write_enable = GND;
R1_ram_block2a49_PORT_B_write_enable_reg = DFFE(R1_ram_block2a49_PORT_B_write_enable, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_clock_0 = M1__clk0;
R1_ram_block2a49_clock_1 = GND;
R1_ram_block2a49_clock_enable_0 = S3L105;
R1_ram_block2a49_clock_enable_1 = GND;
R1_ram_block2a49_PORT_A_data_out = MEMORY(R1_ram_block2a49_PORT_A_data_in_reg, R1_ram_block2a49_PORT_B_data_in_reg, R1_ram_block2a49_PORT_A_address_reg, R1_ram_block2a49_PORT_B_address_reg, R1_ram_block2a49_PORT_A_write_enable_reg, R1_ram_block2a49_PORT_B_write_enable_reg, , , R1_ram_block2a49_clock_0, R1_ram_block2a49_clock_1, R1_ram_block2a49_clock_enable_0, R1_ram_block2a49_clock_enable_1, , );
R1_ram_block2a49_PORT_A_data_out_reg = DFFE(R1_ram_block2a49_PORT_A_data_out, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49 = R1_ram_block2a49_PORT_A_data_out_reg[0];

--R1M2492Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT1
R1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a49_PORT_A_data_in_reg = DFFE(R1_ram_block2a49_PORT_A_data_in, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_data_in = ~GND;
R1_ram_block2a49_PORT_B_data_in_reg = DFFE(R1_ram_block2a49_PORT_B_data_in, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a49_PORT_A_address_reg = DFFE(R1_ram_block2a49_PORT_A_address, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a49_PORT_B_address_reg = DFFE(R1_ram_block2a49_PORT_B_address, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_write_enable = GND;
R1_ram_block2a49_PORT_A_write_enable_reg = DFFE(R1_ram_block2a49_PORT_A_write_enable, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_write_enable = GND;
R1_ram_block2a49_PORT_B_write_enable_reg = DFFE(R1_ram_block2a49_PORT_B_write_enable, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_clock_0 = M1__clk0;
R1_ram_block2a49_clock_1 = GND;
R1_ram_block2a49_clock_enable_0 = S3L105;
R1_ram_block2a49_clock_enable_1 = GND;
R1_ram_block2a49_PORT_A_data_out = MEMORY(R1_ram_block2a49_PORT_A_data_in_reg, R1_ram_block2a49_PORT_B_data_in_reg, R1_ram_block2a49_PORT_A_address_reg, R1_ram_block2a49_PORT_B_address_reg, R1_ram_block2a49_PORT_A_write_enable_reg, R1_ram_block2a49_PORT_B_write_enable_reg, , , R1_ram_block2a49_clock_0, R1_ram_block2a49_clock_1, R1_ram_block2a49_clock_enable_0, R1_ram_block2a49_clock_enable_1, , );
R1_ram_block2a49_PORT_A_data_out_reg = DFFE(R1_ram_block2a49_PORT_A_data_out, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1M2492Q = R1_ram_block2a49_PORT_A_data_out_reg[1];

--R1M2493Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT2
R1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a49_PORT_A_data_in_reg = DFFE(R1_ram_block2a49_PORT_A_data_in, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_data_in = ~GND;
R1_ram_block2a49_PORT_B_data_in_reg = DFFE(R1_ram_block2a49_PORT_B_data_in, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a49_PORT_A_address_reg = DFFE(R1_ram_block2a49_PORT_A_address, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a49_PORT_B_address_reg = DFFE(R1_ram_block2a49_PORT_B_address, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_write_enable = GND;
R1_ram_block2a49_PORT_A_write_enable_reg = DFFE(R1_ram_block2a49_PORT_A_write_enable, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_write_enable = GND;
R1_ram_block2a49_PORT_B_write_enable_reg = DFFE(R1_ram_block2a49_PORT_B_write_enable, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_clock_0 = M1__clk0;
R1_ram_block2a49_clock_1 = GND;
R1_ram_block2a49_clock_enable_0 = S3L105;
R1_ram_block2a49_clock_enable_1 = GND;
R1_ram_block2a49_PORT_A_data_out = MEMORY(R1_ram_block2a49_PORT_A_data_in_reg, R1_ram_block2a49_PORT_B_data_in_reg, R1_ram_block2a49_PORT_A_address_reg, R1_ram_block2a49_PORT_B_address_reg, R1_ram_block2a49_PORT_A_write_enable_reg, R1_ram_block2a49_PORT_B_write_enable_reg, , , R1_ram_block2a49_clock_0, R1_ram_block2a49_clock_1, R1_ram_block2a49_clock_enable_0, R1_ram_block2a49_clock_enable_1, , );
R1_ram_block2a49_PORT_A_data_out_reg = DFFE(R1_ram_block2a49_PORT_A_data_out, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1M2493Q = R1_ram_block2a49_PORT_A_data_out_reg[2];

--R1M2494Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT3
R1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a49_PORT_A_data_in_reg = DFFE(R1_ram_block2a49_PORT_A_data_in, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_data_in = ~GND;
R1_ram_block2a49_PORT_B_data_in_reg = DFFE(R1_ram_block2a49_PORT_B_data_in, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a49_PORT_A_address_reg = DFFE(R1_ram_block2a49_PORT_A_address, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a49_PORT_B_address_reg = DFFE(R1_ram_block2a49_PORT_B_address, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_write_enable = GND;
R1_ram_block2a49_PORT_A_write_enable_reg = DFFE(R1_ram_block2a49_PORT_A_write_enable, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_write_enable = GND;
R1_ram_block2a49_PORT_B_write_enable_reg = DFFE(R1_ram_block2a49_PORT_B_write_enable, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_clock_0 = M1__clk0;
R1_ram_block2a49_clock_1 = GND;
R1_ram_block2a49_clock_enable_0 = S3L105;
R1_ram_block2a49_clock_enable_1 = GND;
R1_ram_block2a49_PORT_A_data_out = MEMORY(R1_ram_block2a49_PORT_A_data_in_reg, R1_ram_block2a49_PORT_B_data_in_reg, R1_ram_block2a49_PORT_A_address_reg, R1_ram_block2a49_PORT_B_address_reg, R1_ram_block2a49_PORT_A_write_enable_reg, R1_ram_block2a49_PORT_B_write_enable_reg, , , R1_ram_block2a49_clock_0, R1_ram_block2a49_clock_1, R1_ram_block2a49_clock_enable_0, R1_ram_block2a49_clock_enable_1, , );
R1_ram_block2a49_PORT_A_data_out_reg = DFFE(R1_ram_block2a49_PORT_A_data_out, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1M2494Q = R1_ram_block2a49_PORT_A_data_out_reg[3];

--R1M2495Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT4
R1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a49_PORT_A_data_in_reg = DFFE(R1_ram_block2a49_PORT_A_data_in, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_data_in = ~GND;
R1_ram_block2a49_PORT_B_data_in_reg = DFFE(R1_ram_block2a49_PORT_B_data_in, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a49_PORT_A_address_reg = DFFE(R1_ram_block2a49_PORT_A_address, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a49_PORT_B_address_reg = DFFE(R1_ram_block2a49_PORT_B_address, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_write_enable = GND;
R1_ram_block2a49_PORT_A_write_enable_reg = DFFE(R1_ram_block2a49_PORT_A_write_enable, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_write_enable = GND;
R1_ram_block2a49_PORT_B_write_enable_reg = DFFE(R1_ram_block2a49_PORT_B_write_enable, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_clock_0 = M1__clk0;
R1_ram_block2a49_clock_1 = GND;
R1_ram_block2a49_clock_enable_0 = S3L105;
R1_ram_block2a49_clock_enable_1 = GND;
R1_ram_block2a49_PORT_A_data_out = MEMORY(R1_ram_block2a49_PORT_A_data_in_reg, R1_ram_block2a49_PORT_B_data_in_reg, R1_ram_block2a49_PORT_A_address_reg, R1_ram_block2a49_PORT_B_address_reg, R1_ram_block2a49_PORT_A_write_enable_reg, R1_ram_block2a49_PORT_B_write_enable_reg, , , R1_ram_block2a49_clock_0, R1_ram_block2a49_clock_1, R1_ram_block2a49_clock_enable_0, R1_ram_block2a49_clock_enable_1, , );
R1_ram_block2a49_PORT_A_data_out_reg = DFFE(R1_ram_block2a49_PORT_A_data_out, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1M2495Q = R1_ram_block2a49_PORT_A_data_out_reg[4];

--R1M2496Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT5
R1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a49_PORT_A_data_in_reg = DFFE(R1_ram_block2a49_PORT_A_data_in, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_data_in = ~GND;
R1_ram_block2a49_PORT_B_data_in_reg = DFFE(R1_ram_block2a49_PORT_B_data_in, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a49_PORT_A_address_reg = DFFE(R1_ram_block2a49_PORT_A_address, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a49_PORT_B_address_reg = DFFE(R1_ram_block2a49_PORT_B_address, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_write_enable = GND;
R1_ram_block2a49_PORT_A_write_enable_reg = DFFE(R1_ram_block2a49_PORT_A_write_enable, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_write_enable = GND;
R1_ram_block2a49_PORT_B_write_enable_reg = DFFE(R1_ram_block2a49_PORT_B_write_enable, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_clock_0 = M1__clk0;
R1_ram_block2a49_clock_1 = GND;
R1_ram_block2a49_clock_enable_0 = S3L105;
R1_ram_block2a49_clock_enable_1 = GND;
R1_ram_block2a49_PORT_A_data_out = MEMORY(R1_ram_block2a49_PORT_A_data_in_reg, R1_ram_block2a49_PORT_B_data_in_reg, R1_ram_block2a49_PORT_A_address_reg, R1_ram_block2a49_PORT_B_address_reg, R1_ram_block2a49_PORT_A_write_enable_reg, R1_ram_block2a49_PORT_B_write_enable_reg, , , R1_ram_block2a49_clock_0, R1_ram_block2a49_clock_1, R1_ram_block2a49_clock_enable_0, R1_ram_block2a49_clock_enable_1, , );
R1_ram_block2a49_PORT_A_data_out_reg = DFFE(R1_ram_block2a49_PORT_A_data_out, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1M2496Q = R1_ram_block2a49_PORT_A_data_out_reg[5];

--R1M2497Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT6
R1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a49_PORT_A_data_in_reg = DFFE(R1_ram_block2a49_PORT_A_data_in, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_data_in = ~GND;
R1_ram_block2a49_PORT_B_data_in_reg = DFFE(R1_ram_block2a49_PORT_B_data_in, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a49_PORT_A_address_reg = DFFE(R1_ram_block2a49_PORT_A_address, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a49_PORT_B_address_reg = DFFE(R1_ram_block2a49_PORT_B_address, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_write_enable = GND;
R1_ram_block2a49_PORT_A_write_enable_reg = DFFE(R1_ram_block2a49_PORT_A_write_enable, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_write_enable = GND;
R1_ram_block2a49_PORT_B_write_enable_reg = DFFE(R1_ram_block2a49_PORT_B_write_enable, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_clock_0 = M1__clk0;
R1_ram_block2a49_clock_1 = GND;
R1_ram_block2a49_clock_enable_0 = S3L105;
R1_ram_block2a49_clock_enable_1 = GND;
R1_ram_block2a49_PORT_A_data_out = MEMORY(R1_ram_block2a49_PORT_A_data_in_reg, R1_ram_block2a49_PORT_B_data_in_reg, R1_ram_block2a49_PORT_A_address_reg, R1_ram_block2a49_PORT_B_address_reg, R1_ram_block2a49_PORT_A_write_enable_reg, R1_ram_block2a49_PORT_B_write_enable_reg, , , R1_ram_block2a49_clock_0, R1_ram_block2a49_clock_1, R1_ram_block2a49_clock_enable_0, R1_ram_block2a49_clock_enable_1, , );
R1_ram_block2a49_PORT_A_data_out_reg = DFFE(R1_ram_block2a49_PORT_A_data_out, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1M2497Q = R1_ram_block2a49_PORT_A_data_out_reg[6];

--R1M2498Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT7
R1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a49_PORT_A_data_in_reg = DFFE(R1_ram_block2a49_PORT_A_data_in, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_data_in = ~GND;
R1_ram_block2a49_PORT_B_data_in_reg = DFFE(R1_ram_block2a49_PORT_B_data_in, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a49_PORT_A_address_reg = DFFE(R1_ram_block2a49_PORT_A_address, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a49_PORT_B_address_reg = DFFE(R1_ram_block2a49_PORT_B_address, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_write_enable = GND;
R1_ram_block2a49_PORT_A_write_enable_reg = DFFE(R1_ram_block2a49_PORT_A_write_enable, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_write_enable = GND;
R1_ram_block2a49_PORT_B_write_enable_reg = DFFE(R1_ram_block2a49_PORT_B_write_enable, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_clock_0 = M1__clk0;
R1_ram_block2a49_clock_1 = GND;
R1_ram_block2a49_clock_enable_0 = S3L105;
R1_ram_block2a49_clock_enable_1 = GND;
R1_ram_block2a49_PORT_A_data_out = MEMORY(R1_ram_block2a49_PORT_A_data_in_reg, R1_ram_block2a49_PORT_B_data_in_reg, R1_ram_block2a49_PORT_A_address_reg, R1_ram_block2a49_PORT_B_address_reg, R1_ram_block2a49_PORT_A_write_enable_reg, R1_ram_block2a49_PORT_B_write_enable_reg, , , R1_ram_block2a49_clock_0, R1_ram_block2a49_clock_1, R1_ram_block2a49_clock_enable_0, R1_ram_block2a49_clock_enable_1, , );
R1_ram_block2a49_PORT_A_data_out_reg = DFFE(R1_ram_block2a49_PORT_A_data_out, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1M2498Q = R1_ram_block2a49_PORT_A_data_out_reg[7];


--R1_ram_block2a48 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a48_PORT_A_data_in_reg = DFFE(R1_ram_block2a48_PORT_A_data_in, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_data_in = ~GND;
R1_ram_block2a48_PORT_B_data_in_reg = DFFE(R1_ram_block2a48_PORT_B_data_in, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a48_PORT_A_address_reg = DFFE(R1_ram_block2a48_PORT_A_address, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a48_PORT_B_address_reg = DFFE(R1_ram_block2a48_PORT_B_address, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_write_enable = GND;
R1_ram_block2a48_PORT_A_write_enable_reg = DFFE(R1_ram_block2a48_PORT_A_write_enable, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_write_enable = GND;
R1_ram_block2a48_PORT_B_write_enable_reg = DFFE(R1_ram_block2a48_PORT_B_write_enable, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_clock_0 = M1__clk0;
R1_ram_block2a48_clock_1 = GND;
R1_ram_block2a48_clock_enable_0 = S3L104;
R1_ram_block2a48_clock_enable_1 = GND;
R1_ram_block2a48_PORT_A_data_out = MEMORY(R1_ram_block2a48_PORT_A_data_in_reg, R1_ram_block2a48_PORT_B_data_in_reg, R1_ram_block2a48_PORT_A_address_reg, R1_ram_block2a48_PORT_B_address_reg, R1_ram_block2a48_PORT_A_write_enable_reg, R1_ram_block2a48_PORT_B_write_enable_reg, , , R1_ram_block2a48_clock_0, R1_ram_block2a48_clock_1, R1_ram_block2a48_clock_enable_0, R1_ram_block2a48_clock_enable_1, , );
R1_ram_block2a48_PORT_A_data_out_reg = DFFE(R1_ram_block2a48_PORT_A_data_out, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48 = R1_ram_block2a48_PORT_A_data_out_reg[0];

--R1M2442Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT1
R1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a48_PORT_A_data_in_reg = DFFE(R1_ram_block2a48_PORT_A_data_in, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_data_in = ~GND;
R1_ram_block2a48_PORT_B_data_in_reg = DFFE(R1_ram_block2a48_PORT_B_data_in, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a48_PORT_A_address_reg = DFFE(R1_ram_block2a48_PORT_A_address, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a48_PORT_B_address_reg = DFFE(R1_ram_block2a48_PORT_B_address, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_write_enable = GND;
R1_ram_block2a48_PORT_A_write_enable_reg = DFFE(R1_ram_block2a48_PORT_A_write_enable, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_write_enable = GND;
R1_ram_block2a48_PORT_B_write_enable_reg = DFFE(R1_ram_block2a48_PORT_B_write_enable, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_clock_0 = M1__clk0;
R1_ram_block2a48_clock_1 = GND;
R1_ram_block2a48_clock_enable_0 = S3L104;
R1_ram_block2a48_clock_enable_1 = GND;
R1_ram_block2a48_PORT_A_data_out = MEMORY(R1_ram_block2a48_PORT_A_data_in_reg, R1_ram_block2a48_PORT_B_data_in_reg, R1_ram_block2a48_PORT_A_address_reg, R1_ram_block2a48_PORT_B_address_reg, R1_ram_block2a48_PORT_A_write_enable_reg, R1_ram_block2a48_PORT_B_write_enable_reg, , , R1_ram_block2a48_clock_0, R1_ram_block2a48_clock_1, R1_ram_block2a48_clock_enable_0, R1_ram_block2a48_clock_enable_1, , );
R1_ram_block2a48_PORT_A_data_out_reg = DFFE(R1_ram_block2a48_PORT_A_data_out, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1M2442Q = R1_ram_block2a48_PORT_A_data_out_reg[1];

--R1M2443Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT2
R1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a48_PORT_A_data_in_reg = DFFE(R1_ram_block2a48_PORT_A_data_in, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_data_in = ~GND;
R1_ram_block2a48_PORT_B_data_in_reg = DFFE(R1_ram_block2a48_PORT_B_data_in, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a48_PORT_A_address_reg = DFFE(R1_ram_block2a48_PORT_A_address, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a48_PORT_B_address_reg = DFFE(R1_ram_block2a48_PORT_B_address, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_write_enable = GND;
R1_ram_block2a48_PORT_A_write_enable_reg = DFFE(R1_ram_block2a48_PORT_A_write_enable, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_write_enable = GND;
R1_ram_block2a48_PORT_B_write_enable_reg = DFFE(R1_ram_block2a48_PORT_B_write_enable, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_clock_0 = M1__clk0;
R1_ram_block2a48_clock_1 = GND;
R1_ram_block2a48_clock_enable_0 = S3L104;
R1_ram_block2a48_clock_enable_1 = GND;
R1_ram_block2a48_PORT_A_data_out = MEMORY(R1_ram_block2a48_PORT_A_data_in_reg, R1_ram_block2a48_PORT_B_data_in_reg, R1_ram_block2a48_PORT_A_address_reg, R1_ram_block2a48_PORT_B_address_reg, R1_ram_block2a48_PORT_A_write_enable_reg, R1_ram_block2a48_PORT_B_write_enable_reg, , , R1_ram_block2a48_clock_0, R1_ram_block2a48_clock_1, R1_ram_block2a48_clock_enable_0, R1_ram_block2a48_clock_enable_1, , );
R1_ram_block2a48_PORT_A_data_out_reg = DFFE(R1_ram_block2a48_PORT_A_data_out, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1M2443Q = R1_ram_block2a48_PORT_A_data_out_reg[2];

--R1M2444Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT3
R1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a48_PORT_A_data_in_reg = DFFE(R1_ram_block2a48_PORT_A_data_in, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_data_in = ~GND;
R1_ram_block2a48_PORT_B_data_in_reg = DFFE(R1_ram_block2a48_PORT_B_data_in, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a48_PORT_A_address_reg = DFFE(R1_ram_block2a48_PORT_A_address, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a48_PORT_B_address_reg = DFFE(R1_ram_block2a48_PORT_B_address, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_write_enable = GND;
R1_ram_block2a48_PORT_A_write_enable_reg = DFFE(R1_ram_block2a48_PORT_A_write_enable, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_write_enable = GND;
R1_ram_block2a48_PORT_B_write_enable_reg = DFFE(R1_ram_block2a48_PORT_B_write_enable, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_clock_0 = M1__clk0;
R1_ram_block2a48_clock_1 = GND;
R1_ram_block2a48_clock_enable_0 = S3L104;
R1_ram_block2a48_clock_enable_1 = GND;
R1_ram_block2a48_PORT_A_data_out = MEMORY(R1_ram_block2a48_PORT_A_data_in_reg, R1_ram_block2a48_PORT_B_data_in_reg, R1_ram_block2a48_PORT_A_address_reg, R1_ram_block2a48_PORT_B_address_reg, R1_ram_block2a48_PORT_A_write_enable_reg, R1_ram_block2a48_PORT_B_write_enable_reg, , , R1_ram_block2a48_clock_0, R1_ram_block2a48_clock_1, R1_ram_block2a48_clock_enable_0, R1_ram_block2a48_clock_enable_1, , );
R1_ram_block2a48_PORT_A_data_out_reg = DFFE(R1_ram_block2a48_PORT_A_data_out, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1M2444Q = R1_ram_block2a48_PORT_A_data_out_reg[3];

--R1M2445Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT4
R1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a48_PORT_A_data_in_reg = DFFE(R1_ram_block2a48_PORT_A_data_in, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_data_in = ~GND;
R1_ram_block2a48_PORT_B_data_in_reg = DFFE(R1_ram_block2a48_PORT_B_data_in, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a48_PORT_A_address_reg = DFFE(R1_ram_block2a48_PORT_A_address, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a48_PORT_B_address_reg = DFFE(R1_ram_block2a48_PORT_B_address, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_write_enable = GND;
R1_ram_block2a48_PORT_A_write_enable_reg = DFFE(R1_ram_block2a48_PORT_A_write_enable, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_write_enable = GND;
R1_ram_block2a48_PORT_B_write_enable_reg = DFFE(R1_ram_block2a48_PORT_B_write_enable, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_clock_0 = M1__clk0;
R1_ram_block2a48_clock_1 = GND;
R1_ram_block2a48_clock_enable_0 = S3L104;
R1_ram_block2a48_clock_enable_1 = GND;
R1_ram_block2a48_PORT_A_data_out = MEMORY(R1_ram_block2a48_PORT_A_data_in_reg, R1_ram_block2a48_PORT_B_data_in_reg, R1_ram_block2a48_PORT_A_address_reg, R1_ram_block2a48_PORT_B_address_reg, R1_ram_block2a48_PORT_A_write_enable_reg, R1_ram_block2a48_PORT_B_write_enable_reg, , , R1_ram_block2a48_clock_0, R1_ram_block2a48_clock_1, R1_ram_block2a48_clock_enable_0, R1_ram_block2a48_clock_enable_1, , );
R1_ram_block2a48_PORT_A_data_out_reg = DFFE(R1_ram_block2a48_PORT_A_data_out, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1M2445Q = R1_ram_block2a48_PORT_A_data_out_reg[4];

--R1M2446Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT5
R1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a48_PORT_A_data_in_reg = DFFE(R1_ram_block2a48_PORT_A_data_in, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_data_in = ~GND;
R1_ram_block2a48_PORT_B_data_in_reg = DFFE(R1_ram_block2a48_PORT_B_data_in, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a48_PORT_A_address_reg = DFFE(R1_ram_block2a48_PORT_A_address, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a48_PORT_B_address_reg = DFFE(R1_ram_block2a48_PORT_B_address, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_write_enable = GND;
R1_ram_block2a48_PORT_A_write_enable_reg = DFFE(R1_ram_block2a48_PORT_A_write_enable, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_write_enable = GND;
R1_ram_block2a48_PORT_B_write_enable_reg = DFFE(R1_ram_block2a48_PORT_B_write_enable, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_clock_0 = M1__clk0;
R1_ram_block2a48_clock_1 = GND;
R1_ram_block2a48_clock_enable_0 = S3L104;
R1_ram_block2a48_clock_enable_1 = GND;
R1_ram_block2a48_PORT_A_data_out = MEMORY(R1_ram_block2a48_PORT_A_data_in_reg, R1_ram_block2a48_PORT_B_data_in_reg, R1_ram_block2a48_PORT_A_address_reg, R1_ram_block2a48_PORT_B_address_reg, R1_ram_block2a48_PORT_A_write_enable_reg, R1_ram_block2a48_PORT_B_write_enable_reg, , , R1_ram_block2a48_clock_0, R1_ram_block2a48_clock_1, R1_ram_block2a48_clock_enable_0, R1_ram_block2a48_clock_enable_1, , );
R1_ram_block2a48_PORT_A_data_out_reg = DFFE(R1_ram_block2a48_PORT_A_data_out, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1M2446Q = R1_ram_block2a48_PORT_A_data_out_reg[5];

--R1M2447Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT6
R1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a48_PORT_A_data_in_reg = DFFE(R1_ram_block2a48_PORT_A_data_in, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_data_in = ~GND;
R1_ram_block2a48_PORT_B_data_in_reg = DFFE(R1_ram_block2a48_PORT_B_data_in, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a48_PORT_A_address_reg = DFFE(R1_ram_block2a48_PORT_A_address, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a48_PORT_B_address_reg = DFFE(R1_ram_block2a48_PORT_B_address, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_write_enable = GND;
R1_ram_block2a48_PORT_A_write_enable_reg = DFFE(R1_ram_block2a48_PORT_A_write_enable, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_write_enable = GND;
R1_ram_block2a48_PORT_B_write_enable_reg = DFFE(R1_ram_block2a48_PORT_B_write_enable, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_clock_0 = M1__clk0;
R1_ram_block2a48_clock_1 = GND;
R1_ram_block2a48_clock_enable_0 = S3L104;
R1_ram_block2a48_clock_enable_1 = GND;
R1_ram_block2a48_PORT_A_data_out = MEMORY(R1_ram_block2a48_PORT_A_data_in_reg, R1_ram_block2a48_PORT_B_data_in_reg, R1_ram_block2a48_PORT_A_address_reg, R1_ram_block2a48_PORT_B_address_reg, R1_ram_block2a48_PORT_A_write_enable_reg, R1_ram_block2a48_PORT_B_write_enable_reg, , , R1_ram_block2a48_clock_0, R1_ram_block2a48_clock_1, R1_ram_block2a48_clock_enable_0, R1_ram_block2a48_clock_enable_1, , );
R1_ram_block2a48_PORT_A_data_out_reg = DFFE(R1_ram_block2a48_PORT_A_data_out, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1M2447Q = R1_ram_block2a48_PORT_A_data_out_reg[6];

--R1M2448Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT7
R1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a48_PORT_A_data_in_reg = DFFE(R1_ram_block2a48_PORT_A_data_in, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_data_in = ~GND;
R1_ram_block2a48_PORT_B_data_in_reg = DFFE(R1_ram_block2a48_PORT_B_data_in, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a48_PORT_A_address_reg = DFFE(R1_ram_block2a48_PORT_A_address, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a48_PORT_B_address_reg = DFFE(R1_ram_block2a48_PORT_B_address, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_write_enable = GND;
R1_ram_block2a48_PORT_A_write_enable_reg = DFFE(R1_ram_block2a48_PORT_A_write_enable, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_write_enable = GND;
R1_ram_block2a48_PORT_B_write_enable_reg = DFFE(R1_ram_block2a48_PORT_B_write_enable, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_clock_0 = M1__clk0;
R1_ram_block2a48_clock_1 = GND;
R1_ram_block2a48_clock_enable_0 = S3L104;
R1_ram_block2a48_clock_enable_1 = GND;
R1_ram_block2a48_PORT_A_data_out = MEMORY(R1_ram_block2a48_PORT_A_data_in_reg, R1_ram_block2a48_PORT_B_data_in_reg, R1_ram_block2a48_PORT_A_address_reg, R1_ram_block2a48_PORT_B_address_reg, R1_ram_block2a48_PORT_A_write_enable_reg, R1_ram_block2a48_PORT_B_write_enable_reg, , , R1_ram_block2a48_clock_0, R1_ram_block2a48_clock_1, R1_ram_block2a48_clock_enable_0, R1_ram_block2a48_clock_enable_1, , );
R1_ram_block2a48_PORT_A_data_out_reg = DFFE(R1_ram_block2a48_PORT_A_data_out, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1M2448Q = R1_ram_block2a48_PORT_A_data_out_reg[7];


--R1_address_reg_a[6] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[6]
R1_address_reg_a[6] = DFFEAS(R1_address_reg_a[0], M1__clk0,  ,  ,  ,  ,  ,  ,  );


--T1L47 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5032
T1L47 = R1_address_reg_a[6] & (R1M2496Q # R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1M2446Q & !R1_address_reg_a[7]);


--T1L48 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5033
T1L48 = !R1_address_reg_a[9] & (T1L46 & R1_address_reg_a[7] & !T1L47 # !T1L46 & !R1_address_reg_a[7] & T1L47);


--R1_ram_block2a30 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a30_PORT_A_data_in_reg = DFFE(R1_ram_block2a30_PORT_A_data_in, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_data_in = ~GND;
R1_ram_block2a30_PORT_B_data_in_reg = DFFE(R1_ram_block2a30_PORT_B_data_in, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a30_PORT_A_address_reg = DFFE(R1_ram_block2a30_PORT_A_address, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a30_PORT_B_address_reg = DFFE(R1_ram_block2a30_PORT_B_address, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_write_enable = GND;
R1_ram_block2a30_PORT_A_write_enable_reg = DFFE(R1_ram_block2a30_PORT_A_write_enable, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_write_enable = GND;
R1_ram_block2a30_PORT_B_write_enable_reg = DFFE(R1_ram_block2a30_PORT_B_write_enable, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_clock_0 = M1__clk0;
R1_ram_block2a30_clock_1 = GND;
R1_ram_block2a30_clock_enable_0 = S3_w_anode3199w[3];
R1_ram_block2a30_clock_enable_1 = GND;
R1_ram_block2a30_PORT_A_data_out = MEMORY(R1_ram_block2a30_PORT_A_data_in_reg, R1_ram_block2a30_PORT_B_data_in_reg, R1_ram_block2a30_PORT_A_address_reg, R1_ram_block2a30_PORT_B_address_reg, R1_ram_block2a30_PORT_A_write_enable_reg, R1_ram_block2a30_PORT_B_write_enable_reg, , , R1_ram_block2a30_clock_0, R1_ram_block2a30_clock_1, R1_ram_block2a30_clock_enable_0, R1_ram_block2a30_clock_enable_1, , );
R1_ram_block2a30_PORT_A_data_out_reg = DFFE(R1_ram_block2a30_PORT_A_data_out, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30 = R1_ram_block2a30_PORT_A_data_out_reg[0];

--R1M1542Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT1
R1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a30_PORT_A_data_in_reg = DFFE(R1_ram_block2a30_PORT_A_data_in, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_data_in = ~GND;
R1_ram_block2a30_PORT_B_data_in_reg = DFFE(R1_ram_block2a30_PORT_B_data_in, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a30_PORT_A_address_reg = DFFE(R1_ram_block2a30_PORT_A_address, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a30_PORT_B_address_reg = DFFE(R1_ram_block2a30_PORT_B_address, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_write_enable = GND;
R1_ram_block2a30_PORT_A_write_enable_reg = DFFE(R1_ram_block2a30_PORT_A_write_enable, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_write_enable = GND;
R1_ram_block2a30_PORT_B_write_enable_reg = DFFE(R1_ram_block2a30_PORT_B_write_enable, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_clock_0 = M1__clk0;
R1_ram_block2a30_clock_1 = GND;
R1_ram_block2a30_clock_enable_0 = S3_w_anode3199w[3];
R1_ram_block2a30_clock_enable_1 = GND;
R1_ram_block2a30_PORT_A_data_out = MEMORY(R1_ram_block2a30_PORT_A_data_in_reg, R1_ram_block2a30_PORT_B_data_in_reg, R1_ram_block2a30_PORT_A_address_reg, R1_ram_block2a30_PORT_B_address_reg, R1_ram_block2a30_PORT_A_write_enable_reg, R1_ram_block2a30_PORT_B_write_enable_reg, , , R1_ram_block2a30_clock_0, R1_ram_block2a30_clock_1, R1_ram_block2a30_clock_enable_0, R1_ram_block2a30_clock_enable_1, , );
R1_ram_block2a30_PORT_A_data_out_reg = DFFE(R1_ram_block2a30_PORT_A_data_out, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1M1542Q = R1_ram_block2a30_PORT_A_data_out_reg[1];

--R1M1543Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT2
R1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a30_PORT_A_data_in_reg = DFFE(R1_ram_block2a30_PORT_A_data_in, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_data_in = ~GND;
R1_ram_block2a30_PORT_B_data_in_reg = DFFE(R1_ram_block2a30_PORT_B_data_in, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a30_PORT_A_address_reg = DFFE(R1_ram_block2a30_PORT_A_address, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a30_PORT_B_address_reg = DFFE(R1_ram_block2a30_PORT_B_address, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_write_enable = GND;
R1_ram_block2a30_PORT_A_write_enable_reg = DFFE(R1_ram_block2a30_PORT_A_write_enable, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_write_enable = GND;
R1_ram_block2a30_PORT_B_write_enable_reg = DFFE(R1_ram_block2a30_PORT_B_write_enable, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_clock_0 = M1__clk0;
R1_ram_block2a30_clock_1 = GND;
R1_ram_block2a30_clock_enable_0 = S3_w_anode3199w[3];
R1_ram_block2a30_clock_enable_1 = GND;
R1_ram_block2a30_PORT_A_data_out = MEMORY(R1_ram_block2a30_PORT_A_data_in_reg, R1_ram_block2a30_PORT_B_data_in_reg, R1_ram_block2a30_PORT_A_address_reg, R1_ram_block2a30_PORT_B_address_reg, R1_ram_block2a30_PORT_A_write_enable_reg, R1_ram_block2a30_PORT_B_write_enable_reg, , , R1_ram_block2a30_clock_0, R1_ram_block2a30_clock_1, R1_ram_block2a30_clock_enable_0, R1_ram_block2a30_clock_enable_1, , );
R1_ram_block2a30_PORT_A_data_out_reg = DFFE(R1_ram_block2a30_PORT_A_data_out, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1M1543Q = R1_ram_block2a30_PORT_A_data_out_reg[2];

--R1M1544Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT3
R1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a30_PORT_A_data_in_reg = DFFE(R1_ram_block2a30_PORT_A_data_in, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_data_in = ~GND;
R1_ram_block2a30_PORT_B_data_in_reg = DFFE(R1_ram_block2a30_PORT_B_data_in, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a30_PORT_A_address_reg = DFFE(R1_ram_block2a30_PORT_A_address, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a30_PORT_B_address_reg = DFFE(R1_ram_block2a30_PORT_B_address, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_write_enable = GND;
R1_ram_block2a30_PORT_A_write_enable_reg = DFFE(R1_ram_block2a30_PORT_A_write_enable, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_write_enable = GND;
R1_ram_block2a30_PORT_B_write_enable_reg = DFFE(R1_ram_block2a30_PORT_B_write_enable, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_clock_0 = M1__clk0;
R1_ram_block2a30_clock_1 = GND;
R1_ram_block2a30_clock_enable_0 = S3_w_anode3199w[3];
R1_ram_block2a30_clock_enable_1 = GND;
R1_ram_block2a30_PORT_A_data_out = MEMORY(R1_ram_block2a30_PORT_A_data_in_reg, R1_ram_block2a30_PORT_B_data_in_reg, R1_ram_block2a30_PORT_A_address_reg, R1_ram_block2a30_PORT_B_address_reg, R1_ram_block2a30_PORT_A_write_enable_reg, R1_ram_block2a30_PORT_B_write_enable_reg, , , R1_ram_block2a30_clock_0, R1_ram_block2a30_clock_1, R1_ram_block2a30_clock_enable_0, R1_ram_block2a30_clock_enable_1, , );
R1_ram_block2a30_PORT_A_data_out_reg = DFFE(R1_ram_block2a30_PORT_A_data_out, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1M1544Q = R1_ram_block2a30_PORT_A_data_out_reg[3];

--R1M1545Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT4
R1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a30_PORT_A_data_in_reg = DFFE(R1_ram_block2a30_PORT_A_data_in, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_data_in = ~GND;
R1_ram_block2a30_PORT_B_data_in_reg = DFFE(R1_ram_block2a30_PORT_B_data_in, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a30_PORT_A_address_reg = DFFE(R1_ram_block2a30_PORT_A_address, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a30_PORT_B_address_reg = DFFE(R1_ram_block2a30_PORT_B_address, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_write_enable = GND;
R1_ram_block2a30_PORT_A_write_enable_reg = DFFE(R1_ram_block2a30_PORT_A_write_enable, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_write_enable = GND;
R1_ram_block2a30_PORT_B_write_enable_reg = DFFE(R1_ram_block2a30_PORT_B_write_enable, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_clock_0 = M1__clk0;
R1_ram_block2a30_clock_1 = GND;
R1_ram_block2a30_clock_enable_0 = S3_w_anode3199w[3];
R1_ram_block2a30_clock_enable_1 = GND;
R1_ram_block2a30_PORT_A_data_out = MEMORY(R1_ram_block2a30_PORT_A_data_in_reg, R1_ram_block2a30_PORT_B_data_in_reg, R1_ram_block2a30_PORT_A_address_reg, R1_ram_block2a30_PORT_B_address_reg, R1_ram_block2a30_PORT_A_write_enable_reg, R1_ram_block2a30_PORT_B_write_enable_reg, , , R1_ram_block2a30_clock_0, R1_ram_block2a30_clock_1, R1_ram_block2a30_clock_enable_0, R1_ram_block2a30_clock_enable_1, , );
R1_ram_block2a30_PORT_A_data_out_reg = DFFE(R1_ram_block2a30_PORT_A_data_out, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1M1545Q = R1_ram_block2a30_PORT_A_data_out_reg[4];

--R1M1546Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT5
R1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a30_PORT_A_data_in_reg = DFFE(R1_ram_block2a30_PORT_A_data_in, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_data_in = ~GND;
R1_ram_block2a30_PORT_B_data_in_reg = DFFE(R1_ram_block2a30_PORT_B_data_in, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a30_PORT_A_address_reg = DFFE(R1_ram_block2a30_PORT_A_address, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a30_PORT_B_address_reg = DFFE(R1_ram_block2a30_PORT_B_address, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_write_enable = GND;
R1_ram_block2a30_PORT_A_write_enable_reg = DFFE(R1_ram_block2a30_PORT_A_write_enable, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_write_enable = GND;
R1_ram_block2a30_PORT_B_write_enable_reg = DFFE(R1_ram_block2a30_PORT_B_write_enable, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_clock_0 = M1__clk0;
R1_ram_block2a30_clock_1 = GND;
R1_ram_block2a30_clock_enable_0 = S3_w_anode3199w[3];
R1_ram_block2a30_clock_enable_1 = GND;
R1_ram_block2a30_PORT_A_data_out = MEMORY(R1_ram_block2a30_PORT_A_data_in_reg, R1_ram_block2a30_PORT_B_data_in_reg, R1_ram_block2a30_PORT_A_address_reg, R1_ram_block2a30_PORT_B_address_reg, R1_ram_block2a30_PORT_A_write_enable_reg, R1_ram_block2a30_PORT_B_write_enable_reg, , , R1_ram_block2a30_clock_0, R1_ram_block2a30_clock_1, R1_ram_block2a30_clock_enable_0, R1_ram_block2a30_clock_enable_1, , );
R1_ram_block2a30_PORT_A_data_out_reg = DFFE(R1_ram_block2a30_PORT_A_data_out, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1M1546Q = R1_ram_block2a30_PORT_A_data_out_reg[5];

--R1M1547Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT6
R1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a30_PORT_A_data_in_reg = DFFE(R1_ram_block2a30_PORT_A_data_in, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_data_in = ~GND;
R1_ram_block2a30_PORT_B_data_in_reg = DFFE(R1_ram_block2a30_PORT_B_data_in, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a30_PORT_A_address_reg = DFFE(R1_ram_block2a30_PORT_A_address, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a30_PORT_B_address_reg = DFFE(R1_ram_block2a30_PORT_B_address, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_write_enable = GND;
R1_ram_block2a30_PORT_A_write_enable_reg = DFFE(R1_ram_block2a30_PORT_A_write_enable, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_write_enable = GND;
R1_ram_block2a30_PORT_B_write_enable_reg = DFFE(R1_ram_block2a30_PORT_B_write_enable, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_clock_0 = M1__clk0;
R1_ram_block2a30_clock_1 = GND;
R1_ram_block2a30_clock_enable_0 = S3_w_anode3199w[3];
R1_ram_block2a30_clock_enable_1 = GND;
R1_ram_block2a30_PORT_A_data_out = MEMORY(R1_ram_block2a30_PORT_A_data_in_reg, R1_ram_block2a30_PORT_B_data_in_reg, R1_ram_block2a30_PORT_A_address_reg, R1_ram_block2a30_PORT_B_address_reg, R1_ram_block2a30_PORT_A_write_enable_reg, R1_ram_block2a30_PORT_B_write_enable_reg, , , R1_ram_block2a30_clock_0, R1_ram_block2a30_clock_1, R1_ram_block2a30_clock_enable_0, R1_ram_block2a30_clock_enable_1, , );
R1_ram_block2a30_PORT_A_data_out_reg = DFFE(R1_ram_block2a30_PORT_A_data_out, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1M1547Q = R1_ram_block2a30_PORT_A_data_out_reg[6];

--R1M1548Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT7
R1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a30_PORT_A_data_in_reg = DFFE(R1_ram_block2a30_PORT_A_data_in, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_data_in = ~GND;
R1_ram_block2a30_PORT_B_data_in_reg = DFFE(R1_ram_block2a30_PORT_B_data_in, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a30_PORT_A_address_reg = DFFE(R1_ram_block2a30_PORT_A_address, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a30_PORT_B_address_reg = DFFE(R1_ram_block2a30_PORT_B_address, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_write_enable = GND;
R1_ram_block2a30_PORT_A_write_enable_reg = DFFE(R1_ram_block2a30_PORT_A_write_enable, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_write_enable = GND;
R1_ram_block2a30_PORT_B_write_enable_reg = DFFE(R1_ram_block2a30_PORT_B_write_enable, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_clock_0 = M1__clk0;
R1_ram_block2a30_clock_1 = GND;
R1_ram_block2a30_clock_enable_0 = S3_w_anode3199w[3];
R1_ram_block2a30_clock_enable_1 = GND;
R1_ram_block2a30_PORT_A_data_out = MEMORY(R1_ram_block2a30_PORT_A_data_in_reg, R1_ram_block2a30_PORT_B_data_in_reg, R1_ram_block2a30_PORT_A_address_reg, R1_ram_block2a30_PORT_B_address_reg, R1_ram_block2a30_PORT_A_write_enable_reg, R1_ram_block2a30_PORT_B_write_enable_reg, , , R1_ram_block2a30_clock_0, R1_ram_block2a30_clock_1, R1_ram_block2a30_clock_enable_0, R1_ram_block2a30_clock_enable_1, , );
R1_ram_block2a30_PORT_A_data_out_reg = DFFE(R1_ram_block2a30_PORT_A_data_out, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1M1548Q = R1_ram_block2a30_PORT_A_data_out_reg[7];


--R1_ram_block2a29 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a29_PORT_A_data_in_reg = DFFE(R1_ram_block2a29_PORT_A_data_in, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_data_in = ~GND;
R1_ram_block2a29_PORT_B_data_in_reg = DFFE(R1_ram_block2a29_PORT_B_data_in, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a29_PORT_A_address_reg = DFFE(R1_ram_block2a29_PORT_A_address, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a29_PORT_B_address_reg = DFFE(R1_ram_block2a29_PORT_B_address, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_write_enable = GND;
R1_ram_block2a29_PORT_A_write_enable_reg = DFFE(R1_ram_block2a29_PORT_A_write_enable, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_write_enable = GND;
R1_ram_block2a29_PORT_B_write_enable_reg = DFFE(R1_ram_block2a29_PORT_B_write_enable, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_clock_0 = M1__clk0;
R1_ram_block2a29_clock_1 = GND;
R1_ram_block2a29_clock_enable_0 = S3_w_anode3189w[3];
R1_ram_block2a29_clock_enable_1 = GND;
R1_ram_block2a29_PORT_A_data_out = MEMORY(R1_ram_block2a29_PORT_A_data_in_reg, R1_ram_block2a29_PORT_B_data_in_reg, R1_ram_block2a29_PORT_A_address_reg, R1_ram_block2a29_PORT_B_address_reg, R1_ram_block2a29_PORT_A_write_enable_reg, R1_ram_block2a29_PORT_B_write_enable_reg, , , R1_ram_block2a29_clock_0, R1_ram_block2a29_clock_1, R1_ram_block2a29_clock_enable_0, R1_ram_block2a29_clock_enable_1, , );
R1_ram_block2a29_PORT_A_data_out_reg = DFFE(R1_ram_block2a29_PORT_A_data_out, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29 = R1_ram_block2a29_PORT_A_data_out_reg[0];

--R1M1492Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT1
R1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a29_PORT_A_data_in_reg = DFFE(R1_ram_block2a29_PORT_A_data_in, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_data_in = ~GND;
R1_ram_block2a29_PORT_B_data_in_reg = DFFE(R1_ram_block2a29_PORT_B_data_in, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a29_PORT_A_address_reg = DFFE(R1_ram_block2a29_PORT_A_address, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a29_PORT_B_address_reg = DFFE(R1_ram_block2a29_PORT_B_address, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_write_enable = GND;
R1_ram_block2a29_PORT_A_write_enable_reg = DFFE(R1_ram_block2a29_PORT_A_write_enable, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_write_enable = GND;
R1_ram_block2a29_PORT_B_write_enable_reg = DFFE(R1_ram_block2a29_PORT_B_write_enable, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_clock_0 = M1__clk0;
R1_ram_block2a29_clock_1 = GND;
R1_ram_block2a29_clock_enable_0 = S3_w_anode3189w[3];
R1_ram_block2a29_clock_enable_1 = GND;
R1_ram_block2a29_PORT_A_data_out = MEMORY(R1_ram_block2a29_PORT_A_data_in_reg, R1_ram_block2a29_PORT_B_data_in_reg, R1_ram_block2a29_PORT_A_address_reg, R1_ram_block2a29_PORT_B_address_reg, R1_ram_block2a29_PORT_A_write_enable_reg, R1_ram_block2a29_PORT_B_write_enable_reg, , , R1_ram_block2a29_clock_0, R1_ram_block2a29_clock_1, R1_ram_block2a29_clock_enable_0, R1_ram_block2a29_clock_enable_1, , );
R1_ram_block2a29_PORT_A_data_out_reg = DFFE(R1_ram_block2a29_PORT_A_data_out, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1M1492Q = R1_ram_block2a29_PORT_A_data_out_reg[1];

--R1M1493Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT2
R1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a29_PORT_A_data_in_reg = DFFE(R1_ram_block2a29_PORT_A_data_in, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_data_in = ~GND;
R1_ram_block2a29_PORT_B_data_in_reg = DFFE(R1_ram_block2a29_PORT_B_data_in, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a29_PORT_A_address_reg = DFFE(R1_ram_block2a29_PORT_A_address, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a29_PORT_B_address_reg = DFFE(R1_ram_block2a29_PORT_B_address, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_write_enable = GND;
R1_ram_block2a29_PORT_A_write_enable_reg = DFFE(R1_ram_block2a29_PORT_A_write_enable, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_write_enable = GND;
R1_ram_block2a29_PORT_B_write_enable_reg = DFFE(R1_ram_block2a29_PORT_B_write_enable, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_clock_0 = M1__clk0;
R1_ram_block2a29_clock_1 = GND;
R1_ram_block2a29_clock_enable_0 = S3_w_anode3189w[3];
R1_ram_block2a29_clock_enable_1 = GND;
R1_ram_block2a29_PORT_A_data_out = MEMORY(R1_ram_block2a29_PORT_A_data_in_reg, R1_ram_block2a29_PORT_B_data_in_reg, R1_ram_block2a29_PORT_A_address_reg, R1_ram_block2a29_PORT_B_address_reg, R1_ram_block2a29_PORT_A_write_enable_reg, R1_ram_block2a29_PORT_B_write_enable_reg, , , R1_ram_block2a29_clock_0, R1_ram_block2a29_clock_1, R1_ram_block2a29_clock_enable_0, R1_ram_block2a29_clock_enable_1, , );
R1_ram_block2a29_PORT_A_data_out_reg = DFFE(R1_ram_block2a29_PORT_A_data_out, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1M1493Q = R1_ram_block2a29_PORT_A_data_out_reg[2];

--R1M1494Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT3
R1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a29_PORT_A_data_in_reg = DFFE(R1_ram_block2a29_PORT_A_data_in, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_data_in = ~GND;
R1_ram_block2a29_PORT_B_data_in_reg = DFFE(R1_ram_block2a29_PORT_B_data_in, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a29_PORT_A_address_reg = DFFE(R1_ram_block2a29_PORT_A_address, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a29_PORT_B_address_reg = DFFE(R1_ram_block2a29_PORT_B_address, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_write_enable = GND;
R1_ram_block2a29_PORT_A_write_enable_reg = DFFE(R1_ram_block2a29_PORT_A_write_enable, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_write_enable = GND;
R1_ram_block2a29_PORT_B_write_enable_reg = DFFE(R1_ram_block2a29_PORT_B_write_enable, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_clock_0 = M1__clk0;
R1_ram_block2a29_clock_1 = GND;
R1_ram_block2a29_clock_enable_0 = S3_w_anode3189w[3];
R1_ram_block2a29_clock_enable_1 = GND;
R1_ram_block2a29_PORT_A_data_out = MEMORY(R1_ram_block2a29_PORT_A_data_in_reg, R1_ram_block2a29_PORT_B_data_in_reg, R1_ram_block2a29_PORT_A_address_reg, R1_ram_block2a29_PORT_B_address_reg, R1_ram_block2a29_PORT_A_write_enable_reg, R1_ram_block2a29_PORT_B_write_enable_reg, , , R1_ram_block2a29_clock_0, R1_ram_block2a29_clock_1, R1_ram_block2a29_clock_enable_0, R1_ram_block2a29_clock_enable_1, , );
R1_ram_block2a29_PORT_A_data_out_reg = DFFE(R1_ram_block2a29_PORT_A_data_out, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1M1494Q = R1_ram_block2a29_PORT_A_data_out_reg[3];

--R1M1495Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT4
R1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a29_PORT_A_data_in_reg = DFFE(R1_ram_block2a29_PORT_A_data_in, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_data_in = ~GND;
R1_ram_block2a29_PORT_B_data_in_reg = DFFE(R1_ram_block2a29_PORT_B_data_in, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a29_PORT_A_address_reg = DFFE(R1_ram_block2a29_PORT_A_address, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a29_PORT_B_address_reg = DFFE(R1_ram_block2a29_PORT_B_address, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_write_enable = GND;
R1_ram_block2a29_PORT_A_write_enable_reg = DFFE(R1_ram_block2a29_PORT_A_write_enable, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_write_enable = GND;
R1_ram_block2a29_PORT_B_write_enable_reg = DFFE(R1_ram_block2a29_PORT_B_write_enable, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_clock_0 = M1__clk0;
R1_ram_block2a29_clock_1 = GND;
R1_ram_block2a29_clock_enable_0 = S3_w_anode3189w[3];
R1_ram_block2a29_clock_enable_1 = GND;
R1_ram_block2a29_PORT_A_data_out = MEMORY(R1_ram_block2a29_PORT_A_data_in_reg, R1_ram_block2a29_PORT_B_data_in_reg, R1_ram_block2a29_PORT_A_address_reg, R1_ram_block2a29_PORT_B_address_reg, R1_ram_block2a29_PORT_A_write_enable_reg, R1_ram_block2a29_PORT_B_write_enable_reg, , , R1_ram_block2a29_clock_0, R1_ram_block2a29_clock_1, R1_ram_block2a29_clock_enable_0, R1_ram_block2a29_clock_enable_1, , );
R1_ram_block2a29_PORT_A_data_out_reg = DFFE(R1_ram_block2a29_PORT_A_data_out, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1M1495Q = R1_ram_block2a29_PORT_A_data_out_reg[4];

--R1M1496Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT5
R1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a29_PORT_A_data_in_reg = DFFE(R1_ram_block2a29_PORT_A_data_in, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_data_in = ~GND;
R1_ram_block2a29_PORT_B_data_in_reg = DFFE(R1_ram_block2a29_PORT_B_data_in, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a29_PORT_A_address_reg = DFFE(R1_ram_block2a29_PORT_A_address, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a29_PORT_B_address_reg = DFFE(R1_ram_block2a29_PORT_B_address, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_write_enable = GND;
R1_ram_block2a29_PORT_A_write_enable_reg = DFFE(R1_ram_block2a29_PORT_A_write_enable, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_write_enable = GND;
R1_ram_block2a29_PORT_B_write_enable_reg = DFFE(R1_ram_block2a29_PORT_B_write_enable, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_clock_0 = M1__clk0;
R1_ram_block2a29_clock_1 = GND;
R1_ram_block2a29_clock_enable_0 = S3_w_anode3189w[3];
R1_ram_block2a29_clock_enable_1 = GND;
R1_ram_block2a29_PORT_A_data_out = MEMORY(R1_ram_block2a29_PORT_A_data_in_reg, R1_ram_block2a29_PORT_B_data_in_reg, R1_ram_block2a29_PORT_A_address_reg, R1_ram_block2a29_PORT_B_address_reg, R1_ram_block2a29_PORT_A_write_enable_reg, R1_ram_block2a29_PORT_B_write_enable_reg, , , R1_ram_block2a29_clock_0, R1_ram_block2a29_clock_1, R1_ram_block2a29_clock_enable_0, R1_ram_block2a29_clock_enable_1, , );
R1_ram_block2a29_PORT_A_data_out_reg = DFFE(R1_ram_block2a29_PORT_A_data_out, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1M1496Q = R1_ram_block2a29_PORT_A_data_out_reg[5];

--R1M1497Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT6
R1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a29_PORT_A_data_in_reg = DFFE(R1_ram_block2a29_PORT_A_data_in, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_data_in = ~GND;
R1_ram_block2a29_PORT_B_data_in_reg = DFFE(R1_ram_block2a29_PORT_B_data_in, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a29_PORT_A_address_reg = DFFE(R1_ram_block2a29_PORT_A_address, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a29_PORT_B_address_reg = DFFE(R1_ram_block2a29_PORT_B_address, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_write_enable = GND;
R1_ram_block2a29_PORT_A_write_enable_reg = DFFE(R1_ram_block2a29_PORT_A_write_enable, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_write_enable = GND;
R1_ram_block2a29_PORT_B_write_enable_reg = DFFE(R1_ram_block2a29_PORT_B_write_enable, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_clock_0 = M1__clk0;
R1_ram_block2a29_clock_1 = GND;
R1_ram_block2a29_clock_enable_0 = S3_w_anode3189w[3];
R1_ram_block2a29_clock_enable_1 = GND;
R1_ram_block2a29_PORT_A_data_out = MEMORY(R1_ram_block2a29_PORT_A_data_in_reg, R1_ram_block2a29_PORT_B_data_in_reg, R1_ram_block2a29_PORT_A_address_reg, R1_ram_block2a29_PORT_B_address_reg, R1_ram_block2a29_PORT_A_write_enable_reg, R1_ram_block2a29_PORT_B_write_enable_reg, , , R1_ram_block2a29_clock_0, R1_ram_block2a29_clock_1, R1_ram_block2a29_clock_enable_0, R1_ram_block2a29_clock_enable_1, , );
R1_ram_block2a29_PORT_A_data_out_reg = DFFE(R1_ram_block2a29_PORT_A_data_out, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1M1497Q = R1_ram_block2a29_PORT_A_data_out_reg[6];

--R1M1498Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT7
R1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a29_PORT_A_data_in_reg = DFFE(R1_ram_block2a29_PORT_A_data_in, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_data_in = ~GND;
R1_ram_block2a29_PORT_B_data_in_reg = DFFE(R1_ram_block2a29_PORT_B_data_in, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a29_PORT_A_address_reg = DFFE(R1_ram_block2a29_PORT_A_address, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a29_PORT_B_address_reg = DFFE(R1_ram_block2a29_PORT_B_address, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_write_enable = GND;
R1_ram_block2a29_PORT_A_write_enable_reg = DFFE(R1_ram_block2a29_PORT_A_write_enable, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_write_enable = GND;
R1_ram_block2a29_PORT_B_write_enable_reg = DFFE(R1_ram_block2a29_PORT_B_write_enable, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_clock_0 = M1__clk0;
R1_ram_block2a29_clock_1 = GND;
R1_ram_block2a29_clock_enable_0 = S3_w_anode3189w[3];
R1_ram_block2a29_clock_enable_1 = GND;
R1_ram_block2a29_PORT_A_data_out = MEMORY(R1_ram_block2a29_PORT_A_data_in_reg, R1_ram_block2a29_PORT_B_data_in_reg, R1_ram_block2a29_PORT_A_address_reg, R1_ram_block2a29_PORT_B_address_reg, R1_ram_block2a29_PORT_A_write_enable_reg, R1_ram_block2a29_PORT_B_write_enable_reg, , , R1_ram_block2a29_clock_0, R1_ram_block2a29_clock_1, R1_ram_block2a29_clock_enable_0, R1_ram_block2a29_clock_enable_1, , );
R1_ram_block2a29_PORT_A_data_out_reg = DFFE(R1_ram_block2a29_PORT_A_data_out, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1M1498Q = R1_ram_block2a29_PORT_A_data_out_reg[7];


--R1_ram_block2a28 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a28_PORT_A_data_in_reg = DFFE(R1_ram_block2a28_PORT_A_data_in, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_data_in = ~GND;
R1_ram_block2a28_PORT_B_data_in_reg = DFFE(R1_ram_block2a28_PORT_B_data_in, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a28_PORT_A_address_reg = DFFE(R1_ram_block2a28_PORT_A_address, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a28_PORT_B_address_reg = DFFE(R1_ram_block2a28_PORT_B_address, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_write_enable = GND;
R1_ram_block2a28_PORT_A_write_enable_reg = DFFE(R1_ram_block2a28_PORT_A_write_enable, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_write_enable = GND;
R1_ram_block2a28_PORT_B_write_enable_reg = DFFE(R1_ram_block2a28_PORT_B_write_enable, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_clock_0 = M1__clk0;
R1_ram_block2a28_clock_1 = GND;
R1_ram_block2a28_clock_enable_0 = S3_w_anode3179w[3];
R1_ram_block2a28_clock_enable_1 = GND;
R1_ram_block2a28_PORT_A_data_out = MEMORY(R1_ram_block2a28_PORT_A_data_in_reg, R1_ram_block2a28_PORT_B_data_in_reg, R1_ram_block2a28_PORT_A_address_reg, R1_ram_block2a28_PORT_B_address_reg, R1_ram_block2a28_PORT_A_write_enable_reg, R1_ram_block2a28_PORT_B_write_enable_reg, , , R1_ram_block2a28_clock_0, R1_ram_block2a28_clock_1, R1_ram_block2a28_clock_enable_0, R1_ram_block2a28_clock_enable_1, , );
R1_ram_block2a28_PORT_A_data_out_reg = DFFE(R1_ram_block2a28_PORT_A_data_out, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28 = R1_ram_block2a28_PORT_A_data_out_reg[0];

--R1M1442Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT1
R1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a28_PORT_A_data_in_reg = DFFE(R1_ram_block2a28_PORT_A_data_in, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_data_in = ~GND;
R1_ram_block2a28_PORT_B_data_in_reg = DFFE(R1_ram_block2a28_PORT_B_data_in, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a28_PORT_A_address_reg = DFFE(R1_ram_block2a28_PORT_A_address, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a28_PORT_B_address_reg = DFFE(R1_ram_block2a28_PORT_B_address, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_write_enable = GND;
R1_ram_block2a28_PORT_A_write_enable_reg = DFFE(R1_ram_block2a28_PORT_A_write_enable, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_write_enable = GND;
R1_ram_block2a28_PORT_B_write_enable_reg = DFFE(R1_ram_block2a28_PORT_B_write_enable, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_clock_0 = M1__clk0;
R1_ram_block2a28_clock_1 = GND;
R1_ram_block2a28_clock_enable_0 = S3_w_anode3179w[3];
R1_ram_block2a28_clock_enable_1 = GND;
R1_ram_block2a28_PORT_A_data_out = MEMORY(R1_ram_block2a28_PORT_A_data_in_reg, R1_ram_block2a28_PORT_B_data_in_reg, R1_ram_block2a28_PORT_A_address_reg, R1_ram_block2a28_PORT_B_address_reg, R1_ram_block2a28_PORT_A_write_enable_reg, R1_ram_block2a28_PORT_B_write_enable_reg, , , R1_ram_block2a28_clock_0, R1_ram_block2a28_clock_1, R1_ram_block2a28_clock_enable_0, R1_ram_block2a28_clock_enable_1, , );
R1_ram_block2a28_PORT_A_data_out_reg = DFFE(R1_ram_block2a28_PORT_A_data_out, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1M1442Q = R1_ram_block2a28_PORT_A_data_out_reg[1];

--R1M1443Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT2
R1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a28_PORT_A_data_in_reg = DFFE(R1_ram_block2a28_PORT_A_data_in, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_data_in = ~GND;
R1_ram_block2a28_PORT_B_data_in_reg = DFFE(R1_ram_block2a28_PORT_B_data_in, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a28_PORT_A_address_reg = DFFE(R1_ram_block2a28_PORT_A_address, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a28_PORT_B_address_reg = DFFE(R1_ram_block2a28_PORT_B_address, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_write_enable = GND;
R1_ram_block2a28_PORT_A_write_enable_reg = DFFE(R1_ram_block2a28_PORT_A_write_enable, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_write_enable = GND;
R1_ram_block2a28_PORT_B_write_enable_reg = DFFE(R1_ram_block2a28_PORT_B_write_enable, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_clock_0 = M1__clk0;
R1_ram_block2a28_clock_1 = GND;
R1_ram_block2a28_clock_enable_0 = S3_w_anode3179w[3];
R1_ram_block2a28_clock_enable_1 = GND;
R1_ram_block2a28_PORT_A_data_out = MEMORY(R1_ram_block2a28_PORT_A_data_in_reg, R1_ram_block2a28_PORT_B_data_in_reg, R1_ram_block2a28_PORT_A_address_reg, R1_ram_block2a28_PORT_B_address_reg, R1_ram_block2a28_PORT_A_write_enable_reg, R1_ram_block2a28_PORT_B_write_enable_reg, , , R1_ram_block2a28_clock_0, R1_ram_block2a28_clock_1, R1_ram_block2a28_clock_enable_0, R1_ram_block2a28_clock_enable_1, , );
R1_ram_block2a28_PORT_A_data_out_reg = DFFE(R1_ram_block2a28_PORT_A_data_out, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1M1443Q = R1_ram_block2a28_PORT_A_data_out_reg[2];

--R1M1444Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT3
R1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a28_PORT_A_data_in_reg = DFFE(R1_ram_block2a28_PORT_A_data_in, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_data_in = ~GND;
R1_ram_block2a28_PORT_B_data_in_reg = DFFE(R1_ram_block2a28_PORT_B_data_in, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a28_PORT_A_address_reg = DFFE(R1_ram_block2a28_PORT_A_address, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a28_PORT_B_address_reg = DFFE(R1_ram_block2a28_PORT_B_address, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_write_enable = GND;
R1_ram_block2a28_PORT_A_write_enable_reg = DFFE(R1_ram_block2a28_PORT_A_write_enable, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_write_enable = GND;
R1_ram_block2a28_PORT_B_write_enable_reg = DFFE(R1_ram_block2a28_PORT_B_write_enable, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_clock_0 = M1__clk0;
R1_ram_block2a28_clock_1 = GND;
R1_ram_block2a28_clock_enable_0 = S3_w_anode3179w[3];
R1_ram_block2a28_clock_enable_1 = GND;
R1_ram_block2a28_PORT_A_data_out = MEMORY(R1_ram_block2a28_PORT_A_data_in_reg, R1_ram_block2a28_PORT_B_data_in_reg, R1_ram_block2a28_PORT_A_address_reg, R1_ram_block2a28_PORT_B_address_reg, R1_ram_block2a28_PORT_A_write_enable_reg, R1_ram_block2a28_PORT_B_write_enable_reg, , , R1_ram_block2a28_clock_0, R1_ram_block2a28_clock_1, R1_ram_block2a28_clock_enable_0, R1_ram_block2a28_clock_enable_1, , );
R1_ram_block2a28_PORT_A_data_out_reg = DFFE(R1_ram_block2a28_PORT_A_data_out, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1M1444Q = R1_ram_block2a28_PORT_A_data_out_reg[3];

--R1M1445Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT4
R1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a28_PORT_A_data_in_reg = DFFE(R1_ram_block2a28_PORT_A_data_in, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_data_in = ~GND;
R1_ram_block2a28_PORT_B_data_in_reg = DFFE(R1_ram_block2a28_PORT_B_data_in, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a28_PORT_A_address_reg = DFFE(R1_ram_block2a28_PORT_A_address, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a28_PORT_B_address_reg = DFFE(R1_ram_block2a28_PORT_B_address, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_write_enable = GND;
R1_ram_block2a28_PORT_A_write_enable_reg = DFFE(R1_ram_block2a28_PORT_A_write_enable, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_write_enable = GND;
R1_ram_block2a28_PORT_B_write_enable_reg = DFFE(R1_ram_block2a28_PORT_B_write_enable, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_clock_0 = M1__clk0;
R1_ram_block2a28_clock_1 = GND;
R1_ram_block2a28_clock_enable_0 = S3_w_anode3179w[3];
R1_ram_block2a28_clock_enable_1 = GND;
R1_ram_block2a28_PORT_A_data_out = MEMORY(R1_ram_block2a28_PORT_A_data_in_reg, R1_ram_block2a28_PORT_B_data_in_reg, R1_ram_block2a28_PORT_A_address_reg, R1_ram_block2a28_PORT_B_address_reg, R1_ram_block2a28_PORT_A_write_enable_reg, R1_ram_block2a28_PORT_B_write_enable_reg, , , R1_ram_block2a28_clock_0, R1_ram_block2a28_clock_1, R1_ram_block2a28_clock_enable_0, R1_ram_block2a28_clock_enable_1, , );
R1_ram_block2a28_PORT_A_data_out_reg = DFFE(R1_ram_block2a28_PORT_A_data_out, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1M1445Q = R1_ram_block2a28_PORT_A_data_out_reg[4];

--R1M1446Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT5
R1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a28_PORT_A_data_in_reg = DFFE(R1_ram_block2a28_PORT_A_data_in, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_data_in = ~GND;
R1_ram_block2a28_PORT_B_data_in_reg = DFFE(R1_ram_block2a28_PORT_B_data_in, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a28_PORT_A_address_reg = DFFE(R1_ram_block2a28_PORT_A_address, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a28_PORT_B_address_reg = DFFE(R1_ram_block2a28_PORT_B_address, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_write_enable = GND;
R1_ram_block2a28_PORT_A_write_enable_reg = DFFE(R1_ram_block2a28_PORT_A_write_enable, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_write_enable = GND;
R1_ram_block2a28_PORT_B_write_enable_reg = DFFE(R1_ram_block2a28_PORT_B_write_enable, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_clock_0 = M1__clk0;
R1_ram_block2a28_clock_1 = GND;
R1_ram_block2a28_clock_enable_0 = S3_w_anode3179w[3];
R1_ram_block2a28_clock_enable_1 = GND;
R1_ram_block2a28_PORT_A_data_out = MEMORY(R1_ram_block2a28_PORT_A_data_in_reg, R1_ram_block2a28_PORT_B_data_in_reg, R1_ram_block2a28_PORT_A_address_reg, R1_ram_block2a28_PORT_B_address_reg, R1_ram_block2a28_PORT_A_write_enable_reg, R1_ram_block2a28_PORT_B_write_enable_reg, , , R1_ram_block2a28_clock_0, R1_ram_block2a28_clock_1, R1_ram_block2a28_clock_enable_0, R1_ram_block2a28_clock_enable_1, , );
R1_ram_block2a28_PORT_A_data_out_reg = DFFE(R1_ram_block2a28_PORT_A_data_out, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1M1446Q = R1_ram_block2a28_PORT_A_data_out_reg[5];

--R1M1447Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT6
R1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a28_PORT_A_data_in_reg = DFFE(R1_ram_block2a28_PORT_A_data_in, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_data_in = ~GND;
R1_ram_block2a28_PORT_B_data_in_reg = DFFE(R1_ram_block2a28_PORT_B_data_in, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a28_PORT_A_address_reg = DFFE(R1_ram_block2a28_PORT_A_address, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a28_PORT_B_address_reg = DFFE(R1_ram_block2a28_PORT_B_address, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_write_enable = GND;
R1_ram_block2a28_PORT_A_write_enable_reg = DFFE(R1_ram_block2a28_PORT_A_write_enable, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_write_enable = GND;
R1_ram_block2a28_PORT_B_write_enable_reg = DFFE(R1_ram_block2a28_PORT_B_write_enable, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_clock_0 = M1__clk0;
R1_ram_block2a28_clock_1 = GND;
R1_ram_block2a28_clock_enable_0 = S3_w_anode3179w[3];
R1_ram_block2a28_clock_enable_1 = GND;
R1_ram_block2a28_PORT_A_data_out = MEMORY(R1_ram_block2a28_PORT_A_data_in_reg, R1_ram_block2a28_PORT_B_data_in_reg, R1_ram_block2a28_PORT_A_address_reg, R1_ram_block2a28_PORT_B_address_reg, R1_ram_block2a28_PORT_A_write_enable_reg, R1_ram_block2a28_PORT_B_write_enable_reg, , , R1_ram_block2a28_clock_0, R1_ram_block2a28_clock_1, R1_ram_block2a28_clock_enable_0, R1_ram_block2a28_clock_enable_1, , );
R1_ram_block2a28_PORT_A_data_out_reg = DFFE(R1_ram_block2a28_PORT_A_data_out, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1M1447Q = R1_ram_block2a28_PORT_A_data_out_reg[6];

--R1M1448Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT7
R1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a28_PORT_A_data_in_reg = DFFE(R1_ram_block2a28_PORT_A_data_in, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_data_in = ~GND;
R1_ram_block2a28_PORT_B_data_in_reg = DFFE(R1_ram_block2a28_PORT_B_data_in, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a28_PORT_A_address_reg = DFFE(R1_ram_block2a28_PORT_A_address, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a28_PORT_B_address_reg = DFFE(R1_ram_block2a28_PORT_B_address, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_write_enable = GND;
R1_ram_block2a28_PORT_A_write_enable_reg = DFFE(R1_ram_block2a28_PORT_A_write_enable, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_write_enable = GND;
R1_ram_block2a28_PORT_B_write_enable_reg = DFFE(R1_ram_block2a28_PORT_B_write_enable, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_clock_0 = M1__clk0;
R1_ram_block2a28_clock_1 = GND;
R1_ram_block2a28_clock_enable_0 = S3_w_anode3179w[3];
R1_ram_block2a28_clock_enable_1 = GND;
R1_ram_block2a28_PORT_A_data_out = MEMORY(R1_ram_block2a28_PORT_A_data_in_reg, R1_ram_block2a28_PORT_B_data_in_reg, R1_ram_block2a28_PORT_A_address_reg, R1_ram_block2a28_PORT_B_address_reg, R1_ram_block2a28_PORT_A_write_enable_reg, R1_ram_block2a28_PORT_B_write_enable_reg, , , R1_ram_block2a28_clock_0, R1_ram_block2a28_clock_1, R1_ram_block2a28_clock_enable_0, R1_ram_block2a28_clock_enable_1, , );
R1_ram_block2a28_PORT_A_data_out_reg = DFFE(R1_ram_block2a28_PORT_A_data_out, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1M1448Q = R1_ram_block2a28_PORT_A_data_out_reg[7];


--T1L222 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6493w~49
T1L222 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1496Q # !R1_address_reg_a[6] & (R1M1446Q));


--R1_ram_block2a31 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a31_PORT_A_data_in_reg = DFFE(R1_ram_block2a31_PORT_A_data_in, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_data_in = ~GND;
R1_ram_block2a31_PORT_B_data_in_reg = DFFE(R1_ram_block2a31_PORT_B_data_in, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a31_PORT_A_address_reg = DFFE(R1_ram_block2a31_PORT_A_address, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a31_PORT_B_address_reg = DFFE(R1_ram_block2a31_PORT_B_address, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_write_enable = GND;
R1_ram_block2a31_PORT_A_write_enable_reg = DFFE(R1_ram_block2a31_PORT_A_write_enable, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_write_enable = GND;
R1_ram_block2a31_PORT_B_write_enable_reg = DFFE(R1_ram_block2a31_PORT_B_write_enable, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_clock_0 = M1__clk0;
R1_ram_block2a31_clock_1 = GND;
R1_ram_block2a31_clock_enable_0 = S3_w_anode3209w[3];
R1_ram_block2a31_clock_enable_1 = GND;
R1_ram_block2a31_PORT_A_data_out = MEMORY(R1_ram_block2a31_PORT_A_data_in_reg, R1_ram_block2a31_PORT_B_data_in_reg, R1_ram_block2a31_PORT_A_address_reg, R1_ram_block2a31_PORT_B_address_reg, R1_ram_block2a31_PORT_A_write_enable_reg, R1_ram_block2a31_PORT_B_write_enable_reg, , , R1_ram_block2a31_clock_0, R1_ram_block2a31_clock_1, R1_ram_block2a31_clock_enable_0, R1_ram_block2a31_clock_enable_1, , );
R1_ram_block2a31_PORT_A_data_out_reg = DFFE(R1_ram_block2a31_PORT_A_data_out, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31 = R1_ram_block2a31_PORT_A_data_out_reg[0];

--R1M1592Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT1
R1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a31_PORT_A_data_in_reg = DFFE(R1_ram_block2a31_PORT_A_data_in, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_data_in = ~GND;
R1_ram_block2a31_PORT_B_data_in_reg = DFFE(R1_ram_block2a31_PORT_B_data_in, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a31_PORT_A_address_reg = DFFE(R1_ram_block2a31_PORT_A_address, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a31_PORT_B_address_reg = DFFE(R1_ram_block2a31_PORT_B_address, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_write_enable = GND;
R1_ram_block2a31_PORT_A_write_enable_reg = DFFE(R1_ram_block2a31_PORT_A_write_enable, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_write_enable = GND;
R1_ram_block2a31_PORT_B_write_enable_reg = DFFE(R1_ram_block2a31_PORT_B_write_enable, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_clock_0 = M1__clk0;
R1_ram_block2a31_clock_1 = GND;
R1_ram_block2a31_clock_enable_0 = S3_w_anode3209w[3];
R1_ram_block2a31_clock_enable_1 = GND;
R1_ram_block2a31_PORT_A_data_out = MEMORY(R1_ram_block2a31_PORT_A_data_in_reg, R1_ram_block2a31_PORT_B_data_in_reg, R1_ram_block2a31_PORT_A_address_reg, R1_ram_block2a31_PORT_B_address_reg, R1_ram_block2a31_PORT_A_write_enable_reg, R1_ram_block2a31_PORT_B_write_enable_reg, , , R1_ram_block2a31_clock_0, R1_ram_block2a31_clock_1, R1_ram_block2a31_clock_enable_0, R1_ram_block2a31_clock_enable_1, , );
R1_ram_block2a31_PORT_A_data_out_reg = DFFE(R1_ram_block2a31_PORT_A_data_out, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1M1592Q = R1_ram_block2a31_PORT_A_data_out_reg[1];

--R1M1593Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT2
R1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a31_PORT_A_data_in_reg = DFFE(R1_ram_block2a31_PORT_A_data_in, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_data_in = ~GND;
R1_ram_block2a31_PORT_B_data_in_reg = DFFE(R1_ram_block2a31_PORT_B_data_in, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a31_PORT_A_address_reg = DFFE(R1_ram_block2a31_PORT_A_address, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a31_PORT_B_address_reg = DFFE(R1_ram_block2a31_PORT_B_address, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_write_enable = GND;
R1_ram_block2a31_PORT_A_write_enable_reg = DFFE(R1_ram_block2a31_PORT_A_write_enable, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_write_enable = GND;
R1_ram_block2a31_PORT_B_write_enable_reg = DFFE(R1_ram_block2a31_PORT_B_write_enable, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_clock_0 = M1__clk0;
R1_ram_block2a31_clock_1 = GND;
R1_ram_block2a31_clock_enable_0 = S3_w_anode3209w[3];
R1_ram_block2a31_clock_enable_1 = GND;
R1_ram_block2a31_PORT_A_data_out = MEMORY(R1_ram_block2a31_PORT_A_data_in_reg, R1_ram_block2a31_PORT_B_data_in_reg, R1_ram_block2a31_PORT_A_address_reg, R1_ram_block2a31_PORT_B_address_reg, R1_ram_block2a31_PORT_A_write_enable_reg, R1_ram_block2a31_PORT_B_write_enable_reg, , , R1_ram_block2a31_clock_0, R1_ram_block2a31_clock_1, R1_ram_block2a31_clock_enable_0, R1_ram_block2a31_clock_enable_1, , );
R1_ram_block2a31_PORT_A_data_out_reg = DFFE(R1_ram_block2a31_PORT_A_data_out, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1M1593Q = R1_ram_block2a31_PORT_A_data_out_reg[2];

--R1M1594Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT3
R1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a31_PORT_A_data_in_reg = DFFE(R1_ram_block2a31_PORT_A_data_in, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_data_in = ~GND;
R1_ram_block2a31_PORT_B_data_in_reg = DFFE(R1_ram_block2a31_PORT_B_data_in, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a31_PORT_A_address_reg = DFFE(R1_ram_block2a31_PORT_A_address, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a31_PORT_B_address_reg = DFFE(R1_ram_block2a31_PORT_B_address, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_write_enable = GND;
R1_ram_block2a31_PORT_A_write_enable_reg = DFFE(R1_ram_block2a31_PORT_A_write_enable, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_write_enable = GND;
R1_ram_block2a31_PORT_B_write_enable_reg = DFFE(R1_ram_block2a31_PORT_B_write_enable, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_clock_0 = M1__clk0;
R1_ram_block2a31_clock_1 = GND;
R1_ram_block2a31_clock_enable_0 = S3_w_anode3209w[3];
R1_ram_block2a31_clock_enable_1 = GND;
R1_ram_block2a31_PORT_A_data_out = MEMORY(R1_ram_block2a31_PORT_A_data_in_reg, R1_ram_block2a31_PORT_B_data_in_reg, R1_ram_block2a31_PORT_A_address_reg, R1_ram_block2a31_PORT_B_address_reg, R1_ram_block2a31_PORT_A_write_enable_reg, R1_ram_block2a31_PORT_B_write_enable_reg, , , R1_ram_block2a31_clock_0, R1_ram_block2a31_clock_1, R1_ram_block2a31_clock_enable_0, R1_ram_block2a31_clock_enable_1, , );
R1_ram_block2a31_PORT_A_data_out_reg = DFFE(R1_ram_block2a31_PORT_A_data_out, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1M1594Q = R1_ram_block2a31_PORT_A_data_out_reg[3];

--R1M1595Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT4
R1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a31_PORT_A_data_in_reg = DFFE(R1_ram_block2a31_PORT_A_data_in, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_data_in = ~GND;
R1_ram_block2a31_PORT_B_data_in_reg = DFFE(R1_ram_block2a31_PORT_B_data_in, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a31_PORT_A_address_reg = DFFE(R1_ram_block2a31_PORT_A_address, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a31_PORT_B_address_reg = DFFE(R1_ram_block2a31_PORT_B_address, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_write_enable = GND;
R1_ram_block2a31_PORT_A_write_enable_reg = DFFE(R1_ram_block2a31_PORT_A_write_enable, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_write_enable = GND;
R1_ram_block2a31_PORT_B_write_enable_reg = DFFE(R1_ram_block2a31_PORT_B_write_enable, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_clock_0 = M1__clk0;
R1_ram_block2a31_clock_1 = GND;
R1_ram_block2a31_clock_enable_0 = S3_w_anode3209w[3];
R1_ram_block2a31_clock_enable_1 = GND;
R1_ram_block2a31_PORT_A_data_out = MEMORY(R1_ram_block2a31_PORT_A_data_in_reg, R1_ram_block2a31_PORT_B_data_in_reg, R1_ram_block2a31_PORT_A_address_reg, R1_ram_block2a31_PORT_B_address_reg, R1_ram_block2a31_PORT_A_write_enable_reg, R1_ram_block2a31_PORT_B_write_enable_reg, , , R1_ram_block2a31_clock_0, R1_ram_block2a31_clock_1, R1_ram_block2a31_clock_enable_0, R1_ram_block2a31_clock_enable_1, , );
R1_ram_block2a31_PORT_A_data_out_reg = DFFE(R1_ram_block2a31_PORT_A_data_out, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1M1595Q = R1_ram_block2a31_PORT_A_data_out_reg[4];

--R1M1596Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT5
R1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a31_PORT_A_data_in_reg = DFFE(R1_ram_block2a31_PORT_A_data_in, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_data_in = ~GND;
R1_ram_block2a31_PORT_B_data_in_reg = DFFE(R1_ram_block2a31_PORT_B_data_in, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a31_PORT_A_address_reg = DFFE(R1_ram_block2a31_PORT_A_address, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a31_PORT_B_address_reg = DFFE(R1_ram_block2a31_PORT_B_address, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_write_enable = GND;
R1_ram_block2a31_PORT_A_write_enable_reg = DFFE(R1_ram_block2a31_PORT_A_write_enable, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_write_enable = GND;
R1_ram_block2a31_PORT_B_write_enable_reg = DFFE(R1_ram_block2a31_PORT_B_write_enable, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_clock_0 = M1__clk0;
R1_ram_block2a31_clock_1 = GND;
R1_ram_block2a31_clock_enable_0 = S3_w_anode3209w[3];
R1_ram_block2a31_clock_enable_1 = GND;
R1_ram_block2a31_PORT_A_data_out = MEMORY(R1_ram_block2a31_PORT_A_data_in_reg, R1_ram_block2a31_PORT_B_data_in_reg, R1_ram_block2a31_PORT_A_address_reg, R1_ram_block2a31_PORT_B_address_reg, R1_ram_block2a31_PORT_A_write_enable_reg, R1_ram_block2a31_PORT_B_write_enable_reg, , , R1_ram_block2a31_clock_0, R1_ram_block2a31_clock_1, R1_ram_block2a31_clock_enable_0, R1_ram_block2a31_clock_enable_1, , );
R1_ram_block2a31_PORT_A_data_out_reg = DFFE(R1_ram_block2a31_PORT_A_data_out, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1M1596Q = R1_ram_block2a31_PORT_A_data_out_reg[5];

--R1M1597Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT6
R1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a31_PORT_A_data_in_reg = DFFE(R1_ram_block2a31_PORT_A_data_in, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_data_in = ~GND;
R1_ram_block2a31_PORT_B_data_in_reg = DFFE(R1_ram_block2a31_PORT_B_data_in, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a31_PORT_A_address_reg = DFFE(R1_ram_block2a31_PORT_A_address, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a31_PORT_B_address_reg = DFFE(R1_ram_block2a31_PORT_B_address, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_write_enable = GND;
R1_ram_block2a31_PORT_A_write_enable_reg = DFFE(R1_ram_block2a31_PORT_A_write_enable, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_write_enable = GND;
R1_ram_block2a31_PORT_B_write_enable_reg = DFFE(R1_ram_block2a31_PORT_B_write_enable, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_clock_0 = M1__clk0;
R1_ram_block2a31_clock_1 = GND;
R1_ram_block2a31_clock_enable_0 = S3_w_anode3209w[3];
R1_ram_block2a31_clock_enable_1 = GND;
R1_ram_block2a31_PORT_A_data_out = MEMORY(R1_ram_block2a31_PORT_A_data_in_reg, R1_ram_block2a31_PORT_B_data_in_reg, R1_ram_block2a31_PORT_A_address_reg, R1_ram_block2a31_PORT_B_address_reg, R1_ram_block2a31_PORT_A_write_enable_reg, R1_ram_block2a31_PORT_B_write_enable_reg, , , R1_ram_block2a31_clock_0, R1_ram_block2a31_clock_1, R1_ram_block2a31_clock_enable_0, R1_ram_block2a31_clock_enable_1, , );
R1_ram_block2a31_PORT_A_data_out_reg = DFFE(R1_ram_block2a31_PORT_A_data_out, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1M1597Q = R1_ram_block2a31_PORT_A_data_out_reg[6];

--R1M1598Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT7
R1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a31_PORT_A_data_in_reg = DFFE(R1_ram_block2a31_PORT_A_data_in, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_data_in = ~GND;
R1_ram_block2a31_PORT_B_data_in_reg = DFFE(R1_ram_block2a31_PORT_B_data_in, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a31_PORT_A_address_reg = DFFE(R1_ram_block2a31_PORT_A_address, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a31_PORT_B_address_reg = DFFE(R1_ram_block2a31_PORT_B_address, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_write_enable = GND;
R1_ram_block2a31_PORT_A_write_enable_reg = DFFE(R1_ram_block2a31_PORT_A_write_enable, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_write_enable = GND;
R1_ram_block2a31_PORT_B_write_enable_reg = DFFE(R1_ram_block2a31_PORT_B_write_enable, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_clock_0 = M1__clk0;
R1_ram_block2a31_clock_1 = GND;
R1_ram_block2a31_clock_enable_0 = S3_w_anode3209w[3];
R1_ram_block2a31_clock_enable_1 = GND;
R1_ram_block2a31_PORT_A_data_out = MEMORY(R1_ram_block2a31_PORT_A_data_in_reg, R1_ram_block2a31_PORT_B_data_in_reg, R1_ram_block2a31_PORT_A_address_reg, R1_ram_block2a31_PORT_B_address_reg, R1_ram_block2a31_PORT_A_write_enable_reg, R1_ram_block2a31_PORT_B_write_enable_reg, , , R1_ram_block2a31_clock_0, R1_ram_block2a31_clock_1, R1_ram_block2a31_clock_enable_0, R1_ram_block2a31_clock_enable_1, , );
R1_ram_block2a31_PORT_A_data_out_reg = DFFE(R1_ram_block2a31_PORT_A_data_out, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1M1598Q = R1_ram_block2a31_PORT_A_data_out_reg[7];


--T1L223 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6493w~50
T1L223 = R1_address_reg_a[7] & (T1L222 & (R1M1596Q) # !T1L222 & R1M1546Q) # !R1_address_reg_a[7] & (T1L222);


--R1_ram_block2a21 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a21_PORT_A_data_in_reg = DFFE(R1_ram_block2a21_PORT_A_data_in, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_data_in = ~GND;
R1_ram_block2a21_PORT_B_data_in_reg = DFFE(R1_ram_block2a21_PORT_B_data_in, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a21_PORT_A_address_reg = DFFE(R1_ram_block2a21_PORT_A_address, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a21_PORT_B_address_reg = DFFE(R1_ram_block2a21_PORT_B_address, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_write_enable = GND;
R1_ram_block2a21_PORT_A_write_enable_reg = DFFE(R1_ram_block2a21_PORT_A_write_enable, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_write_enable = GND;
R1_ram_block2a21_PORT_B_write_enable_reg = DFFE(R1_ram_block2a21_PORT_B_write_enable, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_clock_0 = M1__clk0;
R1_ram_block2a21_clock_1 = GND;
R1_ram_block2a21_clock_enable_0 = S3_w_anode3096w[3];
R1_ram_block2a21_clock_enable_1 = GND;
R1_ram_block2a21_PORT_A_data_out = MEMORY(R1_ram_block2a21_PORT_A_data_in_reg, R1_ram_block2a21_PORT_B_data_in_reg, R1_ram_block2a21_PORT_A_address_reg, R1_ram_block2a21_PORT_B_address_reg, R1_ram_block2a21_PORT_A_write_enable_reg, R1_ram_block2a21_PORT_B_write_enable_reg, , , R1_ram_block2a21_clock_0, R1_ram_block2a21_clock_1, R1_ram_block2a21_clock_enable_0, R1_ram_block2a21_clock_enable_1, , );
R1_ram_block2a21_PORT_A_data_out_reg = DFFE(R1_ram_block2a21_PORT_A_data_out, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21 = R1_ram_block2a21_PORT_A_data_out_reg[0];

--R1M1092Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT1
R1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a21_PORT_A_data_in_reg = DFFE(R1_ram_block2a21_PORT_A_data_in, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_data_in = ~GND;
R1_ram_block2a21_PORT_B_data_in_reg = DFFE(R1_ram_block2a21_PORT_B_data_in, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a21_PORT_A_address_reg = DFFE(R1_ram_block2a21_PORT_A_address, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a21_PORT_B_address_reg = DFFE(R1_ram_block2a21_PORT_B_address, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_write_enable = GND;
R1_ram_block2a21_PORT_A_write_enable_reg = DFFE(R1_ram_block2a21_PORT_A_write_enable, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_write_enable = GND;
R1_ram_block2a21_PORT_B_write_enable_reg = DFFE(R1_ram_block2a21_PORT_B_write_enable, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_clock_0 = M1__clk0;
R1_ram_block2a21_clock_1 = GND;
R1_ram_block2a21_clock_enable_0 = S3_w_anode3096w[3];
R1_ram_block2a21_clock_enable_1 = GND;
R1_ram_block2a21_PORT_A_data_out = MEMORY(R1_ram_block2a21_PORT_A_data_in_reg, R1_ram_block2a21_PORT_B_data_in_reg, R1_ram_block2a21_PORT_A_address_reg, R1_ram_block2a21_PORT_B_address_reg, R1_ram_block2a21_PORT_A_write_enable_reg, R1_ram_block2a21_PORT_B_write_enable_reg, , , R1_ram_block2a21_clock_0, R1_ram_block2a21_clock_1, R1_ram_block2a21_clock_enable_0, R1_ram_block2a21_clock_enable_1, , );
R1_ram_block2a21_PORT_A_data_out_reg = DFFE(R1_ram_block2a21_PORT_A_data_out, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1M1092Q = R1_ram_block2a21_PORT_A_data_out_reg[1];

--R1M1093Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT2
R1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a21_PORT_A_data_in_reg = DFFE(R1_ram_block2a21_PORT_A_data_in, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_data_in = ~GND;
R1_ram_block2a21_PORT_B_data_in_reg = DFFE(R1_ram_block2a21_PORT_B_data_in, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a21_PORT_A_address_reg = DFFE(R1_ram_block2a21_PORT_A_address, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a21_PORT_B_address_reg = DFFE(R1_ram_block2a21_PORT_B_address, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_write_enable = GND;
R1_ram_block2a21_PORT_A_write_enable_reg = DFFE(R1_ram_block2a21_PORT_A_write_enable, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_write_enable = GND;
R1_ram_block2a21_PORT_B_write_enable_reg = DFFE(R1_ram_block2a21_PORT_B_write_enable, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_clock_0 = M1__clk0;
R1_ram_block2a21_clock_1 = GND;
R1_ram_block2a21_clock_enable_0 = S3_w_anode3096w[3];
R1_ram_block2a21_clock_enable_1 = GND;
R1_ram_block2a21_PORT_A_data_out = MEMORY(R1_ram_block2a21_PORT_A_data_in_reg, R1_ram_block2a21_PORT_B_data_in_reg, R1_ram_block2a21_PORT_A_address_reg, R1_ram_block2a21_PORT_B_address_reg, R1_ram_block2a21_PORT_A_write_enable_reg, R1_ram_block2a21_PORT_B_write_enable_reg, , , R1_ram_block2a21_clock_0, R1_ram_block2a21_clock_1, R1_ram_block2a21_clock_enable_0, R1_ram_block2a21_clock_enable_1, , );
R1_ram_block2a21_PORT_A_data_out_reg = DFFE(R1_ram_block2a21_PORT_A_data_out, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1M1093Q = R1_ram_block2a21_PORT_A_data_out_reg[2];

--R1M1094Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT3
R1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a21_PORT_A_data_in_reg = DFFE(R1_ram_block2a21_PORT_A_data_in, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_data_in = ~GND;
R1_ram_block2a21_PORT_B_data_in_reg = DFFE(R1_ram_block2a21_PORT_B_data_in, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a21_PORT_A_address_reg = DFFE(R1_ram_block2a21_PORT_A_address, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a21_PORT_B_address_reg = DFFE(R1_ram_block2a21_PORT_B_address, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_write_enable = GND;
R1_ram_block2a21_PORT_A_write_enable_reg = DFFE(R1_ram_block2a21_PORT_A_write_enable, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_write_enable = GND;
R1_ram_block2a21_PORT_B_write_enable_reg = DFFE(R1_ram_block2a21_PORT_B_write_enable, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_clock_0 = M1__clk0;
R1_ram_block2a21_clock_1 = GND;
R1_ram_block2a21_clock_enable_0 = S3_w_anode3096w[3];
R1_ram_block2a21_clock_enable_1 = GND;
R1_ram_block2a21_PORT_A_data_out = MEMORY(R1_ram_block2a21_PORT_A_data_in_reg, R1_ram_block2a21_PORT_B_data_in_reg, R1_ram_block2a21_PORT_A_address_reg, R1_ram_block2a21_PORT_B_address_reg, R1_ram_block2a21_PORT_A_write_enable_reg, R1_ram_block2a21_PORT_B_write_enable_reg, , , R1_ram_block2a21_clock_0, R1_ram_block2a21_clock_1, R1_ram_block2a21_clock_enable_0, R1_ram_block2a21_clock_enable_1, , );
R1_ram_block2a21_PORT_A_data_out_reg = DFFE(R1_ram_block2a21_PORT_A_data_out, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1M1094Q = R1_ram_block2a21_PORT_A_data_out_reg[3];

--R1M1095Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT4
R1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a21_PORT_A_data_in_reg = DFFE(R1_ram_block2a21_PORT_A_data_in, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_data_in = ~GND;
R1_ram_block2a21_PORT_B_data_in_reg = DFFE(R1_ram_block2a21_PORT_B_data_in, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a21_PORT_A_address_reg = DFFE(R1_ram_block2a21_PORT_A_address, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a21_PORT_B_address_reg = DFFE(R1_ram_block2a21_PORT_B_address, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_write_enable = GND;
R1_ram_block2a21_PORT_A_write_enable_reg = DFFE(R1_ram_block2a21_PORT_A_write_enable, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_write_enable = GND;
R1_ram_block2a21_PORT_B_write_enable_reg = DFFE(R1_ram_block2a21_PORT_B_write_enable, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_clock_0 = M1__clk0;
R1_ram_block2a21_clock_1 = GND;
R1_ram_block2a21_clock_enable_0 = S3_w_anode3096w[3];
R1_ram_block2a21_clock_enable_1 = GND;
R1_ram_block2a21_PORT_A_data_out = MEMORY(R1_ram_block2a21_PORT_A_data_in_reg, R1_ram_block2a21_PORT_B_data_in_reg, R1_ram_block2a21_PORT_A_address_reg, R1_ram_block2a21_PORT_B_address_reg, R1_ram_block2a21_PORT_A_write_enable_reg, R1_ram_block2a21_PORT_B_write_enable_reg, , , R1_ram_block2a21_clock_0, R1_ram_block2a21_clock_1, R1_ram_block2a21_clock_enable_0, R1_ram_block2a21_clock_enable_1, , );
R1_ram_block2a21_PORT_A_data_out_reg = DFFE(R1_ram_block2a21_PORT_A_data_out, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1M1095Q = R1_ram_block2a21_PORT_A_data_out_reg[4];

--R1M1096Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT5
R1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a21_PORT_A_data_in_reg = DFFE(R1_ram_block2a21_PORT_A_data_in, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_data_in = ~GND;
R1_ram_block2a21_PORT_B_data_in_reg = DFFE(R1_ram_block2a21_PORT_B_data_in, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a21_PORT_A_address_reg = DFFE(R1_ram_block2a21_PORT_A_address, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a21_PORT_B_address_reg = DFFE(R1_ram_block2a21_PORT_B_address, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_write_enable = GND;
R1_ram_block2a21_PORT_A_write_enable_reg = DFFE(R1_ram_block2a21_PORT_A_write_enable, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_write_enable = GND;
R1_ram_block2a21_PORT_B_write_enable_reg = DFFE(R1_ram_block2a21_PORT_B_write_enable, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_clock_0 = M1__clk0;
R1_ram_block2a21_clock_1 = GND;
R1_ram_block2a21_clock_enable_0 = S3_w_anode3096w[3];
R1_ram_block2a21_clock_enable_1 = GND;
R1_ram_block2a21_PORT_A_data_out = MEMORY(R1_ram_block2a21_PORT_A_data_in_reg, R1_ram_block2a21_PORT_B_data_in_reg, R1_ram_block2a21_PORT_A_address_reg, R1_ram_block2a21_PORT_B_address_reg, R1_ram_block2a21_PORT_A_write_enable_reg, R1_ram_block2a21_PORT_B_write_enable_reg, , , R1_ram_block2a21_clock_0, R1_ram_block2a21_clock_1, R1_ram_block2a21_clock_enable_0, R1_ram_block2a21_clock_enable_1, , );
R1_ram_block2a21_PORT_A_data_out_reg = DFFE(R1_ram_block2a21_PORT_A_data_out, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1M1096Q = R1_ram_block2a21_PORT_A_data_out_reg[5];

--R1M1097Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT6
R1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a21_PORT_A_data_in_reg = DFFE(R1_ram_block2a21_PORT_A_data_in, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_data_in = ~GND;
R1_ram_block2a21_PORT_B_data_in_reg = DFFE(R1_ram_block2a21_PORT_B_data_in, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a21_PORT_A_address_reg = DFFE(R1_ram_block2a21_PORT_A_address, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a21_PORT_B_address_reg = DFFE(R1_ram_block2a21_PORT_B_address, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_write_enable = GND;
R1_ram_block2a21_PORT_A_write_enable_reg = DFFE(R1_ram_block2a21_PORT_A_write_enable, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_write_enable = GND;
R1_ram_block2a21_PORT_B_write_enable_reg = DFFE(R1_ram_block2a21_PORT_B_write_enable, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_clock_0 = M1__clk0;
R1_ram_block2a21_clock_1 = GND;
R1_ram_block2a21_clock_enable_0 = S3_w_anode3096w[3];
R1_ram_block2a21_clock_enable_1 = GND;
R1_ram_block2a21_PORT_A_data_out = MEMORY(R1_ram_block2a21_PORT_A_data_in_reg, R1_ram_block2a21_PORT_B_data_in_reg, R1_ram_block2a21_PORT_A_address_reg, R1_ram_block2a21_PORT_B_address_reg, R1_ram_block2a21_PORT_A_write_enable_reg, R1_ram_block2a21_PORT_B_write_enable_reg, , , R1_ram_block2a21_clock_0, R1_ram_block2a21_clock_1, R1_ram_block2a21_clock_enable_0, R1_ram_block2a21_clock_enable_1, , );
R1_ram_block2a21_PORT_A_data_out_reg = DFFE(R1_ram_block2a21_PORT_A_data_out, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1M1097Q = R1_ram_block2a21_PORT_A_data_out_reg[6];

--R1M1098Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT7
R1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a21_PORT_A_data_in_reg = DFFE(R1_ram_block2a21_PORT_A_data_in, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_data_in = ~GND;
R1_ram_block2a21_PORT_B_data_in_reg = DFFE(R1_ram_block2a21_PORT_B_data_in, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a21_PORT_A_address_reg = DFFE(R1_ram_block2a21_PORT_A_address, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a21_PORT_B_address_reg = DFFE(R1_ram_block2a21_PORT_B_address, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_write_enable = GND;
R1_ram_block2a21_PORT_A_write_enable_reg = DFFE(R1_ram_block2a21_PORT_A_write_enable, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_write_enable = GND;
R1_ram_block2a21_PORT_B_write_enable_reg = DFFE(R1_ram_block2a21_PORT_B_write_enable, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_clock_0 = M1__clk0;
R1_ram_block2a21_clock_1 = GND;
R1_ram_block2a21_clock_enable_0 = S3_w_anode3096w[3];
R1_ram_block2a21_clock_enable_1 = GND;
R1_ram_block2a21_PORT_A_data_out = MEMORY(R1_ram_block2a21_PORT_A_data_in_reg, R1_ram_block2a21_PORT_B_data_in_reg, R1_ram_block2a21_PORT_A_address_reg, R1_ram_block2a21_PORT_B_address_reg, R1_ram_block2a21_PORT_A_write_enable_reg, R1_ram_block2a21_PORT_B_write_enable_reg, , , R1_ram_block2a21_clock_0, R1_ram_block2a21_clock_1, R1_ram_block2a21_clock_enable_0, R1_ram_block2a21_clock_enable_1, , );
R1_ram_block2a21_PORT_A_data_out_reg = DFFE(R1_ram_block2a21_PORT_A_data_out, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1M1098Q = R1_ram_block2a21_PORT_A_data_out_reg[7];


--R1_ram_block2a22 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a22_PORT_A_data_in_reg = DFFE(R1_ram_block2a22_PORT_A_data_in, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_data_in = ~GND;
R1_ram_block2a22_PORT_B_data_in_reg = DFFE(R1_ram_block2a22_PORT_B_data_in, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a22_PORT_A_address_reg = DFFE(R1_ram_block2a22_PORT_A_address, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a22_PORT_B_address_reg = DFFE(R1_ram_block2a22_PORT_B_address, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_write_enable = GND;
R1_ram_block2a22_PORT_A_write_enable_reg = DFFE(R1_ram_block2a22_PORT_A_write_enable, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_write_enable = GND;
R1_ram_block2a22_PORT_B_write_enable_reg = DFFE(R1_ram_block2a22_PORT_B_write_enable, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_clock_0 = M1__clk0;
R1_ram_block2a22_clock_1 = GND;
R1_ram_block2a22_clock_enable_0 = S3_w_anode3106w[3];
R1_ram_block2a22_clock_enable_1 = GND;
R1_ram_block2a22_PORT_A_data_out = MEMORY(R1_ram_block2a22_PORT_A_data_in_reg, R1_ram_block2a22_PORT_B_data_in_reg, R1_ram_block2a22_PORT_A_address_reg, R1_ram_block2a22_PORT_B_address_reg, R1_ram_block2a22_PORT_A_write_enable_reg, R1_ram_block2a22_PORT_B_write_enable_reg, , , R1_ram_block2a22_clock_0, R1_ram_block2a22_clock_1, R1_ram_block2a22_clock_enable_0, R1_ram_block2a22_clock_enable_1, , );
R1_ram_block2a22_PORT_A_data_out_reg = DFFE(R1_ram_block2a22_PORT_A_data_out, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22 = R1_ram_block2a22_PORT_A_data_out_reg[0];

--R1M1142Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT1
R1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a22_PORT_A_data_in_reg = DFFE(R1_ram_block2a22_PORT_A_data_in, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_data_in = ~GND;
R1_ram_block2a22_PORT_B_data_in_reg = DFFE(R1_ram_block2a22_PORT_B_data_in, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a22_PORT_A_address_reg = DFFE(R1_ram_block2a22_PORT_A_address, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a22_PORT_B_address_reg = DFFE(R1_ram_block2a22_PORT_B_address, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_write_enable = GND;
R1_ram_block2a22_PORT_A_write_enable_reg = DFFE(R1_ram_block2a22_PORT_A_write_enable, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_write_enable = GND;
R1_ram_block2a22_PORT_B_write_enable_reg = DFFE(R1_ram_block2a22_PORT_B_write_enable, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_clock_0 = M1__clk0;
R1_ram_block2a22_clock_1 = GND;
R1_ram_block2a22_clock_enable_0 = S3_w_anode3106w[3];
R1_ram_block2a22_clock_enable_1 = GND;
R1_ram_block2a22_PORT_A_data_out = MEMORY(R1_ram_block2a22_PORT_A_data_in_reg, R1_ram_block2a22_PORT_B_data_in_reg, R1_ram_block2a22_PORT_A_address_reg, R1_ram_block2a22_PORT_B_address_reg, R1_ram_block2a22_PORT_A_write_enable_reg, R1_ram_block2a22_PORT_B_write_enable_reg, , , R1_ram_block2a22_clock_0, R1_ram_block2a22_clock_1, R1_ram_block2a22_clock_enable_0, R1_ram_block2a22_clock_enable_1, , );
R1_ram_block2a22_PORT_A_data_out_reg = DFFE(R1_ram_block2a22_PORT_A_data_out, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1M1142Q = R1_ram_block2a22_PORT_A_data_out_reg[1];

--R1M1143Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT2
R1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a22_PORT_A_data_in_reg = DFFE(R1_ram_block2a22_PORT_A_data_in, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_data_in = ~GND;
R1_ram_block2a22_PORT_B_data_in_reg = DFFE(R1_ram_block2a22_PORT_B_data_in, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a22_PORT_A_address_reg = DFFE(R1_ram_block2a22_PORT_A_address, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a22_PORT_B_address_reg = DFFE(R1_ram_block2a22_PORT_B_address, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_write_enable = GND;
R1_ram_block2a22_PORT_A_write_enable_reg = DFFE(R1_ram_block2a22_PORT_A_write_enable, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_write_enable = GND;
R1_ram_block2a22_PORT_B_write_enable_reg = DFFE(R1_ram_block2a22_PORT_B_write_enable, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_clock_0 = M1__clk0;
R1_ram_block2a22_clock_1 = GND;
R1_ram_block2a22_clock_enable_0 = S3_w_anode3106w[3];
R1_ram_block2a22_clock_enable_1 = GND;
R1_ram_block2a22_PORT_A_data_out = MEMORY(R1_ram_block2a22_PORT_A_data_in_reg, R1_ram_block2a22_PORT_B_data_in_reg, R1_ram_block2a22_PORT_A_address_reg, R1_ram_block2a22_PORT_B_address_reg, R1_ram_block2a22_PORT_A_write_enable_reg, R1_ram_block2a22_PORT_B_write_enable_reg, , , R1_ram_block2a22_clock_0, R1_ram_block2a22_clock_1, R1_ram_block2a22_clock_enable_0, R1_ram_block2a22_clock_enable_1, , );
R1_ram_block2a22_PORT_A_data_out_reg = DFFE(R1_ram_block2a22_PORT_A_data_out, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1M1143Q = R1_ram_block2a22_PORT_A_data_out_reg[2];

--R1M1144Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT3
R1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a22_PORT_A_data_in_reg = DFFE(R1_ram_block2a22_PORT_A_data_in, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_data_in = ~GND;
R1_ram_block2a22_PORT_B_data_in_reg = DFFE(R1_ram_block2a22_PORT_B_data_in, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a22_PORT_A_address_reg = DFFE(R1_ram_block2a22_PORT_A_address, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a22_PORT_B_address_reg = DFFE(R1_ram_block2a22_PORT_B_address, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_write_enable = GND;
R1_ram_block2a22_PORT_A_write_enable_reg = DFFE(R1_ram_block2a22_PORT_A_write_enable, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_write_enable = GND;
R1_ram_block2a22_PORT_B_write_enable_reg = DFFE(R1_ram_block2a22_PORT_B_write_enable, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_clock_0 = M1__clk0;
R1_ram_block2a22_clock_1 = GND;
R1_ram_block2a22_clock_enable_0 = S3_w_anode3106w[3];
R1_ram_block2a22_clock_enable_1 = GND;
R1_ram_block2a22_PORT_A_data_out = MEMORY(R1_ram_block2a22_PORT_A_data_in_reg, R1_ram_block2a22_PORT_B_data_in_reg, R1_ram_block2a22_PORT_A_address_reg, R1_ram_block2a22_PORT_B_address_reg, R1_ram_block2a22_PORT_A_write_enable_reg, R1_ram_block2a22_PORT_B_write_enable_reg, , , R1_ram_block2a22_clock_0, R1_ram_block2a22_clock_1, R1_ram_block2a22_clock_enable_0, R1_ram_block2a22_clock_enable_1, , );
R1_ram_block2a22_PORT_A_data_out_reg = DFFE(R1_ram_block2a22_PORT_A_data_out, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1M1144Q = R1_ram_block2a22_PORT_A_data_out_reg[3];

--R1M1145Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT4
R1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a22_PORT_A_data_in_reg = DFFE(R1_ram_block2a22_PORT_A_data_in, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_data_in = ~GND;
R1_ram_block2a22_PORT_B_data_in_reg = DFFE(R1_ram_block2a22_PORT_B_data_in, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a22_PORT_A_address_reg = DFFE(R1_ram_block2a22_PORT_A_address, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a22_PORT_B_address_reg = DFFE(R1_ram_block2a22_PORT_B_address, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_write_enable = GND;
R1_ram_block2a22_PORT_A_write_enable_reg = DFFE(R1_ram_block2a22_PORT_A_write_enable, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_write_enable = GND;
R1_ram_block2a22_PORT_B_write_enable_reg = DFFE(R1_ram_block2a22_PORT_B_write_enable, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_clock_0 = M1__clk0;
R1_ram_block2a22_clock_1 = GND;
R1_ram_block2a22_clock_enable_0 = S3_w_anode3106w[3];
R1_ram_block2a22_clock_enable_1 = GND;
R1_ram_block2a22_PORT_A_data_out = MEMORY(R1_ram_block2a22_PORT_A_data_in_reg, R1_ram_block2a22_PORT_B_data_in_reg, R1_ram_block2a22_PORT_A_address_reg, R1_ram_block2a22_PORT_B_address_reg, R1_ram_block2a22_PORT_A_write_enable_reg, R1_ram_block2a22_PORT_B_write_enable_reg, , , R1_ram_block2a22_clock_0, R1_ram_block2a22_clock_1, R1_ram_block2a22_clock_enable_0, R1_ram_block2a22_clock_enable_1, , );
R1_ram_block2a22_PORT_A_data_out_reg = DFFE(R1_ram_block2a22_PORT_A_data_out, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1M1145Q = R1_ram_block2a22_PORT_A_data_out_reg[4];

--R1M1146Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT5
R1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a22_PORT_A_data_in_reg = DFFE(R1_ram_block2a22_PORT_A_data_in, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_data_in = ~GND;
R1_ram_block2a22_PORT_B_data_in_reg = DFFE(R1_ram_block2a22_PORT_B_data_in, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a22_PORT_A_address_reg = DFFE(R1_ram_block2a22_PORT_A_address, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a22_PORT_B_address_reg = DFFE(R1_ram_block2a22_PORT_B_address, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_write_enable = GND;
R1_ram_block2a22_PORT_A_write_enable_reg = DFFE(R1_ram_block2a22_PORT_A_write_enable, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_write_enable = GND;
R1_ram_block2a22_PORT_B_write_enable_reg = DFFE(R1_ram_block2a22_PORT_B_write_enable, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_clock_0 = M1__clk0;
R1_ram_block2a22_clock_1 = GND;
R1_ram_block2a22_clock_enable_0 = S3_w_anode3106w[3];
R1_ram_block2a22_clock_enable_1 = GND;
R1_ram_block2a22_PORT_A_data_out = MEMORY(R1_ram_block2a22_PORT_A_data_in_reg, R1_ram_block2a22_PORT_B_data_in_reg, R1_ram_block2a22_PORT_A_address_reg, R1_ram_block2a22_PORT_B_address_reg, R1_ram_block2a22_PORT_A_write_enable_reg, R1_ram_block2a22_PORT_B_write_enable_reg, , , R1_ram_block2a22_clock_0, R1_ram_block2a22_clock_1, R1_ram_block2a22_clock_enable_0, R1_ram_block2a22_clock_enable_1, , );
R1_ram_block2a22_PORT_A_data_out_reg = DFFE(R1_ram_block2a22_PORT_A_data_out, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1M1146Q = R1_ram_block2a22_PORT_A_data_out_reg[5];

--R1M1147Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT6
R1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a22_PORT_A_data_in_reg = DFFE(R1_ram_block2a22_PORT_A_data_in, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_data_in = ~GND;
R1_ram_block2a22_PORT_B_data_in_reg = DFFE(R1_ram_block2a22_PORT_B_data_in, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a22_PORT_A_address_reg = DFFE(R1_ram_block2a22_PORT_A_address, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a22_PORT_B_address_reg = DFFE(R1_ram_block2a22_PORT_B_address, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_write_enable = GND;
R1_ram_block2a22_PORT_A_write_enable_reg = DFFE(R1_ram_block2a22_PORT_A_write_enable, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_write_enable = GND;
R1_ram_block2a22_PORT_B_write_enable_reg = DFFE(R1_ram_block2a22_PORT_B_write_enable, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_clock_0 = M1__clk0;
R1_ram_block2a22_clock_1 = GND;
R1_ram_block2a22_clock_enable_0 = S3_w_anode3106w[3];
R1_ram_block2a22_clock_enable_1 = GND;
R1_ram_block2a22_PORT_A_data_out = MEMORY(R1_ram_block2a22_PORT_A_data_in_reg, R1_ram_block2a22_PORT_B_data_in_reg, R1_ram_block2a22_PORT_A_address_reg, R1_ram_block2a22_PORT_B_address_reg, R1_ram_block2a22_PORT_A_write_enable_reg, R1_ram_block2a22_PORT_B_write_enable_reg, , , R1_ram_block2a22_clock_0, R1_ram_block2a22_clock_1, R1_ram_block2a22_clock_enable_0, R1_ram_block2a22_clock_enable_1, , );
R1_ram_block2a22_PORT_A_data_out_reg = DFFE(R1_ram_block2a22_PORT_A_data_out, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1M1147Q = R1_ram_block2a22_PORT_A_data_out_reg[6];

--R1M1148Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT7
R1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a22_PORT_A_data_in_reg = DFFE(R1_ram_block2a22_PORT_A_data_in, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_data_in = ~GND;
R1_ram_block2a22_PORT_B_data_in_reg = DFFE(R1_ram_block2a22_PORT_B_data_in, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a22_PORT_A_address_reg = DFFE(R1_ram_block2a22_PORT_A_address, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a22_PORT_B_address_reg = DFFE(R1_ram_block2a22_PORT_B_address, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_write_enable = GND;
R1_ram_block2a22_PORT_A_write_enable_reg = DFFE(R1_ram_block2a22_PORT_A_write_enable, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_write_enable = GND;
R1_ram_block2a22_PORT_B_write_enable_reg = DFFE(R1_ram_block2a22_PORT_B_write_enable, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_clock_0 = M1__clk0;
R1_ram_block2a22_clock_1 = GND;
R1_ram_block2a22_clock_enable_0 = S3_w_anode3106w[3];
R1_ram_block2a22_clock_enable_1 = GND;
R1_ram_block2a22_PORT_A_data_out = MEMORY(R1_ram_block2a22_PORT_A_data_in_reg, R1_ram_block2a22_PORT_B_data_in_reg, R1_ram_block2a22_PORT_A_address_reg, R1_ram_block2a22_PORT_B_address_reg, R1_ram_block2a22_PORT_A_write_enable_reg, R1_ram_block2a22_PORT_B_write_enable_reg, , , R1_ram_block2a22_clock_0, R1_ram_block2a22_clock_1, R1_ram_block2a22_clock_enable_0, R1_ram_block2a22_clock_enable_1, , );
R1_ram_block2a22_PORT_A_data_out_reg = DFFE(R1_ram_block2a22_PORT_A_data_out, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1M1148Q = R1_ram_block2a22_PORT_A_data_out_reg[7];


--R1_ram_block2a20 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a20_PORT_A_data_in_reg = DFFE(R1_ram_block2a20_PORT_A_data_in, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_data_in = ~GND;
R1_ram_block2a20_PORT_B_data_in_reg = DFFE(R1_ram_block2a20_PORT_B_data_in, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a20_PORT_A_address_reg = DFFE(R1_ram_block2a20_PORT_A_address, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a20_PORT_B_address_reg = DFFE(R1_ram_block2a20_PORT_B_address, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_write_enable = GND;
R1_ram_block2a20_PORT_A_write_enable_reg = DFFE(R1_ram_block2a20_PORT_A_write_enable, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_write_enable = GND;
R1_ram_block2a20_PORT_B_write_enable_reg = DFFE(R1_ram_block2a20_PORT_B_write_enable, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_clock_0 = M1__clk0;
R1_ram_block2a20_clock_1 = GND;
R1_ram_block2a20_clock_enable_0 = S3_w_anode3086w[3];
R1_ram_block2a20_clock_enable_1 = GND;
R1_ram_block2a20_PORT_A_data_out = MEMORY(R1_ram_block2a20_PORT_A_data_in_reg, R1_ram_block2a20_PORT_B_data_in_reg, R1_ram_block2a20_PORT_A_address_reg, R1_ram_block2a20_PORT_B_address_reg, R1_ram_block2a20_PORT_A_write_enable_reg, R1_ram_block2a20_PORT_B_write_enable_reg, , , R1_ram_block2a20_clock_0, R1_ram_block2a20_clock_1, R1_ram_block2a20_clock_enable_0, R1_ram_block2a20_clock_enable_1, , );
R1_ram_block2a20_PORT_A_data_out_reg = DFFE(R1_ram_block2a20_PORT_A_data_out, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20 = R1_ram_block2a20_PORT_A_data_out_reg[0];

--R1M1042Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT1
R1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a20_PORT_A_data_in_reg = DFFE(R1_ram_block2a20_PORT_A_data_in, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_data_in = ~GND;
R1_ram_block2a20_PORT_B_data_in_reg = DFFE(R1_ram_block2a20_PORT_B_data_in, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a20_PORT_A_address_reg = DFFE(R1_ram_block2a20_PORT_A_address, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a20_PORT_B_address_reg = DFFE(R1_ram_block2a20_PORT_B_address, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_write_enable = GND;
R1_ram_block2a20_PORT_A_write_enable_reg = DFFE(R1_ram_block2a20_PORT_A_write_enable, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_write_enable = GND;
R1_ram_block2a20_PORT_B_write_enable_reg = DFFE(R1_ram_block2a20_PORT_B_write_enable, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_clock_0 = M1__clk0;
R1_ram_block2a20_clock_1 = GND;
R1_ram_block2a20_clock_enable_0 = S3_w_anode3086w[3];
R1_ram_block2a20_clock_enable_1 = GND;
R1_ram_block2a20_PORT_A_data_out = MEMORY(R1_ram_block2a20_PORT_A_data_in_reg, R1_ram_block2a20_PORT_B_data_in_reg, R1_ram_block2a20_PORT_A_address_reg, R1_ram_block2a20_PORT_B_address_reg, R1_ram_block2a20_PORT_A_write_enable_reg, R1_ram_block2a20_PORT_B_write_enable_reg, , , R1_ram_block2a20_clock_0, R1_ram_block2a20_clock_1, R1_ram_block2a20_clock_enable_0, R1_ram_block2a20_clock_enable_1, , );
R1_ram_block2a20_PORT_A_data_out_reg = DFFE(R1_ram_block2a20_PORT_A_data_out, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1M1042Q = R1_ram_block2a20_PORT_A_data_out_reg[1];

--R1M1043Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT2
R1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a20_PORT_A_data_in_reg = DFFE(R1_ram_block2a20_PORT_A_data_in, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_data_in = ~GND;
R1_ram_block2a20_PORT_B_data_in_reg = DFFE(R1_ram_block2a20_PORT_B_data_in, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a20_PORT_A_address_reg = DFFE(R1_ram_block2a20_PORT_A_address, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a20_PORT_B_address_reg = DFFE(R1_ram_block2a20_PORT_B_address, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_write_enable = GND;
R1_ram_block2a20_PORT_A_write_enable_reg = DFFE(R1_ram_block2a20_PORT_A_write_enable, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_write_enable = GND;
R1_ram_block2a20_PORT_B_write_enable_reg = DFFE(R1_ram_block2a20_PORT_B_write_enable, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_clock_0 = M1__clk0;
R1_ram_block2a20_clock_1 = GND;
R1_ram_block2a20_clock_enable_0 = S3_w_anode3086w[3];
R1_ram_block2a20_clock_enable_1 = GND;
R1_ram_block2a20_PORT_A_data_out = MEMORY(R1_ram_block2a20_PORT_A_data_in_reg, R1_ram_block2a20_PORT_B_data_in_reg, R1_ram_block2a20_PORT_A_address_reg, R1_ram_block2a20_PORT_B_address_reg, R1_ram_block2a20_PORT_A_write_enable_reg, R1_ram_block2a20_PORT_B_write_enable_reg, , , R1_ram_block2a20_clock_0, R1_ram_block2a20_clock_1, R1_ram_block2a20_clock_enable_0, R1_ram_block2a20_clock_enable_1, , );
R1_ram_block2a20_PORT_A_data_out_reg = DFFE(R1_ram_block2a20_PORT_A_data_out, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1M1043Q = R1_ram_block2a20_PORT_A_data_out_reg[2];

--R1M1044Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT3
R1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a20_PORT_A_data_in_reg = DFFE(R1_ram_block2a20_PORT_A_data_in, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_data_in = ~GND;
R1_ram_block2a20_PORT_B_data_in_reg = DFFE(R1_ram_block2a20_PORT_B_data_in, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a20_PORT_A_address_reg = DFFE(R1_ram_block2a20_PORT_A_address, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a20_PORT_B_address_reg = DFFE(R1_ram_block2a20_PORT_B_address, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_write_enable = GND;
R1_ram_block2a20_PORT_A_write_enable_reg = DFFE(R1_ram_block2a20_PORT_A_write_enable, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_write_enable = GND;
R1_ram_block2a20_PORT_B_write_enable_reg = DFFE(R1_ram_block2a20_PORT_B_write_enable, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_clock_0 = M1__clk0;
R1_ram_block2a20_clock_1 = GND;
R1_ram_block2a20_clock_enable_0 = S3_w_anode3086w[3];
R1_ram_block2a20_clock_enable_1 = GND;
R1_ram_block2a20_PORT_A_data_out = MEMORY(R1_ram_block2a20_PORT_A_data_in_reg, R1_ram_block2a20_PORT_B_data_in_reg, R1_ram_block2a20_PORT_A_address_reg, R1_ram_block2a20_PORT_B_address_reg, R1_ram_block2a20_PORT_A_write_enable_reg, R1_ram_block2a20_PORT_B_write_enable_reg, , , R1_ram_block2a20_clock_0, R1_ram_block2a20_clock_1, R1_ram_block2a20_clock_enable_0, R1_ram_block2a20_clock_enable_1, , );
R1_ram_block2a20_PORT_A_data_out_reg = DFFE(R1_ram_block2a20_PORT_A_data_out, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1M1044Q = R1_ram_block2a20_PORT_A_data_out_reg[3];

--R1M1045Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT4
R1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a20_PORT_A_data_in_reg = DFFE(R1_ram_block2a20_PORT_A_data_in, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_data_in = ~GND;
R1_ram_block2a20_PORT_B_data_in_reg = DFFE(R1_ram_block2a20_PORT_B_data_in, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a20_PORT_A_address_reg = DFFE(R1_ram_block2a20_PORT_A_address, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a20_PORT_B_address_reg = DFFE(R1_ram_block2a20_PORT_B_address, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_write_enable = GND;
R1_ram_block2a20_PORT_A_write_enable_reg = DFFE(R1_ram_block2a20_PORT_A_write_enable, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_write_enable = GND;
R1_ram_block2a20_PORT_B_write_enable_reg = DFFE(R1_ram_block2a20_PORT_B_write_enable, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_clock_0 = M1__clk0;
R1_ram_block2a20_clock_1 = GND;
R1_ram_block2a20_clock_enable_0 = S3_w_anode3086w[3];
R1_ram_block2a20_clock_enable_1 = GND;
R1_ram_block2a20_PORT_A_data_out = MEMORY(R1_ram_block2a20_PORT_A_data_in_reg, R1_ram_block2a20_PORT_B_data_in_reg, R1_ram_block2a20_PORT_A_address_reg, R1_ram_block2a20_PORT_B_address_reg, R1_ram_block2a20_PORT_A_write_enable_reg, R1_ram_block2a20_PORT_B_write_enable_reg, , , R1_ram_block2a20_clock_0, R1_ram_block2a20_clock_1, R1_ram_block2a20_clock_enable_0, R1_ram_block2a20_clock_enable_1, , );
R1_ram_block2a20_PORT_A_data_out_reg = DFFE(R1_ram_block2a20_PORT_A_data_out, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1M1045Q = R1_ram_block2a20_PORT_A_data_out_reg[4];

--R1M1046Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT5
R1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a20_PORT_A_data_in_reg = DFFE(R1_ram_block2a20_PORT_A_data_in, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_data_in = ~GND;
R1_ram_block2a20_PORT_B_data_in_reg = DFFE(R1_ram_block2a20_PORT_B_data_in, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a20_PORT_A_address_reg = DFFE(R1_ram_block2a20_PORT_A_address, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a20_PORT_B_address_reg = DFFE(R1_ram_block2a20_PORT_B_address, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_write_enable = GND;
R1_ram_block2a20_PORT_A_write_enable_reg = DFFE(R1_ram_block2a20_PORT_A_write_enable, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_write_enable = GND;
R1_ram_block2a20_PORT_B_write_enable_reg = DFFE(R1_ram_block2a20_PORT_B_write_enable, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_clock_0 = M1__clk0;
R1_ram_block2a20_clock_1 = GND;
R1_ram_block2a20_clock_enable_0 = S3_w_anode3086w[3];
R1_ram_block2a20_clock_enable_1 = GND;
R1_ram_block2a20_PORT_A_data_out = MEMORY(R1_ram_block2a20_PORT_A_data_in_reg, R1_ram_block2a20_PORT_B_data_in_reg, R1_ram_block2a20_PORT_A_address_reg, R1_ram_block2a20_PORT_B_address_reg, R1_ram_block2a20_PORT_A_write_enable_reg, R1_ram_block2a20_PORT_B_write_enable_reg, , , R1_ram_block2a20_clock_0, R1_ram_block2a20_clock_1, R1_ram_block2a20_clock_enable_0, R1_ram_block2a20_clock_enable_1, , );
R1_ram_block2a20_PORT_A_data_out_reg = DFFE(R1_ram_block2a20_PORT_A_data_out, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1M1046Q = R1_ram_block2a20_PORT_A_data_out_reg[5];

--R1M1047Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT6
R1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a20_PORT_A_data_in_reg = DFFE(R1_ram_block2a20_PORT_A_data_in, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_data_in = ~GND;
R1_ram_block2a20_PORT_B_data_in_reg = DFFE(R1_ram_block2a20_PORT_B_data_in, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a20_PORT_A_address_reg = DFFE(R1_ram_block2a20_PORT_A_address, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a20_PORT_B_address_reg = DFFE(R1_ram_block2a20_PORT_B_address, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_write_enable = GND;
R1_ram_block2a20_PORT_A_write_enable_reg = DFFE(R1_ram_block2a20_PORT_A_write_enable, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_write_enable = GND;
R1_ram_block2a20_PORT_B_write_enable_reg = DFFE(R1_ram_block2a20_PORT_B_write_enable, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_clock_0 = M1__clk0;
R1_ram_block2a20_clock_1 = GND;
R1_ram_block2a20_clock_enable_0 = S3_w_anode3086w[3];
R1_ram_block2a20_clock_enable_1 = GND;
R1_ram_block2a20_PORT_A_data_out = MEMORY(R1_ram_block2a20_PORT_A_data_in_reg, R1_ram_block2a20_PORT_B_data_in_reg, R1_ram_block2a20_PORT_A_address_reg, R1_ram_block2a20_PORT_B_address_reg, R1_ram_block2a20_PORT_A_write_enable_reg, R1_ram_block2a20_PORT_B_write_enable_reg, , , R1_ram_block2a20_clock_0, R1_ram_block2a20_clock_1, R1_ram_block2a20_clock_enable_0, R1_ram_block2a20_clock_enable_1, , );
R1_ram_block2a20_PORT_A_data_out_reg = DFFE(R1_ram_block2a20_PORT_A_data_out, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1M1047Q = R1_ram_block2a20_PORT_A_data_out_reg[6];

--R1M1048Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT7
R1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a20_PORT_A_data_in_reg = DFFE(R1_ram_block2a20_PORT_A_data_in, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_data_in = ~GND;
R1_ram_block2a20_PORT_B_data_in_reg = DFFE(R1_ram_block2a20_PORT_B_data_in, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a20_PORT_A_address_reg = DFFE(R1_ram_block2a20_PORT_A_address, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a20_PORT_B_address_reg = DFFE(R1_ram_block2a20_PORT_B_address, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_write_enable = GND;
R1_ram_block2a20_PORT_A_write_enable_reg = DFFE(R1_ram_block2a20_PORT_A_write_enable, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_write_enable = GND;
R1_ram_block2a20_PORT_B_write_enable_reg = DFFE(R1_ram_block2a20_PORT_B_write_enable, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_clock_0 = M1__clk0;
R1_ram_block2a20_clock_1 = GND;
R1_ram_block2a20_clock_enable_0 = S3_w_anode3086w[3];
R1_ram_block2a20_clock_enable_1 = GND;
R1_ram_block2a20_PORT_A_data_out = MEMORY(R1_ram_block2a20_PORT_A_data_in_reg, R1_ram_block2a20_PORT_B_data_in_reg, R1_ram_block2a20_PORT_A_address_reg, R1_ram_block2a20_PORT_B_address_reg, R1_ram_block2a20_PORT_A_write_enable_reg, R1_ram_block2a20_PORT_B_write_enable_reg, , , R1_ram_block2a20_clock_0, R1_ram_block2a20_clock_1, R1_ram_block2a20_clock_enable_0, R1_ram_block2a20_clock_enable_1, , );
R1_ram_block2a20_PORT_A_data_out_reg = DFFE(R1_ram_block2a20_PORT_A_data_out, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1M1048Q = R1_ram_block2a20_PORT_A_data_out_reg[7];


--T1L220 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6491w~44
T1L220 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M1146Q # !R1_address_reg_a[7] & (R1M1046Q));


--R1_ram_block2a23 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a23_PORT_A_data_in_reg = DFFE(R1_ram_block2a23_PORT_A_data_in, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_data_in = ~GND;
R1_ram_block2a23_PORT_B_data_in_reg = DFFE(R1_ram_block2a23_PORT_B_data_in, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a23_PORT_A_address_reg = DFFE(R1_ram_block2a23_PORT_A_address, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a23_PORT_B_address_reg = DFFE(R1_ram_block2a23_PORT_B_address, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_write_enable = GND;
R1_ram_block2a23_PORT_A_write_enable_reg = DFFE(R1_ram_block2a23_PORT_A_write_enable, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_write_enable = GND;
R1_ram_block2a23_PORT_B_write_enable_reg = DFFE(R1_ram_block2a23_PORT_B_write_enable, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_clock_0 = M1__clk0;
R1_ram_block2a23_clock_1 = GND;
R1_ram_block2a23_clock_enable_0 = S3_w_anode3116w[3];
R1_ram_block2a23_clock_enable_1 = GND;
R1_ram_block2a23_PORT_A_data_out = MEMORY(R1_ram_block2a23_PORT_A_data_in_reg, R1_ram_block2a23_PORT_B_data_in_reg, R1_ram_block2a23_PORT_A_address_reg, R1_ram_block2a23_PORT_B_address_reg, R1_ram_block2a23_PORT_A_write_enable_reg, R1_ram_block2a23_PORT_B_write_enable_reg, , , R1_ram_block2a23_clock_0, R1_ram_block2a23_clock_1, R1_ram_block2a23_clock_enable_0, R1_ram_block2a23_clock_enable_1, , );
R1_ram_block2a23_PORT_A_data_out_reg = DFFE(R1_ram_block2a23_PORT_A_data_out, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23 = R1_ram_block2a23_PORT_A_data_out_reg[0];

--R1M1192Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT1
R1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a23_PORT_A_data_in_reg = DFFE(R1_ram_block2a23_PORT_A_data_in, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_data_in = ~GND;
R1_ram_block2a23_PORT_B_data_in_reg = DFFE(R1_ram_block2a23_PORT_B_data_in, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a23_PORT_A_address_reg = DFFE(R1_ram_block2a23_PORT_A_address, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a23_PORT_B_address_reg = DFFE(R1_ram_block2a23_PORT_B_address, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_write_enable = GND;
R1_ram_block2a23_PORT_A_write_enable_reg = DFFE(R1_ram_block2a23_PORT_A_write_enable, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_write_enable = GND;
R1_ram_block2a23_PORT_B_write_enable_reg = DFFE(R1_ram_block2a23_PORT_B_write_enable, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_clock_0 = M1__clk0;
R1_ram_block2a23_clock_1 = GND;
R1_ram_block2a23_clock_enable_0 = S3_w_anode3116w[3];
R1_ram_block2a23_clock_enable_1 = GND;
R1_ram_block2a23_PORT_A_data_out = MEMORY(R1_ram_block2a23_PORT_A_data_in_reg, R1_ram_block2a23_PORT_B_data_in_reg, R1_ram_block2a23_PORT_A_address_reg, R1_ram_block2a23_PORT_B_address_reg, R1_ram_block2a23_PORT_A_write_enable_reg, R1_ram_block2a23_PORT_B_write_enable_reg, , , R1_ram_block2a23_clock_0, R1_ram_block2a23_clock_1, R1_ram_block2a23_clock_enable_0, R1_ram_block2a23_clock_enable_1, , );
R1_ram_block2a23_PORT_A_data_out_reg = DFFE(R1_ram_block2a23_PORT_A_data_out, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1M1192Q = R1_ram_block2a23_PORT_A_data_out_reg[1];

--R1M1193Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT2
R1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a23_PORT_A_data_in_reg = DFFE(R1_ram_block2a23_PORT_A_data_in, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_data_in = ~GND;
R1_ram_block2a23_PORT_B_data_in_reg = DFFE(R1_ram_block2a23_PORT_B_data_in, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a23_PORT_A_address_reg = DFFE(R1_ram_block2a23_PORT_A_address, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a23_PORT_B_address_reg = DFFE(R1_ram_block2a23_PORT_B_address, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_write_enable = GND;
R1_ram_block2a23_PORT_A_write_enable_reg = DFFE(R1_ram_block2a23_PORT_A_write_enable, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_write_enable = GND;
R1_ram_block2a23_PORT_B_write_enable_reg = DFFE(R1_ram_block2a23_PORT_B_write_enable, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_clock_0 = M1__clk0;
R1_ram_block2a23_clock_1 = GND;
R1_ram_block2a23_clock_enable_0 = S3_w_anode3116w[3];
R1_ram_block2a23_clock_enable_1 = GND;
R1_ram_block2a23_PORT_A_data_out = MEMORY(R1_ram_block2a23_PORT_A_data_in_reg, R1_ram_block2a23_PORT_B_data_in_reg, R1_ram_block2a23_PORT_A_address_reg, R1_ram_block2a23_PORT_B_address_reg, R1_ram_block2a23_PORT_A_write_enable_reg, R1_ram_block2a23_PORT_B_write_enable_reg, , , R1_ram_block2a23_clock_0, R1_ram_block2a23_clock_1, R1_ram_block2a23_clock_enable_0, R1_ram_block2a23_clock_enable_1, , );
R1_ram_block2a23_PORT_A_data_out_reg = DFFE(R1_ram_block2a23_PORT_A_data_out, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1M1193Q = R1_ram_block2a23_PORT_A_data_out_reg[2];

--R1M1194Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT3
R1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a23_PORT_A_data_in_reg = DFFE(R1_ram_block2a23_PORT_A_data_in, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_data_in = ~GND;
R1_ram_block2a23_PORT_B_data_in_reg = DFFE(R1_ram_block2a23_PORT_B_data_in, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a23_PORT_A_address_reg = DFFE(R1_ram_block2a23_PORT_A_address, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a23_PORT_B_address_reg = DFFE(R1_ram_block2a23_PORT_B_address, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_write_enable = GND;
R1_ram_block2a23_PORT_A_write_enable_reg = DFFE(R1_ram_block2a23_PORT_A_write_enable, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_write_enable = GND;
R1_ram_block2a23_PORT_B_write_enable_reg = DFFE(R1_ram_block2a23_PORT_B_write_enable, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_clock_0 = M1__clk0;
R1_ram_block2a23_clock_1 = GND;
R1_ram_block2a23_clock_enable_0 = S3_w_anode3116w[3];
R1_ram_block2a23_clock_enable_1 = GND;
R1_ram_block2a23_PORT_A_data_out = MEMORY(R1_ram_block2a23_PORT_A_data_in_reg, R1_ram_block2a23_PORT_B_data_in_reg, R1_ram_block2a23_PORT_A_address_reg, R1_ram_block2a23_PORT_B_address_reg, R1_ram_block2a23_PORT_A_write_enable_reg, R1_ram_block2a23_PORT_B_write_enable_reg, , , R1_ram_block2a23_clock_0, R1_ram_block2a23_clock_1, R1_ram_block2a23_clock_enable_0, R1_ram_block2a23_clock_enable_1, , );
R1_ram_block2a23_PORT_A_data_out_reg = DFFE(R1_ram_block2a23_PORT_A_data_out, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1M1194Q = R1_ram_block2a23_PORT_A_data_out_reg[3];

--R1M1195Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT4
R1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a23_PORT_A_data_in_reg = DFFE(R1_ram_block2a23_PORT_A_data_in, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_data_in = ~GND;
R1_ram_block2a23_PORT_B_data_in_reg = DFFE(R1_ram_block2a23_PORT_B_data_in, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a23_PORT_A_address_reg = DFFE(R1_ram_block2a23_PORT_A_address, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a23_PORT_B_address_reg = DFFE(R1_ram_block2a23_PORT_B_address, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_write_enable = GND;
R1_ram_block2a23_PORT_A_write_enable_reg = DFFE(R1_ram_block2a23_PORT_A_write_enable, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_write_enable = GND;
R1_ram_block2a23_PORT_B_write_enable_reg = DFFE(R1_ram_block2a23_PORT_B_write_enable, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_clock_0 = M1__clk0;
R1_ram_block2a23_clock_1 = GND;
R1_ram_block2a23_clock_enable_0 = S3_w_anode3116w[3];
R1_ram_block2a23_clock_enable_1 = GND;
R1_ram_block2a23_PORT_A_data_out = MEMORY(R1_ram_block2a23_PORT_A_data_in_reg, R1_ram_block2a23_PORT_B_data_in_reg, R1_ram_block2a23_PORT_A_address_reg, R1_ram_block2a23_PORT_B_address_reg, R1_ram_block2a23_PORT_A_write_enable_reg, R1_ram_block2a23_PORT_B_write_enable_reg, , , R1_ram_block2a23_clock_0, R1_ram_block2a23_clock_1, R1_ram_block2a23_clock_enable_0, R1_ram_block2a23_clock_enable_1, , );
R1_ram_block2a23_PORT_A_data_out_reg = DFFE(R1_ram_block2a23_PORT_A_data_out, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1M1195Q = R1_ram_block2a23_PORT_A_data_out_reg[4];

--R1M1196Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT5
R1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a23_PORT_A_data_in_reg = DFFE(R1_ram_block2a23_PORT_A_data_in, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_data_in = ~GND;
R1_ram_block2a23_PORT_B_data_in_reg = DFFE(R1_ram_block2a23_PORT_B_data_in, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a23_PORT_A_address_reg = DFFE(R1_ram_block2a23_PORT_A_address, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a23_PORT_B_address_reg = DFFE(R1_ram_block2a23_PORT_B_address, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_write_enable = GND;
R1_ram_block2a23_PORT_A_write_enable_reg = DFFE(R1_ram_block2a23_PORT_A_write_enable, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_write_enable = GND;
R1_ram_block2a23_PORT_B_write_enable_reg = DFFE(R1_ram_block2a23_PORT_B_write_enable, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_clock_0 = M1__clk0;
R1_ram_block2a23_clock_1 = GND;
R1_ram_block2a23_clock_enable_0 = S3_w_anode3116w[3];
R1_ram_block2a23_clock_enable_1 = GND;
R1_ram_block2a23_PORT_A_data_out = MEMORY(R1_ram_block2a23_PORT_A_data_in_reg, R1_ram_block2a23_PORT_B_data_in_reg, R1_ram_block2a23_PORT_A_address_reg, R1_ram_block2a23_PORT_B_address_reg, R1_ram_block2a23_PORT_A_write_enable_reg, R1_ram_block2a23_PORT_B_write_enable_reg, , , R1_ram_block2a23_clock_0, R1_ram_block2a23_clock_1, R1_ram_block2a23_clock_enable_0, R1_ram_block2a23_clock_enable_1, , );
R1_ram_block2a23_PORT_A_data_out_reg = DFFE(R1_ram_block2a23_PORT_A_data_out, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1M1196Q = R1_ram_block2a23_PORT_A_data_out_reg[5];

--R1M1197Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT6
R1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a23_PORT_A_data_in_reg = DFFE(R1_ram_block2a23_PORT_A_data_in, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_data_in = ~GND;
R1_ram_block2a23_PORT_B_data_in_reg = DFFE(R1_ram_block2a23_PORT_B_data_in, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a23_PORT_A_address_reg = DFFE(R1_ram_block2a23_PORT_A_address, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a23_PORT_B_address_reg = DFFE(R1_ram_block2a23_PORT_B_address, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_write_enable = GND;
R1_ram_block2a23_PORT_A_write_enable_reg = DFFE(R1_ram_block2a23_PORT_A_write_enable, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_write_enable = GND;
R1_ram_block2a23_PORT_B_write_enable_reg = DFFE(R1_ram_block2a23_PORT_B_write_enable, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_clock_0 = M1__clk0;
R1_ram_block2a23_clock_1 = GND;
R1_ram_block2a23_clock_enable_0 = S3_w_anode3116w[3];
R1_ram_block2a23_clock_enable_1 = GND;
R1_ram_block2a23_PORT_A_data_out = MEMORY(R1_ram_block2a23_PORT_A_data_in_reg, R1_ram_block2a23_PORT_B_data_in_reg, R1_ram_block2a23_PORT_A_address_reg, R1_ram_block2a23_PORT_B_address_reg, R1_ram_block2a23_PORT_A_write_enable_reg, R1_ram_block2a23_PORT_B_write_enable_reg, , , R1_ram_block2a23_clock_0, R1_ram_block2a23_clock_1, R1_ram_block2a23_clock_enable_0, R1_ram_block2a23_clock_enable_1, , );
R1_ram_block2a23_PORT_A_data_out_reg = DFFE(R1_ram_block2a23_PORT_A_data_out, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1M1197Q = R1_ram_block2a23_PORT_A_data_out_reg[6];

--R1M1198Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT7
R1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a23_PORT_A_data_in_reg = DFFE(R1_ram_block2a23_PORT_A_data_in, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_data_in = ~GND;
R1_ram_block2a23_PORT_B_data_in_reg = DFFE(R1_ram_block2a23_PORT_B_data_in, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a23_PORT_A_address_reg = DFFE(R1_ram_block2a23_PORT_A_address, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a23_PORT_B_address_reg = DFFE(R1_ram_block2a23_PORT_B_address, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_write_enable = GND;
R1_ram_block2a23_PORT_A_write_enable_reg = DFFE(R1_ram_block2a23_PORT_A_write_enable, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_write_enable = GND;
R1_ram_block2a23_PORT_B_write_enable_reg = DFFE(R1_ram_block2a23_PORT_B_write_enable, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_clock_0 = M1__clk0;
R1_ram_block2a23_clock_1 = GND;
R1_ram_block2a23_clock_enable_0 = S3_w_anode3116w[3];
R1_ram_block2a23_clock_enable_1 = GND;
R1_ram_block2a23_PORT_A_data_out = MEMORY(R1_ram_block2a23_PORT_A_data_in_reg, R1_ram_block2a23_PORT_B_data_in_reg, R1_ram_block2a23_PORT_A_address_reg, R1_ram_block2a23_PORT_B_address_reg, R1_ram_block2a23_PORT_A_write_enable_reg, R1_ram_block2a23_PORT_B_write_enable_reg, , , R1_ram_block2a23_clock_0, R1_ram_block2a23_clock_1, R1_ram_block2a23_clock_enable_0, R1_ram_block2a23_clock_enable_1, , );
R1_ram_block2a23_PORT_A_data_out_reg = DFFE(R1_ram_block2a23_PORT_A_data_out, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1M1198Q = R1_ram_block2a23_PORT_A_data_out_reg[7];


--T1L221 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6491w~45
T1L221 = R1_address_reg_a[6] & (T1L220 & (R1M1196Q) # !T1L220 & R1M1096Q) # !R1_address_reg_a[6] & (T1L220);


--T1L49 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5034
T1L49 = R1_address_reg_a[9] & T1L223 # !R1_address_reg_a[9] & (T1L221);


--R1_ram_block2a17 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a17_PORT_A_data_in_reg = DFFE(R1_ram_block2a17_PORT_A_data_in, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_data_in = ~GND;
R1_ram_block2a17_PORT_B_data_in_reg = DFFE(R1_ram_block2a17_PORT_B_data_in, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a17_PORT_A_address_reg = DFFE(R1_ram_block2a17_PORT_A_address, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a17_PORT_B_address_reg = DFFE(R1_ram_block2a17_PORT_B_address, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_write_enable = GND;
R1_ram_block2a17_PORT_A_write_enable_reg = DFFE(R1_ram_block2a17_PORT_A_write_enable, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_write_enable = GND;
R1_ram_block2a17_PORT_B_write_enable_reg = DFFE(R1_ram_block2a17_PORT_B_write_enable, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_clock_0 = M1__clk0;
R1_ram_block2a17_clock_1 = GND;
R1_ram_block2a17_clock_enable_0 = S3_w_anode3056w[3];
R1_ram_block2a17_clock_enable_1 = GND;
R1_ram_block2a17_PORT_A_data_out = MEMORY(R1_ram_block2a17_PORT_A_data_in_reg, R1_ram_block2a17_PORT_B_data_in_reg, R1_ram_block2a17_PORT_A_address_reg, R1_ram_block2a17_PORT_B_address_reg, R1_ram_block2a17_PORT_A_write_enable_reg, R1_ram_block2a17_PORT_B_write_enable_reg, , , R1_ram_block2a17_clock_0, R1_ram_block2a17_clock_1, R1_ram_block2a17_clock_enable_0, R1_ram_block2a17_clock_enable_1, , );
R1_ram_block2a17_PORT_A_data_out_reg = DFFE(R1_ram_block2a17_PORT_A_data_out, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17 = R1_ram_block2a17_PORT_A_data_out_reg[0];

--R1M892Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT1
R1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a17_PORT_A_data_in_reg = DFFE(R1_ram_block2a17_PORT_A_data_in, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_data_in = ~GND;
R1_ram_block2a17_PORT_B_data_in_reg = DFFE(R1_ram_block2a17_PORT_B_data_in, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a17_PORT_A_address_reg = DFFE(R1_ram_block2a17_PORT_A_address, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a17_PORT_B_address_reg = DFFE(R1_ram_block2a17_PORT_B_address, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_write_enable = GND;
R1_ram_block2a17_PORT_A_write_enable_reg = DFFE(R1_ram_block2a17_PORT_A_write_enable, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_write_enable = GND;
R1_ram_block2a17_PORT_B_write_enable_reg = DFFE(R1_ram_block2a17_PORT_B_write_enable, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_clock_0 = M1__clk0;
R1_ram_block2a17_clock_1 = GND;
R1_ram_block2a17_clock_enable_0 = S3_w_anode3056w[3];
R1_ram_block2a17_clock_enable_1 = GND;
R1_ram_block2a17_PORT_A_data_out = MEMORY(R1_ram_block2a17_PORT_A_data_in_reg, R1_ram_block2a17_PORT_B_data_in_reg, R1_ram_block2a17_PORT_A_address_reg, R1_ram_block2a17_PORT_B_address_reg, R1_ram_block2a17_PORT_A_write_enable_reg, R1_ram_block2a17_PORT_B_write_enable_reg, , , R1_ram_block2a17_clock_0, R1_ram_block2a17_clock_1, R1_ram_block2a17_clock_enable_0, R1_ram_block2a17_clock_enable_1, , );
R1_ram_block2a17_PORT_A_data_out_reg = DFFE(R1_ram_block2a17_PORT_A_data_out, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1M892Q = R1_ram_block2a17_PORT_A_data_out_reg[1];

--R1M893Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT2
R1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a17_PORT_A_data_in_reg = DFFE(R1_ram_block2a17_PORT_A_data_in, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_data_in = ~GND;
R1_ram_block2a17_PORT_B_data_in_reg = DFFE(R1_ram_block2a17_PORT_B_data_in, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a17_PORT_A_address_reg = DFFE(R1_ram_block2a17_PORT_A_address, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a17_PORT_B_address_reg = DFFE(R1_ram_block2a17_PORT_B_address, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_write_enable = GND;
R1_ram_block2a17_PORT_A_write_enable_reg = DFFE(R1_ram_block2a17_PORT_A_write_enable, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_write_enable = GND;
R1_ram_block2a17_PORT_B_write_enable_reg = DFFE(R1_ram_block2a17_PORT_B_write_enable, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_clock_0 = M1__clk0;
R1_ram_block2a17_clock_1 = GND;
R1_ram_block2a17_clock_enable_0 = S3_w_anode3056w[3];
R1_ram_block2a17_clock_enable_1 = GND;
R1_ram_block2a17_PORT_A_data_out = MEMORY(R1_ram_block2a17_PORT_A_data_in_reg, R1_ram_block2a17_PORT_B_data_in_reg, R1_ram_block2a17_PORT_A_address_reg, R1_ram_block2a17_PORT_B_address_reg, R1_ram_block2a17_PORT_A_write_enable_reg, R1_ram_block2a17_PORT_B_write_enable_reg, , , R1_ram_block2a17_clock_0, R1_ram_block2a17_clock_1, R1_ram_block2a17_clock_enable_0, R1_ram_block2a17_clock_enable_1, , );
R1_ram_block2a17_PORT_A_data_out_reg = DFFE(R1_ram_block2a17_PORT_A_data_out, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1M893Q = R1_ram_block2a17_PORT_A_data_out_reg[2];

--R1M894Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT3
R1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a17_PORT_A_data_in_reg = DFFE(R1_ram_block2a17_PORT_A_data_in, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_data_in = ~GND;
R1_ram_block2a17_PORT_B_data_in_reg = DFFE(R1_ram_block2a17_PORT_B_data_in, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a17_PORT_A_address_reg = DFFE(R1_ram_block2a17_PORT_A_address, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a17_PORT_B_address_reg = DFFE(R1_ram_block2a17_PORT_B_address, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_write_enable = GND;
R1_ram_block2a17_PORT_A_write_enable_reg = DFFE(R1_ram_block2a17_PORT_A_write_enable, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_write_enable = GND;
R1_ram_block2a17_PORT_B_write_enable_reg = DFFE(R1_ram_block2a17_PORT_B_write_enable, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_clock_0 = M1__clk0;
R1_ram_block2a17_clock_1 = GND;
R1_ram_block2a17_clock_enable_0 = S3_w_anode3056w[3];
R1_ram_block2a17_clock_enable_1 = GND;
R1_ram_block2a17_PORT_A_data_out = MEMORY(R1_ram_block2a17_PORT_A_data_in_reg, R1_ram_block2a17_PORT_B_data_in_reg, R1_ram_block2a17_PORT_A_address_reg, R1_ram_block2a17_PORT_B_address_reg, R1_ram_block2a17_PORT_A_write_enable_reg, R1_ram_block2a17_PORT_B_write_enable_reg, , , R1_ram_block2a17_clock_0, R1_ram_block2a17_clock_1, R1_ram_block2a17_clock_enable_0, R1_ram_block2a17_clock_enable_1, , );
R1_ram_block2a17_PORT_A_data_out_reg = DFFE(R1_ram_block2a17_PORT_A_data_out, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1M894Q = R1_ram_block2a17_PORT_A_data_out_reg[3];

--R1M895Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT4
R1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a17_PORT_A_data_in_reg = DFFE(R1_ram_block2a17_PORT_A_data_in, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_data_in = ~GND;
R1_ram_block2a17_PORT_B_data_in_reg = DFFE(R1_ram_block2a17_PORT_B_data_in, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a17_PORT_A_address_reg = DFFE(R1_ram_block2a17_PORT_A_address, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a17_PORT_B_address_reg = DFFE(R1_ram_block2a17_PORT_B_address, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_write_enable = GND;
R1_ram_block2a17_PORT_A_write_enable_reg = DFFE(R1_ram_block2a17_PORT_A_write_enable, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_write_enable = GND;
R1_ram_block2a17_PORT_B_write_enable_reg = DFFE(R1_ram_block2a17_PORT_B_write_enable, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_clock_0 = M1__clk0;
R1_ram_block2a17_clock_1 = GND;
R1_ram_block2a17_clock_enable_0 = S3_w_anode3056w[3];
R1_ram_block2a17_clock_enable_1 = GND;
R1_ram_block2a17_PORT_A_data_out = MEMORY(R1_ram_block2a17_PORT_A_data_in_reg, R1_ram_block2a17_PORT_B_data_in_reg, R1_ram_block2a17_PORT_A_address_reg, R1_ram_block2a17_PORT_B_address_reg, R1_ram_block2a17_PORT_A_write_enable_reg, R1_ram_block2a17_PORT_B_write_enable_reg, , , R1_ram_block2a17_clock_0, R1_ram_block2a17_clock_1, R1_ram_block2a17_clock_enable_0, R1_ram_block2a17_clock_enable_1, , );
R1_ram_block2a17_PORT_A_data_out_reg = DFFE(R1_ram_block2a17_PORT_A_data_out, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1M895Q = R1_ram_block2a17_PORT_A_data_out_reg[4];

--R1M896Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT5
R1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a17_PORT_A_data_in_reg = DFFE(R1_ram_block2a17_PORT_A_data_in, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_data_in = ~GND;
R1_ram_block2a17_PORT_B_data_in_reg = DFFE(R1_ram_block2a17_PORT_B_data_in, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a17_PORT_A_address_reg = DFFE(R1_ram_block2a17_PORT_A_address, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a17_PORT_B_address_reg = DFFE(R1_ram_block2a17_PORT_B_address, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_write_enable = GND;
R1_ram_block2a17_PORT_A_write_enable_reg = DFFE(R1_ram_block2a17_PORT_A_write_enable, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_write_enable = GND;
R1_ram_block2a17_PORT_B_write_enable_reg = DFFE(R1_ram_block2a17_PORT_B_write_enable, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_clock_0 = M1__clk0;
R1_ram_block2a17_clock_1 = GND;
R1_ram_block2a17_clock_enable_0 = S3_w_anode3056w[3];
R1_ram_block2a17_clock_enable_1 = GND;
R1_ram_block2a17_PORT_A_data_out = MEMORY(R1_ram_block2a17_PORT_A_data_in_reg, R1_ram_block2a17_PORT_B_data_in_reg, R1_ram_block2a17_PORT_A_address_reg, R1_ram_block2a17_PORT_B_address_reg, R1_ram_block2a17_PORT_A_write_enable_reg, R1_ram_block2a17_PORT_B_write_enable_reg, , , R1_ram_block2a17_clock_0, R1_ram_block2a17_clock_1, R1_ram_block2a17_clock_enable_0, R1_ram_block2a17_clock_enable_1, , );
R1_ram_block2a17_PORT_A_data_out_reg = DFFE(R1_ram_block2a17_PORT_A_data_out, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1M896Q = R1_ram_block2a17_PORT_A_data_out_reg[5];

--R1M897Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT6
R1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a17_PORT_A_data_in_reg = DFFE(R1_ram_block2a17_PORT_A_data_in, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_data_in = ~GND;
R1_ram_block2a17_PORT_B_data_in_reg = DFFE(R1_ram_block2a17_PORT_B_data_in, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a17_PORT_A_address_reg = DFFE(R1_ram_block2a17_PORT_A_address, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a17_PORT_B_address_reg = DFFE(R1_ram_block2a17_PORT_B_address, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_write_enable = GND;
R1_ram_block2a17_PORT_A_write_enable_reg = DFFE(R1_ram_block2a17_PORT_A_write_enable, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_write_enable = GND;
R1_ram_block2a17_PORT_B_write_enable_reg = DFFE(R1_ram_block2a17_PORT_B_write_enable, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_clock_0 = M1__clk0;
R1_ram_block2a17_clock_1 = GND;
R1_ram_block2a17_clock_enable_0 = S3_w_anode3056w[3];
R1_ram_block2a17_clock_enable_1 = GND;
R1_ram_block2a17_PORT_A_data_out = MEMORY(R1_ram_block2a17_PORT_A_data_in_reg, R1_ram_block2a17_PORT_B_data_in_reg, R1_ram_block2a17_PORT_A_address_reg, R1_ram_block2a17_PORT_B_address_reg, R1_ram_block2a17_PORT_A_write_enable_reg, R1_ram_block2a17_PORT_B_write_enable_reg, , , R1_ram_block2a17_clock_0, R1_ram_block2a17_clock_1, R1_ram_block2a17_clock_enable_0, R1_ram_block2a17_clock_enable_1, , );
R1_ram_block2a17_PORT_A_data_out_reg = DFFE(R1_ram_block2a17_PORT_A_data_out, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1M897Q = R1_ram_block2a17_PORT_A_data_out_reg[6];

--R1M898Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT7
R1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a17_PORT_A_data_in_reg = DFFE(R1_ram_block2a17_PORT_A_data_in, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_data_in = ~GND;
R1_ram_block2a17_PORT_B_data_in_reg = DFFE(R1_ram_block2a17_PORT_B_data_in, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a17_PORT_A_address_reg = DFFE(R1_ram_block2a17_PORT_A_address, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a17_PORT_B_address_reg = DFFE(R1_ram_block2a17_PORT_B_address, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_write_enable = GND;
R1_ram_block2a17_PORT_A_write_enable_reg = DFFE(R1_ram_block2a17_PORT_A_write_enable, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_write_enable = GND;
R1_ram_block2a17_PORT_B_write_enable_reg = DFFE(R1_ram_block2a17_PORT_B_write_enable, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_clock_0 = M1__clk0;
R1_ram_block2a17_clock_1 = GND;
R1_ram_block2a17_clock_enable_0 = S3_w_anode3056w[3];
R1_ram_block2a17_clock_enable_1 = GND;
R1_ram_block2a17_PORT_A_data_out = MEMORY(R1_ram_block2a17_PORT_A_data_in_reg, R1_ram_block2a17_PORT_B_data_in_reg, R1_ram_block2a17_PORT_A_address_reg, R1_ram_block2a17_PORT_B_address_reg, R1_ram_block2a17_PORT_A_write_enable_reg, R1_ram_block2a17_PORT_B_write_enable_reg, , , R1_ram_block2a17_clock_0, R1_ram_block2a17_clock_1, R1_ram_block2a17_clock_enable_0, R1_ram_block2a17_clock_enable_1, , );
R1_ram_block2a17_PORT_A_data_out_reg = DFFE(R1_ram_block2a17_PORT_A_data_out, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1M898Q = R1_ram_block2a17_PORT_A_data_out_reg[7];


--R1_ram_block2a18 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a18_PORT_A_data_in_reg = DFFE(R1_ram_block2a18_PORT_A_data_in, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_data_in = ~GND;
R1_ram_block2a18_PORT_B_data_in_reg = DFFE(R1_ram_block2a18_PORT_B_data_in, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a18_PORT_A_address_reg = DFFE(R1_ram_block2a18_PORT_A_address, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a18_PORT_B_address_reg = DFFE(R1_ram_block2a18_PORT_B_address, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_write_enable = GND;
R1_ram_block2a18_PORT_A_write_enable_reg = DFFE(R1_ram_block2a18_PORT_A_write_enable, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_write_enable = GND;
R1_ram_block2a18_PORT_B_write_enable_reg = DFFE(R1_ram_block2a18_PORT_B_write_enable, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_clock_0 = M1__clk0;
R1_ram_block2a18_clock_1 = GND;
R1_ram_block2a18_clock_enable_0 = S3_w_anode3066w[3];
R1_ram_block2a18_clock_enable_1 = GND;
R1_ram_block2a18_PORT_A_data_out = MEMORY(R1_ram_block2a18_PORT_A_data_in_reg, R1_ram_block2a18_PORT_B_data_in_reg, R1_ram_block2a18_PORT_A_address_reg, R1_ram_block2a18_PORT_B_address_reg, R1_ram_block2a18_PORT_A_write_enable_reg, R1_ram_block2a18_PORT_B_write_enable_reg, , , R1_ram_block2a18_clock_0, R1_ram_block2a18_clock_1, R1_ram_block2a18_clock_enable_0, R1_ram_block2a18_clock_enable_1, , );
R1_ram_block2a18_PORT_A_data_out_reg = DFFE(R1_ram_block2a18_PORT_A_data_out, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18 = R1_ram_block2a18_PORT_A_data_out_reg[0];

--R1M942Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT1
R1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a18_PORT_A_data_in_reg = DFFE(R1_ram_block2a18_PORT_A_data_in, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_data_in = ~GND;
R1_ram_block2a18_PORT_B_data_in_reg = DFFE(R1_ram_block2a18_PORT_B_data_in, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a18_PORT_A_address_reg = DFFE(R1_ram_block2a18_PORT_A_address, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a18_PORT_B_address_reg = DFFE(R1_ram_block2a18_PORT_B_address, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_write_enable = GND;
R1_ram_block2a18_PORT_A_write_enable_reg = DFFE(R1_ram_block2a18_PORT_A_write_enable, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_write_enable = GND;
R1_ram_block2a18_PORT_B_write_enable_reg = DFFE(R1_ram_block2a18_PORT_B_write_enable, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_clock_0 = M1__clk0;
R1_ram_block2a18_clock_1 = GND;
R1_ram_block2a18_clock_enable_0 = S3_w_anode3066w[3];
R1_ram_block2a18_clock_enable_1 = GND;
R1_ram_block2a18_PORT_A_data_out = MEMORY(R1_ram_block2a18_PORT_A_data_in_reg, R1_ram_block2a18_PORT_B_data_in_reg, R1_ram_block2a18_PORT_A_address_reg, R1_ram_block2a18_PORT_B_address_reg, R1_ram_block2a18_PORT_A_write_enable_reg, R1_ram_block2a18_PORT_B_write_enable_reg, , , R1_ram_block2a18_clock_0, R1_ram_block2a18_clock_1, R1_ram_block2a18_clock_enable_0, R1_ram_block2a18_clock_enable_1, , );
R1_ram_block2a18_PORT_A_data_out_reg = DFFE(R1_ram_block2a18_PORT_A_data_out, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1M942Q = R1_ram_block2a18_PORT_A_data_out_reg[1];

--R1M943Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT2
R1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a18_PORT_A_data_in_reg = DFFE(R1_ram_block2a18_PORT_A_data_in, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_data_in = ~GND;
R1_ram_block2a18_PORT_B_data_in_reg = DFFE(R1_ram_block2a18_PORT_B_data_in, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a18_PORT_A_address_reg = DFFE(R1_ram_block2a18_PORT_A_address, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a18_PORT_B_address_reg = DFFE(R1_ram_block2a18_PORT_B_address, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_write_enable = GND;
R1_ram_block2a18_PORT_A_write_enable_reg = DFFE(R1_ram_block2a18_PORT_A_write_enable, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_write_enable = GND;
R1_ram_block2a18_PORT_B_write_enable_reg = DFFE(R1_ram_block2a18_PORT_B_write_enable, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_clock_0 = M1__clk0;
R1_ram_block2a18_clock_1 = GND;
R1_ram_block2a18_clock_enable_0 = S3_w_anode3066w[3];
R1_ram_block2a18_clock_enable_1 = GND;
R1_ram_block2a18_PORT_A_data_out = MEMORY(R1_ram_block2a18_PORT_A_data_in_reg, R1_ram_block2a18_PORT_B_data_in_reg, R1_ram_block2a18_PORT_A_address_reg, R1_ram_block2a18_PORT_B_address_reg, R1_ram_block2a18_PORT_A_write_enable_reg, R1_ram_block2a18_PORT_B_write_enable_reg, , , R1_ram_block2a18_clock_0, R1_ram_block2a18_clock_1, R1_ram_block2a18_clock_enable_0, R1_ram_block2a18_clock_enable_1, , );
R1_ram_block2a18_PORT_A_data_out_reg = DFFE(R1_ram_block2a18_PORT_A_data_out, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1M943Q = R1_ram_block2a18_PORT_A_data_out_reg[2];

--R1M944Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT3
R1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a18_PORT_A_data_in_reg = DFFE(R1_ram_block2a18_PORT_A_data_in, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_data_in = ~GND;
R1_ram_block2a18_PORT_B_data_in_reg = DFFE(R1_ram_block2a18_PORT_B_data_in, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a18_PORT_A_address_reg = DFFE(R1_ram_block2a18_PORT_A_address, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a18_PORT_B_address_reg = DFFE(R1_ram_block2a18_PORT_B_address, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_write_enable = GND;
R1_ram_block2a18_PORT_A_write_enable_reg = DFFE(R1_ram_block2a18_PORT_A_write_enable, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_write_enable = GND;
R1_ram_block2a18_PORT_B_write_enable_reg = DFFE(R1_ram_block2a18_PORT_B_write_enable, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_clock_0 = M1__clk0;
R1_ram_block2a18_clock_1 = GND;
R1_ram_block2a18_clock_enable_0 = S3_w_anode3066w[3];
R1_ram_block2a18_clock_enable_1 = GND;
R1_ram_block2a18_PORT_A_data_out = MEMORY(R1_ram_block2a18_PORT_A_data_in_reg, R1_ram_block2a18_PORT_B_data_in_reg, R1_ram_block2a18_PORT_A_address_reg, R1_ram_block2a18_PORT_B_address_reg, R1_ram_block2a18_PORT_A_write_enable_reg, R1_ram_block2a18_PORT_B_write_enable_reg, , , R1_ram_block2a18_clock_0, R1_ram_block2a18_clock_1, R1_ram_block2a18_clock_enable_0, R1_ram_block2a18_clock_enable_1, , );
R1_ram_block2a18_PORT_A_data_out_reg = DFFE(R1_ram_block2a18_PORT_A_data_out, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1M944Q = R1_ram_block2a18_PORT_A_data_out_reg[3];

--R1M945Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT4
R1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a18_PORT_A_data_in_reg = DFFE(R1_ram_block2a18_PORT_A_data_in, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_data_in = ~GND;
R1_ram_block2a18_PORT_B_data_in_reg = DFFE(R1_ram_block2a18_PORT_B_data_in, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a18_PORT_A_address_reg = DFFE(R1_ram_block2a18_PORT_A_address, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a18_PORT_B_address_reg = DFFE(R1_ram_block2a18_PORT_B_address, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_write_enable = GND;
R1_ram_block2a18_PORT_A_write_enable_reg = DFFE(R1_ram_block2a18_PORT_A_write_enable, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_write_enable = GND;
R1_ram_block2a18_PORT_B_write_enable_reg = DFFE(R1_ram_block2a18_PORT_B_write_enable, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_clock_0 = M1__clk0;
R1_ram_block2a18_clock_1 = GND;
R1_ram_block2a18_clock_enable_0 = S3_w_anode3066w[3];
R1_ram_block2a18_clock_enable_1 = GND;
R1_ram_block2a18_PORT_A_data_out = MEMORY(R1_ram_block2a18_PORT_A_data_in_reg, R1_ram_block2a18_PORT_B_data_in_reg, R1_ram_block2a18_PORT_A_address_reg, R1_ram_block2a18_PORT_B_address_reg, R1_ram_block2a18_PORT_A_write_enable_reg, R1_ram_block2a18_PORT_B_write_enable_reg, , , R1_ram_block2a18_clock_0, R1_ram_block2a18_clock_1, R1_ram_block2a18_clock_enable_0, R1_ram_block2a18_clock_enable_1, , );
R1_ram_block2a18_PORT_A_data_out_reg = DFFE(R1_ram_block2a18_PORT_A_data_out, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1M945Q = R1_ram_block2a18_PORT_A_data_out_reg[4];

--R1M946Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT5
R1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a18_PORT_A_data_in_reg = DFFE(R1_ram_block2a18_PORT_A_data_in, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_data_in = ~GND;
R1_ram_block2a18_PORT_B_data_in_reg = DFFE(R1_ram_block2a18_PORT_B_data_in, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a18_PORT_A_address_reg = DFFE(R1_ram_block2a18_PORT_A_address, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a18_PORT_B_address_reg = DFFE(R1_ram_block2a18_PORT_B_address, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_write_enable = GND;
R1_ram_block2a18_PORT_A_write_enable_reg = DFFE(R1_ram_block2a18_PORT_A_write_enable, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_write_enable = GND;
R1_ram_block2a18_PORT_B_write_enable_reg = DFFE(R1_ram_block2a18_PORT_B_write_enable, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_clock_0 = M1__clk0;
R1_ram_block2a18_clock_1 = GND;
R1_ram_block2a18_clock_enable_0 = S3_w_anode3066w[3];
R1_ram_block2a18_clock_enable_1 = GND;
R1_ram_block2a18_PORT_A_data_out = MEMORY(R1_ram_block2a18_PORT_A_data_in_reg, R1_ram_block2a18_PORT_B_data_in_reg, R1_ram_block2a18_PORT_A_address_reg, R1_ram_block2a18_PORT_B_address_reg, R1_ram_block2a18_PORT_A_write_enable_reg, R1_ram_block2a18_PORT_B_write_enable_reg, , , R1_ram_block2a18_clock_0, R1_ram_block2a18_clock_1, R1_ram_block2a18_clock_enable_0, R1_ram_block2a18_clock_enable_1, , );
R1_ram_block2a18_PORT_A_data_out_reg = DFFE(R1_ram_block2a18_PORT_A_data_out, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1M946Q = R1_ram_block2a18_PORT_A_data_out_reg[5];

--R1M947Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT6
R1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a18_PORT_A_data_in_reg = DFFE(R1_ram_block2a18_PORT_A_data_in, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_data_in = ~GND;
R1_ram_block2a18_PORT_B_data_in_reg = DFFE(R1_ram_block2a18_PORT_B_data_in, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a18_PORT_A_address_reg = DFFE(R1_ram_block2a18_PORT_A_address, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a18_PORT_B_address_reg = DFFE(R1_ram_block2a18_PORT_B_address, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_write_enable = GND;
R1_ram_block2a18_PORT_A_write_enable_reg = DFFE(R1_ram_block2a18_PORT_A_write_enable, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_write_enable = GND;
R1_ram_block2a18_PORT_B_write_enable_reg = DFFE(R1_ram_block2a18_PORT_B_write_enable, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_clock_0 = M1__clk0;
R1_ram_block2a18_clock_1 = GND;
R1_ram_block2a18_clock_enable_0 = S3_w_anode3066w[3];
R1_ram_block2a18_clock_enable_1 = GND;
R1_ram_block2a18_PORT_A_data_out = MEMORY(R1_ram_block2a18_PORT_A_data_in_reg, R1_ram_block2a18_PORT_B_data_in_reg, R1_ram_block2a18_PORT_A_address_reg, R1_ram_block2a18_PORT_B_address_reg, R1_ram_block2a18_PORT_A_write_enable_reg, R1_ram_block2a18_PORT_B_write_enable_reg, , , R1_ram_block2a18_clock_0, R1_ram_block2a18_clock_1, R1_ram_block2a18_clock_enable_0, R1_ram_block2a18_clock_enable_1, , );
R1_ram_block2a18_PORT_A_data_out_reg = DFFE(R1_ram_block2a18_PORT_A_data_out, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1M947Q = R1_ram_block2a18_PORT_A_data_out_reg[6];

--R1M948Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT7
R1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a18_PORT_A_data_in_reg = DFFE(R1_ram_block2a18_PORT_A_data_in, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_data_in = ~GND;
R1_ram_block2a18_PORT_B_data_in_reg = DFFE(R1_ram_block2a18_PORT_B_data_in, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a18_PORT_A_address_reg = DFFE(R1_ram_block2a18_PORT_A_address, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a18_PORT_B_address_reg = DFFE(R1_ram_block2a18_PORT_B_address, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_write_enable = GND;
R1_ram_block2a18_PORT_A_write_enable_reg = DFFE(R1_ram_block2a18_PORT_A_write_enable, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_write_enable = GND;
R1_ram_block2a18_PORT_B_write_enable_reg = DFFE(R1_ram_block2a18_PORT_B_write_enable, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_clock_0 = M1__clk0;
R1_ram_block2a18_clock_1 = GND;
R1_ram_block2a18_clock_enable_0 = S3_w_anode3066w[3];
R1_ram_block2a18_clock_enable_1 = GND;
R1_ram_block2a18_PORT_A_data_out = MEMORY(R1_ram_block2a18_PORT_A_data_in_reg, R1_ram_block2a18_PORT_B_data_in_reg, R1_ram_block2a18_PORT_A_address_reg, R1_ram_block2a18_PORT_B_address_reg, R1_ram_block2a18_PORT_A_write_enable_reg, R1_ram_block2a18_PORT_B_write_enable_reg, , , R1_ram_block2a18_clock_0, R1_ram_block2a18_clock_1, R1_ram_block2a18_clock_enable_0, R1_ram_block2a18_clock_enable_1, , );
R1_ram_block2a18_PORT_A_data_out_reg = DFFE(R1_ram_block2a18_PORT_A_data_out, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1M948Q = R1_ram_block2a18_PORT_A_data_out_reg[7];


--R1_ram_block2a16 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a16_PORT_A_data_in_reg = DFFE(R1_ram_block2a16_PORT_A_data_in, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_data_in = ~GND;
R1_ram_block2a16_PORT_B_data_in_reg = DFFE(R1_ram_block2a16_PORT_B_data_in, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a16_PORT_A_address_reg = DFFE(R1_ram_block2a16_PORT_A_address, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a16_PORT_B_address_reg = DFFE(R1_ram_block2a16_PORT_B_address, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_write_enable = GND;
R1_ram_block2a16_PORT_A_write_enable_reg = DFFE(R1_ram_block2a16_PORT_A_write_enable, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_write_enable = GND;
R1_ram_block2a16_PORT_B_write_enable_reg = DFFE(R1_ram_block2a16_PORT_B_write_enable, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_clock_0 = M1__clk0;
R1_ram_block2a16_clock_1 = GND;
R1_ram_block2a16_clock_enable_0 = S3_w_anode3045w[3];
R1_ram_block2a16_clock_enable_1 = GND;
R1_ram_block2a16_PORT_A_data_out = MEMORY(R1_ram_block2a16_PORT_A_data_in_reg, R1_ram_block2a16_PORT_B_data_in_reg, R1_ram_block2a16_PORT_A_address_reg, R1_ram_block2a16_PORT_B_address_reg, R1_ram_block2a16_PORT_A_write_enable_reg, R1_ram_block2a16_PORT_B_write_enable_reg, , , R1_ram_block2a16_clock_0, R1_ram_block2a16_clock_1, R1_ram_block2a16_clock_enable_0, R1_ram_block2a16_clock_enable_1, , );
R1_ram_block2a16_PORT_A_data_out_reg = DFFE(R1_ram_block2a16_PORT_A_data_out, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16 = R1_ram_block2a16_PORT_A_data_out_reg[0];

--R1M842Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT1
R1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a16_PORT_A_data_in_reg = DFFE(R1_ram_block2a16_PORT_A_data_in, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_data_in = ~GND;
R1_ram_block2a16_PORT_B_data_in_reg = DFFE(R1_ram_block2a16_PORT_B_data_in, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a16_PORT_A_address_reg = DFFE(R1_ram_block2a16_PORT_A_address, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a16_PORT_B_address_reg = DFFE(R1_ram_block2a16_PORT_B_address, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_write_enable = GND;
R1_ram_block2a16_PORT_A_write_enable_reg = DFFE(R1_ram_block2a16_PORT_A_write_enable, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_write_enable = GND;
R1_ram_block2a16_PORT_B_write_enable_reg = DFFE(R1_ram_block2a16_PORT_B_write_enable, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_clock_0 = M1__clk0;
R1_ram_block2a16_clock_1 = GND;
R1_ram_block2a16_clock_enable_0 = S3_w_anode3045w[3];
R1_ram_block2a16_clock_enable_1 = GND;
R1_ram_block2a16_PORT_A_data_out = MEMORY(R1_ram_block2a16_PORT_A_data_in_reg, R1_ram_block2a16_PORT_B_data_in_reg, R1_ram_block2a16_PORT_A_address_reg, R1_ram_block2a16_PORT_B_address_reg, R1_ram_block2a16_PORT_A_write_enable_reg, R1_ram_block2a16_PORT_B_write_enable_reg, , , R1_ram_block2a16_clock_0, R1_ram_block2a16_clock_1, R1_ram_block2a16_clock_enable_0, R1_ram_block2a16_clock_enable_1, , );
R1_ram_block2a16_PORT_A_data_out_reg = DFFE(R1_ram_block2a16_PORT_A_data_out, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1M842Q = R1_ram_block2a16_PORT_A_data_out_reg[1];

--R1M843Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT2
R1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a16_PORT_A_data_in_reg = DFFE(R1_ram_block2a16_PORT_A_data_in, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_data_in = ~GND;
R1_ram_block2a16_PORT_B_data_in_reg = DFFE(R1_ram_block2a16_PORT_B_data_in, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a16_PORT_A_address_reg = DFFE(R1_ram_block2a16_PORT_A_address, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a16_PORT_B_address_reg = DFFE(R1_ram_block2a16_PORT_B_address, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_write_enable = GND;
R1_ram_block2a16_PORT_A_write_enable_reg = DFFE(R1_ram_block2a16_PORT_A_write_enable, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_write_enable = GND;
R1_ram_block2a16_PORT_B_write_enable_reg = DFFE(R1_ram_block2a16_PORT_B_write_enable, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_clock_0 = M1__clk0;
R1_ram_block2a16_clock_1 = GND;
R1_ram_block2a16_clock_enable_0 = S3_w_anode3045w[3];
R1_ram_block2a16_clock_enable_1 = GND;
R1_ram_block2a16_PORT_A_data_out = MEMORY(R1_ram_block2a16_PORT_A_data_in_reg, R1_ram_block2a16_PORT_B_data_in_reg, R1_ram_block2a16_PORT_A_address_reg, R1_ram_block2a16_PORT_B_address_reg, R1_ram_block2a16_PORT_A_write_enable_reg, R1_ram_block2a16_PORT_B_write_enable_reg, , , R1_ram_block2a16_clock_0, R1_ram_block2a16_clock_1, R1_ram_block2a16_clock_enable_0, R1_ram_block2a16_clock_enable_1, , );
R1_ram_block2a16_PORT_A_data_out_reg = DFFE(R1_ram_block2a16_PORT_A_data_out, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1M843Q = R1_ram_block2a16_PORT_A_data_out_reg[2];

--R1M844Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT3
R1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a16_PORT_A_data_in_reg = DFFE(R1_ram_block2a16_PORT_A_data_in, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_data_in = ~GND;
R1_ram_block2a16_PORT_B_data_in_reg = DFFE(R1_ram_block2a16_PORT_B_data_in, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a16_PORT_A_address_reg = DFFE(R1_ram_block2a16_PORT_A_address, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a16_PORT_B_address_reg = DFFE(R1_ram_block2a16_PORT_B_address, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_write_enable = GND;
R1_ram_block2a16_PORT_A_write_enable_reg = DFFE(R1_ram_block2a16_PORT_A_write_enable, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_write_enable = GND;
R1_ram_block2a16_PORT_B_write_enable_reg = DFFE(R1_ram_block2a16_PORT_B_write_enable, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_clock_0 = M1__clk0;
R1_ram_block2a16_clock_1 = GND;
R1_ram_block2a16_clock_enable_0 = S3_w_anode3045w[3];
R1_ram_block2a16_clock_enable_1 = GND;
R1_ram_block2a16_PORT_A_data_out = MEMORY(R1_ram_block2a16_PORT_A_data_in_reg, R1_ram_block2a16_PORT_B_data_in_reg, R1_ram_block2a16_PORT_A_address_reg, R1_ram_block2a16_PORT_B_address_reg, R1_ram_block2a16_PORT_A_write_enable_reg, R1_ram_block2a16_PORT_B_write_enable_reg, , , R1_ram_block2a16_clock_0, R1_ram_block2a16_clock_1, R1_ram_block2a16_clock_enable_0, R1_ram_block2a16_clock_enable_1, , );
R1_ram_block2a16_PORT_A_data_out_reg = DFFE(R1_ram_block2a16_PORT_A_data_out, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1M844Q = R1_ram_block2a16_PORT_A_data_out_reg[3];

--R1M845Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT4
R1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a16_PORT_A_data_in_reg = DFFE(R1_ram_block2a16_PORT_A_data_in, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_data_in = ~GND;
R1_ram_block2a16_PORT_B_data_in_reg = DFFE(R1_ram_block2a16_PORT_B_data_in, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a16_PORT_A_address_reg = DFFE(R1_ram_block2a16_PORT_A_address, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a16_PORT_B_address_reg = DFFE(R1_ram_block2a16_PORT_B_address, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_write_enable = GND;
R1_ram_block2a16_PORT_A_write_enable_reg = DFFE(R1_ram_block2a16_PORT_A_write_enable, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_write_enable = GND;
R1_ram_block2a16_PORT_B_write_enable_reg = DFFE(R1_ram_block2a16_PORT_B_write_enable, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_clock_0 = M1__clk0;
R1_ram_block2a16_clock_1 = GND;
R1_ram_block2a16_clock_enable_0 = S3_w_anode3045w[3];
R1_ram_block2a16_clock_enable_1 = GND;
R1_ram_block2a16_PORT_A_data_out = MEMORY(R1_ram_block2a16_PORT_A_data_in_reg, R1_ram_block2a16_PORT_B_data_in_reg, R1_ram_block2a16_PORT_A_address_reg, R1_ram_block2a16_PORT_B_address_reg, R1_ram_block2a16_PORT_A_write_enable_reg, R1_ram_block2a16_PORT_B_write_enable_reg, , , R1_ram_block2a16_clock_0, R1_ram_block2a16_clock_1, R1_ram_block2a16_clock_enable_0, R1_ram_block2a16_clock_enable_1, , );
R1_ram_block2a16_PORT_A_data_out_reg = DFFE(R1_ram_block2a16_PORT_A_data_out, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1M845Q = R1_ram_block2a16_PORT_A_data_out_reg[4];

--R1M846Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT5
R1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a16_PORT_A_data_in_reg = DFFE(R1_ram_block2a16_PORT_A_data_in, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_data_in = ~GND;
R1_ram_block2a16_PORT_B_data_in_reg = DFFE(R1_ram_block2a16_PORT_B_data_in, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a16_PORT_A_address_reg = DFFE(R1_ram_block2a16_PORT_A_address, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a16_PORT_B_address_reg = DFFE(R1_ram_block2a16_PORT_B_address, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_write_enable = GND;
R1_ram_block2a16_PORT_A_write_enable_reg = DFFE(R1_ram_block2a16_PORT_A_write_enable, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_write_enable = GND;
R1_ram_block2a16_PORT_B_write_enable_reg = DFFE(R1_ram_block2a16_PORT_B_write_enable, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_clock_0 = M1__clk0;
R1_ram_block2a16_clock_1 = GND;
R1_ram_block2a16_clock_enable_0 = S3_w_anode3045w[3];
R1_ram_block2a16_clock_enable_1 = GND;
R1_ram_block2a16_PORT_A_data_out = MEMORY(R1_ram_block2a16_PORT_A_data_in_reg, R1_ram_block2a16_PORT_B_data_in_reg, R1_ram_block2a16_PORT_A_address_reg, R1_ram_block2a16_PORT_B_address_reg, R1_ram_block2a16_PORT_A_write_enable_reg, R1_ram_block2a16_PORT_B_write_enable_reg, , , R1_ram_block2a16_clock_0, R1_ram_block2a16_clock_1, R1_ram_block2a16_clock_enable_0, R1_ram_block2a16_clock_enable_1, , );
R1_ram_block2a16_PORT_A_data_out_reg = DFFE(R1_ram_block2a16_PORT_A_data_out, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1M846Q = R1_ram_block2a16_PORT_A_data_out_reg[5];

--R1M847Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT6
R1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a16_PORT_A_data_in_reg = DFFE(R1_ram_block2a16_PORT_A_data_in, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_data_in = ~GND;
R1_ram_block2a16_PORT_B_data_in_reg = DFFE(R1_ram_block2a16_PORT_B_data_in, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a16_PORT_A_address_reg = DFFE(R1_ram_block2a16_PORT_A_address, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a16_PORT_B_address_reg = DFFE(R1_ram_block2a16_PORT_B_address, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_write_enable = GND;
R1_ram_block2a16_PORT_A_write_enable_reg = DFFE(R1_ram_block2a16_PORT_A_write_enable, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_write_enable = GND;
R1_ram_block2a16_PORT_B_write_enable_reg = DFFE(R1_ram_block2a16_PORT_B_write_enable, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_clock_0 = M1__clk0;
R1_ram_block2a16_clock_1 = GND;
R1_ram_block2a16_clock_enable_0 = S3_w_anode3045w[3];
R1_ram_block2a16_clock_enable_1 = GND;
R1_ram_block2a16_PORT_A_data_out = MEMORY(R1_ram_block2a16_PORT_A_data_in_reg, R1_ram_block2a16_PORT_B_data_in_reg, R1_ram_block2a16_PORT_A_address_reg, R1_ram_block2a16_PORT_B_address_reg, R1_ram_block2a16_PORT_A_write_enable_reg, R1_ram_block2a16_PORT_B_write_enable_reg, , , R1_ram_block2a16_clock_0, R1_ram_block2a16_clock_1, R1_ram_block2a16_clock_enable_0, R1_ram_block2a16_clock_enable_1, , );
R1_ram_block2a16_PORT_A_data_out_reg = DFFE(R1_ram_block2a16_PORT_A_data_out, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1M847Q = R1_ram_block2a16_PORT_A_data_out_reg[6];

--R1M848Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT7
R1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a16_PORT_A_data_in_reg = DFFE(R1_ram_block2a16_PORT_A_data_in, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_data_in = ~GND;
R1_ram_block2a16_PORT_B_data_in_reg = DFFE(R1_ram_block2a16_PORT_B_data_in, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a16_PORT_A_address_reg = DFFE(R1_ram_block2a16_PORT_A_address, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a16_PORT_B_address_reg = DFFE(R1_ram_block2a16_PORT_B_address, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_write_enable = GND;
R1_ram_block2a16_PORT_A_write_enable_reg = DFFE(R1_ram_block2a16_PORT_A_write_enable, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_write_enable = GND;
R1_ram_block2a16_PORT_B_write_enable_reg = DFFE(R1_ram_block2a16_PORT_B_write_enable, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_clock_0 = M1__clk0;
R1_ram_block2a16_clock_1 = GND;
R1_ram_block2a16_clock_enable_0 = S3_w_anode3045w[3];
R1_ram_block2a16_clock_enable_1 = GND;
R1_ram_block2a16_PORT_A_data_out = MEMORY(R1_ram_block2a16_PORT_A_data_in_reg, R1_ram_block2a16_PORT_B_data_in_reg, R1_ram_block2a16_PORT_A_address_reg, R1_ram_block2a16_PORT_B_address_reg, R1_ram_block2a16_PORT_A_write_enable_reg, R1_ram_block2a16_PORT_B_write_enable_reg, , , R1_ram_block2a16_clock_0, R1_ram_block2a16_clock_1, R1_ram_block2a16_clock_enable_0, R1_ram_block2a16_clock_enable_1, , );
R1_ram_block2a16_PORT_A_data_out_reg = DFFE(R1_ram_block2a16_PORT_A_data_out, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1M848Q = R1_ram_block2a16_PORT_A_data_out_reg[7];


--T1L224 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6575w~407
T1L224 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M946Q # !R1_address_reg_a[7] & (R1M846Q));


--R1_ram_block2a19 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a19_PORT_A_data_in_reg = DFFE(R1_ram_block2a19_PORT_A_data_in, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_data_in = ~GND;
R1_ram_block2a19_PORT_B_data_in_reg = DFFE(R1_ram_block2a19_PORT_B_data_in, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a19_PORT_A_address_reg = DFFE(R1_ram_block2a19_PORT_A_address, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a19_PORT_B_address_reg = DFFE(R1_ram_block2a19_PORT_B_address, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_write_enable = GND;
R1_ram_block2a19_PORT_A_write_enable_reg = DFFE(R1_ram_block2a19_PORT_A_write_enable, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_write_enable = GND;
R1_ram_block2a19_PORT_B_write_enable_reg = DFFE(R1_ram_block2a19_PORT_B_write_enable, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_clock_0 = M1__clk0;
R1_ram_block2a19_clock_1 = GND;
R1_ram_block2a19_clock_enable_0 = S3_w_anode3076w[3];
R1_ram_block2a19_clock_enable_1 = GND;
R1_ram_block2a19_PORT_A_data_out = MEMORY(R1_ram_block2a19_PORT_A_data_in_reg, R1_ram_block2a19_PORT_B_data_in_reg, R1_ram_block2a19_PORT_A_address_reg, R1_ram_block2a19_PORT_B_address_reg, R1_ram_block2a19_PORT_A_write_enable_reg, R1_ram_block2a19_PORT_B_write_enable_reg, , , R1_ram_block2a19_clock_0, R1_ram_block2a19_clock_1, R1_ram_block2a19_clock_enable_0, R1_ram_block2a19_clock_enable_1, , );
R1_ram_block2a19_PORT_A_data_out_reg = DFFE(R1_ram_block2a19_PORT_A_data_out, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19 = R1_ram_block2a19_PORT_A_data_out_reg[0];

--R1M992Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT1
R1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a19_PORT_A_data_in_reg = DFFE(R1_ram_block2a19_PORT_A_data_in, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_data_in = ~GND;
R1_ram_block2a19_PORT_B_data_in_reg = DFFE(R1_ram_block2a19_PORT_B_data_in, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a19_PORT_A_address_reg = DFFE(R1_ram_block2a19_PORT_A_address, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a19_PORT_B_address_reg = DFFE(R1_ram_block2a19_PORT_B_address, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_write_enable = GND;
R1_ram_block2a19_PORT_A_write_enable_reg = DFFE(R1_ram_block2a19_PORT_A_write_enable, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_write_enable = GND;
R1_ram_block2a19_PORT_B_write_enable_reg = DFFE(R1_ram_block2a19_PORT_B_write_enable, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_clock_0 = M1__clk0;
R1_ram_block2a19_clock_1 = GND;
R1_ram_block2a19_clock_enable_0 = S3_w_anode3076w[3];
R1_ram_block2a19_clock_enable_1 = GND;
R1_ram_block2a19_PORT_A_data_out = MEMORY(R1_ram_block2a19_PORT_A_data_in_reg, R1_ram_block2a19_PORT_B_data_in_reg, R1_ram_block2a19_PORT_A_address_reg, R1_ram_block2a19_PORT_B_address_reg, R1_ram_block2a19_PORT_A_write_enable_reg, R1_ram_block2a19_PORT_B_write_enable_reg, , , R1_ram_block2a19_clock_0, R1_ram_block2a19_clock_1, R1_ram_block2a19_clock_enable_0, R1_ram_block2a19_clock_enable_1, , );
R1_ram_block2a19_PORT_A_data_out_reg = DFFE(R1_ram_block2a19_PORT_A_data_out, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1M992Q = R1_ram_block2a19_PORT_A_data_out_reg[1];

--R1M993Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT2
R1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a19_PORT_A_data_in_reg = DFFE(R1_ram_block2a19_PORT_A_data_in, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_data_in = ~GND;
R1_ram_block2a19_PORT_B_data_in_reg = DFFE(R1_ram_block2a19_PORT_B_data_in, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a19_PORT_A_address_reg = DFFE(R1_ram_block2a19_PORT_A_address, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a19_PORT_B_address_reg = DFFE(R1_ram_block2a19_PORT_B_address, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_write_enable = GND;
R1_ram_block2a19_PORT_A_write_enable_reg = DFFE(R1_ram_block2a19_PORT_A_write_enable, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_write_enable = GND;
R1_ram_block2a19_PORT_B_write_enable_reg = DFFE(R1_ram_block2a19_PORT_B_write_enable, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_clock_0 = M1__clk0;
R1_ram_block2a19_clock_1 = GND;
R1_ram_block2a19_clock_enable_0 = S3_w_anode3076w[3];
R1_ram_block2a19_clock_enable_1 = GND;
R1_ram_block2a19_PORT_A_data_out = MEMORY(R1_ram_block2a19_PORT_A_data_in_reg, R1_ram_block2a19_PORT_B_data_in_reg, R1_ram_block2a19_PORT_A_address_reg, R1_ram_block2a19_PORT_B_address_reg, R1_ram_block2a19_PORT_A_write_enable_reg, R1_ram_block2a19_PORT_B_write_enable_reg, , , R1_ram_block2a19_clock_0, R1_ram_block2a19_clock_1, R1_ram_block2a19_clock_enable_0, R1_ram_block2a19_clock_enable_1, , );
R1_ram_block2a19_PORT_A_data_out_reg = DFFE(R1_ram_block2a19_PORT_A_data_out, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1M993Q = R1_ram_block2a19_PORT_A_data_out_reg[2];

--R1M994Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT3
R1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a19_PORT_A_data_in_reg = DFFE(R1_ram_block2a19_PORT_A_data_in, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_data_in = ~GND;
R1_ram_block2a19_PORT_B_data_in_reg = DFFE(R1_ram_block2a19_PORT_B_data_in, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a19_PORT_A_address_reg = DFFE(R1_ram_block2a19_PORT_A_address, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a19_PORT_B_address_reg = DFFE(R1_ram_block2a19_PORT_B_address, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_write_enable = GND;
R1_ram_block2a19_PORT_A_write_enable_reg = DFFE(R1_ram_block2a19_PORT_A_write_enable, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_write_enable = GND;
R1_ram_block2a19_PORT_B_write_enable_reg = DFFE(R1_ram_block2a19_PORT_B_write_enable, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_clock_0 = M1__clk0;
R1_ram_block2a19_clock_1 = GND;
R1_ram_block2a19_clock_enable_0 = S3_w_anode3076w[3];
R1_ram_block2a19_clock_enable_1 = GND;
R1_ram_block2a19_PORT_A_data_out = MEMORY(R1_ram_block2a19_PORT_A_data_in_reg, R1_ram_block2a19_PORT_B_data_in_reg, R1_ram_block2a19_PORT_A_address_reg, R1_ram_block2a19_PORT_B_address_reg, R1_ram_block2a19_PORT_A_write_enable_reg, R1_ram_block2a19_PORT_B_write_enable_reg, , , R1_ram_block2a19_clock_0, R1_ram_block2a19_clock_1, R1_ram_block2a19_clock_enable_0, R1_ram_block2a19_clock_enable_1, , );
R1_ram_block2a19_PORT_A_data_out_reg = DFFE(R1_ram_block2a19_PORT_A_data_out, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1M994Q = R1_ram_block2a19_PORT_A_data_out_reg[3];

--R1M995Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT4
R1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a19_PORT_A_data_in_reg = DFFE(R1_ram_block2a19_PORT_A_data_in, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_data_in = ~GND;
R1_ram_block2a19_PORT_B_data_in_reg = DFFE(R1_ram_block2a19_PORT_B_data_in, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a19_PORT_A_address_reg = DFFE(R1_ram_block2a19_PORT_A_address, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a19_PORT_B_address_reg = DFFE(R1_ram_block2a19_PORT_B_address, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_write_enable = GND;
R1_ram_block2a19_PORT_A_write_enable_reg = DFFE(R1_ram_block2a19_PORT_A_write_enable, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_write_enable = GND;
R1_ram_block2a19_PORT_B_write_enable_reg = DFFE(R1_ram_block2a19_PORT_B_write_enable, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_clock_0 = M1__clk0;
R1_ram_block2a19_clock_1 = GND;
R1_ram_block2a19_clock_enable_0 = S3_w_anode3076w[3];
R1_ram_block2a19_clock_enable_1 = GND;
R1_ram_block2a19_PORT_A_data_out = MEMORY(R1_ram_block2a19_PORT_A_data_in_reg, R1_ram_block2a19_PORT_B_data_in_reg, R1_ram_block2a19_PORT_A_address_reg, R1_ram_block2a19_PORT_B_address_reg, R1_ram_block2a19_PORT_A_write_enable_reg, R1_ram_block2a19_PORT_B_write_enable_reg, , , R1_ram_block2a19_clock_0, R1_ram_block2a19_clock_1, R1_ram_block2a19_clock_enable_0, R1_ram_block2a19_clock_enable_1, , );
R1_ram_block2a19_PORT_A_data_out_reg = DFFE(R1_ram_block2a19_PORT_A_data_out, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1M995Q = R1_ram_block2a19_PORT_A_data_out_reg[4];

--R1M996Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT5
R1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a19_PORT_A_data_in_reg = DFFE(R1_ram_block2a19_PORT_A_data_in, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_data_in = ~GND;
R1_ram_block2a19_PORT_B_data_in_reg = DFFE(R1_ram_block2a19_PORT_B_data_in, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a19_PORT_A_address_reg = DFFE(R1_ram_block2a19_PORT_A_address, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a19_PORT_B_address_reg = DFFE(R1_ram_block2a19_PORT_B_address, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_write_enable = GND;
R1_ram_block2a19_PORT_A_write_enable_reg = DFFE(R1_ram_block2a19_PORT_A_write_enable, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_write_enable = GND;
R1_ram_block2a19_PORT_B_write_enable_reg = DFFE(R1_ram_block2a19_PORT_B_write_enable, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_clock_0 = M1__clk0;
R1_ram_block2a19_clock_1 = GND;
R1_ram_block2a19_clock_enable_0 = S3_w_anode3076w[3];
R1_ram_block2a19_clock_enable_1 = GND;
R1_ram_block2a19_PORT_A_data_out = MEMORY(R1_ram_block2a19_PORT_A_data_in_reg, R1_ram_block2a19_PORT_B_data_in_reg, R1_ram_block2a19_PORT_A_address_reg, R1_ram_block2a19_PORT_B_address_reg, R1_ram_block2a19_PORT_A_write_enable_reg, R1_ram_block2a19_PORT_B_write_enable_reg, , , R1_ram_block2a19_clock_0, R1_ram_block2a19_clock_1, R1_ram_block2a19_clock_enable_0, R1_ram_block2a19_clock_enable_1, , );
R1_ram_block2a19_PORT_A_data_out_reg = DFFE(R1_ram_block2a19_PORT_A_data_out, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1M996Q = R1_ram_block2a19_PORT_A_data_out_reg[5];

--R1M997Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT6
R1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a19_PORT_A_data_in_reg = DFFE(R1_ram_block2a19_PORT_A_data_in, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_data_in = ~GND;
R1_ram_block2a19_PORT_B_data_in_reg = DFFE(R1_ram_block2a19_PORT_B_data_in, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a19_PORT_A_address_reg = DFFE(R1_ram_block2a19_PORT_A_address, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a19_PORT_B_address_reg = DFFE(R1_ram_block2a19_PORT_B_address, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_write_enable = GND;
R1_ram_block2a19_PORT_A_write_enable_reg = DFFE(R1_ram_block2a19_PORT_A_write_enable, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_write_enable = GND;
R1_ram_block2a19_PORT_B_write_enable_reg = DFFE(R1_ram_block2a19_PORT_B_write_enable, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_clock_0 = M1__clk0;
R1_ram_block2a19_clock_1 = GND;
R1_ram_block2a19_clock_enable_0 = S3_w_anode3076w[3];
R1_ram_block2a19_clock_enable_1 = GND;
R1_ram_block2a19_PORT_A_data_out = MEMORY(R1_ram_block2a19_PORT_A_data_in_reg, R1_ram_block2a19_PORT_B_data_in_reg, R1_ram_block2a19_PORT_A_address_reg, R1_ram_block2a19_PORT_B_address_reg, R1_ram_block2a19_PORT_A_write_enable_reg, R1_ram_block2a19_PORT_B_write_enable_reg, , , R1_ram_block2a19_clock_0, R1_ram_block2a19_clock_1, R1_ram_block2a19_clock_enable_0, R1_ram_block2a19_clock_enable_1, , );
R1_ram_block2a19_PORT_A_data_out_reg = DFFE(R1_ram_block2a19_PORT_A_data_out, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1M997Q = R1_ram_block2a19_PORT_A_data_out_reg[6];

--R1M998Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT7
R1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a19_PORT_A_data_in_reg = DFFE(R1_ram_block2a19_PORT_A_data_in, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_data_in = ~GND;
R1_ram_block2a19_PORT_B_data_in_reg = DFFE(R1_ram_block2a19_PORT_B_data_in, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a19_PORT_A_address_reg = DFFE(R1_ram_block2a19_PORT_A_address, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a19_PORT_B_address_reg = DFFE(R1_ram_block2a19_PORT_B_address, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_write_enable = GND;
R1_ram_block2a19_PORT_A_write_enable_reg = DFFE(R1_ram_block2a19_PORT_A_write_enable, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_write_enable = GND;
R1_ram_block2a19_PORT_B_write_enable_reg = DFFE(R1_ram_block2a19_PORT_B_write_enable, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_clock_0 = M1__clk0;
R1_ram_block2a19_clock_1 = GND;
R1_ram_block2a19_clock_enable_0 = S3_w_anode3076w[3];
R1_ram_block2a19_clock_enable_1 = GND;
R1_ram_block2a19_PORT_A_data_out = MEMORY(R1_ram_block2a19_PORT_A_data_in_reg, R1_ram_block2a19_PORT_B_data_in_reg, R1_ram_block2a19_PORT_A_address_reg, R1_ram_block2a19_PORT_B_address_reg, R1_ram_block2a19_PORT_A_write_enable_reg, R1_ram_block2a19_PORT_B_write_enable_reg, , , R1_ram_block2a19_clock_0, R1_ram_block2a19_clock_1, R1_ram_block2a19_clock_enable_0, R1_ram_block2a19_clock_enable_1, , );
R1_ram_block2a19_PORT_A_data_out_reg = DFFE(R1_ram_block2a19_PORT_A_data_out, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1M998Q = R1_ram_block2a19_PORT_A_data_out_reg[7];


--T1L225 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6575w~408
T1L225 = R1_address_reg_a[6] & (T1L224 & (R1M996Q) # !T1L224 & R1M896Q) # !R1_address_reg_a[6] & (T1L224);


--R1_ram_block2a27 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a27_PORT_A_data_in_reg = DFFE(R1_ram_block2a27_PORT_A_data_in, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_data_in = ~GND;
R1_ram_block2a27_PORT_B_data_in_reg = DFFE(R1_ram_block2a27_PORT_B_data_in, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a27_PORT_A_address_reg = DFFE(R1_ram_block2a27_PORT_A_address, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a27_PORT_B_address_reg = DFFE(R1_ram_block2a27_PORT_B_address, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_write_enable = GND;
R1_ram_block2a27_PORT_A_write_enable_reg = DFFE(R1_ram_block2a27_PORT_A_write_enable, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_write_enable = GND;
R1_ram_block2a27_PORT_B_write_enable_reg = DFFE(R1_ram_block2a27_PORT_B_write_enable, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_clock_0 = M1__clk0;
R1_ram_block2a27_clock_1 = GND;
R1_ram_block2a27_clock_enable_0 = S3_w_anode3169w[3];
R1_ram_block2a27_clock_enable_1 = GND;
R1_ram_block2a27_PORT_A_data_out = MEMORY(R1_ram_block2a27_PORT_A_data_in_reg, R1_ram_block2a27_PORT_B_data_in_reg, R1_ram_block2a27_PORT_A_address_reg, R1_ram_block2a27_PORT_B_address_reg, R1_ram_block2a27_PORT_A_write_enable_reg, R1_ram_block2a27_PORT_B_write_enable_reg, , , R1_ram_block2a27_clock_0, R1_ram_block2a27_clock_1, R1_ram_block2a27_clock_enable_0, R1_ram_block2a27_clock_enable_1, , );
R1_ram_block2a27_PORT_A_data_out_reg = DFFE(R1_ram_block2a27_PORT_A_data_out, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27 = R1_ram_block2a27_PORT_A_data_out_reg[0];

--R1M1392Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT1
R1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a27_PORT_A_data_in_reg = DFFE(R1_ram_block2a27_PORT_A_data_in, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_data_in = ~GND;
R1_ram_block2a27_PORT_B_data_in_reg = DFFE(R1_ram_block2a27_PORT_B_data_in, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a27_PORT_A_address_reg = DFFE(R1_ram_block2a27_PORT_A_address, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a27_PORT_B_address_reg = DFFE(R1_ram_block2a27_PORT_B_address, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_write_enable = GND;
R1_ram_block2a27_PORT_A_write_enable_reg = DFFE(R1_ram_block2a27_PORT_A_write_enable, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_write_enable = GND;
R1_ram_block2a27_PORT_B_write_enable_reg = DFFE(R1_ram_block2a27_PORT_B_write_enable, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_clock_0 = M1__clk0;
R1_ram_block2a27_clock_1 = GND;
R1_ram_block2a27_clock_enable_0 = S3_w_anode3169w[3];
R1_ram_block2a27_clock_enable_1 = GND;
R1_ram_block2a27_PORT_A_data_out = MEMORY(R1_ram_block2a27_PORT_A_data_in_reg, R1_ram_block2a27_PORT_B_data_in_reg, R1_ram_block2a27_PORT_A_address_reg, R1_ram_block2a27_PORT_B_address_reg, R1_ram_block2a27_PORT_A_write_enable_reg, R1_ram_block2a27_PORT_B_write_enable_reg, , , R1_ram_block2a27_clock_0, R1_ram_block2a27_clock_1, R1_ram_block2a27_clock_enable_0, R1_ram_block2a27_clock_enable_1, , );
R1_ram_block2a27_PORT_A_data_out_reg = DFFE(R1_ram_block2a27_PORT_A_data_out, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1M1392Q = R1_ram_block2a27_PORT_A_data_out_reg[1];

--R1M1393Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT2
R1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a27_PORT_A_data_in_reg = DFFE(R1_ram_block2a27_PORT_A_data_in, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_data_in = ~GND;
R1_ram_block2a27_PORT_B_data_in_reg = DFFE(R1_ram_block2a27_PORT_B_data_in, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a27_PORT_A_address_reg = DFFE(R1_ram_block2a27_PORT_A_address, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a27_PORT_B_address_reg = DFFE(R1_ram_block2a27_PORT_B_address, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_write_enable = GND;
R1_ram_block2a27_PORT_A_write_enable_reg = DFFE(R1_ram_block2a27_PORT_A_write_enable, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_write_enable = GND;
R1_ram_block2a27_PORT_B_write_enable_reg = DFFE(R1_ram_block2a27_PORT_B_write_enable, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_clock_0 = M1__clk0;
R1_ram_block2a27_clock_1 = GND;
R1_ram_block2a27_clock_enable_0 = S3_w_anode3169w[3];
R1_ram_block2a27_clock_enable_1 = GND;
R1_ram_block2a27_PORT_A_data_out = MEMORY(R1_ram_block2a27_PORT_A_data_in_reg, R1_ram_block2a27_PORT_B_data_in_reg, R1_ram_block2a27_PORT_A_address_reg, R1_ram_block2a27_PORT_B_address_reg, R1_ram_block2a27_PORT_A_write_enable_reg, R1_ram_block2a27_PORT_B_write_enable_reg, , , R1_ram_block2a27_clock_0, R1_ram_block2a27_clock_1, R1_ram_block2a27_clock_enable_0, R1_ram_block2a27_clock_enable_1, , );
R1_ram_block2a27_PORT_A_data_out_reg = DFFE(R1_ram_block2a27_PORT_A_data_out, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1M1393Q = R1_ram_block2a27_PORT_A_data_out_reg[2];

--R1M1394Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT3
R1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a27_PORT_A_data_in_reg = DFFE(R1_ram_block2a27_PORT_A_data_in, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_data_in = ~GND;
R1_ram_block2a27_PORT_B_data_in_reg = DFFE(R1_ram_block2a27_PORT_B_data_in, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a27_PORT_A_address_reg = DFFE(R1_ram_block2a27_PORT_A_address, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a27_PORT_B_address_reg = DFFE(R1_ram_block2a27_PORT_B_address, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_write_enable = GND;
R1_ram_block2a27_PORT_A_write_enable_reg = DFFE(R1_ram_block2a27_PORT_A_write_enable, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_write_enable = GND;
R1_ram_block2a27_PORT_B_write_enable_reg = DFFE(R1_ram_block2a27_PORT_B_write_enable, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_clock_0 = M1__clk0;
R1_ram_block2a27_clock_1 = GND;
R1_ram_block2a27_clock_enable_0 = S3_w_anode3169w[3];
R1_ram_block2a27_clock_enable_1 = GND;
R1_ram_block2a27_PORT_A_data_out = MEMORY(R1_ram_block2a27_PORT_A_data_in_reg, R1_ram_block2a27_PORT_B_data_in_reg, R1_ram_block2a27_PORT_A_address_reg, R1_ram_block2a27_PORT_B_address_reg, R1_ram_block2a27_PORT_A_write_enable_reg, R1_ram_block2a27_PORT_B_write_enable_reg, , , R1_ram_block2a27_clock_0, R1_ram_block2a27_clock_1, R1_ram_block2a27_clock_enable_0, R1_ram_block2a27_clock_enable_1, , );
R1_ram_block2a27_PORT_A_data_out_reg = DFFE(R1_ram_block2a27_PORT_A_data_out, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1M1394Q = R1_ram_block2a27_PORT_A_data_out_reg[3];

--R1M1395Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT4
R1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a27_PORT_A_data_in_reg = DFFE(R1_ram_block2a27_PORT_A_data_in, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_data_in = ~GND;
R1_ram_block2a27_PORT_B_data_in_reg = DFFE(R1_ram_block2a27_PORT_B_data_in, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a27_PORT_A_address_reg = DFFE(R1_ram_block2a27_PORT_A_address, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a27_PORT_B_address_reg = DFFE(R1_ram_block2a27_PORT_B_address, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_write_enable = GND;
R1_ram_block2a27_PORT_A_write_enable_reg = DFFE(R1_ram_block2a27_PORT_A_write_enable, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_write_enable = GND;
R1_ram_block2a27_PORT_B_write_enable_reg = DFFE(R1_ram_block2a27_PORT_B_write_enable, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_clock_0 = M1__clk0;
R1_ram_block2a27_clock_1 = GND;
R1_ram_block2a27_clock_enable_0 = S3_w_anode3169w[3];
R1_ram_block2a27_clock_enable_1 = GND;
R1_ram_block2a27_PORT_A_data_out = MEMORY(R1_ram_block2a27_PORT_A_data_in_reg, R1_ram_block2a27_PORT_B_data_in_reg, R1_ram_block2a27_PORT_A_address_reg, R1_ram_block2a27_PORT_B_address_reg, R1_ram_block2a27_PORT_A_write_enable_reg, R1_ram_block2a27_PORT_B_write_enable_reg, , , R1_ram_block2a27_clock_0, R1_ram_block2a27_clock_1, R1_ram_block2a27_clock_enable_0, R1_ram_block2a27_clock_enable_1, , );
R1_ram_block2a27_PORT_A_data_out_reg = DFFE(R1_ram_block2a27_PORT_A_data_out, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1M1395Q = R1_ram_block2a27_PORT_A_data_out_reg[4];

--R1M1396Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT5
R1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a27_PORT_A_data_in_reg = DFFE(R1_ram_block2a27_PORT_A_data_in, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_data_in = ~GND;
R1_ram_block2a27_PORT_B_data_in_reg = DFFE(R1_ram_block2a27_PORT_B_data_in, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a27_PORT_A_address_reg = DFFE(R1_ram_block2a27_PORT_A_address, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a27_PORT_B_address_reg = DFFE(R1_ram_block2a27_PORT_B_address, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_write_enable = GND;
R1_ram_block2a27_PORT_A_write_enable_reg = DFFE(R1_ram_block2a27_PORT_A_write_enable, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_write_enable = GND;
R1_ram_block2a27_PORT_B_write_enable_reg = DFFE(R1_ram_block2a27_PORT_B_write_enable, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_clock_0 = M1__clk0;
R1_ram_block2a27_clock_1 = GND;
R1_ram_block2a27_clock_enable_0 = S3_w_anode3169w[3];
R1_ram_block2a27_clock_enable_1 = GND;
R1_ram_block2a27_PORT_A_data_out = MEMORY(R1_ram_block2a27_PORT_A_data_in_reg, R1_ram_block2a27_PORT_B_data_in_reg, R1_ram_block2a27_PORT_A_address_reg, R1_ram_block2a27_PORT_B_address_reg, R1_ram_block2a27_PORT_A_write_enable_reg, R1_ram_block2a27_PORT_B_write_enable_reg, , , R1_ram_block2a27_clock_0, R1_ram_block2a27_clock_1, R1_ram_block2a27_clock_enable_0, R1_ram_block2a27_clock_enable_1, , );
R1_ram_block2a27_PORT_A_data_out_reg = DFFE(R1_ram_block2a27_PORT_A_data_out, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1M1396Q = R1_ram_block2a27_PORT_A_data_out_reg[5];

--R1M1397Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT6
R1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a27_PORT_A_data_in_reg = DFFE(R1_ram_block2a27_PORT_A_data_in, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_data_in = ~GND;
R1_ram_block2a27_PORT_B_data_in_reg = DFFE(R1_ram_block2a27_PORT_B_data_in, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a27_PORT_A_address_reg = DFFE(R1_ram_block2a27_PORT_A_address, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a27_PORT_B_address_reg = DFFE(R1_ram_block2a27_PORT_B_address, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_write_enable = GND;
R1_ram_block2a27_PORT_A_write_enable_reg = DFFE(R1_ram_block2a27_PORT_A_write_enable, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_write_enable = GND;
R1_ram_block2a27_PORT_B_write_enable_reg = DFFE(R1_ram_block2a27_PORT_B_write_enable, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_clock_0 = M1__clk0;
R1_ram_block2a27_clock_1 = GND;
R1_ram_block2a27_clock_enable_0 = S3_w_anode3169w[3];
R1_ram_block2a27_clock_enable_1 = GND;
R1_ram_block2a27_PORT_A_data_out = MEMORY(R1_ram_block2a27_PORT_A_data_in_reg, R1_ram_block2a27_PORT_B_data_in_reg, R1_ram_block2a27_PORT_A_address_reg, R1_ram_block2a27_PORT_B_address_reg, R1_ram_block2a27_PORT_A_write_enable_reg, R1_ram_block2a27_PORT_B_write_enable_reg, , , R1_ram_block2a27_clock_0, R1_ram_block2a27_clock_1, R1_ram_block2a27_clock_enable_0, R1_ram_block2a27_clock_enable_1, , );
R1_ram_block2a27_PORT_A_data_out_reg = DFFE(R1_ram_block2a27_PORT_A_data_out, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1M1397Q = R1_ram_block2a27_PORT_A_data_out_reg[6];

--R1M1398Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT7
R1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a27_PORT_A_data_in_reg = DFFE(R1_ram_block2a27_PORT_A_data_in, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_data_in = ~GND;
R1_ram_block2a27_PORT_B_data_in_reg = DFFE(R1_ram_block2a27_PORT_B_data_in, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a27_PORT_A_address_reg = DFFE(R1_ram_block2a27_PORT_A_address, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a27_PORT_B_address_reg = DFFE(R1_ram_block2a27_PORT_B_address, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_write_enable = GND;
R1_ram_block2a27_PORT_A_write_enable_reg = DFFE(R1_ram_block2a27_PORT_A_write_enable, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_write_enable = GND;
R1_ram_block2a27_PORT_B_write_enable_reg = DFFE(R1_ram_block2a27_PORT_B_write_enable, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_clock_0 = M1__clk0;
R1_ram_block2a27_clock_1 = GND;
R1_ram_block2a27_clock_enable_0 = S3_w_anode3169w[3];
R1_ram_block2a27_clock_enable_1 = GND;
R1_ram_block2a27_PORT_A_data_out = MEMORY(R1_ram_block2a27_PORT_A_data_in_reg, R1_ram_block2a27_PORT_B_data_in_reg, R1_ram_block2a27_PORT_A_address_reg, R1_ram_block2a27_PORT_B_address_reg, R1_ram_block2a27_PORT_A_write_enable_reg, R1_ram_block2a27_PORT_B_write_enable_reg, , , R1_ram_block2a27_clock_0, R1_ram_block2a27_clock_1, R1_ram_block2a27_clock_enable_0, R1_ram_block2a27_clock_enable_1, , );
R1_ram_block2a27_PORT_A_data_out_reg = DFFE(R1_ram_block2a27_PORT_A_data_out, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1M1398Q = R1_ram_block2a27_PORT_A_data_out_reg[7];


--R1_ram_block2a26 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a26_PORT_A_data_in_reg = DFFE(R1_ram_block2a26_PORT_A_data_in, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_data_in = ~GND;
R1_ram_block2a26_PORT_B_data_in_reg = DFFE(R1_ram_block2a26_PORT_B_data_in, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a26_PORT_A_address_reg = DFFE(R1_ram_block2a26_PORT_A_address, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a26_PORT_B_address_reg = DFFE(R1_ram_block2a26_PORT_B_address, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_write_enable = GND;
R1_ram_block2a26_PORT_A_write_enable_reg = DFFE(R1_ram_block2a26_PORT_A_write_enable, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_write_enable = GND;
R1_ram_block2a26_PORT_B_write_enable_reg = DFFE(R1_ram_block2a26_PORT_B_write_enable, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_clock_0 = M1__clk0;
R1_ram_block2a26_clock_1 = GND;
R1_ram_block2a26_clock_enable_0 = S3_w_anode3159w[3];
R1_ram_block2a26_clock_enable_1 = GND;
R1_ram_block2a26_PORT_A_data_out = MEMORY(R1_ram_block2a26_PORT_A_data_in_reg, R1_ram_block2a26_PORT_B_data_in_reg, R1_ram_block2a26_PORT_A_address_reg, R1_ram_block2a26_PORT_B_address_reg, R1_ram_block2a26_PORT_A_write_enable_reg, R1_ram_block2a26_PORT_B_write_enable_reg, , , R1_ram_block2a26_clock_0, R1_ram_block2a26_clock_1, R1_ram_block2a26_clock_enable_0, R1_ram_block2a26_clock_enable_1, , );
R1_ram_block2a26_PORT_A_data_out_reg = DFFE(R1_ram_block2a26_PORT_A_data_out, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26 = R1_ram_block2a26_PORT_A_data_out_reg[0];

--R1M1342Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT1
R1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a26_PORT_A_data_in_reg = DFFE(R1_ram_block2a26_PORT_A_data_in, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_data_in = ~GND;
R1_ram_block2a26_PORT_B_data_in_reg = DFFE(R1_ram_block2a26_PORT_B_data_in, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a26_PORT_A_address_reg = DFFE(R1_ram_block2a26_PORT_A_address, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a26_PORT_B_address_reg = DFFE(R1_ram_block2a26_PORT_B_address, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_write_enable = GND;
R1_ram_block2a26_PORT_A_write_enable_reg = DFFE(R1_ram_block2a26_PORT_A_write_enable, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_write_enable = GND;
R1_ram_block2a26_PORT_B_write_enable_reg = DFFE(R1_ram_block2a26_PORT_B_write_enable, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_clock_0 = M1__clk0;
R1_ram_block2a26_clock_1 = GND;
R1_ram_block2a26_clock_enable_0 = S3_w_anode3159w[3];
R1_ram_block2a26_clock_enable_1 = GND;
R1_ram_block2a26_PORT_A_data_out = MEMORY(R1_ram_block2a26_PORT_A_data_in_reg, R1_ram_block2a26_PORT_B_data_in_reg, R1_ram_block2a26_PORT_A_address_reg, R1_ram_block2a26_PORT_B_address_reg, R1_ram_block2a26_PORT_A_write_enable_reg, R1_ram_block2a26_PORT_B_write_enable_reg, , , R1_ram_block2a26_clock_0, R1_ram_block2a26_clock_1, R1_ram_block2a26_clock_enable_0, R1_ram_block2a26_clock_enable_1, , );
R1_ram_block2a26_PORT_A_data_out_reg = DFFE(R1_ram_block2a26_PORT_A_data_out, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1M1342Q = R1_ram_block2a26_PORT_A_data_out_reg[1];

--R1M1343Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT2
R1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a26_PORT_A_data_in_reg = DFFE(R1_ram_block2a26_PORT_A_data_in, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_data_in = ~GND;
R1_ram_block2a26_PORT_B_data_in_reg = DFFE(R1_ram_block2a26_PORT_B_data_in, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a26_PORT_A_address_reg = DFFE(R1_ram_block2a26_PORT_A_address, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a26_PORT_B_address_reg = DFFE(R1_ram_block2a26_PORT_B_address, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_write_enable = GND;
R1_ram_block2a26_PORT_A_write_enable_reg = DFFE(R1_ram_block2a26_PORT_A_write_enable, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_write_enable = GND;
R1_ram_block2a26_PORT_B_write_enable_reg = DFFE(R1_ram_block2a26_PORT_B_write_enable, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_clock_0 = M1__clk0;
R1_ram_block2a26_clock_1 = GND;
R1_ram_block2a26_clock_enable_0 = S3_w_anode3159w[3];
R1_ram_block2a26_clock_enable_1 = GND;
R1_ram_block2a26_PORT_A_data_out = MEMORY(R1_ram_block2a26_PORT_A_data_in_reg, R1_ram_block2a26_PORT_B_data_in_reg, R1_ram_block2a26_PORT_A_address_reg, R1_ram_block2a26_PORT_B_address_reg, R1_ram_block2a26_PORT_A_write_enable_reg, R1_ram_block2a26_PORT_B_write_enable_reg, , , R1_ram_block2a26_clock_0, R1_ram_block2a26_clock_1, R1_ram_block2a26_clock_enable_0, R1_ram_block2a26_clock_enable_1, , );
R1_ram_block2a26_PORT_A_data_out_reg = DFFE(R1_ram_block2a26_PORT_A_data_out, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1M1343Q = R1_ram_block2a26_PORT_A_data_out_reg[2];

--R1M1344Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT3
R1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a26_PORT_A_data_in_reg = DFFE(R1_ram_block2a26_PORT_A_data_in, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_data_in = ~GND;
R1_ram_block2a26_PORT_B_data_in_reg = DFFE(R1_ram_block2a26_PORT_B_data_in, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a26_PORT_A_address_reg = DFFE(R1_ram_block2a26_PORT_A_address, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a26_PORT_B_address_reg = DFFE(R1_ram_block2a26_PORT_B_address, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_write_enable = GND;
R1_ram_block2a26_PORT_A_write_enable_reg = DFFE(R1_ram_block2a26_PORT_A_write_enable, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_write_enable = GND;
R1_ram_block2a26_PORT_B_write_enable_reg = DFFE(R1_ram_block2a26_PORT_B_write_enable, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_clock_0 = M1__clk0;
R1_ram_block2a26_clock_1 = GND;
R1_ram_block2a26_clock_enable_0 = S3_w_anode3159w[3];
R1_ram_block2a26_clock_enable_1 = GND;
R1_ram_block2a26_PORT_A_data_out = MEMORY(R1_ram_block2a26_PORT_A_data_in_reg, R1_ram_block2a26_PORT_B_data_in_reg, R1_ram_block2a26_PORT_A_address_reg, R1_ram_block2a26_PORT_B_address_reg, R1_ram_block2a26_PORT_A_write_enable_reg, R1_ram_block2a26_PORT_B_write_enable_reg, , , R1_ram_block2a26_clock_0, R1_ram_block2a26_clock_1, R1_ram_block2a26_clock_enable_0, R1_ram_block2a26_clock_enable_1, , );
R1_ram_block2a26_PORT_A_data_out_reg = DFFE(R1_ram_block2a26_PORT_A_data_out, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1M1344Q = R1_ram_block2a26_PORT_A_data_out_reg[3];

--R1M1345Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT4
R1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a26_PORT_A_data_in_reg = DFFE(R1_ram_block2a26_PORT_A_data_in, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_data_in = ~GND;
R1_ram_block2a26_PORT_B_data_in_reg = DFFE(R1_ram_block2a26_PORT_B_data_in, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a26_PORT_A_address_reg = DFFE(R1_ram_block2a26_PORT_A_address, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a26_PORT_B_address_reg = DFFE(R1_ram_block2a26_PORT_B_address, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_write_enable = GND;
R1_ram_block2a26_PORT_A_write_enable_reg = DFFE(R1_ram_block2a26_PORT_A_write_enable, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_write_enable = GND;
R1_ram_block2a26_PORT_B_write_enable_reg = DFFE(R1_ram_block2a26_PORT_B_write_enable, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_clock_0 = M1__clk0;
R1_ram_block2a26_clock_1 = GND;
R1_ram_block2a26_clock_enable_0 = S3_w_anode3159w[3];
R1_ram_block2a26_clock_enable_1 = GND;
R1_ram_block2a26_PORT_A_data_out = MEMORY(R1_ram_block2a26_PORT_A_data_in_reg, R1_ram_block2a26_PORT_B_data_in_reg, R1_ram_block2a26_PORT_A_address_reg, R1_ram_block2a26_PORT_B_address_reg, R1_ram_block2a26_PORT_A_write_enable_reg, R1_ram_block2a26_PORT_B_write_enable_reg, , , R1_ram_block2a26_clock_0, R1_ram_block2a26_clock_1, R1_ram_block2a26_clock_enable_0, R1_ram_block2a26_clock_enable_1, , );
R1_ram_block2a26_PORT_A_data_out_reg = DFFE(R1_ram_block2a26_PORT_A_data_out, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1M1345Q = R1_ram_block2a26_PORT_A_data_out_reg[4];

--R1M1346Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT5
R1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a26_PORT_A_data_in_reg = DFFE(R1_ram_block2a26_PORT_A_data_in, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_data_in = ~GND;
R1_ram_block2a26_PORT_B_data_in_reg = DFFE(R1_ram_block2a26_PORT_B_data_in, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a26_PORT_A_address_reg = DFFE(R1_ram_block2a26_PORT_A_address, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a26_PORT_B_address_reg = DFFE(R1_ram_block2a26_PORT_B_address, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_write_enable = GND;
R1_ram_block2a26_PORT_A_write_enable_reg = DFFE(R1_ram_block2a26_PORT_A_write_enable, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_write_enable = GND;
R1_ram_block2a26_PORT_B_write_enable_reg = DFFE(R1_ram_block2a26_PORT_B_write_enable, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_clock_0 = M1__clk0;
R1_ram_block2a26_clock_1 = GND;
R1_ram_block2a26_clock_enable_0 = S3_w_anode3159w[3];
R1_ram_block2a26_clock_enable_1 = GND;
R1_ram_block2a26_PORT_A_data_out = MEMORY(R1_ram_block2a26_PORT_A_data_in_reg, R1_ram_block2a26_PORT_B_data_in_reg, R1_ram_block2a26_PORT_A_address_reg, R1_ram_block2a26_PORT_B_address_reg, R1_ram_block2a26_PORT_A_write_enable_reg, R1_ram_block2a26_PORT_B_write_enable_reg, , , R1_ram_block2a26_clock_0, R1_ram_block2a26_clock_1, R1_ram_block2a26_clock_enable_0, R1_ram_block2a26_clock_enable_1, , );
R1_ram_block2a26_PORT_A_data_out_reg = DFFE(R1_ram_block2a26_PORT_A_data_out, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1M1346Q = R1_ram_block2a26_PORT_A_data_out_reg[5];

--R1M1347Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT6
R1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a26_PORT_A_data_in_reg = DFFE(R1_ram_block2a26_PORT_A_data_in, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_data_in = ~GND;
R1_ram_block2a26_PORT_B_data_in_reg = DFFE(R1_ram_block2a26_PORT_B_data_in, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a26_PORT_A_address_reg = DFFE(R1_ram_block2a26_PORT_A_address, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a26_PORT_B_address_reg = DFFE(R1_ram_block2a26_PORT_B_address, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_write_enable = GND;
R1_ram_block2a26_PORT_A_write_enable_reg = DFFE(R1_ram_block2a26_PORT_A_write_enable, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_write_enable = GND;
R1_ram_block2a26_PORT_B_write_enable_reg = DFFE(R1_ram_block2a26_PORT_B_write_enable, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_clock_0 = M1__clk0;
R1_ram_block2a26_clock_1 = GND;
R1_ram_block2a26_clock_enable_0 = S3_w_anode3159w[3];
R1_ram_block2a26_clock_enable_1 = GND;
R1_ram_block2a26_PORT_A_data_out = MEMORY(R1_ram_block2a26_PORT_A_data_in_reg, R1_ram_block2a26_PORT_B_data_in_reg, R1_ram_block2a26_PORT_A_address_reg, R1_ram_block2a26_PORT_B_address_reg, R1_ram_block2a26_PORT_A_write_enable_reg, R1_ram_block2a26_PORT_B_write_enable_reg, , , R1_ram_block2a26_clock_0, R1_ram_block2a26_clock_1, R1_ram_block2a26_clock_enable_0, R1_ram_block2a26_clock_enable_1, , );
R1_ram_block2a26_PORT_A_data_out_reg = DFFE(R1_ram_block2a26_PORT_A_data_out, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1M1347Q = R1_ram_block2a26_PORT_A_data_out_reg[6];

--R1M1348Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT7
R1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a26_PORT_A_data_in_reg = DFFE(R1_ram_block2a26_PORT_A_data_in, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_data_in = ~GND;
R1_ram_block2a26_PORT_B_data_in_reg = DFFE(R1_ram_block2a26_PORT_B_data_in, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a26_PORT_A_address_reg = DFFE(R1_ram_block2a26_PORT_A_address, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a26_PORT_B_address_reg = DFFE(R1_ram_block2a26_PORT_B_address, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_write_enable = GND;
R1_ram_block2a26_PORT_A_write_enable_reg = DFFE(R1_ram_block2a26_PORT_A_write_enable, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_write_enable = GND;
R1_ram_block2a26_PORT_B_write_enable_reg = DFFE(R1_ram_block2a26_PORT_B_write_enable, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_clock_0 = M1__clk0;
R1_ram_block2a26_clock_1 = GND;
R1_ram_block2a26_clock_enable_0 = S3_w_anode3159w[3];
R1_ram_block2a26_clock_enable_1 = GND;
R1_ram_block2a26_PORT_A_data_out = MEMORY(R1_ram_block2a26_PORT_A_data_in_reg, R1_ram_block2a26_PORT_B_data_in_reg, R1_ram_block2a26_PORT_A_address_reg, R1_ram_block2a26_PORT_B_address_reg, R1_ram_block2a26_PORT_A_write_enable_reg, R1_ram_block2a26_PORT_B_write_enable_reg, , , R1_ram_block2a26_clock_0, R1_ram_block2a26_clock_1, R1_ram_block2a26_clock_enable_0, R1_ram_block2a26_clock_enable_1, , );
R1_ram_block2a26_PORT_A_data_out_reg = DFFE(R1_ram_block2a26_PORT_A_data_out, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1M1348Q = R1_ram_block2a26_PORT_A_data_out_reg[7];


--T1L50 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5035
T1L50 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1396Q # !R1_address_reg_a[6] & (R1M1346Q));


--R1_ram_block2a25 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a25_PORT_A_data_in_reg = DFFE(R1_ram_block2a25_PORT_A_data_in, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_data_in = ~GND;
R1_ram_block2a25_PORT_B_data_in_reg = DFFE(R1_ram_block2a25_PORT_B_data_in, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a25_PORT_A_address_reg = DFFE(R1_ram_block2a25_PORT_A_address, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a25_PORT_B_address_reg = DFFE(R1_ram_block2a25_PORT_B_address, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_write_enable = GND;
R1_ram_block2a25_PORT_A_write_enable_reg = DFFE(R1_ram_block2a25_PORT_A_write_enable, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_write_enable = GND;
R1_ram_block2a25_PORT_B_write_enable_reg = DFFE(R1_ram_block2a25_PORT_B_write_enable, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_clock_0 = M1__clk0;
R1_ram_block2a25_clock_1 = GND;
R1_ram_block2a25_clock_enable_0 = S3_w_anode3149w[3];
R1_ram_block2a25_clock_enable_1 = GND;
R1_ram_block2a25_PORT_A_data_out = MEMORY(R1_ram_block2a25_PORT_A_data_in_reg, R1_ram_block2a25_PORT_B_data_in_reg, R1_ram_block2a25_PORT_A_address_reg, R1_ram_block2a25_PORT_B_address_reg, R1_ram_block2a25_PORT_A_write_enable_reg, R1_ram_block2a25_PORT_B_write_enable_reg, , , R1_ram_block2a25_clock_0, R1_ram_block2a25_clock_1, R1_ram_block2a25_clock_enable_0, R1_ram_block2a25_clock_enable_1, , );
R1_ram_block2a25_PORT_A_data_out_reg = DFFE(R1_ram_block2a25_PORT_A_data_out, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25 = R1_ram_block2a25_PORT_A_data_out_reg[0];

--R1M1292Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT1
R1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a25_PORT_A_data_in_reg = DFFE(R1_ram_block2a25_PORT_A_data_in, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_data_in = ~GND;
R1_ram_block2a25_PORT_B_data_in_reg = DFFE(R1_ram_block2a25_PORT_B_data_in, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a25_PORT_A_address_reg = DFFE(R1_ram_block2a25_PORT_A_address, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a25_PORT_B_address_reg = DFFE(R1_ram_block2a25_PORT_B_address, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_write_enable = GND;
R1_ram_block2a25_PORT_A_write_enable_reg = DFFE(R1_ram_block2a25_PORT_A_write_enable, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_write_enable = GND;
R1_ram_block2a25_PORT_B_write_enable_reg = DFFE(R1_ram_block2a25_PORT_B_write_enable, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_clock_0 = M1__clk0;
R1_ram_block2a25_clock_1 = GND;
R1_ram_block2a25_clock_enable_0 = S3_w_anode3149w[3];
R1_ram_block2a25_clock_enable_1 = GND;
R1_ram_block2a25_PORT_A_data_out = MEMORY(R1_ram_block2a25_PORT_A_data_in_reg, R1_ram_block2a25_PORT_B_data_in_reg, R1_ram_block2a25_PORT_A_address_reg, R1_ram_block2a25_PORT_B_address_reg, R1_ram_block2a25_PORT_A_write_enable_reg, R1_ram_block2a25_PORT_B_write_enable_reg, , , R1_ram_block2a25_clock_0, R1_ram_block2a25_clock_1, R1_ram_block2a25_clock_enable_0, R1_ram_block2a25_clock_enable_1, , );
R1_ram_block2a25_PORT_A_data_out_reg = DFFE(R1_ram_block2a25_PORT_A_data_out, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1M1292Q = R1_ram_block2a25_PORT_A_data_out_reg[1];

--R1M1293Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT2
R1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a25_PORT_A_data_in_reg = DFFE(R1_ram_block2a25_PORT_A_data_in, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_data_in = ~GND;
R1_ram_block2a25_PORT_B_data_in_reg = DFFE(R1_ram_block2a25_PORT_B_data_in, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a25_PORT_A_address_reg = DFFE(R1_ram_block2a25_PORT_A_address, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a25_PORT_B_address_reg = DFFE(R1_ram_block2a25_PORT_B_address, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_write_enable = GND;
R1_ram_block2a25_PORT_A_write_enable_reg = DFFE(R1_ram_block2a25_PORT_A_write_enable, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_write_enable = GND;
R1_ram_block2a25_PORT_B_write_enable_reg = DFFE(R1_ram_block2a25_PORT_B_write_enable, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_clock_0 = M1__clk0;
R1_ram_block2a25_clock_1 = GND;
R1_ram_block2a25_clock_enable_0 = S3_w_anode3149w[3];
R1_ram_block2a25_clock_enable_1 = GND;
R1_ram_block2a25_PORT_A_data_out = MEMORY(R1_ram_block2a25_PORT_A_data_in_reg, R1_ram_block2a25_PORT_B_data_in_reg, R1_ram_block2a25_PORT_A_address_reg, R1_ram_block2a25_PORT_B_address_reg, R1_ram_block2a25_PORT_A_write_enable_reg, R1_ram_block2a25_PORT_B_write_enable_reg, , , R1_ram_block2a25_clock_0, R1_ram_block2a25_clock_1, R1_ram_block2a25_clock_enable_0, R1_ram_block2a25_clock_enable_1, , );
R1_ram_block2a25_PORT_A_data_out_reg = DFFE(R1_ram_block2a25_PORT_A_data_out, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1M1293Q = R1_ram_block2a25_PORT_A_data_out_reg[2];

--R1M1294Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT3
R1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a25_PORT_A_data_in_reg = DFFE(R1_ram_block2a25_PORT_A_data_in, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_data_in = ~GND;
R1_ram_block2a25_PORT_B_data_in_reg = DFFE(R1_ram_block2a25_PORT_B_data_in, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a25_PORT_A_address_reg = DFFE(R1_ram_block2a25_PORT_A_address, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a25_PORT_B_address_reg = DFFE(R1_ram_block2a25_PORT_B_address, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_write_enable = GND;
R1_ram_block2a25_PORT_A_write_enable_reg = DFFE(R1_ram_block2a25_PORT_A_write_enable, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_write_enable = GND;
R1_ram_block2a25_PORT_B_write_enable_reg = DFFE(R1_ram_block2a25_PORT_B_write_enable, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_clock_0 = M1__clk0;
R1_ram_block2a25_clock_1 = GND;
R1_ram_block2a25_clock_enable_0 = S3_w_anode3149w[3];
R1_ram_block2a25_clock_enable_1 = GND;
R1_ram_block2a25_PORT_A_data_out = MEMORY(R1_ram_block2a25_PORT_A_data_in_reg, R1_ram_block2a25_PORT_B_data_in_reg, R1_ram_block2a25_PORT_A_address_reg, R1_ram_block2a25_PORT_B_address_reg, R1_ram_block2a25_PORT_A_write_enable_reg, R1_ram_block2a25_PORT_B_write_enable_reg, , , R1_ram_block2a25_clock_0, R1_ram_block2a25_clock_1, R1_ram_block2a25_clock_enable_0, R1_ram_block2a25_clock_enable_1, , );
R1_ram_block2a25_PORT_A_data_out_reg = DFFE(R1_ram_block2a25_PORT_A_data_out, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1M1294Q = R1_ram_block2a25_PORT_A_data_out_reg[3];

--R1M1295Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT4
R1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a25_PORT_A_data_in_reg = DFFE(R1_ram_block2a25_PORT_A_data_in, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_data_in = ~GND;
R1_ram_block2a25_PORT_B_data_in_reg = DFFE(R1_ram_block2a25_PORT_B_data_in, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a25_PORT_A_address_reg = DFFE(R1_ram_block2a25_PORT_A_address, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a25_PORT_B_address_reg = DFFE(R1_ram_block2a25_PORT_B_address, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_write_enable = GND;
R1_ram_block2a25_PORT_A_write_enable_reg = DFFE(R1_ram_block2a25_PORT_A_write_enable, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_write_enable = GND;
R1_ram_block2a25_PORT_B_write_enable_reg = DFFE(R1_ram_block2a25_PORT_B_write_enable, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_clock_0 = M1__clk0;
R1_ram_block2a25_clock_1 = GND;
R1_ram_block2a25_clock_enable_0 = S3_w_anode3149w[3];
R1_ram_block2a25_clock_enable_1 = GND;
R1_ram_block2a25_PORT_A_data_out = MEMORY(R1_ram_block2a25_PORT_A_data_in_reg, R1_ram_block2a25_PORT_B_data_in_reg, R1_ram_block2a25_PORT_A_address_reg, R1_ram_block2a25_PORT_B_address_reg, R1_ram_block2a25_PORT_A_write_enable_reg, R1_ram_block2a25_PORT_B_write_enable_reg, , , R1_ram_block2a25_clock_0, R1_ram_block2a25_clock_1, R1_ram_block2a25_clock_enable_0, R1_ram_block2a25_clock_enable_1, , );
R1_ram_block2a25_PORT_A_data_out_reg = DFFE(R1_ram_block2a25_PORT_A_data_out, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1M1295Q = R1_ram_block2a25_PORT_A_data_out_reg[4];

--R1M1296Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT5
R1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a25_PORT_A_data_in_reg = DFFE(R1_ram_block2a25_PORT_A_data_in, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_data_in = ~GND;
R1_ram_block2a25_PORT_B_data_in_reg = DFFE(R1_ram_block2a25_PORT_B_data_in, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a25_PORT_A_address_reg = DFFE(R1_ram_block2a25_PORT_A_address, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a25_PORT_B_address_reg = DFFE(R1_ram_block2a25_PORT_B_address, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_write_enable = GND;
R1_ram_block2a25_PORT_A_write_enable_reg = DFFE(R1_ram_block2a25_PORT_A_write_enable, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_write_enable = GND;
R1_ram_block2a25_PORT_B_write_enable_reg = DFFE(R1_ram_block2a25_PORT_B_write_enable, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_clock_0 = M1__clk0;
R1_ram_block2a25_clock_1 = GND;
R1_ram_block2a25_clock_enable_0 = S3_w_anode3149w[3];
R1_ram_block2a25_clock_enable_1 = GND;
R1_ram_block2a25_PORT_A_data_out = MEMORY(R1_ram_block2a25_PORT_A_data_in_reg, R1_ram_block2a25_PORT_B_data_in_reg, R1_ram_block2a25_PORT_A_address_reg, R1_ram_block2a25_PORT_B_address_reg, R1_ram_block2a25_PORT_A_write_enable_reg, R1_ram_block2a25_PORT_B_write_enable_reg, , , R1_ram_block2a25_clock_0, R1_ram_block2a25_clock_1, R1_ram_block2a25_clock_enable_0, R1_ram_block2a25_clock_enable_1, , );
R1_ram_block2a25_PORT_A_data_out_reg = DFFE(R1_ram_block2a25_PORT_A_data_out, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1M1296Q = R1_ram_block2a25_PORT_A_data_out_reg[5];

--R1M1297Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT6
R1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a25_PORT_A_data_in_reg = DFFE(R1_ram_block2a25_PORT_A_data_in, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_data_in = ~GND;
R1_ram_block2a25_PORT_B_data_in_reg = DFFE(R1_ram_block2a25_PORT_B_data_in, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a25_PORT_A_address_reg = DFFE(R1_ram_block2a25_PORT_A_address, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a25_PORT_B_address_reg = DFFE(R1_ram_block2a25_PORT_B_address, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_write_enable = GND;
R1_ram_block2a25_PORT_A_write_enable_reg = DFFE(R1_ram_block2a25_PORT_A_write_enable, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_write_enable = GND;
R1_ram_block2a25_PORT_B_write_enable_reg = DFFE(R1_ram_block2a25_PORT_B_write_enable, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_clock_0 = M1__clk0;
R1_ram_block2a25_clock_1 = GND;
R1_ram_block2a25_clock_enable_0 = S3_w_anode3149w[3];
R1_ram_block2a25_clock_enable_1 = GND;
R1_ram_block2a25_PORT_A_data_out = MEMORY(R1_ram_block2a25_PORT_A_data_in_reg, R1_ram_block2a25_PORT_B_data_in_reg, R1_ram_block2a25_PORT_A_address_reg, R1_ram_block2a25_PORT_B_address_reg, R1_ram_block2a25_PORT_A_write_enable_reg, R1_ram_block2a25_PORT_B_write_enable_reg, , , R1_ram_block2a25_clock_0, R1_ram_block2a25_clock_1, R1_ram_block2a25_clock_enable_0, R1_ram_block2a25_clock_enable_1, , );
R1_ram_block2a25_PORT_A_data_out_reg = DFFE(R1_ram_block2a25_PORT_A_data_out, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1M1297Q = R1_ram_block2a25_PORT_A_data_out_reg[6];

--R1M1298Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT7
R1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a25_PORT_A_data_in_reg = DFFE(R1_ram_block2a25_PORT_A_data_in, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_data_in = ~GND;
R1_ram_block2a25_PORT_B_data_in_reg = DFFE(R1_ram_block2a25_PORT_B_data_in, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a25_PORT_A_address_reg = DFFE(R1_ram_block2a25_PORT_A_address, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a25_PORT_B_address_reg = DFFE(R1_ram_block2a25_PORT_B_address, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_write_enable = GND;
R1_ram_block2a25_PORT_A_write_enable_reg = DFFE(R1_ram_block2a25_PORT_A_write_enable, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_write_enable = GND;
R1_ram_block2a25_PORT_B_write_enable_reg = DFFE(R1_ram_block2a25_PORT_B_write_enable, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_clock_0 = M1__clk0;
R1_ram_block2a25_clock_1 = GND;
R1_ram_block2a25_clock_enable_0 = S3_w_anode3149w[3];
R1_ram_block2a25_clock_enable_1 = GND;
R1_ram_block2a25_PORT_A_data_out = MEMORY(R1_ram_block2a25_PORT_A_data_in_reg, R1_ram_block2a25_PORT_B_data_in_reg, R1_ram_block2a25_PORT_A_address_reg, R1_ram_block2a25_PORT_B_address_reg, R1_ram_block2a25_PORT_A_write_enable_reg, R1_ram_block2a25_PORT_B_write_enable_reg, , , R1_ram_block2a25_clock_0, R1_ram_block2a25_clock_1, R1_ram_block2a25_clock_enable_0, R1_ram_block2a25_clock_enable_1, , );
R1_ram_block2a25_PORT_A_data_out_reg = DFFE(R1_ram_block2a25_PORT_A_data_out, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1M1298Q = R1_ram_block2a25_PORT_A_data_out_reg[7];


--R1_ram_block2a24 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a24_PORT_A_data_in_reg = DFFE(R1_ram_block2a24_PORT_A_data_in, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_data_in = ~GND;
R1_ram_block2a24_PORT_B_data_in_reg = DFFE(R1_ram_block2a24_PORT_B_data_in, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a24_PORT_A_address_reg = DFFE(R1_ram_block2a24_PORT_A_address, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a24_PORT_B_address_reg = DFFE(R1_ram_block2a24_PORT_B_address, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_write_enable = GND;
R1_ram_block2a24_PORT_A_write_enable_reg = DFFE(R1_ram_block2a24_PORT_A_write_enable, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_write_enable = GND;
R1_ram_block2a24_PORT_B_write_enable_reg = DFFE(R1_ram_block2a24_PORT_B_write_enable, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_clock_0 = M1__clk0;
R1_ram_block2a24_clock_1 = GND;
R1_ram_block2a24_clock_enable_0 = S3_w_anode3138w[3];
R1_ram_block2a24_clock_enable_1 = GND;
R1_ram_block2a24_PORT_A_data_out = MEMORY(R1_ram_block2a24_PORT_A_data_in_reg, R1_ram_block2a24_PORT_B_data_in_reg, R1_ram_block2a24_PORT_A_address_reg, R1_ram_block2a24_PORT_B_address_reg, R1_ram_block2a24_PORT_A_write_enable_reg, R1_ram_block2a24_PORT_B_write_enable_reg, , , R1_ram_block2a24_clock_0, R1_ram_block2a24_clock_1, R1_ram_block2a24_clock_enable_0, R1_ram_block2a24_clock_enable_1, , );
R1_ram_block2a24_PORT_A_data_out_reg = DFFE(R1_ram_block2a24_PORT_A_data_out, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24 = R1_ram_block2a24_PORT_A_data_out_reg[0];

--R1M1242Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT1
R1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a24_PORT_A_data_in_reg = DFFE(R1_ram_block2a24_PORT_A_data_in, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_data_in = ~GND;
R1_ram_block2a24_PORT_B_data_in_reg = DFFE(R1_ram_block2a24_PORT_B_data_in, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a24_PORT_A_address_reg = DFFE(R1_ram_block2a24_PORT_A_address, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a24_PORT_B_address_reg = DFFE(R1_ram_block2a24_PORT_B_address, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_write_enable = GND;
R1_ram_block2a24_PORT_A_write_enable_reg = DFFE(R1_ram_block2a24_PORT_A_write_enable, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_write_enable = GND;
R1_ram_block2a24_PORT_B_write_enable_reg = DFFE(R1_ram_block2a24_PORT_B_write_enable, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_clock_0 = M1__clk0;
R1_ram_block2a24_clock_1 = GND;
R1_ram_block2a24_clock_enable_0 = S3_w_anode3138w[3];
R1_ram_block2a24_clock_enable_1 = GND;
R1_ram_block2a24_PORT_A_data_out = MEMORY(R1_ram_block2a24_PORT_A_data_in_reg, R1_ram_block2a24_PORT_B_data_in_reg, R1_ram_block2a24_PORT_A_address_reg, R1_ram_block2a24_PORT_B_address_reg, R1_ram_block2a24_PORT_A_write_enable_reg, R1_ram_block2a24_PORT_B_write_enable_reg, , , R1_ram_block2a24_clock_0, R1_ram_block2a24_clock_1, R1_ram_block2a24_clock_enable_0, R1_ram_block2a24_clock_enable_1, , );
R1_ram_block2a24_PORT_A_data_out_reg = DFFE(R1_ram_block2a24_PORT_A_data_out, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1M1242Q = R1_ram_block2a24_PORT_A_data_out_reg[1];

--R1M1243Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT2
R1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a24_PORT_A_data_in_reg = DFFE(R1_ram_block2a24_PORT_A_data_in, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_data_in = ~GND;
R1_ram_block2a24_PORT_B_data_in_reg = DFFE(R1_ram_block2a24_PORT_B_data_in, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a24_PORT_A_address_reg = DFFE(R1_ram_block2a24_PORT_A_address, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a24_PORT_B_address_reg = DFFE(R1_ram_block2a24_PORT_B_address, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_write_enable = GND;
R1_ram_block2a24_PORT_A_write_enable_reg = DFFE(R1_ram_block2a24_PORT_A_write_enable, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_write_enable = GND;
R1_ram_block2a24_PORT_B_write_enable_reg = DFFE(R1_ram_block2a24_PORT_B_write_enable, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_clock_0 = M1__clk0;
R1_ram_block2a24_clock_1 = GND;
R1_ram_block2a24_clock_enable_0 = S3_w_anode3138w[3];
R1_ram_block2a24_clock_enable_1 = GND;
R1_ram_block2a24_PORT_A_data_out = MEMORY(R1_ram_block2a24_PORT_A_data_in_reg, R1_ram_block2a24_PORT_B_data_in_reg, R1_ram_block2a24_PORT_A_address_reg, R1_ram_block2a24_PORT_B_address_reg, R1_ram_block2a24_PORT_A_write_enable_reg, R1_ram_block2a24_PORT_B_write_enable_reg, , , R1_ram_block2a24_clock_0, R1_ram_block2a24_clock_1, R1_ram_block2a24_clock_enable_0, R1_ram_block2a24_clock_enable_1, , );
R1_ram_block2a24_PORT_A_data_out_reg = DFFE(R1_ram_block2a24_PORT_A_data_out, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1M1243Q = R1_ram_block2a24_PORT_A_data_out_reg[2];

--R1M1244Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT3
R1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a24_PORT_A_data_in_reg = DFFE(R1_ram_block2a24_PORT_A_data_in, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_data_in = ~GND;
R1_ram_block2a24_PORT_B_data_in_reg = DFFE(R1_ram_block2a24_PORT_B_data_in, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a24_PORT_A_address_reg = DFFE(R1_ram_block2a24_PORT_A_address, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a24_PORT_B_address_reg = DFFE(R1_ram_block2a24_PORT_B_address, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_write_enable = GND;
R1_ram_block2a24_PORT_A_write_enable_reg = DFFE(R1_ram_block2a24_PORT_A_write_enable, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_write_enable = GND;
R1_ram_block2a24_PORT_B_write_enable_reg = DFFE(R1_ram_block2a24_PORT_B_write_enable, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_clock_0 = M1__clk0;
R1_ram_block2a24_clock_1 = GND;
R1_ram_block2a24_clock_enable_0 = S3_w_anode3138w[3];
R1_ram_block2a24_clock_enable_1 = GND;
R1_ram_block2a24_PORT_A_data_out = MEMORY(R1_ram_block2a24_PORT_A_data_in_reg, R1_ram_block2a24_PORT_B_data_in_reg, R1_ram_block2a24_PORT_A_address_reg, R1_ram_block2a24_PORT_B_address_reg, R1_ram_block2a24_PORT_A_write_enable_reg, R1_ram_block2a24_PORT_B_write_enable_reg, , , R1_ram_block2a24_clock_0, R1_ram_block2a24_clock_1, R1_ram_block2a24_clock_enable_0, R1_ram_block2a24_clock_enable_1, , );
R1_ram_block2a24_PORT_A_data_out_reg = DFFE(R1_ram_block2a24_PORT_A_data_out, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1M1244Q = R1_ram_block2a24_PORT_A_data_out_reg[3];

--R1M1245Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT4
R1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a24_PORT_A_data_in_reg = DFFE(R1_ram_block2a24_PORT_A_data_in, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_data_in = ~GND;
R1_ram_block2a24_PORT_B_data_in_reg = DFFE(R1_ram_block2a24_PORT_B_data_in, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a24_PORT_A_address_reg = DFFE(R1_ram_block2a24_PORT_A_address, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a24_PORT_B_address_reg = DFFE(R1_ram_block2a24_PORT_B_address, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_write_enable = GND;
R1_ram_block2a24_PORT_A_write_enable_reg = DFFE(R1_ram_block2a24_PORT_A_write_enable, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_write_enable = GND;
R1_ram_block2a24_PORT_B_write_enable_reg = DFFE(R1_ram_block2a24_PORT_B_write_enable, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_clock_0 = M1__clk0;
R1_ram_block2a24_clock_1 = GND;
R1_ram_block2a24_clock_enable_0 = S3_w_anode3138w[3];
R1_ram_block2a24_clock_enable_1 = GND;
R1_ram_block2a24_PORT_A_data_out = MEMORY(R1_ram_block2a24_PORT_A_data_in_reg, R1_ram_block2a24_PORT_B_data_in_reg, R1_ram_block2a24_PORT_A_address_reg, R1_ram_block2a24_PORT_B_address_reg, R1_ram_block2a24_PORT_A_write_enable_reg, R1_ram_block2a24_PORT_B_write_enable_reg, , , R1_ram_block2a24_clock_0, R1_ram_block2a24_clock_1, R1_ram_block2a24_clock_enable_0, R1_ram_block2a24_clock_enable_1, , );
R1_ram_block2a24_PORT_A_data_out_reg = DFFE(R1_ram_block2a24_PORT_A_data_out, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1M1245Q = R1_ram_block2a24_PORT_A_data_out_reg[4];

--R1M1246Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT5
R1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a24_PORT_A_data_in_reg = DFFE(R1_ram_block2a24_PORT_A_data_in, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_data_in = ~GND;
R1_ram_block2a24_PORT_B_data_in_reg = DFFE(R1_ram_block2a24_PORT_B_data_in, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a24_PORT_A_address_reg = DFFE(R1_ram_block2a24_PORT_A_address, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a24_PORT_B_address_reg = DFFE(R1_ram_block2a24_PORT_B_address, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_write_enable = GND;
R1_ram_block2a24_PORT_A_write_enable_reg = DFFE(R1_ram_block2a24_PORT_A_write_enable, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_write_enable = GND;
R1_ram_block2a24_PORT_B_write_enable_reg = DFFE(R1_ram_block2a24_PORT_B_write_enable, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_clock_0 = M1__clk0;
R1_ram_block2a24_clock_1 = GND;
R1_ram_block2a24_clock_enable_0 = S3_w_anode3138w[3];
R1_ram_block2a24_clock_enable_1 = GND;
R1_ram_block2a24_PORT_A_data_out = MEMORY(R1_ram_block2a24_PORT_A_data_in_reg, R1_ram_block2a24_PORT_B_data_in_reg, R1_ram_block2a24_PORT_A_address_reg, R1_ram_block2a24_PORT_B_address_reg, R1_ram_block2a24_PORT_A_write_enable_reg, R1_ram_block2a24_PORT_B_write_enable_reg, , , R1_ram_block2a24_clock_0, R1_ram_block2a24_clock_1, R1_ram_block2a24_clock_enable_0, R1_ram_block2a24_clock_enable_1, , );
R1_ram_block2a24_PORT_A_data_out_reg = DFFE(R1_ram_block2a24_PORT_A_data_out, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1M1246Q = R1_ram_block2a24_PORT_A_data_out_reg[5];

--R1M1247Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT6
R1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a24_PORT_A_data_in_reg = DFFE(R1_ram_block2a24_PORT_A_data_in, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_data_in = ~GND;
R1_ram_block2a24_PORT_B_data_in_reg = DFFE(R1_ram_block2a24_PORT_B_data_in, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a24_PORT_A_address_reg = DFFE(R1_ram_block2a24_PORT_A_address, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a24_PORT_B_address_reg = DFFE(R1_ram_block2a24_PORT_B_address, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_write_enable = GND;
R1_ram_block2a24_PORT_A_write_enable_reg = DFFE(R1_ram_block2a24_PORT_A_write_enable, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_write_enable = GND;
R1_ram_block2a24_PORT_B_write_enable_reg = DFFE(R1_ram_block2a24_PORT_B_write_enable, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_clock_0 = M1__clk0;
R1_ram_block2a24_clock_1 = GND;
R1_ram_block2a24_clock_enable_0 = S3_w_anode3138w[3];
R1_ram_block2a24_clock_enable_1 = GND;
R1_ram_block2a24_PORT_A_data_out = MEMORY(R1_ram_block2a24_PORT_A_data_in_reg, R1_ram_block2a24_PORT_B_data_in_reg, R1_ram_block2a24_PORT_A_address_reg, R1_ram_block2a24_PORT_B_address_reg, R1_ram_block2a24_PORT_A_write_enable_reg, R1_ram_block2a24_PORT_B_write_enable_reg, , , R1_ram_block2a24_clock_0, R1_ram_block2a24_clock_1, R1_ram_block2a24_clock_enable_0, R1_ram_block2a24_clock_enable_1, , );
R1_ram_block2a24_PORT_A_data_out_reg = DFFE(R1_ram_block2a24_PORT_A_data_out, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1M1247Q = R1_ram_block2a24_PORT_A_data_out_reg[6];

--R1M1248Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT7
R1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a24_PORT_A_data_in_reg = DFFE(R1_ram_block2a24_PORT_A_data_in, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_data_in = ~GND;
R1_ram_block2a24_PORT_B_data_in_reg = DFFE(R1_ram_block2a24_PORT_B_data_in, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a24_PORT_A_address_reg = DFFE(R1_ram_block2a24_PORT_A_address, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a24_PORT_B_address_reg = DFFE(R1_ram_block2a24_PORT_B_address, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_write_enable = GND;
R1_ram_block2a24_PORT_A_write_enable_reg = DFFE(R1_ram_block2a24_PORT_A_write_enable, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_write_enable = GND;
R1_ram_block2a24_PORT_B_write_enable_reg = DFFE(R1_ram_block2a24_PORT_B_write_enable, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_clock_0 = M1__clk0;
R1_ram_block2a24_clock_1 = GND;
R1_ram_block2a24_clock_enable_0 = S3_w_anode3138w[3];
R1_ram_block2a24_clock_enable_1 = GND;
R1_ram_block2a24_PORT_A_data_out = MEMORY(R1_ram_block2a24_PORT_A_data_in_reg, R1_ram_block2a24_PORT_B_data_in_reg, R1_ram_block2a24_PORT_A_address_reg, R1_ram_block2a24_PORT_B_address_reg, R1_ram_block2a24_PORT_A_write_enable_reg, R1_ram_block2a24_PORT_B_write_enable_reg, , , R1_ram_block2a24_clock_0, R1_ram_block2a24_clock_1, R1_ram_block2a24_clock_enable_0, R1_ram_block2a24_clock_enable_1, , );
R1_ram_block2a24_PORT_A_data_out_reg = DFFE(R1_ram_block2a24_PORT_A_data_out, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1M1248Q = R1_ram_block2a24_PORT_A_data_out_reg[7];


--T1L51 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5036
T1L51 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1296Q # !R1_address_reg_a[6] & (R1M1246Q));


--T1L52 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5037
T1L52 = R1_address_reg_a[9] & (T1L50 # T1L51) # !R1_address_reg_a[9] & T1L225;


--T1L53 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5038
T1L53 = R1_address_reg_a[8] & T1L49 # !R1_address_reg_a[8] & (T1L52);


--R1_address_reg_a[11] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[11]
R1_address_reg_a[11] = DFFEAS(R1_address_reg_a[5], M1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1_address_reg_a[10] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[10]
R1_address_reg_a[10] = DFFEAS(R1_address_reg_a[4], M1__clk0,  ,  ,  ,  ,  ,  ,  );


--T1L147 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~608
T1L147 = R1_address_reg_a[11] & R1_address_reg_a[10];


--T1L232 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~573
T1L232 = R1_address_reg_a[8] & !R1_address_reg_a[10];


--R1_ram_block2a46 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a46_PORT_A_data_in_reg = DFFE(R1_ram_block2a46_PORT_A_data_in, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_data_in = ~GND;
R1_ram_block2a46_PORT_B_data_in_reg = DFFE(R1_ram_block2a46_PORT_B_data_in, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a46_PORT_A_address_reg = DFFE(R1_ram_block2a46_PORT_A_address, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a46_PORT_B_address_reg = DFFE(R1_ram_block2a46_PORT_B_address, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_write_enable = GND;
R1_ram_block2a46_PORT_A_write_enable_reg = DFFE(R1_ram_block2a46_PORT_A_write_enable, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_write_enable = GND;
R1_ram_block2a46_PORT_B_write_enable_reg = DFFE(R1_ram_block2a46_PORT_B_write_enable, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_clock_0 = M1__clk0;
R1_ram_block2a46_clock_1 = GND;
R1_ram_block2a46_clock_enable_0 = S3_w_anode3385w[3];
R1_ram_block2a46_clock_enable_1 = GND;
R1_ram_block2a46_PORT_A_data_out = MEMORY(R1_ram_block2a46_PORT_A_data_in_reg, R1_ram_block2a46_PORT_B_data_in_reg, R1_ram_block2a46_PORT_A_address_reg, R1_ram_block2a46_PORT_B_address_reg, R1_ram_block2a46_PORT_A_write_enable_reg, R1_ram_block2a46_PORT_B_write_enable_reg, , , R1_ram_block2a46_clock_0, R1_ram_block2a46_clock_1, R1_ram_block2a46_clock_enable_0, R1_ram_block2a46_clock_enable_1, , );
R1_ram_block2a46_PORT_A_data_out_reg = DFFE(R1_ram_block2a46_PORT_A_data_out, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46 = R1_ram_block2a46_PORT_A_data_out_reg[0];

--R1M2342Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT1
R1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a46_PORT_A_data_in_reg = DFFE(R1_ram_block2a46_PORT_A_data_in, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_data_in = ~GND;
R1_ram_block2a46_PORT_B_data_in_reg = DFFE(R1_ram_block2a46_PORT_B_data_in, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a46_PORT_A_address_reg = DFFE(R1_ram_block2a46_PORT_A_address, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a46_PORT_B_address_reg = DFFE(R1_ram_block2a46_PORT_B_address, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_write_enable = GND;
R1_ram_block2a46_PORT_A_write_enable_reg = DFFE(R1_ram_block2a46_PORT_A_write_enable, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_write_enable = GND;
R1_ram_block2a46_PORT_B_write_enable_reg = DFFE(R1_ram_block2a46_PORT_B_write_enable, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_clock_0 = M1__clk0;
R1_ram_block2a46_clock_1 = GND;
R1_ram_block2a46_clock_enable_0 = S3_w_anode3385w[3];
R1_ram_block2a46_clock_enable_1 = GND;
R1_ram_block2a46_PORT_A_data_out = MEMORY(R1_ram_block2a46_PORT_A_data_in_reg, R1_ram_block2a46_PORT_B_data_in_reg, R1_ram_block2a46_PORT_A_address_reg, R1_ram_block2a46_PORT_B_address_reg, R1_ram_block2a46_PORT_A_write_enable_reg, R1_ram_block2a46_PORT_B_write_enable_reg, , , R1_ram_block2a46_clock_0, R1_ram_block2a46_clock_1, R1_ram_block2a46_clock_enable_0, R1_ram_block2a46_clock_enable_1, , );
R1_ram_block2a46_PORT_A_data_out_reg = DFFE(R1_ram_block2a46_PORT_A_data_out, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1M2342Q = R1_ram_block2a46_PORT_A_data_out_reg[1];

--R1M2343Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT2
R1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a46_PORT_A_data_in_reg = DFFE(R1_ram_block2a46_PORT_A_data_in, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_data_in = ~GND;
R1_ram_block2a46_PORT_B_data_in_reg = DFFE(R1_ram_block2a46_PORT_B_data_in, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a46_PORT_A_address_reg = DFFE(R1_ram_block2a46_PORT_A_address, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a46_PORT_B_address_reg = DFFE(R1_ram_block2a46_PORT_B_address, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_write_enable = GND;
R1_ram_block2a46_PORT_A_write_enable_reg = DFFE(R1_ram_block2a46_PORT_A_write_enable, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_write_enable = GND;
R1_ram_block2a46_PORT_B_write_enable_reg = DFFE(R1_ram_block2a46_PORT_B_write_enable, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_clock_0 = M1__clk0;
R1_ram_block2a46_clock_1 = GND;
R1_ram_block2a46_clock_enable_0 = S3_w_anode3385w[3];
R1_ram_block2a46_clock_enable_1 = GND;
R1_ram_block2a46_PORT_A_data_out = MEMORY(R1_ram_block2a46_PORT_A_data_in_reg, R1_ram_block2a46_PORT_B_data_in_reg, R1_ram_block2a46_PORT_A_address_reg, R1_ram_block2a46_PORT_B_address_reg, R1_ram_block2a46_PORT_A_write_enable_reg, R1_ram_block2a46_PORT_B_write_enable_reg, , , R1_ram_block2a46_clock_0, R1_ram_block2a46_clock_1, R1_ram_block2a46_clock_enable_0, R1_ram_block2a46_clock_enable_1, , );
R1_ram_block2a46_PORT_A_data_out_reg = DFFE(R1_ram_block2a46_PORT_A_data_out, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1M2343Q = R1_ram_block2a46_PORT_A_data_out_reg[2];

--R1M2344Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT3
R1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a46_PORT_A_data_in_reg = DFFE(R1_ram_block2a46_PORT_A_data_in, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_data_in = ~GND;
R1_ram_block2a46_PORT_B_data_in_reg = DFFE(R1_ram_block2a46_PORT_B_data_in, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a46_PORT_A_address_reg = DFFE(R1_ram_block2a46_PORT_A_address, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a46_PORT_B_address_reg = DFFE(R1_ram_block2a46_PORT_B_address, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_write_enable = GND;
R1_ram_block2a46_PORT_A_write_enable_reg = DFFE(R1_ram_block2a46_PORT_A_write_enable, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_write_enable = GND;
R1_ram_block2a46_PORT_B_write_enable_reg = DFFE(R1_ram_block2a46_PORT_B_write_enable, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_clock_0 = M1__clk0;
R1_ram_block2a46_clock_1 = GND;
R1_ram_block2a46_clock_enable_0 = S3_w_anode3385w[3];
R1_ram_block2a46_clock_enable_1 = GND;
R1_ram_block2a46_PORT_A_data_out = MEMORY(R1_ram_block2a46_PORT_A_data_in_reg, R1_ram_block2a46_PORT_B_data_in_reg, R1_ram_block2a46_PORT_A_address_reg, R1_ram_block2a46_PORT_B_address_reg, R1_ram_block2a46_PORT_A_write_enable_reg, R1_ram_block2a46_PORT_B_write_enable_reg, , , R1_ram_block2a46_clock_0, R1_ram_block2a46_clock_1, R1_ram_block2a46_clock_enable_0, R1_ram_block2a46_clock_enable_1, , );
R1_ram_block2a46_PORT_A_data_out_reg = DFFE(R1_ram_block2a46_PORT_A_data_out, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1M2344Q = R1_ram_block2a46_PORT_A_data_out_reg[3];

--R1M2345Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT4
R1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a46_PORT_A_data_in_reg = DFFE(R1_ram_block2a46_PORT_A_data_in, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_data_in = ~GND;
R1_ram_block2a46_PORT_B_data_in_reg = DFFE(R1_ram_block2a46_PORT_B_data_in, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a46_PORT_A_address_reg = DFFE(R1_ram_block2a46_PORT_A_address, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a46_PORT_B_address_reg = DFFE(R1_ram_block2a46_PORT_B_address, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_write_enable = GND;
R1_ram_block2a46_PORT_A_write_enable_reg = DFFE(R1_ram_block2a46_PORT_A_write_enable, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_write_enable = GND;
R1_ram_block2a46_PORT_B_write_enable_reg = DFFE(R1_ram_block2a46_PORT_B_write_enable, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_clock_0 = M1__clk0;
R1_ram_block2a46_clock_1 = GND;
R1_ram_block2a46_clock_enable_0 = S3_w_anode3385w[3];
R1_ram_block2a46_clock_enable_1 = GND;
R1_ram_block2a46_PORT_A_data_out = MEMORY(R1_ram_block2a46_PORT_A_data_in_reg, R1_ram_block2a46_PORT_B_data_in_reg, R1_ram_block2a46_PORT_A_address_reg, R1_ram_block2a46_PORT_B_address_reg, R1_ram_block2a46_PORT_A_write_enable_reg, R1_ram_block2a46_PORT_B_write_enable_reg, , , R1_ram_block2a46_clock_0, R1_ram_block2a46_clock_1, R1_ram_block2a46_clock_enable_0, R1_ram_block2a46_clock_enable_1, , );
R1_ram_block2a46_PORT_A_data_out_reg = DFFE(R1_ram_block2a46_PORT_A_data_out, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1M2345Q = R1_ram_block2a46_PORT_A_data_out_reg[4];

--R1M2346Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT5
R1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a46_PORT_A_data_in_reg = DFFE(R1_ram_block2a46_PORT_A_data_in, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_data_in = ~GND;
R1_ram_block2a46_PORT_B_data_in_reg = DFFE(R1_ram_block2a46_PORT_B_data_in, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a46_PORT_A_address_reg = DFFE(R1_ram_block2a46_PORT_A_address, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a46_PORT_B_address_reg = DFFE(R1_ram_block2a46_PORT_B_address, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_write_enable = GND;
R1_ram_block2a46_PORT_A_write_enable_reg = DFFE(R1_ram_block2a46_PORT_A_write_enable, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_write_enable = GND;
R1_ram_block2a46_PORT_B_write_enable_reg = DFFE(R1_ram_block2a46_PORT_B_write_enable, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_clock_0 = M1__clk0;
R1_ram_block2a46_clock_1 = GND;
R1_ram_block2a46_clock_enable_0 = S3_w_anode3385w[3];
R1_ram_block2a46_clock_enable_1 = GND;
R1_ram_block2a46_PORT_A_data_out = MEMORY(R1_ram_block2a46_PORT_A_data_in_reg, R1_ram_block2a46_PORT_B_data_in_reg, R1_ram_block2a46_PORT_A_address_reg, R1_ram_block2a46_PORT_B_address_reg, R1_ram_block2a46_PORT_A_write_enable_reg, R1_ram_block2a46_PORT_B_write_enable_reg, , , R1_ram_block2a46_clock_0, R1_ram_block2a46_clock_1, R1_ram_block2a46_clock_enable_0, R1_ram_block2a46_clock_enable_1, , );
R1_ram_block2a46_PORT_A_data_out_reg = DFFE(R1_ram_block2a46_PORT_A_data_out, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1M2346Q = R1_ram_block2a46_PORT_A_data_out_reg[5];

--R1M2347Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT6
R1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a46_PORT_A_data_in_reg = DFFE(R1_ram_block2a46_PORT_A_data_in, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_data_in = ~GND;
R1_ram_block2a46_PORT_B_data_in_reg = DFFE(R1_ram_block2a46_PORT_B_data_in, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a46_PORT_A_address_reg = DFFE(R1_ram_block2a46_PORT_A_address, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a46_PORT_B_address_reg = DFFE(R1_ram_block2a46_PORT_B_address, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_write_enable = GND;
R1_ram_block2a46_PORT_A_write_enable_reg = DFFE(R1_ram_block2a46_PORT_A_write_enable, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_write_enable = GND;
R1_ram_block2a46_PORT_B_write_enable_reg = DFFE(R1_ram_block2a46_PORT_B_write_enable, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_clock_0 = M1__clk0;
R1_ram_block2a46_clock_1 = GND;
R1_ram_block2a46_clock_enable_0 = S3_w_anode3385w[3];
R1_ram_block2a46_clock_enable_1 = GND;
R1_ram_block2a46_PORT_A_data_out = MEMORY(R1_ram_block2a46_PORT_A_data_in_reg, R1_ram_block2a46_PORT_B_data_in_reg, R1_ram_block2a46_PORT_A_address_reg, R1_ram_block2a46_PORT_B_address_reg, R1_ram_block2a46_PORT_A_write_enable_reg, R1_ram_block2a46_PORT_B_write_enable_reg, , , R1_ram_block2a46_clock_0, R1_ram_block2a46_clock_1, R1_ram_block2a46_clock_enable_0, R1_ram_block2a46_clock_enable_1, , );
R1_ram_block2a46_PORT_A_data_out_reg = DFFE(R1_ram_block2a46_PORT_A_data_out, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1M2347Q = R1_ram_block2a46_PORT_A_data_out_reg[6];

--R1M2348Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT7
R1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a46_PORT_A_data_in_reg = DFFE(R1_ram_block2a46_PORT_A_data_in, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_data_in = ~GND;
R1_ram_block2a46_PORT_B_data_in_reg = DFFE(R1_ram_block2a46_PORT_B_data_in, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a46_PORT_A_address_reg = DFFE(R1_ram_block2a46_PORT_A_address, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a46_PORT_B_address_reg = DFFE(R1_ram_block2a46_PORT_B_address, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_write_enable = GND;
R1_ram_block2a46_PORT_A_write_enable_reg = DFFE(R1_ram_block2a46_PORT_A_write_enable, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_write_enable = GND;
R1_ram_block2a46_PORT_B_write_enable_reg = DFFE(R1_ram_block2a46_PORT_B_write_enable, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_clock_0 = M1__clk0;
R1_ram_block2a46_clock_1 = GND;
R1_ram_block2a46_clock_enable_0 = S3_w_anode3385w[3];
R1_ram_block2a46_clock_enable_1 = GND;
R1_ram_block2a46_PORT_A_data_out = MEMORY(R1_ram_block2a46_PORT_A_data_in_reg, R1_ram_block2a46_PORT_B_data_in_reg, R1_ram_block2a46_PORT_A_address_reg, R1_ram_block2a46_PORT_B_address_reg, R1_ram_block2a46_PORT_A_write_enable_reg, R1_ram_block2a46_PORT_B_write_enable_reg, , , R1_ram_block2a46_clock_0, R1_ram_block2a46_clock_1, R1_ram_block2a46_clock_enable_0, R1_ram_block2a46_clock_enable_1, , );
R1_ram_block2a46_PORT_A_data_out_reg = DFFE(R1_ram_block2a46_PORT_A_data_out, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1M2348Q = R1_ram_block2a46_PORT_A_data_out_reg[7];


--R1_ram_block2a45 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a45_PORT_A_data_in_reg = DFFE(R1_ram_block2a45_PORT_A_data_in, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_data_in = ~GND;
R1_ram_block2a45_PORT_B_data_in_reg = DFFE(R1_ram_block2a45_PORT_B_data_in, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a45_PORT_A_address_reg = DFFE(R1_ram_block2a45_PORT_A_address, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a45_PORT_B_address_reg = DFFE(R1_ram_block2a45_PORT_B_address, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_write_enable = GND;
R1_ram_block2a45_PORT_A_write_enable_reg = DFFE(R1_ram_block2a45_PORT_A_write_enable, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_write_enable = GND;
R1_ram_block2a45_PORT_B_write_enable_reg = DFFE(R1_ram_block2a45_PORT_B_write_enable, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_clock_0 = M1__clk0;
R1_ram_block2a45_clock_1 = GND;
R1_ram_block2a45_clock_enable_0 = S3_w_anode3375w[3];
R1_ram_block2a45_clock_enable_1 = GND;
R1_ram_block2a45_PORT_A_data_out = MEMORY(R1_ram_block2a45_PORT_A_data_in_reg, R1_ram_block2a45_PORT_B_data_in_reg, R1_ram_block2a45_PORT_A_address_reg, R1_ram_block2a45_PORT_B_address_reg, R1_ram_block2a45_PORT_A_write_enable_reg, R1_ram_block2a45_PORT_B_write_enable_reg, , , R1_ram_block2a45_clock_0, R1_ram_block2a45_clock_1, R1_ram_block2a45_clock_enable_0, R1_ram_block2a45_clock_enable_1, , );
R1_ram_block2a45_PORT_A_data_out_reg = DFFE(R1_ram_block2a45_PORT_A_data_out, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45 = R1_ram_block2a45_PORT_A_data_out_reg[0];

--R1M2292Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT1
R1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a45_PORT_A_data_in_reg = DFFE(R1_ram_block2a45_PORT_A_data_in, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_data_in = ~GND;
R1_ram_block2a45_PORT_B_data_in_reg = DFFE(R1_ram_block2a45_PORT_B_data_in, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a45_PORT_A_address_reg = DFFE(R1_ram_block2a45_PORT_A_address, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a45_PORT_B_address_reg = DFFE(R1_ram_block2a45_PORT_B_address, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_write_enable = GND;
R1_ram_block2a45_PORT_A_write_enable_reg = DFFE(R1_ram_block2a45_PORT_A_write_enable, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_write_enable = GND;
R1_ram_block2a45_PORT_B_write_enable_reg = DFFE(R1_ram_block2a45_PORT_B_write_enable, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_clock_0 = M1__clk0;
R1_ram_block2a45_clock_1 = GND;
R1_ram_block2a45_clock_enable_0 = S3_w_anode3375w[3];
R1_ram_block2a45_clock_enable_1 = GND;
R1_ram_block2a45_PORT_A_data_out = MEMORY(R1_ram_block2a45_PORT_A_data_in_reg, R1_ram_block2a45_PORT_B_data_in_reg, R1_ram_block2a45_PORT_A_address_reg, R1_ram_block2a45_PORT_B_address_reg, R1_ram_block2a45_PORT_A_write_enable_reg, R1_ram_block2a45_PORT_B_write_enable_reg, , , R1_ram_block2a45_clock_0, R1_ram_block2a45_clock_1, R1_ram_block2a45_clock_enable_0, R1_ram_block2a45_clock_enable_1, , );
R1_ram_block2a45_PORT_A_data_out_reg = DFFE(R1_ram_block2a45_PORT_A_data_out, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1M2292Q = R1_ram_block2a45_PORT_A_data_out_reg[1];

--R1M2293Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT2
R1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a45_PORT_A_data_in_reg = DFFE(R1_ram_block2a45_PORT_A_data_in, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_data_in = ~GND;
R1_ram_block2a45_PORT_B_data_in_reg = DFFE(R1_ram_block2a45_PORT_B_data_in, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a45_PORT_A_address_reg = DFFE(R1_ram_block2a45_PORT_A_address, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a45_PORT_B_address_reg = DFFE(R1_ram_block2a45_PORT_B_address, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_write_enable = GND;
R1_ram_block2a45_PORT_A_write_enable_reg = DFFE(R1_ram_block2a45_PORT_A_write_enable, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_write_enable = GND;
R1_ram_block2a45_PORT_B_write_enable_reg = DFFE(R1_ram_block2a45_PORT_B_write_enable, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_clock_0 = M1__clk0;
R1_ram_block2a45_clock_1 = GND;
R1_ram_block2a45_clock_enable_0 = S3_w_anode3375w[3];
R1_ram_block2a45_clock_enable_1 = GND;
R1_ram_block2a45_PORT_A_data_out = MEMORY(R1_ram_block2a45_PORT_A_data_in_reg, R1_ram_block2a45_PORT_B_data_in_reg, R1_ram_block2a45_PORT_A_address_reg, R1_ram_block2a45_PORT_B_address_reg, R1_ram_block2a45_PORT_A_write_enable_reg, R1_ram_block2a45_PORT_B_write_enable_reg, , , R1_ram_block2a45_clock_0, R1_ram_block2a45_clock_1, R1_ram_block2a45_clock_enable_0, R1_ram_block2a45_clock_enable_1, , );
R1_ram_block2a45_PORT_A_data_out_reg = DFFE(R1_ram_block2a45_PORT_A_data_out, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1M2293Q = R1_ram_block2a45_PORT_A_data_out_reg[2];

--R1M2294Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT3
R1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a45_PORT_A_data_in_reg = DFFE(R1_ram_block2a45_PORT_A_data_in, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_data_in = ~GND;
R1_ram_block2a45_PORT_B_data_in_reg = DFFE(R1_ram_block2a45_PORT_B_data_in, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a45_PORT_A_address_reg = DFFE(R1_ram_block2a45_PORT_A_address, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a45_PORT_B_address_reg = DFFE(R1_ram_block2a45_PORT_B_address, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_write_enable = GND;
R1_ram_block2a45_PORT_A_write_enable_reg = DFFE(R1_ram_block2a45_PORT_A_write_enable, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_write_enable = GND;
R1_ram_block2a45_PORT_B_write_enable_reg = DFFE(R1_ram_block2a45_PORT_B_write_enable, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_clock_0 = M1__clk0;
R1_ram_block2a45_clock_1 = GND;
R1_ram_block2a45_clock_enable_0 = S3_w_anode3375w[3];
R1_ram_block2a45_clock_enable_1 = GND;
R1_ram_block2a45_PORT_A_data_out = MEMORY(R1_ram_block2a45_PORT_A_data_in_reg, R1_ram_block2a45_PORT_B_data_in_reg, R1_ram_block2a45_PORT_A_address_reg, R1_ram_block2a45_PORT_B_address_reg, R1_ram_block2a45_PORT_A_write_enable_reg, R1_ram_block2a45_PORT_B_write_enable_reg, , , R1_ram_block2a45_clock_0, R1_ram_block2a45_clock_1, R1_ram_block2a45_clock_enable_0, R1_ram_block2a45_clock_enable_1, , );
R1_ram_block2a45_PORT_A_data_out_reg = DFFE(R1_ram_block2a45_PORT_A_data_out, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1M2294Q = R1_ram_block2a45_PORT_A_data_out_reg[3];

--R1M2295Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT4
R1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a45_PORT_A_data_in_reg = DFFE(R1_ram_block2a45_PORT_A_data_in, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_data_in = ~GND;
R1_ram_block2a45_PORT_B_data_in_reg = DFFE(R1_ram_block2a45_PORT_B_data_in, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a45_PORT_A_address_reg = DFFE(R1_ram_block2a45_PORT_A_address, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a45_PORT_B_address_reg = DFFE(R1_ram_block2a45_PORT_B_address, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_write_enable = GND;
R1_ram_block2a45_PORT_A_write_enable_reg = DFFE(R1_ram_block2a45_PORT_A_write_enable, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_write_enable = GND;
R1_ram_block2a45_PORT_B_write_enable_reg = DFFE(R1_ram_block2a45_PORT_B_write_enable, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_clock_0 = M1__clk0;
R1_ram_block2a45_clock_1 = GND;
R1_ram_block2a45_clock_enable_0 = S3_w_anode3375w[3];
R1_ram_block2a45_clock_enable_1 = GND;
R1_ram_block2a45_PORT_A_data_out = MEMORY(R1_ram_block2a45_PORT_A_data_in_reg, R1_ram_block2a45_PORT_B_data_in_reg, R1_ram_block2a45_PORT_A_address_reg, R1_ram_block2a45_PORT_B_address_reg, R1_ram_block2a45_PORT_A_write_enable_reg, R1_ram_block2a45_PORT_B_write_enable_reg, , , R1_ram_block2a45_clock_0, R1_ram_block2a45_clock_1, R1_ram_block2a45_clock_enable_0, R1_ram_block2a45_clock_enable_1, , );
R1_ram_block2a45_PORT_A_data_out_reg = DFFE(R1_ram_block2a45_PORT_A_data_out, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1M2295Q = R1_ram_block2a45_PORT_A_data_out_reg[4];

--R1M2296Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT5
R1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a45_PORT_A_data_in_reg = DFFE(R1_ram_block2a45_PORT_A_data_in, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_data_in = ~GND;
R1_ram_block2a45_PORT_B_data_in_reg = DFFE(R1_ram_block2a45_PORT_B_data_in, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a45_PORT_A_address_reg = DFFE(R1_ram_block2a45_PORT_A_address, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a45_PORT_B_address_reg = DFFE(R1_ram_block2a45_PORT_B_address, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_write_enable = GND;
R1_ram_block2a45_PORT_A_write_enable_reg = DFFE(R1_ram_block2a45_PORT_A_write_enable, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_write_enable = GND;
R1_ram_block2a45_PORT_B_write_enable_reg = DFFE(R1_ram_block2a45_PORT_B_write_enable, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_clock_0 = M1__clk0;
R1_ram_block2a45_clock_1 = GND;
R1_ram_block2a45_clock_enable_0 = S3_w_anode3375w[3];
R1_ram_block2a45_clock_enable_1 = GND;
R1_ram_block2a45_PORT_A_data_out = MEMORY(R1_ram_block2a45_PORT_A_data_in_reg, R1_ram_block2a45_PORT_B_data_in_reg, R1_ram_block2a45_PORT_A_address_reg, R1_ram_block2a45_PORT_B_address_reg, R1_ram_block2a45_PORT_A_write_enable_reg, R1_ram_block2a45_PORT_B_write_enable_reg, , , R1_ram_block2a45_clock_0, R1_ram_block2a45_clock_1, R1_ram_block2a45_clock_enable_0, R1_ram_block2a45_clock_enable_1, , );
R1_ram_block2a45_PORT_A_data_out_reg = DFFE(R1_ram_block2a45_PORT_A_data_out, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1M2296Q = R1_ram_block2a45_PORT_A_data_out_reg[5];

--R1M2297Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT6
R1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a45_PORT_A_data_in_reg = DFFE(R1_ram_block2a45_PORT_A_data_in, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_data_in = ~GND;
R1_ram_block2a45_PORT_B_data_in_reg = DFFE(R1_ram_block2a45_PORT_B_data_in, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a45_PORT_A_address_reg = DFFE(R1_ram_block2a45_PORT_A_address, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a45_PORT_B_address_reg = DFFE(R1_ram_block2a45_PORT_B_address, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_write_enable = GND;
R1_ram_block2a45_PORT_A_write_enable_reg = DFFE(R1_ram_block2a45_PORT_A_write_enable, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_write_enable = GND;
R1_ram_block2a45_PORT_B_write_enable_reg = DFFE(R1_ram_block2a45_PORT_B_write_enable, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_clock_0 = M1__clk0;
R1_ram_block2a45_clock_1 = GND;
R1_ram_block2a45_clock_enable_0 = S3_w_anode3375w[3];
R1_ram_block2a45_clock_enable_1 = GND;
R1_ram_block2a45_PORT_A_data_out = MEMORY(R1_ram_block2a45_PORT_A_data_in_reg, R1_ram_block2a45_PORT_B_data_in_reg, R1_ram_block2a45_PORT_A_address_reg, R1_ram_block2a45_PORT_B_address_reg, R1_ram_block2a45_PORT_A_write_enable_reg, R1_ram_block2a45_PORT_B_write_enable_reg, , , R1_ram_block2a45_clock_0, R1_ram_block2a45_clock_1, R1_ram_block2a45_clock_enable_0, R1_ram_block2a45_clock_enable_1, , );
R1_ram_block2a45_PORT_A_data_out_reg = DFFE(R1_ram_block2a45_PORT_A_data_out, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1M2297Q = R1_ram_block2a45_PORT_A_data_out_reg[6];

--R1M2298Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT7
R1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a45_PORT_A_data_in_reg = DFFE(R1_ram_block2a45_PORT_A_data_in, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_data_in = ~GND;
R1_ram_block2a45_PORT_B_data_in_reg = DFFE(R1_ram_block2a45_PORT_B_data_in, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a45_PORT_A_address_reg = DFFE(R1_ram_block2a45_PORT_A_address, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a45_PORT_B_address_reg = DFFE(R1_ram_block2a45_PORT_B_address, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_write_enable = GND;
R1_ram_block2a45_PORT_A_write_enable_reg = DFFE(R1_ram_block2a45_PORT_A_write_enable, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_write_enable = GND;
R1_ram_block2a45_PORT_B_write_enable_reg = DFFE(R1_ram_block2a45_PORT_B_write_enable, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_clock_0 = M1__clk0;
R1_ram_block2a45_clock_1 = GND;
R1_ram_block2a45_clock_enable_0 = S3_w_anode3375w[3];
R1_ram_block2a45_clock_enable_1 = GND;
R1_ram_block2a45_PORT_A_data_out = MEMORY(R1_ram_block2a45_PORT_A_data_in_reg, R1_ram_block2a45_PORT_B_data_in_reg, R1_ram_block2a45_PORT_A_address_reg, R1_ram_block2a45_PORT_B_address_reg, R1_ram_block2a45_PORT_A_write_enable_reg, R1_ram_block2a45_PORT_B_write_enable_reg, , , R1_ram_block2a45_clock_0, R1_ram_block2a45_clock_1, R1_ram_block2a45_clock_enable_0, R1_ram_block2a45_clock_enable_1, , );
R1_ram_block2a45_PORT_A_data_out_reg = DFFE(R1_ram_block2a45_PORT_A_data_out, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1M2298Q = R1_ram_block2a45_PORT_A_data_out_reg[7];


--R1_ram_block2a44 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a44_PORT_A_data_in_reg = DFFE(R1_ram_block2a44_PORT_A_data_in, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_data_in = ~GND;
R1_ram_block2a44_PORT_B_data_in_reg = DFFE(R1_ram_block2a44_PORT_B_data_in, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a44_PORT_A_address_reg = DFFE(R1_ram_block2a44_PORT_A_address, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a44_PORT_B_address_reg = DFFE(R1_ram_block2a44_PORT_B_address, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_write_enable = GND;
R1_ram_block2a44_PORT_A_write_enable_reg = DFFE(R1_ram_block2a44_PORT_A_write_enable, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_write_enable = GND;
R1_ram_block2a44_PORT_B_write_enable_reg = DFFE(R1_ram_block2a44_PORT_B_write_enable, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_clock_0 = M1__clk0;
R1_ram_block2a44_clock_1 = GND;
R1_ram_block2a44_clock_enable_0 = S3_w_anode3365w[3];
R1_ram_block2a44_clock_enable_1 = GND;
R1_ram_block2a44_PORT_A_data_out = MEMORY(R1_ram_block2a44_PORT_A_data_in_reg, R1_ram_block2a44_PORT_B_data_in_reg, R1_ram_block2a44_PORT_A_address_reg, R1_ram_block2a44_PORT_B_address_reg, R1_ram_block2a44_PORT_A_write_enable_reg, R1_ram_block2a44_PORT_B_write_enable_reg, , , R1_ram_block2a44_clock_0, R1_ram_block2a44_clock_1, R1_ram_block2a44_clock_enable_0, R1_ram_block2a44_clock_enable_1, , );
R1_ram_block2a44_PORT_A_data_out_reg = DFFE(R1_ram_block2a44_PORT_A_data_out, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44 = R1_ram_block2a44_PORT_A_data_out_reg[0];

--R1M2242Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT1
R1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a44_PORT_A_data_in_reg = DFFE(R1_ram_block2a44_PORT_A_data_in, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_data_in = ~GND;
R1_ram_block2a44_PORT_B_data_in_reg = DFFE(R1_ram_block2a44_PORT_B_data_in, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a44_PORT_A_address_reg = DFFE(R1_ram_block2a44_PORT_A_address, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a44_PORT_B_address_reg = DFFE(R1_ram_block2a44_PORT_B_address, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_write_enable = GND;
R1_ram_block2a44_PORT_A_write_enable_reg = DFFE(R1_ram_block2a44_PORT_A_write_enable, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_write_enable = GND;
R1_ram_block2a44_PORT_B_write_enable_reg = DFFE(R1_ram_block2a44_PORT_B_write_enable, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_clock_0 = M1__clk0;
R1_ram_block2a44_clock_1 = GND;
R1_ram_block2a44_clock_enable_0 = S3_w_anode3365w[3];
R1_ram_block2a44_clock_enable_1 = GND;
R1_ram_block2a44_PORT_A_data_out = MEMORY(R1_ram_block2a44_PORT_A_data_in_reg, R1_ram_block2a44_PORT_B_data_in_reg, R1_ram_block2a44_PORT_A_address_reg, R1_ram_block2a44_PORT_B_address_reg, R1_ram_block2a44_PORT_A_write_enable_reg, R1_ram_block2a44_PORT_B_write_enable_reg, , , R1_ram_block2a44_clock_0, R1_ram_block2a44_clock_1, R1_ram_block2a44_clock_enable_0, R1_ram_block2a44_clock_enable_1, , );
R1_ram_block2a44_PORT_A_data_out_reg = DFFE(R1_ram_block2a44_PORT_A_data_out, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1M2242Q = R1_ram_block2a44_PORT_A_data_out_reg[1];

--R1M2243Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT2
R1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a44_PORT_A_data_in_reg = DFFE(R1_ram_block2a44_PORT_A_data_in, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_data_in = ~GND;
R1_ram_block2a44_PORT_B_data_in_reg = DFFE(R1_ram_block2a44_PORT_B_data_in, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a44_PORT_A_address_reg = DFFE(R1_ram_block2a44_PORT_A_address, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a44_PORT_B_address_reg = DFFE(R1_ram_block2a44_PORT_B_address, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_write_enable = GND;
R1_ram_block2a44_PORT_A_write_enable_reg = DFFE(R1_ram_block2a44_PORT_A_write_enable, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_write_enable = GND;
R1_ram_block2a44_PORT_B_write_enable_reg = DFFE(R1_ram_block2a44_PORT_B_write_enable, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_clock_0 = M1__clk0;
R1_ram_block2a44_clock_1 = GND;
R1_ram_block2a44_clock_enable_0 = S3_w_anode3365w[3];
R1_ram_block2a44_clock_enable_1 = GND;
R1_ram_block2a44_PORT_A_data_out = MEMORY(R1_ram_block2a44_PORT_A_data_in_reg, R1_ram_block2a44_PORT_B_data_in_reg, R1_ram_block2a44_PORT_A_address_reg, R1_ram_block2a44_PORT_B_address_reg, R1_ram_block2a44_PORT_A_write_enable_reg, R1_ram_block2a44_PORT_B_write_enable_reg, , , R1_ram_block2a44_clock_0, R1_ram_block2a44_clock_1, R1_ram_block2a44_clock_enable_0, R1_ram_block2a44_clock_enable_1, , );
R1_ram_block2a44_PORT_A_data_out_reg = DFFE(R1_ram_block2a44_PORT_A_data_out, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1M2243Q = R1_ram_block2a44_PORT_A_data_out_reg[2];

--R1M2244Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT3
R1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a44_PORT_A_data_in_reg = DFFE(R1_ram_block2a44_PORT_A_data_in, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_data_in = ~GND;
R1_ram_block2a44_PORT_B_data_in_reg = DFFE(R1_ram_block2a44_PORT_B_data_in, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a44_PORT_A_address_reg = DFFE(R1_ram_block2a44_PORT_A_address, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a44_PORT_B_address_reg = DFFE(R1_ram_block2a44_PORT_B_address, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_write_enable = GND;
R1_ram_block2a44_PORT_A_write_enable_reg = DFFE(R1_ram_block2a44_PORT_A_write_enable, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_write_enable = GND;
R1_ram_block2a44_PORT_B_write_enable_reg = DFFE(R1_ram_block2a44_PORT_B_write_enable, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_clock_0 = M1__clk0;
R1_ram_block2a44_clock_1 = GND;
R1_ram_block2a44_clock_enable_0 = S3_w_anode3365w[3];
R1_ram_block2a44_clock_enable_1 = GND;
R1_ram_block2a44_PORT_A_data_out = MEMORY(R1_ram_block2a44_PORT_A_data_in_reg, R1_ram_block2a44_PORT_B_data_in_reg, R1_ram_block2a44_PORT_A_address_reg, R1_ram_block2a44_PORT_B_address_reg, R1_ram_block2a44_PORT_A_write_enable_reg, R1_ram_block2a44_PORT_B_write_enable_reg, , , R1_ram_block2a44_clock_0, R1_ram_block2a44_clock_1, R1_ram_block2a44_clock_enable_0, R1_ram_block2a44_clock_enable_1, , );
R1_ram_block2a44_PORT_A_data_out_reg = DFFE(R1_ram_block2a44_PORT_A_data_out, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1M2244Q = R1_ram_block2a44_PORT_A_data_out_reg[3];

--R1M2245Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT4
R1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a44_PORT_A_data_in_reg = DFFE(R1_ram_block2a44_PORT_A_data_in, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_data_in = ~GND;
R1_ram_block2a44_PORT_B_data_in_reg = DFFE(R1_ram_block2a44_PORT_B_data_in, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a44_PORT_A_address_reg = DFFE(R1_ram_block2a44_PORT_A_address, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a44_PORT_B_address_reg = DFFE(R1_ram_block2a44_PORT_B_address, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_write_enable = GND;
R1_ram_block2a44_PORT_A_write_enable_reg = DFFE(R1_ram_block2a44_PORT_A_write_enable, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_write_enable = GND;
R1_ram_block2a44_PORT_B_write_enable_reg = DFFE(R1_ram_block2a44_PORT_B_write_enable, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_clock_0 = M1__clk0;
R1_ram_block2a44_clock_1 = GND;
R1_ram_block2a44_clock_enable_0 = S3_w_anode3365w[3];
R1_ram_block2a44_clock_enable_1 = GND;
R1_ram_block2a44_PORT_A_data_out = MEMORY(R1_ram_block2a44_PORT_A_data_in_reg, R1_ram_block2a44_PORT_B_data_in_reg, R1_ram_block2a44_PORT_A_address_reg, R1_ram_block2a44_PORT_B_address_reg, R1_ram_block2a44_PORT_A_write_enable_reg, R1_ram_block2a44_PORT_B_write_enable_reg, , , R1_ram_block2a44_clock_0, R1_ram_block2a44_clock_1, R1_ram_block2a44_clock_enable_0, R1_ram_block2a44_clock_enable_1, , );
R1_ram_block2a44_PORT_A_data_out_reg = DFFE(R1_ram_block2a44_PORT_A_data_out, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1M2245Q = R1_ram_block2a44_PORT_A_data_out_reg[4];

--R1M2246Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT5
R1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a44_PORT_A_data_in_reg = DFFE(R1_ram_block2a44_PORT_A_data_in, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_data_in = ~GND;
R1_ram_block2a44_PORT_B_data_in_reg = DFFE(R1_ram_block2a44_PORT_B_data_in, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a44_PORT_A_address_reg = DFFE(R1_ram_block2a44_PORT_A_address, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a44_PORT_B_address_reg = DFFE(R1_ram_block2a44_PORT_B_address, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_write_enable = GND;
R1_ram_block2a44_PORT_A_write_enable_reg = DFFE(R1_ram_block2a44_PORT_A_write_enable, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_write_enable = GND;
R1_ram_block2a44_PORT_B_write_enable_reg = DFFE(R1_ram_block2a44_PORT_B_write_enable, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_clock_0 = M1__clk0;
R1_ram_block2a44_clock_1 = GND;
R1_ram_block2a44_clock_enable_0 = S3_w_anode3365w[3];
R1_ram_block2a44_clock_enable_1 = GND;
R1_ram_block2a44_PORT_A_data_out = MEMORY(R1_ram_block2a44_PORT_A_data_in_reg, R1_ram_block2a44_PORT_B_data_in_reg, R1_ram_block2a44_PORT_A_address_reg, R1_ram_block2a44_PORT_B_address_reg, R1_ram_block2a44_PORT_A_write_enable_reg, R1_ram_block2a44_PORT_B_write_enable_reg, , , R1_ram_block2a44_clock_0, R1_ram_block2a44_clock_1, R1_ram_block2a44_clock_enable_0, R1_ram_block2a44_clock_enable_1, , );
R1_ram_block2a44_PORT_A_data_out_reg = DFFE(R1_ram_block2a44_PORT_A_data_out, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1M2246Q = R1_ram_block2a44_PORT_A_data_out_reg[5];

--R1M2247Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT6
R1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a44_PORT_A_data_in_reg = DFFE(R1_ram_block2a44_PORT_A_data_in, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_data_in = ~GND;
R1_ram_block2a44_PORT_B_data_in_reg = DFFE(R1_ram_block2a44_PORT_B_data_in, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a44_PORT_A_address_reg = DFFE(R1_ram_block2a44_PORT_A_address, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a44_PORT_B_address_reg = DFFE(R1_ram_block2a44_PORT_B_address, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_write_enable = GND;
R1_ram_block2a44_PORT_A_write_enable_reg = DFFE(R1_ram_block2a44_PORT_A_write_enable, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_write_enable = GND;
R1_ram_block2a44_PORT_B_write_enable_reg = DFFE(R1_ram_block2a44_PORT_B_write_enable, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_clock_0 = M1__clk0;
R1_ram_block2a44_clock_1 = GND;
R1_ram_block2a44_clock_enable_0 = S3_w_anode3365w[3];
R1_ram_block2a44_clock_enable_1 = GND;
R1_ram_block2a44_PORT_A_data_out = MEMORY(R1_ram_block2a44_PORT_A_data_in_reg, R1_ram_block2a44_PORT_B_data_in_reg, R1_ram_block2a44_PORT_A_address_reg, R1_ram_block2a44_PORT_B_address_reg, R1_ram_block2a44_PORT_A_write_enable_reg, R1_ram_block2a44_PORT_B_write_enable_reg, , , R1_ram_block2a44_clock_0, R1_ram_block2a44_clock_1, R1_ram_block2a44_clock_enable_0, R1_ram_block2a44_clock_enable_1, , );
R1_ram_block2a44_PORT_A_data_out_reg = DFFE(R1_ram_block2a44_PORT_A_data_out, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1M2247Q = R1_ram_block2a44_PORT_A_data_out_reg[6];

--R1M2248Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT7
R1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a44_PORT_A_data_in_reg = DFFE(R1_ram_block2a44_PORT_A_data_in, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_data_in = ~GND;
R1_ram_block2a44_PORT_B_data_in_reg = DFFE(R1_ram_block2a44_PORT_B_data_in, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a44_PORT_A_address_reg = DFFE(R1_ram_block2a44_PORT_A_address, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a44_PORT_B_address_reg = DFFE(R1_ram_block2a44_PORT_B_address, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_write_enable = GND;
R1_ram_block2a44_PORT_A_write_enable_reg = DFFE(R1_ram_block2a44_PORT_A_write_enable, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_write_enable = GND;
R1_ram_block2a44_PORT_B_write_enable_reg = DFFE(R1_ram_block2a44_PORT_B_write_enable, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_clock_0 = M1__clk0;
R1_ram_block2a44_clock_1 = GND;
R1_ram_block2a44_clock_enable_0 = S3_w_anode3365w[3];
R1_ram_block2a44_clock_enable_1 = GND;
R1_ram_block2a44_PORT_A_data_out = MEMORY(R1_ram_block2a44_PORT_A_data_in_reg, R1_ram_block2a44_PORT_B_data_in_reg, R1_ram_block2a44_PORT_A_address_reg, R1_ram_block2a44_PORT_B_address_reg, R1_ram_block2a44_PORT_A_write_enable_reg, R1_ram_block2a44_PORT_B_write_enable_reg, , , R1_ram_block2a44_clock_0, R1_ram_block2a44_clock_1, R1_ram_block2a44_clock_enable_0, R1_ram_block2a44_clock_enable_1, , );
R1_ram_block2a44_PORT_A_data_out_reg = DFFE(R1_ram_block2a44_PORT_A_data_out, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1M2248Q = R1_ram_block2a44_PORT_A_data_out_reg[7];


--T1L228 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6591w~47
T1L228 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M2296Q # !R1_address_reg_a[6] & (R1M2246Q));


--R1_ram_block2a47 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a47_PORT_A_data_in_reg = DFFE(R1_ram_block2a47_PORT_A_data_in, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_data_in = ~GND;
R1_ram_block2a47_PORT_B_data_in_reg = DFFE(R1_ram_block2a47_PORT_B_data_in, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a47_PORT_A_address_reg = DFFE(R1_ram_block2a47_PORT_A_address, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a47_PORT_B_address_reg = DFFE(R1_ram_block2a47_PORT_B_address, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_write_enable = GND;
R1_ram_block2a47_PORT_A_write_enable_reg = DFFE(R1_ram_block2a47_PORT_A_write_enable, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_write_enable = GND;
R1_ram_block2a47_PORT_B_write_enable_reg = DFFE(R1_ram_block2a47_PORT_B_write_enable, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_clock_0 = M1__clk0;
R1_ram_block2a47_clock_1 = GND;
R1_ram_block2a47_clock_enable_0 = S3_w_anode3395w[3];
R1_ram_block2a47_clock_enable_1 = GND;
R1_ram_block2a47_PORT_A_data_out = MEMORY(R1_ram_block2a47_PORT_A_data_in_reg, R1_ram_block2a47_PORT_B_data_in_reg, R1_ram_block2a47_PORT_A_address_reg, R1_ram_block2a47_PORT_B_address_reg, R1_ram_block2a47_PORT_A_write_enable_reg, R1_ram_block2a47_PORT_B_write_enable_reg, , , R1_ram_block2a47_clock_0, R1_ram_block2a47_clock_1, R1_ram_block2a47_clock_enable_0, R1_ram_block2a47_clock_enable_1, , );
R1_ram_block2a47_PORT_A_data_out_reg = DFFE(R1_ram_block2a47_PORT_A_data_out, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47 = R1_ram_block2a47_PORT_A_data_out_reg[0];

--R1M2392Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT1
R1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a47_PORT_A_data_in_reg = DFFE(R1_ram_block2a47_PORT_A_data_in, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_data_in = ~GND;
R1_ram_block2a47_PORT_B_data_in_reg = DFFE(R1_ram_block2a47_PORT_B_data_in, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a47_PORT_A_address_reg = DFFE(R1_ram_block2a47_PORT_A_address, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a47_PORT_B_address_reg = DFFE(R1_ram_block2a47_PORT_B_address, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_write_enable = GND;
R1_ram_block2a47_PORT_A_write_enable_reg = DFFE(R1_ram_block2a47_PORT_A_write_enable, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_write_enable = GND;
R1_ram_block2a47_PORT_B_write_enable_reg = DFFE(R1_ram_block2a47_PORT_B_write_enable, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_clock_0 = M1__clk0;
R1_ram_block2a47_clock_1 = GND;
R1_ram_block2a47_clock_enable_0 = S3_w_anode3395w[3];
R1_ram_block2a47_clock_enable_1 = GND;
R1_ram_block2a47_PORT_A_data_out = MEMORY(R1_ram_block2a47_PORT_A_data_in_reg, R1_ram_block2a47_PORT_B_data_in_reg, R1_ram_block2a47_PORT_A_address_reg, R1_ram_block2a47_PORT_B_address_reg, R1_ram_block2a47_PORT_A_write_enable_reg, R1_ram_block2a47_PORT_B_write_enable_reg, , , R1_ram_block2a47_clock_0, R1_ram_block2a47_clock_1, R1_ram_block2a47_clock_enable_0, R1_ram_block2a47_clock_enable_1, , );
R1_ram_block2a47_PORT_A_data_out_reg = DFFE(R1_ram_block2a47_PORT_A_data_out, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1M2392Q = R1_ram_block2a47_PORT_A_data_out_reg[1];

--R1M2393Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT2
R1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a47_PORT_A_data_in_reg = DFFE(R1_ram_block2a47_PORT_A_data_in, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_data_in = ~GND;
R1_ram_block2a47_PORT_B_data_in_reg = DFFE(R1_ram_block2a47_PORT_B_data_in, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a47_PORT_A_address_reg = DFFE(R1_ram_block2a47_PORT_A_address, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a47_PORT_B_address_reg = DFFE(R1_ram_block2a47_PORT_B_address, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_write_enable = GND;
R1_ram_block2a47_PORT_A_write_enable_reg = DFFE(R1_ram_block2a47_PORT_A_write_enable, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_write_enable = GND;
R1_ram_block2a47_PORT_B_write_enable_reg = DFFE(R1_ram_block2a47_PORT_B_write_enable, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_clock_0 = M1__clk0;
R1_ram_block2a47_clock_1 = GND;
R1_ram_block2a47_clock_enable_0 = S3_w_anode3395w[3];
R1_ram_block2a47_clock_enable_1 = GND;
R1_ram_block2a47_PORT_A_data_out = MEMORY(R1_ram_block2a47_PORT_A_data_in_reg, R1_ram_block2a47_PORT_B_data_in_reg, R1_ram_block2a47_PORT_A_address_reg, R1_ram_block2a47_PORT_B_address_reg, R1_ram_block2a47_PORT_A_write_enable_reg, R1_ram_block2a47_PORT_B_write_enable_reg, , , R1_ram_block2a47_clock_0, R1_ram_block2a47_clock_1, R1_ram_block2a47_clock_enable_0, R1_ram_block2a47_clock_enable_1, , );
R1_ram_block2a47_PORT_A_data_out_reg = DFFE(R1_ram_block2a47_PORT_A_data_out, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1M2393Q = R1_ram_block2a47_PORT_A_data_out_reg[2];

--R1M2394Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT3
R1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a47_PORT_A_data_in_reg = DFFE(R1_ram_block2a47_PORT_A_data_in, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_data_in = ~GND;
R1_ram_block2a47_PORT_B_data_in_reg = DFFE(R1_ram_block2a47_PORT_B_data_in, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a47_PORT_A_address_reg = DFFE(R1_ram_block2a47_PORT_A_address, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a47_PORT_B_address_reg = DFFE(R1_ram_block2a47_PORT_B_address, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_write_enable = GND;
R1_ram_block2a47_PORT_A_write_enable_reg = DFFE(R1_ram_block2a47_PORT_A_write_enable, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_write_enable = GND;
R1_ram_block2a47_PORT_B_write_enable_reg = DFFE(R1_ram_block2a47_PORT_B_write_enable, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_clock_0 = M1__clk0;
R1_ram_block2a47_clock_1 = GND;
R1_ram_block2a47_clock_enable_0 = S3_w_anode3395w[3];
R1_ram_block2a47_clock_enable_1 = GND;
R1_ram_block2a47_PORT_A_data_out = MEMORY(R1_ram_block2a47_PORT_A_data_in_reg, R1_ram_block2a47_PORT_B_data_in_reg, R1_ram_block2a47_PORT_A_address_reg, R1_ram_block2a47_PORT_B_address_reg, R1_ram_block2a47_PORT_A_write_enable_reg, R1_ram_block2a47_PORT_B_write_enable_reg, , , R1_ram_block2a47_clock_0, R1_ram_block2a47_clock_1, R1_ram_block2a47_clock_enable_0, R1_ram_block2a47_clock_enable_1, , );
R1_ram_block2a47_PORT_A_data_out_reg = DFFE(R1_ram_block2a47_PORT_A_data_out, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1M2394Q = R1_ram_block2a47_PORT_A_data_out_reg[3];

--R1M2395Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT4
R1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a47_PORT_A_data_in_reg = DFFE(R1_ram_block2a47_PORT_A_data_in, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_data_in = ~GND;
R1_ram_block2a47_PORT_B_data_in_reg = DFFE(R1_ram_block2a47_PORT_B_data_in, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a47_PORT_A_address_reg = DFFE(R1_ram_block2a47_PORT_A_address, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a47_PORT_B_address_reg = DFFE(R1_ram_block2a47_PORT_B_address, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_write_enable = GND;
R1_ram_block2a47_PORT_A_write_enable_reg = DFFE(R1_ram_block2a47_PORT_A_write_enable, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_write_enable = GND;
R1_ram_block2a47_PORT_B_write_enable_reg = DFFE(R1_ram_block2a47_PORT_B_write_enable, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_clock_0 = M1__clk0;
R1_ram_block2a47_clock_1 = GND;
R1_ram_block2a47_clock_enable_0 = S3_w_anode3395w[3];
R1_ram_block2a47_clock_enable_1 = GND;
R1_ram_block2a47_PORT_A_data_out = MEMORY(R1_ram_block2a47_PORT_A_data_in_reg, R1_ram_block2a47_PORT_B_data_in_reg, R1_ram_block2a47_PORT_A_address_reg, R1_ram_block2a47_PORT_B_address_reg, R1_ram_block2a47_PORT_A_write_enable_reg, R1_ram_block2a47_PORT_B_write_enable_reg, , , R1_ram_block2a47_clock_0, R1_ram_block2a47_clock_1, R1_ram_block2a47_clock_enable_0, R1_ram_block2a47_clock_enable_1, , );
R1_ram_block2a47_PORT_A_data_out_reg = DFFE(R1_ram_block2a47_PORT_A_data_out, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1M2395Q = R1_ram_block2a47_PORT_A_data_out_reg[4];

--R1M2396Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT5
R1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a47_PORT_A_data_in_reg = DFFE(R1_ram_block2a47_PORT_A_data_in, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_data_in = ~GND;
R1_ram_block2a47_PORT_B_data_in_reg = DFFE(R1_ram_block2a47_PORT_B_data_in, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a47_PORT_A_address_reg = DFFE(R1_ram_block2a47_PORT_A_address, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a47_PORT_B_address_reg = DFFE(R1_ram_block2a47_PORT_B_address, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_write_enable = GND;
R1_ram_block2a47_PORT_A_write_enable_reg = DFFE(R1_ram_block2a47_PORT_A_write_enable, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_write_enable = GND;
R1_ram_block2a47_PORT_B_write_enable_reg = DFFE(R1_ram_block2a47_PORT_B_write_enable, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_clock_0 = M1__clk0;
R1_ram_block2a47_clock_1 = GND;
R1_ram_block2a47_clock_enable_0 = S3_w_anode3395w[3];
R1_ram_block2a47_clock_enable_1 = GND;
R1_ram_block2a47_PORT_A_data_out = MEMORY(R1_ram_block2a47_PORT_A_data_in_reg, R1_ram_block2a47_PORT_B_data_in_reg, R1_ram_block2a47_PORT_A_address_reg, R1_ram_block2a47_PORT_B_address_reg, R1_ram_block2a47_PORT_A_write_enable_reg, R1_ram_block2a47_PORT_B_write_enable_reg, , , R1_ram_block2a47_clock_0, R1_ram_block2a47_clock_1, R1_ram_block2a47_clock_enable_0, R1_ram_block2a47_clock_enable_1, , );
R1_ram_block2a47_PORT_A_data_out_reg = DFFE(R1_ram_block2a47_PORT_A_data_out, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1M2396Q = R1_ram_block2a47_PORT_A_data_out_reg[5];

--R1M2397Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT6
R1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a47_PORT_A_data_in_reg = DFFE(R1_ram_block2a47_PORT_A_data_in, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_data_in = ~GND;
R1_ram_block2a47_PORT_B_data_in_reg = DFFE(R1_ram_block2a47_PORT_B_data_in, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a47_PORT_A_address_reg = DFFE(R1_ram_block2a47_PORT_A_address, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a47_PORT_B_address_reg = DFFE(R1_ram_block2a47_PORT_B_address, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_write_enable = GND;
R1_ram_block2a47_PORT_A_write_enable_reg = DFFE(R1_ram_block2a47_PORT_A_write_enable, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_write_enable = GND;
R1_ram_block2a47_PORT_B_write_enable_reg = DFFE(R1_ram_block2a47_PORT_B_write_enable, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_clock_0 = M1__clk0;
R1_ram_block2a47_clock_1 = GND;
R1_ram_block2a47_clock_enable_0 = S3_w_anode3395w[3];
R1_ram_block2a47_clock_enable_1 = GND;
R1_ram_block2a47_PORT_A_data_out = MEMORY(R1_ram_block2a47_PORT_A_data_in_reg, R1_ram_block2a47_PORT_B_data_in_reg, R1_ram_block2a47_PORT_A_address_reg, R1_ram_block2a47_PORT_B_address_reg, R1_ram_block2a47_PORT_A_write_enable_reg, R1_ram_block2a47_PORT_B_write_enable_reg, , , R1_ram_block2a47_clock_0, R1_ram_block2a47_clock_1, R1_ram_block2a47_clock_enable_0, R1_ram_block2a47_clock_enable_1, , );
R1_ram_block2a47_PORT_A_data_out_reg = DFFE(R1_ram_block2a47_PORT_A_data_out, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1M2397Q = R1_ram_block2a47_PORT_A_data_out_reg[6];

--R1M2398Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT7
R1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a47_PORT_A_data_in_reg = DFFE(R1_ram_block2a47_PORT_A_data_in, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_data_in = ~GND;
R1_ram_block2a47_PORT_B_data_in_reg = DFFE(R1_ram_block2a47_PORT_B_data_in, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a47_PORT_A_address_reg = DFFE(R1_ram_block2a47_PORT_A_address, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a47_PORT_B_address_reg = DFFE(R1_ram_block2a47_PORT_B_address, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_write_enable = GND;
R1_ram_block2a47_PORT_A_write_enable_reg = DFFE(R1_ram_block2a47_PORT_A_write_enable, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_write_enable = GND;
R1_ram_block2a47_PORT_B_write_enable_reg = DFFE(R1_ram_block2a47_PORT_B_write_enable, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_clock_0 = M1__clk0;
R1_ram_block2a47_clock_1 = GND;
R1_ram_block2a47_clock_enable_0 = S3_w_anode3395w[3];
R1_ram_block2a47_clock_enable_1 = GND;
R1_ram_block2a47_PORT_A_data_out = MEMORY(R1_ram_block2a47_PORT_A_data_in_reg, R1_ram_block2a47_PORT_B_data_in_reg, R1_ram_block2a47_PORT_A_address_reg, R1_ram_block2a47_PORT_B_address_reg, R1_ram_block2a47_PORT_A_write_enable_reg, R1_ram_block2a47_PORT_B_write_enable_reg, , , R1_ram_block2a47_clock_0, R1_ram_block2a47_clock_1, R1_ram_block2a47_clock_enable_0, R1_ram_block2a47_clock_enable_1, , );
R1_ram_block2a47_PORT_A_data_out_reg = DFFE(R1_ram_block2a47_PORT_A_data_out, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1M2398Q = R1_ram_block2a47_PORT_A_data_out_reg[7];


--T1L229 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6591w~48
T1L229 = R1_address_reg_a[7] & (T1L228 & (R1M2396Q) # !T1L228 & R1M2346Q) # !R1_address_reg_a[7] & (T1L228);


--R1_ram_block2a13 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a13_PORT_A_data_in_reg = DFFE(R1_ram_block2a13_PORT_A_data_in, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_data_in = ~GND;
R1_ram_block2a13_PORT_B_data_in_reg = DFFE(R1_ram_block2a13_PORT_B_data_in, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a13_PORT_A_address_reg = DFFE(R1_ram_block2a13_PORT_A_address, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a13_PORT_B_address_reg = DFFE(R1_ram_block2a13_PORT_B_address, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_write_enable = GND;
R1_ram_block2a13_PORT_A_write_enable_reg = DFFE(R1_ram_block2a13_PORT_A_write_enable, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_write_enable = GND;
R1_ram_block2a13_PORT_B_write_enable_reg = DFFE(R1_ram_block2a13_PORT_B_write_enable, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_clock_0 = M1__clk0;
R1_ram_block2a13_clock_1 = GND;
R1_ram_block2a13_clock_enable_0 = S3_w_anode3003w[3];
R1_ram_block2a13_clock_enable_1 = GND;
R1_ram_block2a13_PORT_A_data_out = MEMORY(R1_ram_block2a13_PORT_A_data_in_reg, R1_ram_block2a13_PORT_B_data_in_reg, R1_ram_block2a13_PORT_A_address_reg, R1_ram_block2a13_PORT_B_address_reg, R1_ram_block2a13_PORT_A_write_enable_reg, R1_ram_block2a13_PORT_B_write_enable_reg, , , R1_ram_block2a13_clock_0, R1_ram_block2a13_clock_1, R1_ram_block2a13_clock_enable_0, R1_ram_block2a13_clock_enable_1, , );
R1_ram_block2a13_PORT_A_data_out_reg = DFFE(R1_ram_block2a13_PORT_A_data_out, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13 = R1_ram_block2a13_PORT_A_data_out_reg[0];

--R1M692Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT1
R1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a13_PORT_A_data_in_reg = DFFE(R1_ram_block2a13_PORT_A_data_in, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_data_in = ~GND;
R1_ram_block2a13_PORT_B_data_in_reg = DFFE(R1_ram_block2a13_PORT_B_data_in, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a13_PORT_A_address_reg = DFFE(R1_ram_block2a13_PORT_A_address, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a13_PORT_B_address_reg = DFFE(R1_ram_block2a13_PORT_B_address, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_write_enable = GND;
R1_ram_block2a13_PORT_A_write_enable_reg = DFFE(R1_ram_block2a13_PORT_A_write_enable, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_write_enable = GND;
R1_ram_block2a13_PORT_B_write_enable_reg = DFFE(R1_ram_block2a13_PORT_B_write_enable, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_clock_0 = M1__clk0;
R1_ram_block2a13_clock_1 = GND;
R1_ram_block2a13_clock_enable_0 = S3_w_anode3003w[3];
R1_ram_block2a13_clock_enable_1 = GND;
R1_ram_block2a13_PORT_A_data_out = MEMORY(R1_ram_block2a13_PORT_A_data_in_reg, R1_ram_block2a13_PORT_B_data_in_reg, R1_ram_block2a13_PORT_A_address_reg, R1_ram_block2a13_PORT_B_address_reg, R1_ram_block2a13_PORT_A_write_enable_reg, R1_ram_block2a13_PORT_B_write_enable_reg, , , R1_ram_block2a13_clock_0, R1_ram_block2a13_clock_1, R1_ram_block2a13_clock_enable_0, R1_ram_block2a13_clock_enable_1, , );
R1_ram_block2a13_PORT_A_data_out_reg = DFFE(R1_ram_block2a13_PORT_A_data_out, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1M692Q = R1_ram_block2a13_PORT_A_data_out_reg[1];

--R1M693Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT2
R1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a13_PORT_A_data_in_reg = DFFE(R1_ram_block2a13_PORT_A_data_in, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_data_in = ~GND;
R1_ram_block2a13_PORT_B_data_in_reg = DFFE(R1_ram_block2a13_PORT_B_data_in, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a13_PORT_A_address_reg = DFFE(R1_ram_block2a13_PORT_A_address, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a13_PORT_B_address_reg = DFFE(R1_ram_block2a13_PORT_B_address, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_write_enable = GND;
R1_ram_block2a13_PORT_A_write_enable_reg = DFFE(R1_ram_block2a13_PORT_A_write_enable, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_write_enable = GND;
R1_ram_block2a13_PORT_B_write_enable_reg = DFFE(R1_ram_block2a13_PORT_B_write_enable, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_clock_0 = M1__clk0;
R1_ram_block2a13_clock_1 = GND;
R1_ram_block2a13_clock_enable_0 = S3_w_anode3003w[3];
R1_ram_block2a13_clock_enable_1 = GND;
R1_ram_block2a13_PORT_A_data_out = MEMORY(R1_ram_block2a13_PORT_A_data_in_reg, R1_ram_block2a13_PORT_B_data_in_reg, R1_ram_block2a13_PORT_A_address_reg, R1_ram_block2a13_PORT_B_address_reg, R1_ram_block2a13_PORT_A_write_enable_reg, R1_ram_block2a13_PORT_B_write_enable_reg, , , R1_ram_block2a13_clock_0, R1_ram_block2a13_clock_1, R1_ram_block2a13_clock_enable_0, R1_ram_block2a13_clock_enable_1, , );
R1_ram_block2a13_PORT_A_data_out_reg = DFFE(R1_ram_block2a13_PORT_A_data_out, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1M693Q = R1_ram_block2a13_PORT_A_data_out_reg[2];

--R1M694Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT3
R1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a13_PORT_A_data_in_reg = DFFE(R1_ram_block2a13_PORT_A_data_in, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_data_in = ~GND;
R1_ram_block2a13_PORT_B_data_in_reg = DFFE(R1_ram_block2a13_PORT_B_data_in, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a13_PORT_A_address_reg = DFFE(R1_ram_block2a13_PORT_A_address, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a13_PORT_B_address_reg = DFFE(R1_ram_block2a13_PORT_B_address, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_write_enable = GND;
R1_ram_block2a13_PORT_A_write_enable_reg = DFFE(R1_ram_block2a13_PORT_A_write_enable, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_write_enable = GND;
R1_ram_block2a13_PORT_B_write_enable_reg = DFFE(R1_ram_block2a13_PORT_B_write_enable, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_clock_0 = M1__clk0;
R1_ram_block2a13_clock_1 = GND;
R1_ram_block2a13_clock_enable_0 = S3_w_anode3003w[3];
R1_ram_block2a13_clock_enable_1 = GND;
R1_ram_block2a13_PORT_A_data_out = MEMORY(R1_ram_block2a13_PORT_A_data_in_reg, R1_ram_block2a13_PORT_B_data_in_reg, R1_ram_block2a13_PORT_A_address_reg, R1_ram_block2a13_PORT_B_address_reg, R1_ram_block2a13_PORT_A_write_enable_reg, R1_ram_block2a13_PORT_B_write_enable_reg, , , R1_ram_block2a13_clock_0, R1_ram_block2a13_clock_1, R1_ram_block2a13_clock_enable_0, R1_ram_block2a13_clock_enable_1, , );
R1_ram_block2a13_PORT_A_data_out_reg = DFFE(R1_ram_block2a13_PORT_A_data_out, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1M694Q = R1_ram_block2a13_PORT_A_data_out_reg[3];

--R1M695Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT4
R1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a13_PORT_A_data_in_reg = DFFE(R1_ram_block2a13_PORT_A_data_in, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_data_in = ~GND;
R1_ram_block2a13_PORT_B_data_in_reg = DFFE(R1_ram_block2a13_PORT_B_data_in, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a13_PORT_A_address_reg = DFFE(R1_ram_block2a13_PORT_A_address, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a13_PORT_B_address_reg = DFFE(R1_ram_block2a13_PORT_B_address, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_write_enable = GND;
R1_ram_block2a13_PORT_A_write_enable_reg = DFFE(R1_ram_block2a13_PORT_A_write_enable, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_write_enable = GND;
R1_ram_block2a13_PORT_B_write_enable_reg = DFFE(R1_ram_block2a13_PORT_B_write_enable, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_clock_0 = M1__clk0;
R1_ram_block2a13_clock_1 = GND;
R1_ram_block2a13_clock_enable_0 = S3_w_anode3003w[3];
R1_ram_block2a13_clock_enable_1 = GND;
R1_ram_block2a13_PORT_A_data_out = MEMORY(R1_ram_block2a13_PORT_A_data_in_reg, R1_ram_block2a13_PORT_B_data_in_reg, R1_ram_block2a13_PORT_A_address_reg, R1_ram_block2a13_PORT_B_address_reg, R1_ram_block2a13_PORT_A_write_enable_reg, R1_ram_block2a13_PORT_B_write_enable_reg, , , R1_ram_block2a13_clock_0, R1_ram_block2a13_clock_1, R1_ram_block2a13_clock_enable_0, R1_ram_block2a13_clock_enable_1, , );
R1_ram_block2a13_PORT_A_data_out_reg = DFFE(R1_ram_block2a13_PORT_A_data_out, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1M695Q = R1_ram_block2a13_PORT_A_data_out_reg[4];

--R1M696Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT5
R1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a13_PORT_A_data_in_reg = DFFE(R1_ram_block2a13_PORT_A_data_in, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_data_in = ~GND;
R1_ram_block2a13_PORT_B_data_in_reg = DFFE(R1_ram_block2a13_PORT_B_data_in, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a13_PORT_A_address_reg = DFFE(R1_ram_block2a13_PORT_A_address, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a13_PORT_B_address_reg = DFFE(R1_ram_block2a13_PORT_B_address, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_write_enable = GND;
R1_ram_block2a13_PORT_A_write_enable_reg = DFFE(R1_ram_block2a13_PORT_A_write_enable, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_write_enable = GND;
R1_ram_block2a13_PORT_B_write_enable_reg = DFFE(R1_ram_block2a13_PORT_B_write_enable, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_clock_0 = M1__clk0;
R1_ram_block2a13_clock_1 = GND;
R1_ram_block2a13_clock_enable_0 = S3_w_anode3003w[3];
R1_ram_block2a13_clock_enable_1 = GND;
R1_ram_block2a13_PORT_A_data_out = MEMORY(R1_ram_block2a13_PORT_A_data_in_reg, R1_ram_block2a13_PORT_B_data_in_reg, R1_ram_block2a13_PORT_A_address_reg, R1_ram_block2a13_PORT_B_address_reg, R1_ram_block2a13_PORT_A_write_enable_reg, R1_ram_block2a13_PORT_B_write_enable_reg, , , R1_ram_block2a13_clock_0, R1_ram_block2a13_clock_1, R1_ram_block2a13_clock_enable_0, R1_ram_block2a13_clock_enable_1, , );
R1_ram_block2a13_PORT_A_data_out_reg = DFFE(R1_ram_block2a13_PORT_A_data_out, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1M696Q = R1_ram_block2a13_PORT_A_data_out_reg[5];

--R1M697Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT6
R1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a13_PORT_A_data_in_reg = DFFE(R1_ram_block2a13_PORT_A_data_in, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_data_in = ~GND;
R1_ram_block2a13_PORT_B_data_in_reg = DFFE(R1_ram_block2a13_PORT_B_data_in, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a13_PORT_A_address_reg = DFFE(R1_ram_block2a13_PORT_A_address, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a13_PORT_B_address_reg = DFFE(R1_ram_block2a13_PORT_B_address, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_write_enable = GND;
R1_ram_block2a13_PORT_A_write_enable_reg = DFFE(R1_ram_block2a13_PORT_A_write_enable, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_write_enable = GND;
R1_ram_block2a13_PORT_B_write_enable_reg = DFFE(R1_ram_block2a13_PORT_B_write_enable, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_clock_0 = M1__clk0;
R1_ram_block2a13_clock_1 = GND;
R1_ram_block2a13_clock_enable_0 = S3_w_anode3003w[3];
R1_ram_block2a13_clock_enable_1 = GND;
R1_ram_block2a13_PORT_A_data_out = MEMORY(R1_ram_block2a13_PORT_A_data_in_reg, R1_ram_block2a13_PORT_B_data_in_reg, R1_ram_block2a13_PORT_A_address_reg, R1_ram_block2a13_PORT_B_address_reg, R1_ram_block2a13_PORT_A_write_enable_reg, R1_ram_block2a13_PORT_B_write_enable_reg, , , R1_ram_block2a13_clock_0, R1_ram_block2a13_clock_1, R1_ram_block2a13_clock_enable_0, R1_ram_block2a13_clock_enable_1, , );
R1_ram_block2a13_PORT_A_data_out_reg = DFFE(R1_ram_block2a13_PORT_A_data_out, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1M697Q = R1_ram_block2a13_PORT_A_data_out_reg[6];

--R1M698Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT7
R1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a13_PORT_A_data_in_reg = DFFE(R1_ram_block2a13_PORT_A_data_in, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_data_in = ~GND;
R1_ram_block2a13_PORT_B_data_in_reg = DFFE(R1_ram_block2a13_PORT_B_data_in, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a13_PORT_A_address_reg = DFFE(R1_ram_block2a13_PORT_A_address, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a13_PORT_B_address_reg = DFFE(R1_ram_block2a13_PORT_B_address, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_write_enable = GND;
R1_ram_block2a13_PORT_A_write_enable_reg = DFFE(R1_ram_block2a13_PORT_A_write_enable, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_write_enable = GND;
R1_ram_block2a13_PORT_B_write_enable_reg = DFFE(R1_ram_block2a13_PORT_B_write_enable, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_clock_0 = M1__clk0;
R1_ram_block2a13_clock_1 = GND;
R1_ram_block2a13_clock_enable_0 = S3_w_anode3003w[3];
R1_ram_block2a13_clock_enable_1 = GND;
R1_ram_block2a13_PORT_A_data_out = MEMORY(R1_ram_block2a13_PORT_A_data_in_reg, R1_ram_block2a13_PORT_B_data_in_reg, R1_ram_block2a13_PORT_A_address_reg, R1_ram_block2a13_PORT_B_address_reg, R1_ram_block2a13_PORT_A_write_enable_reg, R1_ram_block2a13_PORT_B_write_enable_reg, , , R1_ram_block2a13_clock_0, R1_ram_block2a13_clock_1, R1_ram_block2a13_clock_enable_0, R1_ram_block2a13_clock_enable_1, , );
R1_ram_block2a13_PORT_A_data_out_reg = DFFE(R1_ram_block2a13_PORT_A_data_out, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1M698Q = R1_ram_block2a13_PORT_A_data_out_reg[7];


--R1_ram_block2a14 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a14_PORT_A_data_in_reg = DFFE(R1_ram_block2a14_PORT_A_data_in, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_data_in = ~GND;
R1_ram_block2a14_PORT_B_data_in_reg = DFFE(R1_ram_block2a14_PORT_B_data_in, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a14_PORT_A_address_reg = DFFE(R1_ram_block2a14_PORT_A_address, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a14_PORT_B_address_reg = DFFE(R1_ram_block2a14_PORT_B_address, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_write_enable = GND;
R1_ram_block2a14_PORT_A_write_enable_reg = DFFE(R1_ram_block2a14_PORT_A_write_enable, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_write_enable = GND;
R1_ram_block2a14_PORT_B_write_enable_reg = DFFE(R1_ram_block2a14_PORT_B_write_enable, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_clock_0 = M1__clk0;
R1_ram_block2a14_clock_1 = GND;
R1_ram_block2a14_clock_enable_0 = S3_w_anode3013w[3];
R1_ram_block2a14_clock_enable_1 = GND;
R1_ram_block2a14_PORT_A_data_out = MEMORY(R1_ram_block2a14_PORT_A_data_in_reg, R1_ram_block2a14_PORT_B_data_in_reg, R1_ram_block2a14_PORT_A_address_reg, R1_ram_block2a14_PORT_B_address_reg, R1_ram_block2a14_PORT_A_write_enable_reg, R1_ram_block2a14_PORT_B_write_enable_reg, , , R1_ram_block2a14_clock_0, R1_ram_block2a14_clock_1, R1_ram_block2a14_clock_enable_0, R1_ram_block2a14_clock_enable_1, , );
R1_ram_block2a14_PORT_A_data_out_reg = DFFE(R1_ram_block2a14_PORT_A_data_out, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14 = R1_ram_block2a14_PORT_A_data_out_reg[0];

--R1M742Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT1
R1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a14_PORT_A_data_in_reg = DFFE(R1_ram_block2a14_PORT_A_data_in, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_data_in = ~GND;
R1_ram_block2a14_PORT_B_data_in_reg = DFFE(R1_ram_block2a14_PORT_B_data_in, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a14_PORT_A_address_reg = DFFE(R1_ram_block2a14_PORT_A_address, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a14_PORT_B_address_reg = DFFE(R1_ram_block2a14_PORT_B_address, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_write_enable = GND;
R1_ram_block2a14_PORT_A_write_enable_reg = DFFE(R1_ram_block2a14_PORT_A_write_enable, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_write_enable = GND;
R1_ram_block2a14_PORT_B_write_enable_reg = DFFE(R1_ram_block2a14_PORT_B_write_enable, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_clock_0 = M1__clk0;
R1_ram_block2a14_clock_1 = GND;
R1_ram_block2a14_clock_enable_0 = S3_w_anode3013w[3];
R1_ram_block2a14_clock_enable_1 = GND;
R1_ram_block2a14_PORT_A_data_out = MEMORY(R1_ram_block2a14_PORT_A_data_in_reg, R1_ram_block2a14_PORT_B_data_in_reg, R1_ram_block2a14_PORT_A_address_reg, R1_ram_block2a14_PORT_B_address_reg, R1_ram_block2a14_PORT_A_write_enable_reg, R1_ram_block2a14_PORT_B_write_enable_reg, , , R1_ram_block2a14_clock_0, R1_ram_block2a14_clock_1, R1_ram_block2a14_clock_enable_0, R1_ram_block2a14_clock_enable_1, , );
R1_ram_block2a14_PORT_A_data_out_reg = DFFE(R1_ram_block2a14_PORT_A_data_out, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1M742Q = R1_ram_block2a14_PORT_A_data_out_reg[1];

--R1M743Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT2
R1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a14_PORT_A_data_in_reg = DFFE(R1_ram_block2a14_PORT_A_data_in, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_data_in = ~GND;
R1_ram_block2a14_PORT_B_data_in_reg = DFFE(R1_ram_block2a14_PORT_B_data_in, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a14_PORT_A_address_reg = DFFE(R1_ram_block2a14_PORT_A_address, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a14_PORT_B_address_reg = DFFE(R1_ram_block2a14_PORT_B_address, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_write_enable = GND;
R1_ram_block2a14_PORT_A_write_enable_reg = DFFE(R1_ram_block2a14_PORT_A_write_enable, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_write_enable = GND;
R1_ram_block2a14_PORT_B_write_enable_reg = DFFE(R1_ram_block2a14_PORT_B_write_enable, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_clock_0 = M1__clk0;
R1_ram_block2a14_clock_1 = GND;
R1_ram_block2a14_clock_enable_0 = S3_w_anode3013w[3];
R1_ram_block2a14_clock_enable_1 = GND;
R1_ram_block2a14_PORT_A_data_out = MEMORY(R1_ram_block2a14_PORT_A_data_in_reg, R1_ram_block2a14_PORT_B_data_in_reg, R1_ram_block2a14_PORT_A_address_reg, R1_ram_block2a14_PORT_B_address_reg, R1_ram_block2a14_PORT_A_write_enable_reg, R1_ram_block2a14_PORT_B_write_enable_reg, , , R1_ram_block2a14_clock_0, R1_ram_block2a14_clock_1, R1_ram_block2a14_clock_enable_0, R1_ram_block2a14_clock_enable_1, , );
R1_ram_block2a14_PORT_A_data_out_reg = DFFE(R1_ram_block2a14_PORT_A_data_out, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1M743Q = R1_ram_block2a14_PORT_A_data_out_reg[2];

--R1M744Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT3
R1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a14_PORT_A_data_in_reg = DFFE(R1_ram_block2a14_PORT_A_data_in, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_data_in = ~GND;
R1_ram_block2a14_PORT_B_data_in_reg = DFFE(R1_ram_block2a14_PORT_B_data_in, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a14_PORT_A_address_reg = DFFE(R1_ram_block2a14_PORT_A_address, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a14_PORT_B_address_reg = DFFE(R1_ram_block2a14_PORT_B_address, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_write_enable = GND;
R1_ram_block2a14_PORT_A_write_enable_reg = DFFE(R1_ram_block2a14_PORT_A_write_enable, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_write_enable = GND;
R1_ram_block2a14_PORT_B_write_enable_reg = DFFE(R1_ram_block2a14_PORT_B_write_enable, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_clock_0 = M1__clk0;
R1_ram_block2a14_clock_1 = GND;
R1_ram_block2a14_clock_enable_0 = S3_w_anode3013w[3];
R1_ram_block2a14_clock_enable_1 = GND;
R1_ram_block2a14_PORT_A_data_out = MEMORY(R1_ram_block2a14_PORT_A_data_in_reg, R1_ram_block2a14_PORT_B_data_in_reg, R1_ram_block2a14_PORT_A_address_reg, R1_ram_block2a14_PORT_B_address_reg, R1_ram_block2a14_PORT_A_write_enable_reg, R1_ram_block2a14_PORT_B_write_enable_reg, , , R1_ram_block2a14_clock_0, R1_ram_block2a14_clock_1, R1_ram_block2a14_clock_enable_0, R1_ram_block2a14_clock_enable_1, , );
R1_ram_block2a14_PORT_A_data_out_reg = DFFE(R1_ram_block2a14_PORT_A_data_out, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1M744Q = R1_ram_block2a14_PORT_A_data_out_reg[3];

--R1M745Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT4
R1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a14_PORT_A_data_in_reg = DFFE(R1_ram_block2a14_PORT_A_data_in, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_data_in = ~GND;
R1_ram_block2a14_PORT_B_data_in_reg = DFFE(R1_ram_block2a14_PORT_B_data_in, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a14_PORT_A_address_reg = DFFE(R1_ram_block2a14_PORT_A_address, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a14_PORT_B_address_reg = DFFE(R1_ram_block2a14_PORT_B_address, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_write_enable = GND;
R1_ram_block2a14_PORT_A_write_enable_reg = DFFE(R1_ram_block2a14_PORT_A_write_enable, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_write_enable = GND;
R1_ram_block2a14_PORT_B_write_enable_reg = DFFE(R1_ram_block2a14_PORT_B_write_enable, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_clock_0 = M1__clk0;
R1_ram_block2a14_clock_1 = GND;
R1_ram_block2a14_clock_enable_0 = S3_w_anode3013w[3];
R1_ram_block2a14_clock_enable_1 = GND;
R1_ram_block2a14_PORT_A_data_out = MEMORY(R1_ram_block2a14_PORT_A_data_in_reg, R1_ram_block2a14_PORT_B_data_in_reg, R1_ram_block2a14_PORT_A_address_reg, R1_ram_block2a14_PORT_B_address_reg, R1_ram_block2a14_PORT_A_write_enable_reg, R1_ram_block2a14_PORT_B_write_enable_reg, , , R1_ram_block2a14_clock_0, R1_ram_block2a14_clock_1, R1_ram_block2a14_clock_enable_0, R1_ram_block2a14_clock_enable_1, , );
R1_ram_block2a14_PORT_A_data_out_reg = DFFE(R1_ram_block2a14_PORT_A_data_out, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1M745Q = R1_ram_block2a14_PORT_A_data_out_reg[4];

--R1M746Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT5
R1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a14_PORT_A_data_in_reg = DFFE(R1_ram_block2a14_PORT_A_data_in, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_data_in = ~GND;
R1_ram_block2a14_PORT_B_data_in_reg = DFFE(R1_ram_block2a14_PORT_B_data_in, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a14_PORT_A_address_reg = DFFE(R1_ram_block2a14_PORT_A_address, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a14_PORT_B_address_reg = DFFE(R1_ram_block2a14_PORT_B_address, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_write_enable = GND;
R1_ram_block2a14_PORT_A_write_enable_reg = DFFE(R1_ram_block2a14_PORT_A_write_enable, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_write_enable = GND;
R1_ram_block2a14_PORT_B_write_enable_reg = DFFE(R1_ram_block2a14_PORT_B_write_enable, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_clock_0 = M1__clk0;
R1_ram_block2a14_clock_1 = GND;
R1_ram_block2a14_clock_enable_0 = S3_w_anode3013w[3];
R1_ram_block2a14_clock_enable_1 = GND;
R1_ram_block2a14_PORT_A_data_out = MEMORY(R1_ram_block2a14_PORT_A_data_in_reg, R1_ram_block2a14_PORT_B_data_in_reg, R1_ram_block2a14_PORT_A_address_reg, R1_ram_block2a14_PORT_B_address_reg, R1_ram_block2a14_PORT_A_write_enable_reg, R1_ram_block2a14_PORT_B_write_enable_reg, , , R1_ram_block2a14_clock_0, R1_ram_block2a14_clock_1, R1_ram_block2a14_clock_enable_0, R1_ram_block2a14_clock_enable_1, , );
R1_ram_block2a14_PORT_A_data_out_reg = DFFE(R1_ram_block2a14_PORT_A_data_out, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1M746Q = R1_ram_block2a14_PORT_A_data_out_reg[5];

--R1M747Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT6
R1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a14_PORT_A_data_in_reg = DFFE(R1_ram_block2a14_PORT_A_data_in, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_data_in = ~GND;
R1_ram_block2a14_PORT_B_data_in_reg = DFFE(R1_ram_block2a14_PORT_B_data_in, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a14_PORT_A_address_reg = DFFE(R1_ram_block2a14_PORT_A_address, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a14_PORT_B_address_reg = DFFE(R1_ram_block2a14_PORT_B_address, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_write_enable = GND;
R1_ram_block2a14_PORT_A_write_enable_reg = DFFE(R1_ram_block2a14_PORT_A_write_enable, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_write_enable = GND;
R1_ram_block2a14_PORT_B_write_enable_reg = DFFE(R1_ram_block2a14_PORT_B_write_enable, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_clock_0 = M1__clk0;
R1_ram_block2a14_clock_1 = GND;
R1_ram_block2a14_clock_enable_0 = S3_w_anode3013w[3];
R1_ram_block2a14_clock_enable_1 = GND;
R1_ram_block2a14_PORT_A_data_out = MEMORY(R1_ram_block2a14_PORT_A_data_in_reg, R1_ram_block2a14_PORT_B_data_in_reg, R1_ram_block2a14_PORT_A_address_reg, R1_ram_block2a14_PORT_B_address_reg, R1_ram_block2a14_PORT_A_write_enable_reg, R1_ram_block2a14_PORT_B_write_enable_reg, , , R1_ram_block2a14_clock_0, R1_ram_block2a14_clock_1, R1_ram_block2a14_clock_enable_0, R1_ram_block2a14_clock_enable_1, , );
R1_ram_block2a14_PORT_A_data_out_reg = DFFE(R1_ram_block2a14_PORT_A_data_out, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1M747Q = R1_ram_block2a14_PORT_A_data_out_reg[6];

--R1M748Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT7
R1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a14_PORT_A_data_in_reg = DFFE(R1_ram_block2a14_PORT_A_data_in, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_data_in = ~GND;
R1_ram_block2a14_PORT_B_data_in_reg = DFFE(R1_ram_block2a14_PORT_B_data_in, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a14_PORT_A_address_reg = DFFE(R1_ram_block2a14_PORT_A_address, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a14_PORT_B_address_reg = DFFE(R1_ram_block2a14_PORT_B_address, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_write_enable = GND;
R1_ram_block2a14_PORT_A_write_enable_reg = DFFE(R1_ram_block2a14_PORT_A_write_enable, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_write_enable = GND;
R1_ram_block2a14_PORT_B_write_enable_reg = DFFE(R1_ram_block2a14_PORT_B_write_enable, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_clock_0 = M1__clk0;
R1_ram_block2a14_clock_1 = GND;
R1_ram_block2a14_clock_enable_0 = S3_w_anode3013w[3];
R1_ram_block2a14_clock_enable_1 = GND;
R1_ram_block2a14_PORT_A_data_out = MEMORY(R1_ram_block2a14_PORT_A_data_in_reg, R1_ram_block2a14_PORT_B_data_in_reg, R1_ram_block2a14_PORT_A_address_reg, R1_ram_block2a14_PORT_B_address_reg, R1_ram_block2a14_PORT_A_write_enable_reg, R1_ram_block2a14_PORT_B_write_enable_reg, , , R1_ram_block2a14_clock_0, R1_ram_block2a14_clock_1, R1_ram_block2a14_clock_enable_0, R1_ram_block2a14_clock_enable_1, , );
R1_ram_block2a14_PORT_A_data_out_reg = DFFE(R1_ram_block2a14_PORT_A_data_out, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1M748Q = R1_ram_block2a14_PORT_A_data_out_reg[7];


--R1_ram_block2a12 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a12_PORT_A_data_in_reg = DFFE(R1_ram_block2a12_PORT_A_data_in, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_data_in = ~GND;
R1_ram_block2a12_PORT_B_data_in_reg = DFFE(R1_ram_block2a12_PORT_B_data_in, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a12_PORT_A_address_reg = DFFE(R1_ram_block2a12_PORT_A_address, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a12_PORT_B_address_reg = DFFE(R1_ram_block2a12_PORT_B_address, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_write_enable = GND;
R1_ram_block2a12_PORT_A_write_enable_reg = DFFE(R1_ram_block2a12_PORT_A_write_enable, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_write_enable = GND;
R1_ram_block2a12_PORT_B_write_enable_reg = DFFE(R1_ram_block2a12_PORT_B_write_enable, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_clock_0 = M1__clk0;
R1_ram_block2a12_clock_1 = GND;
R1_ram_block2a12_clock_enable_0 = S3_w_anode2993w[3];
R1_ram_block2a12_clock_enable_1 = GND;
R1_ram_block2a12_PORT_A_data_out = MEMORY(R1_ram_block2a12_PORT_A_data_in_reg, R1_ram_block2a12_PORT_B_data_in_reg, R1_ram_block2a12_PORT_A_address_reg, R1_ram_block2a12_PORT_B_address_reg, R1_ram_block2a12_PORT_A_write_enable_reg, R1_ram_block2a12_PORT_B_write_enable_reg, , , R1_ram_block2a12_clock_0, R1_ram_block2a12_clock_1, R1_ram_block2a12_clock_enable_0, R1_ram_block2a12_clock_enable_1, , );
R1_ram_block2a12_PORT_A_data_out_reg = DFFE(R1_ram_block2a12_PORT_A_data_out, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12 = R1_ram_block2a12_PORT_A_data_out_reg[0];

--R1M642Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT1
R1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a12_PORT_A_data_in_reg = DFFE(R1_ram_block2a12_PORT_A_data_in, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_data_in = ~GND;
R1_ram_block2a12_PORT_B_data_in_reg = DFFE(R1_ram_block2a12_PORT_B_data_in, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a12_PORT_A_address_reg = DFFE(R1_ram_block2a12_PORT_A_address, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a12_PORT_B_address_reg = DFFE(R1_ram_block2a12_PORT_B_address, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_write_enable = GND;
R1_ram_block2a12_PORT_A_write_enable_reg = DFFE(R1_ram_block2a12_PORT_A_write_enable, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_write_enable = GND;
R1_ram_block2a12_PORT_B_write_enable_reg = DFFE(R1_ram_block2a12_PORT_B_write_enable, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_clock_0 = M1__clk0;
R1_ram_block2a12_clock_1 = GND;
R1_ram_block2a12_clock_enable_0 = S3_w_anode2993w[3];
R1_ram_block2a12_clock_enable_1 = GND;
R1_ram_block2a12_PORT_A_data_out = MEMORY(R1_ram_block2a12_PORT_A_data_in_reg, R1_ram_block2a12_PORT_B_data_in_reg, R1_ram_block2a12_PORT_A_address_reg, R1_ram_block2a12_PORT_B_address_reg, R1_ram_block2a12_PORT_A_write_enable_reg, R1_ram_block2a12_PORT_B_write_enable_reg, , , R1_ram_block2a12_clock_0, R1_ram_block2a12_clock_1, R1_ram_block2a12_clock_enable_0, R1_ram_block2a12_clock_enable_1, , );
R1_ram_block2a12_PORT_A_data_out_reg = DFFE(R1_ram_block2a12_PORT_A_data_out, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1M642Q = R1_ram_block2a12_PORT_A_data_out_reg[1];

--R1M643Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT2
R1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a12_PORT_A_data_in_reg = DFFE(R1_ram_block2a12_PORT_A_data_in, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_data_in = ~GND;
R1_ram_block2a12_PORT_B_data_in_reg = DFFE(R1_ram_block2a12_PORT_B_data_in, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a12_PORT_A_address_reg = DFFE(R1_ram_block2a12_PORT_A_address, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a12_PORT_B_address_reg = DFFE(R1_ram_block2a12_PORT_B_address, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_write_enable = GND;
R1_ram_block2a12_PORT_A_write_enable_reg = DFFE(R1_ram_block2a12_PORT_A_write_enable, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_write_enable = GND;
R1_ram_block2a12_PORT_B_write_enable_reg = DFFE(R1_ram_block2a12_PORT_B_write_enable, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_clock_0 = M1__clk0;
R1_ram_block2a12_clock_1 = GND;
R1_ram_block2a12_clock_enable_0 = S3_w_anode2993w[3];
R1_ram_block2a12_clock_enable_1 = GND;
R1_ram_block2a12_PORT_A_data_out = MEMORY(R1_ram_block2a12_PORT_A_data_in_reg, R1_ram_block2a12_PORT_B_data_in_reg, R1_ram_block2a12_PORT_A_address_reg, R1_ram_block2a12_PORT_B_address_reg, R1_ram_block2a12_PORT_A_write_enable_reg, R1_ram_block2a12_PORT_B_write_enable_reg, , , R1_ram_block2a12_clock_0, R1_ram_block2a12_clock_1, R1_ram_block2a12_clock_enable_0, R1_ram_block2a12_clock_enable_1, , );
R1_ram_block2a12_PORT_A_data_out_reg = DFFE(R1_ram_block2a12_PORT_A_data_out, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1M643Q = R1_ram_block2a12_PORT_A_data_out_reg[2];

--R1M644Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT3
R1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a12_PORT_A_data_in_reg = DFFE(R1_ram_block2a12_PORT_A_data_in, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_data_in = ~GND;
R1_ram_block2a12_PORT_B_data_in_reg = DFFE(R1_ram_block2a12_PORT_B_data_in, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a12_PORT_A_address_reg = DFFE(R1_ram_block2a12_PORT_A_address, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a12_PORT_B_address_reg = DFFE(R1_ram_block2a12_PORT_B_address, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_write_enable = GND;
R1_ram_block2a12_PORT_A_write_enable_reg = DFFE(R1_ram_block2a12_PORT_A_write_enable, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_write_enable = GND;
R1_ram_block2a12_PORT_B_write_enable_reg = DFFE(R1_ram_block2a12_PORT_B_write_enable, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_clock_0 = M1__clk0;
R1_ram_block2a12_clock_1 = GND;
R1_ram_block2a12_clock_enable_0 = S3_w_anode2993w[3];
R1_ram_block2a12_clock_enable_1 = GND;
R1_ram_block2a12_PORT_A_data_out = MEMORY(R1_ram_block2a12_PORT_A_data_in_reg, R1_ram_block2a12_PORT_B_data_in_reg, R1_ram_block2a12_PORT_A_address_reg, R1_ram_block2a12_PORT_B_address_reg, R1_ram_block2a12_PORT_A_write_enable_reg, R1_ram_block2a12_PORT_B_write_enable_reg, , , R1_ram_block2a12_clock_0, R1_ram_block2a12_clock_1, R1_ram_block2a12_clock_enable_0, R1_ram_block2a12_clock_enable_1, , );
R1_ram_block2a12_PORT_A_data_out_reg = DFFE(R1_ram_block2a12_PORT_A_data_out, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1M644Q = R1_ram_block2a12_PORT_A_data_out_reg[3];

--R1M645Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT4
R1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a12_PORT_A_data_in_reg = DFFE(R1_ram_block2a12_PORT_A_data_in, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_data_in = ~GND;
R1_ram_block2a12_PORT_B_data_in_reg = DFFE(R1_ram_block2a12_PORT_B_data_in, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a12_PORT_A_address_reg = DFFE(R1_ram_block2a12_PORT_A_address, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a12_PORT_B_address_reg = DFFE(R1_ram_block2a12_PORT_B_address, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_write_enable = GND;
R1_ram_block2a12_PORT_A_write_enable_reg = DFFE(R1_ram_block2a12_PORT_A_write_enable, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_write_enable = GND;
R1_ram_block2a12_PORT_B_write_enable_reg = DFFE(R1_ram_block2a12_PORT_B_write_enable, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_clock_0 = M1__clk0;
R1_ram_block2a12_clock_1 = GND;
R1_ram_block2a12_clock_enable_0 = S3_w_anode2993w[3];
R1_ram_block2a12_clock_enable_1 = GND;
R1_ram_block2a12_PORT_A_data_out = MEMORY(R1_ram_block2a12_PORT_A_data_in_reg, R1_ram_block2a12_PORT_B_data_in_reg, R1_ram_block2a12_PORT_A_address_reg, R1_ram_block2a12_PORT_B_address_reg, R1_ram_block2a12_PORT_A_write_enable_reg, R1_ram_block2a12_PORT_B_write_enable_reg, , , R1_ram_block2a12_clock_0, R1_ram_block2a12_clock_1, R1_ram_block2a12_clock_enable_0, R1_ram_block2a12_clock_enable_1, , );
R1_ram_block2a12_PORT_A_data_out_reg = DFFE(R1_ram_block2a12_PORT_A_data_out, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1M645Q = R1_ram_block2a12_PORT_A_data_out_reg[4];

--R1M646Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT5
R1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a12_PORT_A_data_in_reg = DFFE(R1_ram_block2a12_PORT_A_data_in, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_data_in = ~GND;
R1_ram_block2a12_PORT_B_data_in_reg = DFFE(R1_ram_block2a12_PORT_B_data_in, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a12_PORT_A_address_reg = DFFE(R1_ram_block2a12_PORT_A_address, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a12_PORT_B_address_reg = DFFE(R1_ram_block2a12_PORT_B_address, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_write_enable = GND;
R1_ram_block2a12_PORT_A_write_enable_reg = DFFE(R1_ram_block2a12_PORT_A_write_enable, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_write_enable = GND;
R1_ram_block2a12_PORT_B_write_enable_reg = DFFE(R1_ram_block2a12_PORT_B_write_enable, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_clock_0 = M1__clk0;
R1_ram_block2a12_clock_1 = GND;
R1_ram_block2a12_clock_enable_0 = S3_w_anode2993w[3];
R1_ram_block2a12_clock_enable_1 = GND;
R1_ram_block2a12_PORT_A_data_out = MEMORY(R1_ram_block2a12_PORT_A_data_in_reg, R1_ram_block2a12_PORT_B_data_in_reg, R1_ram_block2a12_PORT_A_address_reg, R1_ram_block2a12_PORT_B_address_reg, R1_ram_block2a12_PORT_A_write_enable_reg, R1_ram_block2a12_PORT_B_write_enable_reg, , , R1_ram_block2a12_clock_0, R1_ram_block2a12_clock_1, R1_ram_block2a12_clock_enable_0, R1_ram_block2a12_clock_enable_1, , );
R1_ram_block2a12_PORT_A_data_out_reg = DFFE(R1_ram_block2a12_PORT_A_data_out, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1M646Q = R1_ram_block2a12_PORT_A_data_out_reg[5];

--R1M647Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT6
R1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a12_PORT_A_data_in_reg = DFFE(R1_ram_block2a12_PORT_A_data_in, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_data_in = ~GND;
R1_ram_block2a12_PORT_B_data_in_reg = DFFE(R1_ram_block2a12_PORT_B_data_in, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a12_PORT_A_address_reg = DFFE(R1_ram_block2a12_PORT_A_address, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a12_PORT_B_address_reg = DFFE(R1_ram_block2a12_PORT_B_address, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_write_enable = GND;
R1_ram_block2a12_PORT_A_write_enable_reg = DFFE(R1_ram_block2a12_PORT_A_write_enable, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_write_enable = GND;
R1_ram_block2a12_PORT_B_write_enable_reg = DFFE(R1_ram_block2a12_PORT_B_write_enable, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_clock_0 = M1__clk0;
R1_ram_block2a12_clock_1 = GND;
R1_ram_block2a12_clock_enable_0 = S3_w_anode2993w[3];
R1_ram_block2a12_clock_enable_1 = GND;
R1_ram_block2a12_PORT_A_data_out = MEMORY(R1_ram_block2a12_PORT_A_data_in_reg, R1_ram_block2a12_PORT_B_data_in_reg, R1_ram_block2a12_PORT_A_address_reg, R1_ram_block2a12_PORT_B_address_reg, R1_ram_block2a12_PORT_A_write_enable_reg, R1_ram_block2a12_PORT_B_write_enable_reg, , , R1_ram_block2a12_clock_0, R1_ram_block2a12_clock_1, R1_ram_block2a12_clock_enable_0, R1_ram_block2a12_clock_enable_1, , );
R1_ram_block2a12_PORT_A_data_out_reg = DFFE(R1_ram_block2a12_PORT_A_data_out, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1M647Q = R1_ram_block2a12_PORT_A_data_out_reg[6];

--R1M648Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT7
R1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a12_PORT_A_data_in_reg = DFFE(R1_ram_block2a12_PORT_A_data_in, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_data_in = ~GND;
R1_ram_block2a12_PORT_B_data_in_reg = DFFE(R1_ram_block2a12_PORT_B_data_in, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a12_PORT_A_address_reg = DFFE(R1_ram_block2a12_PORT_A_address, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a12_PORT_B_address_reg = DFFE(R1_ram_block2a12_PORT_B_address, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_write_enable = GND;
R1_ram_block2a12_PORT_A_write_enable_reg = DFFE(R1_ram_block2a12_PORT_A_write_enable, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_write_enable = GND;
R1_ram_block2a12_PORT_B_write_enable_reg = DFFE(R1_ram_block2a12_PORT_B_write_enable, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_clock_0 = M1__clk0;
R1_ram_block2a12_clock_1 = GND;
R1_ram_block2a12_clock_enable_0 = S3_w_anode2993w[3];
R1_ram_block2a12_clock_enable_1 = GND;
R1_ram_block2a12_PORT_A_data_out = MEMORY(R1_ram_block2a12_PORT_A_data_in_reg, R1_ram_block2a12_PORT_B_data_in_reg, R1_ram_block2a12_PORT_A_address_reg, R1_ram_block2a12_PORT_B_address_reg, R1_ram_block2a12_PORT_A_write_enable_reg, R1_ram_block2a12_PORT_B_write_enable_reg, , , R1_ram_block2a12_clock_0, R1_ram_block2a12_clock_1, R1_ram_block2a12_clock_enable_0, R1_ram_block2a12_clock_enable_1, , );
R1_ram_block2a12_PORT_A_data_out_reg = DFFE(R1_ram_block2a12_PORT_A_data_out, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1M648Q = R1_ram_block2a12_PORT_A_data_out_reg[7];


--T1L216 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6390w~47
T1L216 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M746Q # !R1_address_reg_a[7] & (R1M646Q));


--R1_ram_block2a15 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a15_PORT_A_data_in_reg = DFFE(R1_ram_block2a15_PORT_A_data_in, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_data_in = ~GND;
R1_ram_block2a15_PORT_B_data_in_reg = DFFE(R1_ram_block2a15_PORT_B_data_in, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a15_PORT_A_address_reg = DFFE(R1_ram_block2a15_PORT_A_address, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a15_PORT_B_address_reg = DFFE(R1_ram_block2a15_PORT_B_address, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_write_enable = GND;
R1_ram_block2a15_PORT_A_write_enable_reg = DFFE(R1_ram_block2a15_PORT_A_write_enable, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_write_enable = GND;
R1_ram_block2a15_PORT_B_write_enable_reg = DFFE(R1_ram_block2a15_PORT_B_write_enable, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_clock_0 = M1__clk0;
R1_ram_block2a15_clock_1 = GND;
R1_ram_block2a15_clock_enable_0 = S3_w_anode3023w[3];
R1_ram_block2a15_clock_enable_1 = GND;
R1_ram_block2a15_PORT_A_data_out = MEMORY(R1_ram_block2a15_PORT_A_data_in_reg, R1_ram_block2a15_PORT_B_data_in_reg, R1_ram_block2a15_PORT_A_address_reg, R1_ram_block2a15_PORT_B_address_reg, R1_ram_block2a15_PORT_A_write_enable_reg, R1_ram_block2a15_PORT_B_write_enable_reg, , , R1_ram_block2a15_clock_0, R1_ram_block2a15_clock_1, R1_ram_block2a15_clock_enable_0, R1_ram_block2a15_clock_enable_1, , );
R1_ram_block2a15_PORT_A_data_out_reg = DFFE(R1_ram_block2a15_PORT_A_data_out, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15 = R1_ram_block2a15_PORT_A_data_out_reg[0];

--R1M792Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT1
R1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a15_PORT_A_data_in_reg = DFFE(R1_ram_block2a15_PORT_A_data_in, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_data_in = ~GND;
R1_ram_block2a15_PORT_B_data_in_reg = DFFE(R1_ram_block2a15_PORT_B_data_in, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a15_PORT_A_address_reg = DFFE(R1_ram_block2a15_PORT_A_address, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a15_PORT_B_address_reg = DFFE(R1_ram_block2a15_PORT_B_address, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_write_enable = GND;
R1_ram_block2a15_PORT_A_write_enable_reg = DFFE(R1_ram_block2a15_PORT_A_write_enable, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_write_enable = GND;
R1_ram_block2a15_PORT_B_write_enable_reg = DFFE(R1_ram_block2a15_PORT_B_write_enable, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_clock_0 = M1__clk0;
R1_ram_block2a15_clock_1 = GND;
R1_ram_block2a15_clock_enable_0 = S3_w_anode3023w[3];
R1_ram_block2a15_clock_enable_1 = GND;
R1_ram_block2a15_PORT_A_data_out = MEMORY(R1_ram_block2a15_PORT_A_data_in_reg, R1_ram_block2a15_PORT_B_data_in_reg, R1_ram_block2a15_PORT_A_address_reg, R1_ram_block2a15_PORT_B_address_reg, R1_ram_block2a15_PORT_A_write_enable_reg, R1_ram_block2a15_PORT_B_write_enable_reg, , , R1_ram_block2a15_clock_0, R1_ram_block2a15_clock_1, R1_ram_block2a15_clock_enable_0, R1_ram_block2a15_clock_enable_1, , );
R1_ram_block2a15_PORT_A_data_out_reg = DFFE(R1_ram_block2a15_PORT_A_data_out, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1M792Q = R1_ram_block2a15_PORT_A_data_out_reg[1];

--R1M793Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT2
R1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a15_PORT_A_data_in_reg = DFFE(R1_ram_block2a15_PORT_A_data_in, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_data_in = ~GND;
R1_ram_block2a15_PORT_B_data_in_reg = DFFE(R1_ram_block2a15_PORT_B_data_in, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a15_PORT_A_address_reg = DFFE(R1_ram_block2a15_PORT_A_address, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a15_PORT_B_address_reg = DFFE(R1_ram_block2a15_PORT_B_address, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_write_enable = GND;
R1_ram_block2a15_PORT_A_write_enable_reg = DFFE(R1_ram_block2a15_PORT_A_write_enable, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_write_enable = GND;
R1_ram_block2a15_PORT_B_write_enable_reg = DFFE(R1_ram_block2a15_PORT_B_write_enable, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_clock_0 = M1__clk0;
R1_ram_block2a15_clock_1 = GND;
R1_ram_block2a15_clock_enable_0 = S3_w_anode3023w[3];
R1_ram_block2a15_clock_enable_1 = GND;
R1_ram_block2a15_PORT_A_data_out = MEMORY(R1_ram_block2a15_PORT_A_data_in_reg, R1_ram_block2a15_PORT_B_data_in_reg, R1_ram_block2a15_PORT_A_address_reg, R1_ram_block2a15_PORT_B_address_reg, R1_ram_block2a15_PORT_A_write_enable_reg, R1_ram_block2a15_PORT_B_write_enable_reg, , , R1_ram_block2a15_clock_0, R1_ram_block2a15_clock_1, R1_ram_block2a15_clock_enable_0, R1_ram_block2a15_clock_enable_1, , );
R1_ram_block2a15_PORT_A_data_out_reg = DFFE(R1_ram_block2a15_PORT_A_data_out, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1M793Q = R1_ram_block2a15_PORT_A_data_out_reg[2];

--R1M794Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT3
R1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a15_PORT_A_data_in_reg = DFFE(R1_ram_block2a15_PORT_A_data_in, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_data_in = ~GND;
R1_ram_block2a15_PORT_B_data_in_reg = DFFE(R1_ram_block2a15_PORT_B_data_in, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a15_PORT_A_address_reg = DFFE(R1_ram_block2a15_PORT_A_address, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a15_PORT_B_address_reg = DFFE(R1_ram_block2a15_PORT_B_address, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_write_enable = GND;
R1_ram_block2a15_PORT_A_write_enable_reg = DFFE(R1_ram_block2a15_PORT_A_write_enable, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_write_enable = GND;
R1_ram_block2a15_PORT_B_write_enable_reg = DFFE(R1_ram_block2a15_PORT_B_write_enable, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_clock_0 = M1__clk0;
R1_ram_block2a15_clock_1 = GND;
R1_ram_block2a15_clock_enable_0 = S3_w_anode3023w[3];
R1_ram_block2a15_clock_enable_1 = GND;
R1_ram_block2a15_PORT_A_data_out = MEMORY(R1_ram_block2a15_PORT_A_data_in_reg, R1_ram_block2a15_PORT_B_data_in_reg, R1_ram_block2a15_PORT_A_address_reg, R1_ram_block2a15_PORT_B_address_reg, R1_ram_block2a15_PORT_A_write_enable_reg, R1_ram_block2a15_PORT_B_write_enable_reg, , , R1_ram_block2a15_clock_0, R1_ram_block2a15_clock_1, R1_ram_block2a15_clock_enable_0, R1_ram_block2a15_clock_enable_1, , );
R1_ram_block2a15_PORT_A_data_out_reg = DFFE(R1_ram_block2a15_PORT_A_data_out, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1M794Q = R1_ram_block2a15_PORT_A_data_out_reg[3];

--R1M795Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT4
R1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a15_PORT_A_data_in_reg = DFFE(R1_ram_block2a15_PORT_A_data_in, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_data_in = ~GND;
R1_ram_block2a15_PORT_B_data_in_reg = DFFE(R1_ram_block2a15_PORT_B_data_in, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a15_PORT_A_address_reg = DFFE(R1_ram_block2a15_PORT_A_address, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a15_PORT_B_address_reg = DFFE(R1_ram_block2a15_PORT_B_address, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_write_enable = GND;
R1_ram_block2a15_PORT_A_write_enable_reg = DFFE(R1_ram_block2a15_PORT_A_write_enable, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_write_enable = GND;
R1_ram_block2a15_PORT_B_write_enable_reg = DFFE(R1_ram_block2a15_PORT_B_write_enable, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_clock_0 = M1__clk0;
R1_ram_block2a15_clock_1 = GND;
R1_ram_block2a15_clock_enable_0 = S3_w_anode3023w[3];
R1_ram_block2a15_clock_enable_1 = GND;
R1_ram_block2a15_PORT_A_data_out = MEMORY(R1_ram_block2a15_PORT_A_data_in_reg, R1_ram_block2a15_PORT_B_data_in_reg, R1_ram_block2a15_PORT_A_address_reg, R1_ram_block2a15_PORT_B_address_reg, R1_ram_block2a15_PORT_A_write_enable_reg, R1_ram_block2a15_PORT_B_write_enable_reg, , , R1_ram_block2a15_clock_0, R1_ram_block2a15_clock_1, R1_ram_block2a15_clock_enable_0, R1_ram_block2a15_clock_enable_1, , );
R1_ram_block2a15_PORT_A_data_out_reg = DFFE(R1_ram_block2a15_PORT_A_data_out, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1M795Q = R1_ram_block2a15_PORT_A_data_out_reg[4];

--R1M796Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT5
R1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a15_PORT_A_data_in_reg = DFFE(R1_ram_block2a15_PORT_A_data_in, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_data_in = ~GND;
R1_ram_block2a15_PORT_B_data_in_reg = DFFE(R1_ram_block2a15_PORT_B_data_in, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a15_PORT_A_address_reg = DFFE(R1_ram_block2a15_PORT_A_address, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a15_PORT_B_address_reg = DFFE(R1_ram_block2a15_PORT_B_address, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_write_enable = GND;
R1_ram_block2a15_PORT_A_write_enable_reg = DFFE(R1_ram_block2a15_PORT_A_write_enable, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_write_enable = GND;
R1_ram_block2a15_PORT_B_write_enable_reg = DFFE(R1_ram_block2a15_PORT_B_write_enable, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_clock_0 = M1__clk0;
R1_ram_block2a15_clock_1 = GND;
R1_ram_block2a15_clock_enable_0 = S3_w_anode3023w[3];
R1_ram_block2a15_clock_enable_1 = GND;
R1_ram_block2a15_PORT_A_data_out = MEMORY(R1_ram_block2a15_PORT_A_data_in_reg, R1_ram_block2a15_PORT_B_data_in_reg, R1_ram_block2a15_PORT_A_address_reg, R1_ram_block2a15_PORT_B_address_reg, R1_ram_block2a15_PORT_A_write_enable_reg, R1_ram_block2a15_PORT_B_write_enable_reg, , , R1_ram_block2a15_clock_0, R1_ram_block2a15_clock_1, R1_ram_block2a15_clock_enable_0, R1_ram_block2a15_clock_enable_1, , );
R1_ram_block2a15_PORT_A_data_out_reg = DFFE(R1_ram_block2a15_PORT_A_data_out, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1M796Q = R1_ram_block2a15_PORT_A_data_out_reg[5];

--R1M797Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT6
R1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a15_PORT_A_data_in_reg = DFFE(R1_ram_block2a15_PORT_A_data_in, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_data_in = ~GND;
R1_ram_block2a15_PORT_B_data_in_reg = DFFE(R1_ram_block2a15_PORT_B_data_in, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a15_PORT_A_address_reg = DFFE(R1_ram_block2a15_PORT_A_address, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a15_PORT_B_address_reg = DFFE(R1_ram_block2a15_PORT_B_address, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_write_enable = GND;
R1_ram_block2a15_PORT_A_write_enable_reg = DFFE(R1_ram_block2a15_PORT_A_write_enable, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_write_enable = GND;
R1_ram_block2a15_PORT_B_write_enable_reg = DFFE(R1_ram_block2a15_PORT_B_write_enable, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_clock_0 = M1__clk0;
R1_ram_block2a15_clock_1 = GND;
R1_ram_block2a15_clock_enable_0 = S3_w_anode3023w[3];
R1_ram_block2a15_clock_enable_1 = GND;
R1_ram_block2a15_PORT_A_data_out = MEMORY(R1_ram_block2a15_PORT_A_data_in_reg, R1_ram_block2a15_PORT_B_data_in_reg, R1_ram_block2a15_PORT_A_address_reg, R1_ram_block2a15_PORT_B_address_reg, R1_ram_block2a15_PORT_A_write_enable_reg, R1_ram_block2a15_PORT_B_write_enable_reg, , , R1_ram_block2a15_clock_0, R1_ram_block2a15_clock_1, R1_ram_block2a15_clock_enable_0, R1_ram_block2a15_clock_enable_1, , );
R1_ram_block2a15_PORT_A_data_out_reg = DFFE(R1_ram_block2a15_PORT_A_data_out, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1M797Q = R1_ram_block2a15_PORT_A_data_out_reg[6];

--R1M798Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT7
R1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a15_PORT_A_data_in_reg = DFFE(R1_ram_block2a15_PORT_A_data_in, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_data_in = ~GND;
R1_ram_block2a15_PORT_B_data_in_reg = DFFE(R1_ram_block2a15_PORT_B_data_in, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a15_PORT_A_address_reg = DFFE(R1_ram_block2a15_PORT_A_address, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a15_PORT_B_address_reg = DFFE(R1_ram_block2a15_PORT_B_address, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_write_enable = GND;
R1_ram_block2a15_PORT_A_write_enable_reg = DFFE(R1_ram_block2a15_PORT_A_write_enable, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_write_enable = GND;
R1_ram_block2a15_PORT_B_write_enable_reg = DFFE(R1_ram_block2a15_PORT_B_write_enable, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_clock_0 = M1__clk0;
R1_ram_block2a15_clock_1 = GND;
R1_ram_block2a15_clock_enable_0 = S3_w_anode3023w[3];
R1_ram_block2a15_clock_enable_1 = GND;
R1_ram_block2a15_PORT_A_data_out = MEMORY(R1_ram_block2a15_PORT_A_data_in_reg, R1_ram_block2a15_PORT_B_data_in_reg, R1_ram_block2a15_PORT_A_address_reg, R1_ram_block2a15_PORT_B_address_reg, R1_ram_block2a15_PORT_A_write_enable_reg, R1_ram_block2a15_PORT_B_write_enable_reg, , , R1_ram_block2a15_clock_0, R1_ram_block2a15_clock_1, R1_ram_block2a15_clock_enable_0, R1_ram_block2a15_clock_enable_1, , );
R1_ram_block2a15_PORT_A_data_out_reg = DFFE(R1_ram_block2a15_PORT_A_data_out, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1M798Q = R1_ram_block2a15_PORT_A_data_out_reg[7];


--T1L217 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6390w~48
T1L217 = R1_address_reg_a[6] & (T1L216 & (R1M796Q) # !T1L216 & R1M696Q) # !R1_address_reg_a[6] & (T1L216);


--T1L233 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~574
T1L233 = R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L229 # !R1_address_reg_a[11] & (T1L217));


--R1_ram_block2a37 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a37_PORT_A_data_in_reg = DFFE(R1_ram_block2a37_PORT_A_data_in, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_data_in = ~GND;
R1_ram_block2a37_PORT_B_data_in_reg = DFFE(R1_ram_block2a37_PORT_B_data_in, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a37_PORT_A_address_reg = DFFE(R1_ram_block2a37_PORT_A_address, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a37_PORT_B_address_reg = DFFE(R1_ram_block2a37_PORT_B_address, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_write_enable = GND;
R1_ram_block2a37_PORT_A_write_enable_reg = DFFE(R1_ram_block2a37_PORT_A_write_enable, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_write_enable = GND;
R1_ram_block2a37_PORT_B_write_enable_reg = DFFE(R1_ram_block2a37_PORT_B_write_enable, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_clock_0 = M1__clk0;
R1_ram_block2a37_clock_1 = GND;
R1_ram_block2a37_clock_enable_0 = S3_w_anode3282w[3];
R1_ram_block2a37_clock_enable_1 = GND;
R1_ram_block2a37_PORT_A_data_out = MEMORY(R1_ram_block2a37_PORT_A_data_in_reg, R1_ram_block2a37_PORT_B_data_in_reg, R1_ram_block2a37_PORT_A_address_reg, R1_ram_block2a37_PORT_B_address_reg, R1_ram_block2a37_PORT_A_write_enable_reg, R1_ram_block2a37_PORT_B_write_enable_reg, , , R1_ram_block2a37_clock_0, R1_ram_block2a37_clock_1, R1_ram_block2a37_clock_enable_0, R1_ram_block2a37_clock_enable_1, , );
R1_ram_block2a37_PORT_A_data_out_reg = DFFE(R1_ram_block2a37_PORT_A_data_out, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37 = R1_ram_block2a37_PORT_A_data_out_reg[0];

--R1M1892Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT1
R1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a37_PORT_A_data_in_reg = DFFE(R1_ram_block2a37_PORT_A_data_in, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_data_in = ~GND;
R1_ram_block2a37_PORT_B_data_in_reg = DFFE(R1_ram_block2a37_PORT_B_data_in, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a37_PORT_A_address_reg = DFFE(R1_ram_block2a37_PORT_A_address, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a37_PORT_B_address_reg = DFFE(R1_ram_block2a37_PORT_B_address, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_write_enable = GND;
R1_ram_block2a37_PORT_A_write_enable_reg = DFFE(R1_ram_block2a37_PORT_A_write_enable, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_write_enable = GND;
R1_ram_block2a37_PORT_B_write_enable_reg = DFFE(R1_ram_block2a37_PORT_B_write_enable, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_clock_0 = M1__clk0;
R1_ram_block2a37_clock_1 = GND;
R1_ram_block2a37_clock_enable_0 = S3_w_anode3282w[3];
R1_ram_block2a37_clock_enable_1 = GND;
R1_ram_block2a37_PORT_A_data_out = MEMORY(R1_ram_block2a37_PORT_A_data_in_reg, R1_ram_block2a37_PORT_B_data_in_reg, R1_ram_block2a37_PORT_A_address_reg, R1_ram_block2a37_PORT_B_address_reg, R1_ram_block2a37_PORT_A_write_enable_reg, R1_ram_block2a37_PORT_B_write_enable_reg, , , R1_ram_block2a37_clock_0, R1_ram_block2a37_clock_1, R1_ram_block2a37_clock_enable_0, R1_ram_block2a37_clock_enable_1, , );
R1_ram_block2a37_PORT_A_data_out_reg = DFFE(R1_ram_block2a37_PORT_A_data_out, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1M1892Q = R1_ram_block2a37_PORT_A_data_out_reg[1];

--R1M1893Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT2
R1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a37_PORT_A_data_in_reg = DFFE(R1_ram_block2a37_PORT_A_data_in, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_data_in = ~GND;
R1_ram_block2a37_PORT_B_data_in_reg = DFFE(R1_ram_block2a37_PORT_B_data_in, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a37_PORT_A_address_reg = DFFE(R1_ram_block2a37_PORT_A_address, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a37_PORT_B_address_reg = DFFE(R1_ram_block2a37_PORT_B_address, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_write_enable = GND;
R1_ram_block2a37_PORT_A_write_enable_reg = DFFE(R1_ram_block2a37_PORT_A_write_enable, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_write_enable = GND;
R1_ram_block2a37_PORT_B_write_enable_reg = DFFE(R1_ram_block2a37_PORT_B_write_enable, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_clock_0 = M1__clk0;
R1_ram_block2a37_clock_1 = GND;
R1_ram_block2a37_clock_enable_0 = S3_w_anode3282w[3];
R1_ram_block2a37_clock_enable_1 = GND;
R1_ram_block2a37_PORT_A_data_out = MEMORY(R1_ram_block2a37_PORT_A_data_in_reg, R1_ram_block2a37_PORT_B_data_in_reg, R1_ram_block2a37_PORT_A_address_reg, R1_ram_block2a37_PORT_B_address_reg, R1_ram_block2a37_PORT_A_write_enable_reg, R1_ram_block2a37_PORT_B_write_enable_reg, , , R1_ram_block2a37_clock_0, R1_ram_block2a37_clock_1, R1_ram_block2a37_clock_enable_0, R1_ram_block2a37_clock_enable_1, , );
R1_ram_block2a37_PORT_A_data_out_reg = DFFE(R1_ram_block2a37_PORT_A_data_out, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1M1893Q = R1_ram_block2a37_PORT_A_data_out_reg[2];

--R1M1894Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT3
R1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a37_PORT_A_data_in_reg = DFFE(R1_ram_block2a37_PORT_A_data_in, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_data_in = ~GND;
R1_ram_block2a37_PORT_B_data_in_reg = DFFE(R1_ram_block2a37_PORT_B_data_in, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a37_PORT_A_address_reg = DFFE(R1_ram_block2a37_PORT_A_address, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a37_PORT_B_address_reg = DFFE(R1_ram_block2a37_PORT_B_address, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_write_enable = GND;
R1_ram_block2a37_PORT_A_write_enable_reg = DFFE(R1_ram_block2a37_PORT_A_write_enable, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_write_enable = GND;
R1_ram_block2a37_PORT_B_write_enable_reg = DFFE(R1_ram_block2a37_PORT_B_write_enable, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_clock_0 = M1__clk0;
R1_ram_block2a37_clock_1 = GND;
R1_ram_block2a37_clock_enable_0 = S3_w_anode3282w[3];
R1_ram_block2a37_clock_enable_1 = GND;
R1_ram_block2a37_PORT_A_data_out = MEMORY(R1_ram_block2a37_PORT_A_data_in_reg, R1_ram_block2a37_PORT_B_data_in_reg, R1_ram_block2a37_PORT_A_address_reg, R1_ram_block2a37_PORT_B_address_reg, R1_ram_block2a37_PORT_A_write_enable_reg, R1_ram_block2a37_PORT_B_write_enable_reg, , , R1_ram_block2a37_clock_0, R1_ram_block2a37_clock_1, R1_ram_block2a37_clock_enable_0, R1_ram_block2a37_clock_enable_1, , );
R1_ram_block2a37_PORT_A_data_out_reg = DFFE(R1_ram_block2a37_PORT_A_data_out, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1M1894Q = R1_ram_block2a37_PORT_A_data_out_reg[3];

--R1M1895Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT4
R1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a37_PORT_A_data_in_reg = DFFE(R1_ram_block2a37_PORT_A_data_in, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_data_in = ~GND;
R1_ram_block2a37_PORT_B_data_in_reg = DFFE(R1_ram_block2a37_PORT_B_data_in, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a37_PORT_A_address_reg = DFFE(R1_ram_block2a37_PORT_A_address, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a37_PORT_B_address_reg = DFFE(R1_ram_block2a37_PORT_B_address, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_write_enable = GND;
R1_ram_block2a37_PORT_A_write_enable_reg = DFFE(R1_ram_block2a37_PORT_A_write_enable, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_write_enable = GND;
R1_ram_block2a37_PORT_B_write_enable_reg = DFFE(R1_ram_block2a37_PORT_B_write_enable, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_clock_0 = M1__clk0;
R1_ram_block2a37_clock_1 = GND;
R1_ram_block2a37_clock_enable_0 = S3_w_anode3282w[3];
R1_ram_block2a37_clock_enable_1 = GND;
R1_ram_block2a37_PORT_A_data_out = MEMORY(R1_ram_block2a37_PORT_A_data_in_reg, R1_ram_block2a37_PORT_B_data_in_reg, R1_ram_block2a37_PORT_A_address_reg, R1_ram_block2a37_PORT_B_address_reg, R1_ram_block2a37_PORT_A_write_enable_reg, R1_ram_block2a37_PORT_B_write_enable_reg, , , R1_ram_block2a37_clock_0, R1_ram_block2a37_clock_1, R1_ram_block2a37_clock_enable_0, R1_ram_block2a37_clock_enable_1, , );
R1_ram_block2a37_PORT_A_data_out_reg = DFFE(R1_ram_block2a37_PORT_A_data_out, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1M1895Q = R1_ram_block2a37_PORT_A_data_out_reg[4];

--R1M1896Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT5
R1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a37_PORT_A_data_in_reg = DFFE(R1_ram_block2a37_PORT_A_data_in, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_data_in = ~GND;
R1_ram_block2a37_PORT_B_data_in_reg = DFFE(R1_ram_block2a37_PORT_B_data_in, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a37_PORT_A_address_reg = DFFE(R1_ram_block2a37_PORT_A_address, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a37_PORT_B_address_reg = DFFE(R1_ram_block2a37_PORT_B_address, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_write_enable = GND;
R1_ram_block2a37_PORT_A_write_enable_reg = DFFE(R1_ram_block2a37_PORT_A_write_enable, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_write_enable = GND;
R1_ram_block2a37_PORT_B_write_enable_reg = DFFE(R1_ram_block2a37_PORT_B_write_enable, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_clock_0 = M1__clk0;
R1_ram_block2a37_clock_1 = GND;
R1_ram_block2a37_clock_enable_0 = S3_w_anode3282w[3];
R1_ram_block2a37_clock_enable_1 = GND;
R1_ram_block2a37_PORT_A_data_out = MEMORY(R1_ram_block2a37_PORT_A_data_in_reg, R1_ram_block2a37_PORT_B_data_in_reg, R1_ram_block2a37_PORT_A_address_reg, R1_ram_block2a37_PORT_B_address_reg, R1_ram_block2a37_PORT_A_write_enable_reg, R1_ram_block2a37_PORT_B_write_enable_reg, , , R1_ram_block2a37_clock_0, R1_ram_block2a37_clock_1, R1_ram_block2a37_clock_enable_0, R1_ram_block2a37_clock_enable_1, , );
R1_ram_block2a37_PORT_A_data_out_reg = DFFE(R1_ram_block2a37_PORT_A_data_out, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1M1896Q = R1_ram_block2a37_PORT_A_data_out_reg[5];

--R1M1897Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT6
R1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a37_PORT_A_data_in_reg = DFFE(R1_ram_block2a37_PORT_A_data_in, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_data_in = ~GND;
R1_ram_block2a37_PORT_B_data_in_reg = DFFE(R1_ram_block2a37_PORT_B_data_in, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a37_PORT_A_address_reg = DFFE(R1_ram_block2a37_PORT_A_address, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a37_PORT_B_address_reg = DFFE(R1_ram_block2a37_PORT_B_address, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_write_enable = GND;
R1_ram_block2a37_PORT_A_write_enable_reg = DFFE(R1_ram_block2a37_PORT_A_write_enable, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_write_enable = GND;
R1_ram_block2a37_PORT_B_write_enable_reg = DFFE(R1_ram_block2a37_PORT_B_write_enable, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_clock_0 = M1__clk0;
R1_ram_block2a37_clock_1 = GND;
R1_ram_block2a37_clock_enable_0 = S3_w_anode3282w[3];
R1_ram_block2a37_clock_enable_1 = GND;
R1_ram_block2a37_PORT_A_data_out = MEMORY(R1_ram_block2a37_PORT_A_data_in_reg, R1_ram_block2a37_PORT_B_data_in_reg, R1_ram_block2a37_PORT_A_address_reg, R1_ram_block2a37_PORT_B_address_reg, R1_ram_block2a37_PORT_A_write_enable_reg, R1_ram_block2a37_PORT_B_write_enable_reg, , , R1_ram_block2a37_clock_0, R1_ram_block2a37_clock_1, R1_ram_block2a37_clock_enable_0, R1_ram_block2a37_clock_enable_1, , );
R1_ram_block2a37_PORT_A_data_out_reg = DFFE(R1_ram_block2a37_PORT_A_data_out, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1M1897Q = R1_ram_block2a37_PORT_A_data_out_reg[6];

--R1M1898Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT7
R1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a37_PORT_A_data_in_reg = DFFE(R1_ram_block2a37_PORT_A_data_in, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_data_in = ~GND;
R1_ram_block2a37_PORT_B_data_in_reg = DFFE(R1_ram_block2a37_PORT_B_data_in, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a37_PORT_A_address_reg = DFFE(R1_ram_block2a37_PORT_A_address, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a37_PORT_B_address_reg = DFFE(R1_ram_block2a37_PORT_B_address, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_write_enable = GND;
R1_ram_block2a37_PORT_A_write_enable_reg = DFFE(R1_ram_block2a37_PORT_A_write_enable, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_write_enable = GND;
R1_ram_block2a37_PORT_B_write_enable_reg = DFFE(R1_ram_block2a37_PORT_B_write_enable, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_clock_0 = M1__clk0;
R1_ram_block2a37_clock_1 = GND;
R1_ram_block2a37_clock_enable_0 = S3_w_anode3282w[3];
R1_ram_block2a37_clock_enable_1 = GND;
R1_ram_block2a37_PORT_A_data_out = MEMORY(R1_ram_block2a37_PORT_A_data_in_reg, R1_ram_block2a37_PORT_B_data_in_reg, R1_ram_block2a37_PORT_A_address_reg, R1_ram_block2a37_PORT_B_address_reg, R1_ram_block2a37_PORT_A_write_enable_reg, R1_ram_block2a37_PORT_B_write_enable_reg, , , R1_ram_block2a37_clock_0, R1_ram_block2a37_clock_1, R1_ram_block2a37_clock_enable_0, R1_ram_block2a37_clock_enable_1, , );
R1_ram_block2a37_PORT_A_data_out_reg = DFFE(R1_ram_block2a37_PORT_A_data_out, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1M1898Q = R1_ram_block2a37_PORT_A_data_out_reg[7];


--R1_ram_block2a38 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a38_PORT_A_data_in_reg = DFFE(R1_ram_block2a38_PORT_A_data_in, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_data_in = ~GND;
R1_ram_block2a38_PORT_B_data_in_reg = DFFE(R1_ram_block2a38_PORT_B_data_in, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a38_PORT_A_address_reg = DFFE(R1_ram_block2a38_PORT_A_address, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a38_PORT_B_address_reg = DFFE(R1_ram_block2a38_PORT_B_address, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_write_enable = GND;
R1_ram_block2a38_PORT_A_write_enable_reg = DFFE(R1_ram_block2a38_PORT_A_write_enable, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_write_enable = GND;
R1_ram_block2a38_PORT_B_write_enable_reg = DFFE(R1_ram_block2a38_PORT_B_write_enable, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_clock_0 = M1__clk0;
R1_ram_block2a38_clock_1 = GND;
R1_ram_block2a38_clock_enable_0 = S3_w_anode3292w[3];
R1_ram_block2a38_clock_enable_1 = GND;
R1_ram_block2a38_PORT_A_data_out = MEMORY(R1_ram_block2a38_PORT_A_data_in_reg, R1_ram_block2a38_PORT_B_data_in_reg, R1_ram_block2a38_PORT_A_address_reg, R1_ram_block2a38_PORT_B_address_reg, R1_ram_block2a38_PORT_A_write_enable_reg, R1_ram_block2a38_PORT_B_write_enable_reg, , , R1_ram_block2a38_clock_0, R1_ram_block2a38_clock_1, R1_ram_block2a38_clock_enable_0, R1_ram_block2a38_clock_enable_1, , );
R1_ram_block2a38_PORT_A_data_out_reg = DFFE(R1_ram_block2a38_PORT_A_data_out, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38 = R1_ram_block2a38_PORT_A_data_out_reg[0];

--R1M1942Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT1
R1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a38_PORT_A_data_in_reg = DFFE(R1_ram_block2a38_PORT_A_data_in, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_data_in = ~GND;
R1_ram_block2a38_PORT_B_data_in_reg = DFFE(R1_ram_block2a38_PORT_B_data_in, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a38_PORT_A_address_reg = DFFE(R1_ram_block2a38_PORT_A_address, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a38_PORT_B_address_reg = DFFE(R1_ram_block2a38_PORT_B_address, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_write_enable = GND;
R1_ram_block2a38_PORT_A_write_enable_reg = DFFE(R1_ram_block2a38_PORT_A_write_enable, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_write_enable = GND;
R1_ram_block2a38_PORT_B_write_enable_reg = DFFE(R1_ram_block2a38_PORT_B_write_enable, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_clock_0 = M1__clk0;
R1_ram_block2a38_clock_1 = GND;
R1_ram_block2a38_clock_enable_0 = S3_w_anode3292w[3];
R1_ram_block2a38_clock_enable_1 = GND;
R1_ram_block2a38_PORT_A_data_out = MEMORY(R1_ram_block2a38_PORT_A_data_in_reg, R1_ram_block2a38_PORT_B_data_in_reg, R1_ram_block2a38_PORT_A_address_reg, R1_ram_block2a38_PORT_B_address_reg, R1_ram_block2a38_PORT_A_write_enable_reg, R1_ram_block2a38_PORT_B_write_enable_reg, , , R1_ram_block2a38_clock_0, R1_ram_block2a38_clock_1, R1_ram_block2a38_clock_enable_0, R1_ram_block2a38_clock_enable_1, , );
R1_ram_block2a38_PORT_A_data_out_reg = DFFE(R1_ram_block2a38_PORT_A_data_out, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1M1942Q = R1_ram_block2a38_PORT_A_data_out_reg[1];

--R1M1943Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT2
R1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a38_PORT_A_data_in_reg = DFFE(R1_ram_block2a38_PORT_A_data_in, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_data_in = ~GND;
R1_ram_block2a38_PORT_B_data_in_reg = DFFE(R1_ram_block2a38_PORT_B_data_in, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a38_PORT_A_address_reg = DFFE(R1_ram_block2a38_PORT_A_address, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a38_PORT_B_address_reg = DFFE(R1_ram_block2a38_PORT_B_address, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_write_enable = GND;
R1_ram_block2a38_PORT_A_write_enable_reg = DFFE(R1_ram_block2a38_PORT_A_write_enable, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_write_enable = GND;
R1_ram_block2a38_PORT_B_write_enable_reg = DFFE(R1_ram_block2a38_PORT_B_write_enable, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_clock_0 = M1__clk0;
R1_ram_block2a38_clock_1 = GND;
R1_ram_block2a38_clock_enable_0 = S3_w_anode3292w[3];
R1_ram_block2a38_clock_enable_1 = GND;
R1_ram_block2a38_PORT_A_data_out = MEMORY(R1_ram_block2a38_PORT_A_data_in_reg, R1_ram_block2a38_PORT_B_data_in_reg, R1_ram_block2a38_PORT_A_address_reg, R1_ram_block2a38_PORT_B_address_reg, R1_ram_block2a38_PORT_A_write_enable_reg, R1_ram_block2a38_PORT_B_write_enable_reg, , , R1_ram_block2a38_clock_0, R1_ram_block2a38_clock_1, R1_ram_block2a38_clock_enable_0, R1_ram_block2a38_clock_enable_1, , );
R1_ram_block2a38_PORT_A_data_out_reg = DFFE(R1_ram_block2a38_PORT_A_data_out, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1M1943Q = R1_ram_block2a38_PORT_A_data_out_reg[2];

--R1M1944Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT3
R1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a38_PORT_A_data_in_reg = DFFE(R1_ram_block2a38_PORT_A_data_in, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_data_in = ~GND;
R1_ram_block2a38_PORT_B_data_in_reg = DFFE(R1_ram_block2a38_PORT_B_data_in, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a38_PORT_A_address_reg = DFFE(R1_ram_block2a38_PORT_A_address, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a38_PORT_B_address_reg = DFFE(R1_ram_block2a38_PORT_B_address, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_write_enable = GND;
R1_ram_block2a38_PORT_A_write_enable_reg = DFFE(R1_ram_block2a38_PORT_A_write_enable, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_write_enable = GND;
R1_ram_block2a38_PORT_B_write_enable_reg = DFFE(R1_ram_block2a38_PORT_B_write_enable, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_clock_0 = M1__clk0;
R1_ram_block2a38_clock_1 = GND;
R1_ram_block2a38_clock_enable_0 = S3_w_anode3292w[3];
R1_ram_block2a38_clock_enable_1 = GND;
R1_ram_block2a38_PORT_A_data_out = MEMORY(R1_ram_block2a38_PORT_A_data_in_reg, R1_ram_block2a38_PORT_B_data_in_reg, R1_ram_block2a38_PORT_A_address_reg, R1_ram_block2a38_PORT_B_address_reg, R1_ram_block2a38_PORT_A_write_enable_reg, R1_ram_block2a38_PORT_B_write_enable_reg, , , R1_ram_block2a38_clock_0, R1_ram_block2a38_clock_1, R1_ram_block2a38_clock_enable_0, R1_ram_block2a38_clock_enable_1, , );
R1_ram_block2a38_PORT_A_data_out_reg = DFFE(R1_ram_block2a38_PORT_A_data_out, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1M1944Q = R1_ram_block2a38_PORT_A_data_out_reg[3];

--R1M1945Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT4
R1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a38_PORT_A_data_in_reg = DFFE(R1_ram_block2a38_PORT_A_data_in, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_data_in = ~GND;
R1_ram_block2a38_PORT_B_data_in_reg = DFFE(R1_ram_block2a38_PORT_B_data_in, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a38_PORT_A_address_reg = DFFE(R1_ram_block2a38_PORT_A_address, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a38_PORT_B_address_reg = DFFE(R1_ram_block2a38_PORT_B_address, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_write_enable = GND;
R1_ram_block2a38_PORT_A_write_enable_reg = DFFE(R1_ram_block2a38_PORT_A_write_enable, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_write_enable = GND;
R1_ram_block2a38_PORT_B_write_enable_reg = DFFE(R1_ram_block2a38_PORT_B_write_enable, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_clock_0 = M1__clk0;
R1_ram_block2a38_clock_1 = GND;
R1_ram_block2a38_clock_enable_0 = S3_w_anode3292w[3];
R1_ram_block2a38_clock_enable_1 = GND;
R1_ram_block2a38_PORT_A_data_out = MEMORY(R1_ram_block2a38_PORT_A_data_in_reg, R1_ram_block2a38_PORT_B_data_in_reg, R1_ram_block2a38_PORT_A_address_reg, R1_ram_block2a38_PORT_B_address_reg, R1_ram_block2a38_PORT_A_write_enable_reg, R1_ram_block2a38_PORT_B_write_enable_reg, , , R1_ram_block2a38_clock_0, R1_ram_block2a38_clock_1, R1_ram_block2a38_clock_enable_0, R1_ram_block2a38_clock_enable_1, , );
R1_ram_block2a38_PORT_A_data_out_reg = DFFE(R1_ram_block2a38_PORT_A_data_out, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1M1945Q = R1_ram_block2a38_PORT_A_data_out_reg[4];

--R1M1946Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT5
R1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a38_PORT_A_data_in_reg = DFFE(R1_ram_block2a38_PORT_A_data_in, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_data_in = ~GND;
R1_ram_block2a38_PORT_B_data_in_reg = DFFE(R1_ram_block2a38_PORT_B_data_in, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a38_PORT_A_address_reg = DFFE(R1_ram_block2a38_PORT_A_address, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a38_PORT_B_address_reg = DFFE(R1_ram_block2a38_PORT_B_address, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_write_enable = GND;
R1_ram_block2a38_PORT_A_write_enable_reg = DFFE(R1_ram_block2a38_PORT_A_write_enable, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_write_enable = GND;
R1_ram_block2a38_PORT_B_write_enable_reg = DFFE(R1_ram_block2a38_PORT_B_write_enable, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_clock_0 = M1__clk0;
R1_ram_block2a38_clock_1 = GND;
R1_ram_block2a38_clock_enable_0 = S3_w_anode3292w[3];
R1_ram_block2a38_clock_enable_1 = GND;
R1_ram_block2a38_PORT_A_data_out = MEMORY(R1_ram_block2a38_PORT_A_data_in_reg, R1_ram_block2a38_PORT_B_data_in_reg, R1_ram_block2a38_PORT_A_address_reg, R1_ram_block2a38_PORT_B_address_reg, R1_ram_block2a38_PORT_A_write_enable_reg, R1_ram_block2a38_PORT_B_write_enable_reg, , , R1_ram_block2a38_clock_0, R1_ram_block2a38_clock_1, R1_ram_block2a38_clock_enable_0, R1_ram_block2a38_clock_enable_1, , );
R1_ram_block2a38_PORT_A_data_out_reg = DFFE(R1_ram_block2a38_PORT_A_data_out, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1M1946Q = R1_ram_block2a38_PORT_A_data_out_reg[5];

--R1M1947Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT6
R1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a38_PORT_A_data_in_reg = DFFE(R1_ram_block2a38_PORT_A_data_in, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_data_in = ~GND;
R1_ram_block2a38_PORT_B_data_in_reg = DFFE(R1_ram_block2a38_PORT_B_data_in, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a38_PORT_A_address_reg = DFFE(R1_ram_block2a38_PORT_A_address, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a38_PORT_B_address_reg = DFFE(R1_ram_block2a38_PORT_B_address, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_write_enable = GND;
R1_ram_block2a38_PORT_A_write_enable_reg = DFFE(R1_ram_block2a38_PORT_A_write_enable, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_write_enable = GND;
R1_ram_block2a38_PORT_B_write_enable_reg = DFFE(R1_ram_block2a38_PORT_B_write_enable, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_clock_0 = M1__clk0;
R1_ram_block2a38_clock_1 = GND;
R1_ram_block2a38_clock_enable_0 = S3_w_anode3292w[3];
R1_ram_block2a38_clock_enable_1 = GND;
R1_ram_block2a38_PORT_A_data_out = MEMORY(R1_ram_block2a38_PORT_A_data_in_reg, R1_ram_block2a38_PORT_B_data_in_reg, R1_ram_block2a38_PORT_A_address_reg, R1_ram_block2a38_PORT_B_address_reg, R1_ram_block2a38_PORT_A_write_enable_reg, R1_ram_block2a38_PORT_B_write_enable_reg, , , R1_ram_block2a38_clock_0, R1_ram_block2a38_clock_1, R1_ram_block2a38_clock_enable_0, R1_ram_block2a38_clock_enable_1, , );
R1_ram_block2a38_PORT_A_data_out_reg = DFFE(R1_ram_block2a38_PORT_A_data_out, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1M1947Q = R1_ram_block2a38_PORT_A_data_out_reg[6];

--R1M1948Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT7
R1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a38_PORT_A_data_in_reg = DFFE(R1_ram_block2a38_PORT_A_data_in, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_data_in = ~GND;
R1_ram_block2a38_PORT_B_data_in_reg = DFFE(R1_ram_block2a38_PORT_B_data_in, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a38_PORT_A_address_reg = DFFE(R1_ram_block2a38_PORT_A_address, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a38_PORT_B_address_reg = DFFE(R1_ram_block2a38_PORT_B_address, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_write_enable = GND;
R1_ram_block2a38_PORT_A_write_enable_reg = DFFE(R1_ram_block2a38_PORT_A_write_enable, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_write_enable = GND;
R1_ram_block2a38_PORT_B_write_enable_reg = DFFE(R1_ram_block2a38_PORT_B_write_enable, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_clock_0 = M1__clk0;
R1_ram_block2a38_clock_1 = GND;
R1_ram_block2a38_clock_enable_0 = S3_w_anode3292w[3];
R1_ram_block2a38_clock_enable_1 = GND;
R1_ram_block2a38_PORT_A_data_out = MEMORY(R1_ram_block2a38_PORT_A_data_in_reg, R1_ram_block2a38_PORT_B_data_in_reg, R1_ram_block2a38_PORT_A_address_reg, R1_ram_block2a38_PORT_B_address_reg, R1_ram_block2a38_PORT_A_write_enable_reg, R1_ram_block2a38_PORT_B_write_enable_reg, , , R1_ram_block2a38_clock_0, R1_ram_block2a38_clock_1, R1_ram_block2a38_clock_enable_0, R1_ram_block2a38_clock_enable_1, , );
R1_ram_block2a38_PORT_A_data_out_reg = DFFE(R1_ram_block2a38_PORT_A_data_out, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1M1948Q = R1_ram_block2a38_PORT_A_data_out_reg[7];


--R1_ram_block2a36 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a36_PORT_A_data_in_reg = DFFE(R1_ram_block2a36_PORT_A_data_in, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_data_in = ~GND;
R1_ram_block2a36_PORT_B_data_in_reg = DFFE(R1_ram_block2a36_PORT_B_data_in, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a36_PORT_A_address_reg = DFFE(R1_ram_block2a36_PORT_A_address, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a36_PORT_B_address_reg = DFFE(R1_ram_block2a36_PORT_B_address, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_write_enable = GND;
R1_ram_block2a36_PORT_A_write_enable_reg = DFFE(R1_ram_block2a36_PORT_A_write_enable, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_write_enable = GND;
R1_ram_block2a36_PORT_B_write_enable_reg = DFFE(R1_ram_block2a36_PORT_B_write_enable, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_clock_0 = M1__clk0;
R1_ram_block2a36_clock_1 = GND;
R1_ram_block2a36_clock_enable_0 = S3_w_anode3272w[3];
R1_ram_block2a36_clock_enable_1 = GND;
R1_ram_block2a36_PORT_A_data_out = MEMORY(R1_ram_block2a36_PORT_A_data_in_reg, R1_ram_block2a36_PORT_B_data_in_reg, R1_ram_block2a36_PORT_A_address_reg, R1_ram_block2a36_PORT_B_address_reg, R1_ram_block2a36_PORT_A_write_enable_reg, R1_ram_block2a36_PORT_B_write_enable_reg, , , R1_ram_block2a36_clock_0, R1_ram_block2a36_clock_1, R1_ram_block2a36_clock_enable_0, R1_ram_block2a36_clock_enable_1, , );
R1_ram_block2a36_PORT_A_data_out_reg = DFFE(R1_ram_block2a36_PORT_A_data_out, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36 = R1_ram_block2a36_PORT_A_data_out_reg[0];

--R1M1842Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT1
R1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a36_PORT_A_data_in_reg = DFFE(R1_ram_block2a36_PORT_A_data_in, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_data_in = ~GND;
R1_ram_block2a36_PORT_B_data_in_reg = DFFE(R1_ram_block2a36_PORT_B_data_in, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a36_PORT_A_address_reg = DFFE(R1_ram_block2a36_PORT_A_address, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a36_PORT_B_address_reg = DFFE(R1_ram_block2a36_PORT_B_address, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_write_enable = GND;
R1_ram_block2a36_PORT_A_write_enable_reg = DFFE(R1_ram_block2a36_PORT_A_write_enable, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_write_enable = GND;
R1_ram_block2a36_PORT_B_write_enable_reg = DFFE(R1_ram_block2a36_PORT_B_write_enable, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_clock_0 = M1__clk0;
R1_ram_block2a36_clock_1 = GND;
R1_ram_block2a36_clock_enable_0 = S3_w_anode3272w[3];
R1_ram_block2a36_clock_enable_1 = GND;
R1_ram_block2a36_PORT_A_data_out = MEMORY(R1_ram_block2a36_PORT_A_data_in_reg, R1_ram_block2a36_PORT_B_data_in_reg, R1_ram_block2a36_PORT_A_address_reg, R1_ram_block2a36_PORT_B_address_reg, R1_ram_block2a36_PORT_A_write_enable_reg, R1_ram_block2a36_PORT_B_write_enable_reg, , , R1_ram_block2a36_clock_0, R1_ram_block2a36_clock_1, R1_ram_block2a36_clock_enable_0, R1_ram_block2a36_clock_enable_1, , );
R1_ram_block2a36_PORT_A_data_out_reg = DFFE(R1_ram_block2a36_PORT_A_data_out, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1M1842Q = R1_ram_block2a36_PORT_A_data_out_reg[1];

--R1M1843Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT2
R1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a36_PORT_A_data_in_reg = DFFE(R1_ram_block2a36_PORT_A_data_in, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_data_in = ~GND;
R1_ram_block2a36_PORT_B_data_in_reg = DFFE(R1_ram_block2a36_PORT_B_data_in, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a36_PORT_A_address_reg = DFFE(R1_ram_block2a36_PORT_A_address, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a36_PORT_B_address_reg = DFFE(R1_ram_block2a36_PORT_B_address, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_write_enable = GND;
R1_ram_block2a36_PORT_A_write_enable_reg = DFFE(R1_ram_block2a36_PORT_A_write_enable, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_write_enable = GND;
R1_ram_block2a36_PORT_B_write_enable_reg = DFFE(R1_ram_block2a36_PORT_B_write_enable, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_clock_0 = M1__clk0;
R1_ram_block2a36_clock_1 = GND;
R1_ram_block2a36_clock_enable_0 = S3_w_anode3272w[3];
R1_ram_block2a36_clock_enable_1 = GND;
R1_ram_block2a36_PORT_A_data_out = MEMORY(R1_ram_block2a36_PORT_A_data_in_reg, R1_ram_block2a36_PORT_B_data_in_reg, R1_ram_block2a36_PORT_A_address_reg, R1_ram_block2a36_PORT_B_address_reg, R1_ram_block2a36_PORT_A_write_enable_reg, R1_ram_block2a36_PORT_B_write_enable_reg, , , R1_ram_block2a36_clock_0, R1_ram_block2a36_clock_1, R1_ram_block2a36_clock_enable_0, R1_ram_block2a36_clock_enable_1, , );
R1_ram_block2a36_PORT_A_data_out_reg = DFFE(R1_ram_block2a36_PORT_A_data_out, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1M1843Q = R1_ram_block2a36_PORT_A_data_out_reg[2];

--R1M1844Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT3
R1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a36_PORT_A_data_in_reg = DFFE(R1_ram_block2a36_PORT_A_data_in, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_data_in = ~GND;
R1_ram_block2a36_PORT_B_data_in_reg = DFFE(R1_ram_block2a36_PORT_B_data_in, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a36_PORT_A_address_reg = DFFE(R1_ram_block2a36_PORT_A_address, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a36_PORT_B_address_reg = DFFE(R1_ram_block2a36_PORT_B_address, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_write_enable = GND;
R1_ram_block2a36_PORT_A_write_enable_reg = DFFE(R1_ram_block2a36_PORT_A_write_enable, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_write_enable = GND;
R1_ram_block2a36_PORT_B_write_enable_reg = DFFE(R1_ram_block2a36_PORT_B_write_enable, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_clock_0 = M1__clk0;
R1_ram_block2a36_clock_1 = GND;
R1_ram_block2a36_clock_enable_0 = S3_w_anode3272w[3];
R1_ram_block2a36_clock_enable_1 = GND;
R1_ram_block2a36_PORT_A_data_out = MEMORY(R1_ram_block2a36_PORT_A_data_in_reg, R1_ram_block2a36_PORT_B_data_in_reg, R1_ram_block2a36_PORT_A_address_reg, R1_ram_block2a36_PORT_B_address_reg, R1_ram_block2a36_PORT_A_write_enable_reg, R1_ram_block2a36_PORT_B_write_enable_reg, , , R1_ram_block2a36_clock_0, R1_ram_block2a36_clock_1, R1_ram_block2a36_clock_enable_0, R1_ram_block2a36_clock_enable_1, , );
R1_ram_block2a36_PORT_A_data_out_reg = DFFE(R1_ram_block2a36_PORT_A_data_out, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1M1844Q = R1_ram_block2a36_PORT_A_data_out_reg[3];

--R1M1845Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT4
R1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a36_PORT_A_data_in_reg = DFFE(R1_ram_block2a36_PORT_A_data_in, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_data_in = ~GND;
R1_ram_block2a36_PORT_B_data_in_reg = DFFE(R1_ram_block2a36_PORT_B_data_in, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a36_PORT_A_address_reg = DFFE(R1_ram_block2a36_PORT_A_address, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a36_PORT_B_address_reg = DFFE(R1_ram_block2a36_PORT_B_address, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_write_enable = GND;
R1_ram_block2a36_PORT_A_write_enable_reg = DFFE(R1_ram_block2a36_PORT_A_write_enable, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_write_enable = GND;
R1_ram_block2a36_PORT_B_write_enable_reg = DFFE(R1_ram_block2a36_PORT_B_write_enable, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_clock_0 = M1__clk0;
R1_ram_block2a36_clock_1 = GND;
R1_ram_block2a36_clock_enable_0 = S3_w_anode3272w[3];
R1_ram_block2a36_clock_enable_1 = GND;
R1_ram_block2a36_PORT_A_data_out = MEMORY(R1_ram_block2a36_PORT_A_data_in_reg, R1_ram_block2a36_PORT_B_data_in_reg, R1_ram_block2a36_PORT_A_address_reg, R1_ram_block2a36_PORT_B_address_reg, R1_ram_block2a36_PORT_A_write_enable_reg, R1_ram_block2a36_PORT_B_write_enable_reg, , , R1_ram_block2a36_clock_0, R1_ram_block2a36_clock_1, R1_ram_block2a36_clock_enable_0, R1_ram_block2a36_clock_enable_1, , );
R1_ram_block2a36_PORT_A_data_out_reg = DFFE(R1_ram_block2a36_PORT_A_data_out, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1M1845Q = R1_ram_block2a36_PORT_A_data_out_reg[4];

--R1M1846Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT5
R1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a36_PORT_A_data_in_reg = DFFE(R1_ram_block2a36_PORT_A_data_in, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_data_in = ~GND;
R1_ram_block2a36_PORT_B_data_in_reg = DFFE(R1_ram_block2a36_PORT_B_data_in, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a36_PORT_A_address_reg = DFFE(R1_ram_block2a36_PORT_A_address, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a36_PORT_B_address_reg = DFFE(R1_ram_block2a36_PORT_B_address, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_write_enable = GND;
R1_ram_block2a36_PORT_A_write_enable_reg = DFFE(R1_ram_block2a36_PORT_A_write_enable, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_write_enable = GND;
R1_ram_block2a36_PORT_B_write_enable_reg = DFFE(R1_ram_block2a36_PORT_B_write_enable, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_clock_0 = M1__clk0;
R1_ram_block2a36_clock_1 = GND;
R1_ram_block2a36_clock_enable_0 = S3_w_anode3272w[3];
R1_ram_block2a36_clock_enable_1 = GND;
R1_ram_block2a36_PORT_A_data_out = MEMORY(R1_ram_block2a36_PORT_A_data_in_reg, R1_ram_block2a36_PORT_B_data_in_reg, R1_ram_block2a36_PORT_A_address_reg, R1_ram_block2a36_PORT_B_address_reg, R1_ram_block2a36_PORT_A_write_enable_reg, R1_ram_block2a36_PORT_B_write_enable_reg, , , R1_ram_block2a36_clock_0, R1_ram_block2a36_clock_1, R1_ram_block2a36_clock_enable_0, R1_ram_block2a36_clock_enable_1, , );
R1_ram_block2a36_PORT_A_data_out_reg = DFFE(R1_ram_block2a36_PORT_A_data_out, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1M1846Q = R1_ram_block2a36_PORT_A_data_out_reg[5];

--R1M1847Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT6
R1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a36_PORT_A_data_in_reg = DFFE(R1_ram_block2a36_PORT_A_data_in, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_data_in = ~GND;
R1_ram_block2a36_PORT_B_data_in_reg = DFFE(R1_ram_block2a36_PORT_B_data_in, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a36_PORT_A_address_reg = DFFE(R1_ram_block2a36_PORT_A_address, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a36_PORT_B_address_reg = DFFE(R1_ram_block2a36_PORT_B_address, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_write_enable = GND;
R1_ram_block2a36_PORT_A_write_enable_reg = DFFE(R1_ram_block2a36_PORT_A_write_enable, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_write_enable = GND;
R1_ram_block2a36_PORT_B_write_enable_reg = DFFE(R1_ram_block2a36_PORT_B_write_enable, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_clock_0 = M1__clk0;
R1_ram_block2a36_clock_1 = GND;
R1_ram_block2a36_clock_enable_0 = S3_w_anode3272w[3];
R1_ram_block2a36_clock_enable_1 = GND;
R1_ram_block2a36_PORT_A_data_out = MEMORY(R1_ram_block2a36_PORT_A_data_in_reg, R1_ram_block2a36_PORT_B_data_in_reg, R1_ram_block2a36_PORT_A_address_reg, R1_ram_block2a36_PORT_B_address_reg, R1_ram_block2a36_PORT_A_write_enable_reg, R1_ram_block2a36_PORT_B_write_enable_reg, , , R1_ram_block2a36_clock_0, R1_ram_block2a36_clock_1, R1_ram_block2a36_clock_enable_0, R1_ram_block2a36_clock_enable_1, , );
R1_ram_block2a36_PORT_A_data_out_reg = DFFE(R1_ram_block2a36_PORT_A_data_out, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1M1847Q = R1_ram_block2a36_PORT_A_data_out_reg[6];

--R1M1848Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT7
R1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a36_PORT_A_data_in_reg = DFFE(R1_ram_block2a36_PORT_A_data_in, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_data_in = ~GND;
R1_ram_block2a36_PORT_B_data_in_reg = DFFE(R1_ram_block2a36_PORT_B_data_in, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a36_PORT_A_address_reg = DFFE(R1_ram_block2a36_PORT_A_address, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a36_PORT_B_address_reg = DFFE(R1_ram_block2a36_PORT_B_address, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_write_enable = GND;
R1_ram_block2a36_PORT_A_write_enable_reg = DFFE(R1_ram_block2a36_PORT_A_write_enable, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_write_enable = GND;
R1_ram_block2a36_PORT_B_write_enable_reg = DFFE(R1_ram_block2a36_PORT_B_write_enable, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_clock_0 = M1__clk0;
R1_ram_block2a36_clock_1 = GND;
R1_ram_block2a36_clock_enable_0 = S3_w_anode3272w[3];
R1_ram_block2a36_clock_enable_1 = GND;
R1_ram_block2a36_PORT_A_data_out = MEMORY(R1_ram_block2a36_PORT_A_data_in_reg, R1_ram_block2a36_PORT_B_data_in_reg, R1_ram_block2a36_PORT_A_address_reg, R1_ram_block2a36_PORT_B_address_reg, R1_ram_block2a36_PORT_A_write_enable_reg, R1_ram_block2a36_PORT_B_write_enable_reg, , , R1_ram_block2a36_clock_0, R1_ram_block2a36_clock_1, R1_ram_block2a36_clock_enable_0, R1_ram_block2a36_clock_enable_1, , );
R1_ram_block2a36_PORT_A_data_out_reg = DFFE(R1_ram_block2a36_PORT_A_data_out, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1M1848Q = R1_ram_block2a36_PORT_A_data_out_reg[7];


--T1L226 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6589w~44
T1L226 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M1946Q # !R1_address_reg_a[7] & (R1M1846Q));


--R1_ram_block2a39 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a39_PORT_A_data_in_reg = DFFE(R1_ram_block2a39_PORT_A_data_in, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_data_in = ~GND;
R1_ram_block2a39_PORT_B_data_in_reg = DFFE(R1_ram_block2a39_PORT_B_data_in, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a39_PORT_A_address_reg = DFFE(R1_ram_block2a39_PORT_A_address, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a39_PORT_B_address_reg = DFFE(R1_ram_block2a39_PORT_B_address, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_write_enable = GND;
R1_ram_block2a39_PORT_A_write_enable_reg = DFFE(R1_ram_block2a39_PORT_A_write_enable, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_write_enable = GND;
R1_ram_block2a39_PORT_B_write_enable_reg = DFFE(R1_ram_block2a39_PORT_B_write_enable, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_clock_0 = M1__clk0;
R1_ram_block2a39_clock_1 = GND;
R1_ram_block2a39_clock_enable_0 = S3_w_anode3302w[3];
R1_ram_block2a39_clock_enable_1 = GND;
R1_ram_block2a39_PORT_A_data_out = MEMORY(R1_ram_block2a39_PORT_A_data_in_reg, R1_ram_block2a39_PORT_B_data_in_reg, R1_ram_block2a39_PORT_A_address_reg, R1_ram_block2a39_PORT_B_address_reg, R1_ram_block2a39_PORT_A_write_enable_reg, R1_ram_block2a39_PORT_B_write_enable_reg, , , R1_ram_block2a39_clock_0, R1_ram_block2a39_clock_1, R1_ram_block2a39_clock_enable_0, R1_ram_block2a39_clock_enable_1, , );
R1_ram_block2a39_PORT_A_data_out_reg = DFFE(R1_ram_block2a39_PORT_A_data_out, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39 = R1_ram_block2a39_PORT_A_data_out_reg[0];

--R1M1992Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT1
R1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a39_PORT_A_data_in_reg = DFFE(R1_ram_block2a39_PORT_A_data_in, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_data_in = ~GND;
R1_ram_block2a39_PORT_B_data_in_reg = DFFE(R1_ram_block2a39_PORT_B_data_in, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a39_PORT_A_address_reg = DFFE(R1_ram_block2a39_PORT_A_address, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a39_PORT_B_address_reg = DFFE(R1_ram_block2a39_PORT_B_address, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_write_enable = GND;
R1_ram_block2a39_PORT_A_write_enable_reg = DFFE(R1_ram_block2a39_PORT_A_write_enable, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_write_enable = GND;
R1_ram_block2a39_PORT_B_write_enable_reg = DFFE(R1_ram_block2a39_PORT_B_write_enable, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_clock_0 = M1__clk0;
R1_ram_block2a39_clock_1 = GND;
R1_ram_block2a39_clock_enable_0 = S3_w_anode3302w[3];
R1_ram_block2a39_clock_enable_1 = GND;
R1_ram_block2a39_PORT_A_data_out = MEMORY(R1_ram_block2a39_PORT_A_data_in_reg, R1_ram_block2a39_PORT_B_data_in_reg, R1_ram_block2a39_PORT_A_address_reg, R1_ram_block2a39_PORT_B_address_reg, R1_ram_block2a39_PORT_A_write_enable_reg, R1_ram_block2a39_PORT_B_write_enable_reg, , , R1_ram_block2a39_clock_0, R1_ram_block2a39_clock_1, R1_ram_block2a39_clock_enable_0, R1_ram_block2a39_clock_enable_1, , );
R1_ram_block2a39_PORT_A_data_out_reg = DFFE(R1_ram_block2a39_PORT_A_data_out, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1M1992Q = R1_ram_block2a39_PORT_A_data_out_reg[1];

--R1M1993Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT2
R1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a39_PORT_A_data_in_reg = DFFE(R1_ram_block2a39_PORT_A_data_in, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_data_in = ~GND;
R1_ram_block2a39_PORT_B_data_in_reg = DFFE(R1_ram_block2a39_PORT_B_data_in, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a39_PORT_A_address_reg = DFFE(R1_ram_block2a39_PORT_A_address, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a39_PORT_B_address_reg = DFFE(R1_ram_block2a39_PORT_B_address, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_write_enable = GND;
R1_ram_block2a39_PORT_A_write_enable_reg = DFFE(R1_ram_block2a39_PORT_A_write_enable, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_write_enable = GND;
R1_ram_block2a39_PORT_B_write_enable_reg = DFFE(R1_ram_block2a39_PORT_B_write_enable, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_clock_0 = M1__clk0;
R1_ram_block2a39_clock_1 = GND;
R1_ram_block2a39_clock_enable_0 = S3_w_anode3302w[3];
R1_ram_block2a39_clock_enable_1 = GND;
R1_ram_block2a39_PORT_A_data_out = MEMORY(R1_ram_block2a39_PORT_A_data_in_reg, R1_ram_block2a39_PORT_B_data_in_reg, R1_ram_block2a39_PORT_A_address_reg, R1_ram_block2a39_PORT_B_address_reg, R1_ram_block2a39_PORT_A_write_enable_reg, R1_ram_block2a39_PORT_B_write_enable_reg, , , R1_ram_block2a39_clock_0, R1_ram_block2a39_clock_1, R1_ram_block2a39_clock_enable_0, R1_ram_block2a39_clock_enable_1, , );
R1_ram_block2a39_PORT_A_data_out_reg = DFFE(R1_ram_block2a39_PORT_A_data_out, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1M1993Q = R1_ram_block2a39_PORT_A_data_out_reg[2];

--R1M1994Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT3
R1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a39_PORT_A_data_in_reg = DFFE(R1_ram_block2a39_PORT_A_data_in, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_data_in = ~GND;
R1_ram_block2a39_PORT_B_data_in_reg = DFFE(R1_ram_block2a39_PORT_B_data_in, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a39_PORT_A_address_reg = DFFE(R1_ram_block2a39_PORT_A_address, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a39_PORT_B_address_reg = DFFE(R1_ram_block2a39_PORT_B_address, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_write_enable = GND;
R1_ram_block2a39_PORT_A_write_enable_reg = DFFE(R1_ram_block2a39_PORT_A_write_enable, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_write_enable = GND;
R1_ram_block2a39_PORT_B_write_enable_reg = DFFE(R1_ram_block2a39_PORT_B_write_enable, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_clock_0 = M1__clk0;
R1_ram_block2a39_clock_1 = GND;
R1_ram_block2a39_clock_enable_0 = S3_w_anode3302w[3];
R1_ram_block2a39_clock_enable_1 = GND;
R1_ram_block2a39_PORT_A_data_out = MEMORY(R1_ram_block2a39_PORT_A_data_in_reg, R1_ram_block2a39_PORT_B_data_in_reg, R1_ram_block2a39_PORT_A_address_reg, R1_ram_block2a39_PORT_B_address_reg, R1_ram_block2a39_PORT_A_write_enable_reg, R1_ram_block2a39_PORT_B_write_enable_reg, , , R1_ram_block2a39_clock_0, R1_ram_block2a39_clock_1, R1_ram_block2a39_clock_enable_0, R1_ram_block2a39_clock_enable_1, , );
R1_ram_block2a39_PORT_A_data_out_reg = DFFE(R1_ram_block2a39_PORT_A_data_out, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1M1994Q = R1_ram_block2a39_PORT_A_data_out_reg[3];

--R1M1995Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT4
R1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a39_PORT_A_data_in_reg = DFFE(R1_ram_block2a39_PORT_A_data_in, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_data_in = ~GND;
R1_ram_block2a39_PORT_B_data_in_reg = DFFE(R1_ram_block2a39_PORT_B_data_in, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a39_PORT_A_address_reg = DFFE(R1_ram_block2a39_PORT_A_address, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a39_PORT_B_address_reg = DFFE(R1_ram_block2a39_PORT_B_address, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_write_enable = GND;
R1_ram_block2a39_PORT_A_write_enable_reg = DFFE(R1_ram_block2a39_PORT_A_write_enable, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_write_enable = GND;
R1_ram_block2a39_PORT_B_write_enable_reg = DFFE(R1_ram_block2a39_PORT_B_write_enable, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_clock_0 = M1__clk0;
R1_ram_block2a39_clock_1 = GND;
R1_ram_block2a39_clock_enable_0 = S3_w_anode3302w[3];
R1_ram_block2a39_clock_enable_1 = GND;
R1_ram_block2a39_PORT_A_data_out = MEMORY(R1_ram_block2a39_PORT_A_data_in_reg, R1_ram_block2a39_PORT_B_data_in_reg, R1_ram_block2a39_PORT_A_address_reg, R1_ram_block2a39_PORT_B_address_reg, R1_ram_block2a39_PORT_A_write_enable_reg, R1_ram_block2a39_PORT_B_write_enable_reg, , , R1_ram_block2a39_clock_0, R1_ram_block2a39_clock_1, R1_ram_block2a39_clock_enable_0, R1_ram_block2a39_clock_enable_1, , );
R1_ram_block2a39_PORT_A_data_out_reg = DFFE(R1_ram_block2a39_PORT_A_data_out, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1M1995Q = R1_ram_block2a39_PORT_A_data_out_reg[4];

--R1M1996Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT5
R1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a39_PORT_A_data_in_reg = DFFE(R1_ram_block2a39_PORT_A_data_in, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_data_in = ~GND;
R1_ram_block2a39_PORT_B_data_in_reg = DFFE(R1_ram_block2a39_PORT_B_data_in, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a39_PORT_A_address_reg = DFFE(R1_ram_block2a39_PORT_A_address, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a39_PORT_B_address_reg = DFFE(R1_ram_block2a39_PORT_B_address, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_write_enable = GND;
R1_ram_block2a39_PORT_A_write_enable_reg = DFFE(R1_ram_block2a39_PORT_A_write_enable, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_write_enable = GND;
R1_ram_block2a39_PORT_B_write_enable_reg = DFFE(R1_ram_block2a39_PORT_B_write_enable, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_clock_0 = M1__clk0;
R1_ram_block2a39_clock_1 = GND;
R1_ram_block2a39_clock_enable_0 = S3_w_anode3302w[3];
R1_ram_block2a39_clock_enable_1 = GND;
R1_ram_block2a39_PORT_A_data_out = MEMORY(R1_ram_block2a39_PORT_A_data_in_reg, R1_ram_block2a39_PORT_B_data_in_reg, R1_ram_block2a39_PORT_A_address_reg, R1_ram_block2a39_PORT_B_address_reg, R1_ram_block2a39_PORT_A_write_enable_reg, R1_ram_block2a39_PORT_B_write_enable_reg, , , R1_ram_block2a39_clock_0, R1_ram_block2a39_clock_1, R1_ram_block2a39_clock_enable_0, R1_ram_block2a39_clock_enable_1, , );
R1_ram_block2a39_PORT_A_data_out_reg = DFFE(R1_ram_block2a39_PORT_A_data_out, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1M1996Q = R1_ram_block2a39_PORT_A_data_out_reg[5];

--R1M1997Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT6
R1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a39_PORT_A_data_in_reg = DFFE(R1_ram_block2a39_PORT_A_data_in, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_data_in = ~GND;
R1_ram_block2a39_PORT_B_data_in_reg = DFFE(R1_ram_block2a39_PORT_B_data_in, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a39_PORT_A_address_reg = DFFE(R1_ram_block2a39_PORT_A_address, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a39_PORT_B_address_reg = DFFE(R1_ram_block2a39_PORT_B_address, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_write_enable = GND;
R1_ram_block2a39_PORT_A_write_enable_reg = DFFE(R1_ram_block2a39_PORT_A_write_enable, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_write_enable = GND;
R1_ram_block2a39_PORT_B_write_enable_reg = DFFE(R1_ram_block2a39_PORT_B_write_enable, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_clock_0 = M1__clk0;
R1_ram_block2a39_clock_1 = GND;
R1_ram_block2a39_clock_enable_0 = S3_w_anode3302w[3];
R1_ram_block2a39_clock_enable_1 = GND;
R1_ram_block2a39_PORT_A_data_out = MEMORY(R1_ram_block2a39_PORT_A_data_in_reg, R1_ram_block2a39_PORT_B_data_in_reg, R1_ram_block2a39_PORT_A_address_reg, R1_ram_block2a39_PORT_B_address_reg, R1_ram_block2a39_PORT_A_write_enable_reg, R1_ram_block2a39_PORT_B_write_enable_reg, , , R1_ram_block2a39_clock_0, R1_ram_block2a39_clock_1, R1_ram_block2a39_clock_enable_0, R1_ram_block2a39_clock_enable_1, , );
R1_ram_block2a39_PORT_A_data_out_reg = DFFE(R1_ram_block2a39_PORT_A_data_out, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1M1997Q = R1_ram_block2a39_PORT_A_data_out_reg[6];

--R1M1998Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT7
R1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a39_PORT_A_data_in_reg = DFFE(R1_ram_block2a39_PORT_A_data_in, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_data_in = ~GND;
R1_ram_block2a39_PORT_B_data_in_reg = DFFE(R1_ram_block2a39_PORT_B_data_in, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a39_PORT_A_address_reg = DFFE(R1_ram_block2a39_PORT_A_address, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a39_PORT_B_address_reg = DFFE(R1_ram_block2a39_PORT_B_address, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_write_enable = GND;
R1_ram_block2a39_PORT_A_write_enable_reg = DFFE(R1_ram_block2a39_PORT_A_write_enable, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_write_enable = GND;
R1_ram_block2a39_PORT_B_write_enable_reg = DFFE(R1_ram_block2a39_PORT_B_write_enable, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_clock_0 = M1__clk0;
R1_ram_block2a39_clock_1 = GND;
R1_ram_block2a39_clock_enable_0 = S3_w_anode3302w[3];
R1_ram_block2a39_clock_enable_1 = GND;
R1_ram_block2a39_PORT_A_data_out = MEMORY(R1_ram_block2a39_PORT_A_data_in_reg, R1_ram_block2a39_PORT_B_data_in_reg, R1_ram_block2a39_PORT_A_address_reg, R1_ram_block2a39_PORT_B_address_reg, R1_ram_block2a39_PORT_A_write_enable_reg, R1_ram_block2a39_PORT_B_write_enable_reg, , , R1_ram_block2a39_clock_0, R1_ram_block2a39_clock_1, R1_ram_block2a39_clock_enable_0, R1_ram_block2a39_clock_enable_1, , );
R1_ram_block2a39_PORT_A_data_out_reg = DFFE(R1_ram_block2a39_PORT_A_data_out, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1M1998Q = R1_ram_block2a39_PORT_A_data_out_reg[7];


--T1L227 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6589w~45
T1L227 = R1_address_reg_a[6] & (T1L226 & (R1M1996Q) # !T1L226 & R1M1896Q) # !R1_address_reg_a[6] & (T1L226);


--R1_ram_block2a6 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a6_PORT_A_data_in_reg = DFFE(R1_ram_block2a6_PORT_A_data_in, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_data_in = ~GND;
R1_ram_block2a6_PORT_B_data_in_reg = DFFE(R1_ram_block2a6_PORT_B_data_in, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a6_PORT_A_address_reg = DFFE(R1_ram_block2a6_PORT_A_address, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a6_PORT_B_address_reg = DFFE(R1_ram_block2a6_PORT_B_address, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_write_enable = GND;
R1_ram_block2a6_PORT_A_write_enable_reg = DFFE(R1_ram_block2a6_PORT_A_write_enable, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_write_enable = GND;
R1_ram_block2a6_PORT_B_write_enable_reg = DFFE(R1_ram_block2a6_PORT_B_write_enable, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_clock_0 = M1__clk0;
R1_ram_block2a6_clock_1 = GND;
R1_ram_block2a6_clock_enable_0 = S3L14;
R1_ram_block2a6_clock_enable_1 = GND;
R1_ram_block2a6_PORT_A_data_out = MEMORY(R1_ram_block2a6_PORT_A_data_in_reg, R1_ram_block2a6_PORT_B_data_in_reg, R1_ram_block2a6_PORT_A_address_reg, R1_ram_block2a6_PORT_B_address_reg, R1_ram_block2a6_PORT_A_write_enable_reg, R1_ram_block2a6_PORT_B_write_enable_reg, , , R1_ram_block2a6_clock_0, R1_ram_block2a6_clock_1, R1_ram_block2a6_clock_enable_0, R1_ram_block2a6_clock_enable_1, , );
R1_ram_block2a6_PORT_A_data_out_reg = DFFE(R1_ram_block2a6_PORT_A_data_out, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6 = R1_ram_block2a6_PORT_A_data_out_reg[0];

--R1M342Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT1
R1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a6_PORT_A_data_in_reg = DFFE(R1_ram_block2a6_PORT_A_data_in, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_data_in = ~GND;
R1_ram_block2a6_PORT_B_data_in_reg = DFFE(R1_ram_block2a6_PORT_B_data_in, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a6_PORT_A_address_reg = DFFE(R1_ram_block2a6_PORT_A_address, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a6_PORT_B_address_reg = DFFE(R1_ram_block2a6_PORT_B_address, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_write_enable = GND;
R1_ram_block2a6_PORT_A_write_enable_reg = DFFE(R1_ram_block2a6_PORT_A_write_enable, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_write_enable = GND;
R1_ram_block2a6_PORT_B_write_enable_reg = DFFE(R1_ram_block2a6_PORT_B_write_enable, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_clock_0 = M1__clk0;
R1_ram_block2a6_clock_1 = GND;
R1_ram_block2a6_clock_enable_0 = S3L14;
R1_ram_block2a6_clock_enable_1 = GND;
R1_ram_block2a6_PORT_A_data_out = MEMORY(R1_ram_block2a6_PORT_A_data_in_reg, R1_ram_block2a6_PORT_B_data_in_reg, R1_ram_block2a6_PORT_A_address_reg, R1_ram_block2a6_PORT_B_address_reg, R1_ram_block2a6_PORT_A_write_enable_reg, R1_ram_block2a6_PORT_B_write_enable_reg, , , R1_ram_block2a6_clock_0, R1_ram_block2a6_clock_1, R1_ram_block2a6_clock_enable_0, R1_ram_block2a6_clock_enable_1, , );
R1_ram_block2a6_PORT_A_data_out_reg = DFFE(R1_ram_block2a6_PORT_A_data_out, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1M342Q = R1_ram_block2a6_PORT_A_data_out_reg[1];

--R1M343Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT2
R1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a6_PORT_A_data_in_reg = DFFE(R1_ram_block2a6_PORT_A_data_in, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_data_in = ~GND;
R1_ram_block2a6_PORT_B_data_in_reg = DFFE(R1_ram_block2a6_PORT_B_data_in, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a6_PORT_A_address_reg = DFFE(R1_ram_block2a6_PORT_A_address, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a6_PORT_B_address_reg = DFFE(R1_ram_block2a6_PORT_B_address, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_write_enable = GND;
R1_ram_block2a6_PORT_A_write_enable_reg = DFFE(R1_ram_block2a6_PORT_A_write_enable, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_write_enable = GND;
R1_ram_block2a6_PORT_B_write_enable_reg = DFFE(R1_ram_block2a6_PORT_B_write_enable, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_clock_0 = M1__clk0;
R1_ram_block2a6_clock_1 = GND;
R1_ram_block2a6_clock_enable_0 = S3L14;
R1_ram_block2a6_clock_enable_1 = GND;
R1_ram_block2a6_PORT_A_data_out = MEMORY(R1_ram_block2a6_PORT_A_data_in_reg, R1_ram_block2a6_PORT_B_data_in_reg, R1_ram_block2a6_PORT_A_address_reg, R1_ram_block2a6_PORT_B_address_reg, R1_ram_block2a6_PORT_A_write_enable_reg, R1_ram_block2a6_PORT_B_write_enable_reg, , , R1_ram_block2a6_clock_0, R1_ram_block2a6_clock_1, R1_ram_block2a6_clock_enable_0, R1_ram_block2a6_clock_enable_1, , );
R1_ram_block2a6_PORT_A_data_out_reg = DFFE(R1_ram_block2a6_PORT_A_data_out, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1M343Q = R1_ram_block2a6_PORT_A_data_out_reg[2];

--R1M344Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT3
R1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a6_PORT_A_data_in_reg = DFFE(R1_ram_block2a6_PORT_A_data_in, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_data_in = ~GND;
R1_ram_block2a6_PORT_B_data_in_reg = DFFE(R1_ram_block2a6_PORT_B_data_in, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a6_PORT_A_address_reg = DFFE(R1_ram_block2a6_PORT_A_address, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a6_PORT_B_address_reg = DFFE(R1_ram_block2a6_PORT_B_address, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_write_enable = GND;
R1_ram_block2a6_PORT_A_write_enable_reg = DFFE(R1_ram_block2a6_PORT_A_write_enable, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_write_enable = GND;
R1_ram_block2a6_PORT_B_write_enable_reg = DFFE(R1_ram_block2a6_PORT_B_write_enable, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_clock_0 = M1__clk0;
R1_ram_block2a6_clock_1 = GND;
R1_ram_block2a6_clock_enable_0 = S3L14;
R1_ram_block2a6_clock_enable_1 = GND;
R1_ram_block2a6_PORT_A_data_out = MEMORY(R1_ram_block2a6_PORT_A_data_in_reg, R1_ram_block2a6_PORT_B_data_in_reg, R1_ram_block2a6_PORT_A_address_reg, R1_ram_block2a6_PORT_B_address_reg, R1_ram_block2a6_PORT_A_write_enable_reg, R1_ram_block2a6_PORT_B_write_enable_reg, , , R1_ram_block2a6_clock_0, R1_ram_block2a6_clock_1, R1_ram_block2a6_clock_enable_0, R1_ram_block2a6_clock_enable_1, , );
R1_ram_block2a6_PORT_A_data_out_reg = DFFE(R1_ram_block2a6_PORT_A_data_out, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1M344Q = R1_ram_block2a6_PORT_A_data_out_reg[3];

--R1M345Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT4
R1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a6_PORT_A_data_in_reg = DFFE(R1_ram_block2a6_PORT_A_data_in, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_data_in = ~GND;
R1_ram_block2a6_PORT_B_data_in_reg = DFFE(R1_ram_block2a6_PORT_B_data_in, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a6_PORT_A_address_reg = DFFE(R1_ram_block2a6_PORT_A_address, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a6_PORT_B_address_reg = DFFE(R1_ram_block2a6_PORT_B_address, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_write_enable = GND;
R1_ram_block2a6_PORT_A_write_enable_reg = DFFE(R1_ram_block2a6_PORT_A_write_enable, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_write_enable = GND;
R1_ram_block2a6_PORT_B_write_enable_reg = DFFE(R1_ram_block2a6_PORT_B_write_enable, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_clock_0 = M1__clk0;
R1_ram_block2a6_clock_1 = GND;
R1_ram_block2a6_clock_enable_0 = S3L14;
R1_ram_block2a6_clock_enable_1 = GND;
R1_ram_block2a6_PORT_A_data_out = MEMORY(R1_ram_block2a6_PORT_A_data_in_reg, R1_ram_block2a6_PORT_B_data_in_reg, R1_ram_block2a6_PORT_A_address_reg, R1_ram_block2a6_PORT_B_address_reg, R1_ram_block2a6_PORT_A_write_enable_reg, R1_ram_block2a6_PORT_B_write_enable_reg, , , R1_ram_block2a6_clock_0, R1_ram_block2a6_clock_1, R1_ram_block2a6_clock_enable_0, R1_ram_block2a6_clock_enable_1, , );
R1_ram_block2a6_PORT_A_data_out_reg = DFFE(R1_ram_block2a6_PORT_A_data_out, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1M345Q = R1_ram_block2a6_PORT_A_data_out_reg[4];

--R1M346Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT5
R1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a6_PORT_A_data_in_reg = DFFE(R1_ram_block2a6_PORT_A_data_in, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_data_in = ~GND;
R1_ram_block2a6_PORT_B_data_in_reg = DFFE(R1_ram_block2a6_PORT_B_data_in, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a6_PORT_A_address_reg = DFFE(R1_ram_block2a6_PORT_A_address, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a6_PORT_B_address_reg = DFFE(R1_ram_block2a6_PORT_B_address, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_write_enable = GND;
R1_ram_block2a6_PORT_A_write_enable_reg = DFFE(R1_ram_block2a6_PORT_A_write_enable, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_write_enable = GND;
R1_ram_block2a6_PORT_B_write_enable_reg = DFFE(R1_ram_block2a6_PORT_B_write_enable, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_clock_0 = M1__clk0;
R1_ram_block2a6_clock_1 = GND;
R1_ram_block2a6_clock_enable_0 = S3L14;
R1_ram_block2a6_clock_enable_1 = GND;
R1_ram_block2a6_PORT_A_data_out = MEMORY(R1_ram_block2a6_PORT_A_data_in_reg, R1_ram_block2a6_PORT_B_data_in_reg, R1_ram_block2a6_PORT_A_address_reg, R1_ram_block2a6_PORT_B_address_reg, R1_ram_block2a6_PORT_A_write_enable_reg, R1_ram_block2a6_PORT_B_write_enable_reg, , , R1_ram_block2a6_clock_0, R1_ram_block2a6_clock_1, R1_ram_block2a6_clock_enable_0, R1_ram_block2a6_clock_enable_1, , );
R1_ram_block2a6_PORT_A_data_out_reg = DFFE(R1_ram_block2a6_PORT_A_data_out, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1M346Q = R1_ram_block2a6_PORT_A_data_out_reg[5];

--R1M347Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT6
R1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a6_PORT_A_data_in_reg = DFFE(R1_ram_block2a6_PORT_A_data_in, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_data_in = ~GND;
R1_ram_block2a6_PORT_B_data_in_reg = DFFE(R1_ram_block2a6_PORT_B_data_in, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a6_PORT_A_address_reg = DFFE(R1_ram_block2a6_PORT_A_address, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a6_PORT_B_address_reg = DFFE(R1_ram_block2a6_PORT_B_address, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_write_enable = GND;
R1_ram_block2a6_PORT_A_write_enable_reg = DFFE(R1_ram_block2a6_PORT_A_write_enable, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_write_enable = GND;
R1_ram_block2a6_PORT_B_write_enable_reg = DFFE(R1_ram_block2a6_PORT_B_write_enable, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_clock_0 = M1__clk0;
R1_ram_block2a6_clock_1 = GND;
R1_ram_block2a6_clock_enable_0 = S3L14;
R1_ram_block2a6_clock_enable_1 = GND;
R1_ram_block2a6_PORT_A_data_out = MEMORY(R1_ram_block2a6_PORT_A_data_in_reg, R1_ram_block2a6_PORT_B_data_in_reg, R1_ram_block2a6_PORT_A_address_reg, R1_ram_block2a6_PORT_B_address_reg, R1_ram_block2a6_PORT_A_write_enable_reg, R1_ram_block2a6_PORT_B_write_enable_reg, , , R1_ram_block2a6_clock_0, R1_ram_block2a6_clock_1, R1_ram_block2a6_clock_enable_0, R1_ram_block2a6_clock_enable_1, , );
R1_ram_block2a6_PORT_A_data_out_reg = DFFE(R1_ram_block2a6_PORT_A_data_out, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1M347Q = R1_ram_block2a6_PORT_A_data_out_reg[6];

--R1M348Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT7
R1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a6_PORT_A_data_in_reg = DFFE(R1_ram_block2a6_PORT_A_data_in, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_data_in = ~GND;
R1_ram_block2a6_PORT_B_data_in_reg = DFFE(R1_ram_block2a6_PORT_B_data_in, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a6_PORT_A_address_reg = DFFE(R1_ram_block2a6_PORT_A_address, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a6_PORT_B_address_reg = DFFE(R1_ram_block2a6_PORT_B_address, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_write_enable = GND;
R1_ram_block2a6_PORT_A_write_enable_reg = DFFE(R1_ram_block2a6_PORT_A_write_enable, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_write_enable = GND;
R1_ram_block2a6_PORT_B_write_enable_reg = DFFE(R1_ram_block2a6_PORT_B_write_enable, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_clock_0 = M1__clk0;
R1_ram_block2a6_clock_1 = GND;
R1_ram_block2a6_clock_enable_0 = S3L14;
R1_ram_block2a6_clock_enable_1 = GND;
R1_ram_block2a6_PORT_A_data_out = MEMORY(R1_ram_block2a6_PORT_A_data_in_reg, R1_ram_block2a6_PORT_B_data_in_reg, R1_ram_block2a6_PORT_A_address_reg, R1_ram_block2a6_PORT_B_address_reg, R1_ram_block2a6_PORT_A_write_enable_reg, R1_ram_block2a6_PORT_B_write_enable_reg, , , R1_ram_block2a6_clock_0, R1_ram_block2a6_clock_1, R1_ram_block2a6_clock_enable_0, R1_ram_block2a6_clock_enable_1, , );
R1_ram_block2a6_PORT_A_data_out_reg = DFFE(R1_ram_block2a6_PORT_A_data_out, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1M348Q = R1_ram_block2a6_PORT_A_data_out_reg[7];


--R1_ram_block2a5 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a5_PORT_A_data_in_reg = DFFE(R1_ram_block2a5_PORT_A_data_in, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_data_in = ~GND;
R1_ram_block2a5_PORT_B_data_in_reg = DFFE(R1_ram_block2a5_PORT_B_data_in, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a5_PORT_A_address_reg = DFFE(R1_ram_block2a5_PORT_A_address, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a5_PORT_B_address_reg = DFFE(R1_ram_block2a5_PORT_B_address, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_write_enable = GND;
R1_ram_block2a5_PORT_A_write_enable_reg = DFFE(R1_ram_block2a5_PORT_A_write_enable, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_write_enable = GND;
R1_ram_block2a5_PORT_B_write_enable_reg = DFFE(R1_ram_block2a5_PORT_B_write_enable, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_clock_0 = M1__clk0;
R1_ram_block2a5_clock_1 = GND;
R1_ram_block2a5_clock_enable_0 = S3_w_anode2909w[3];
R1_ram_block2a5_clock_enable_1 = GND;
R1_ram_block2a5_PORT_A_data_out = MEMORY(R1_ram_block2a5_PORT_A_data_in_reg, R1_ram_block2a5_PORT_B_data_in_reg, R1_ram_block2a5_PORT_A_address_reg, R1_ram_block2a5_PORT_B_address_reg, R1_ram_block2a5_PORT_A_write_enable_reg, R1_ram_block2a5_PORT_B_write_enable_reg, , , R1_ram_block2a5_clock_0, R1_ram_block2a5_clock_1, R1_ram_block2a5_clock_enable_0, R1_ram_block2a5_clock_enable_1, , );
R1_ram_block2a5_PORT_A_data_out_reg = DFFE(R1_ram_block2a5_PORT_A_data_out, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5 = R1_ram_block2a5_PORT_A_data_out_reg[0];

--R1M292Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT1
R1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a5_PORT_A_data_in_reg = DFFE(R1_ram_block2a5_PORT_A_data_in, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_data_in = ~GND;
R1_ram_block2a5_PORT_B_data_in_reg = DFFE(R1_ram_block2a5_PORT_B_data_in, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a5_PORT_A_address_reg = DFFE(R1_ram_block2a5_PORT_A_address, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a5_PORT_B_address_reg = DFFE(R1_ram_block2a5_PORT_B_address, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_write_enable = GND;
R1_ram_block2a5_PORT_A_write_enable_reg = DFFE(R1_ram_block2a5_PORT_A_write_enable, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_write_enable = GND;
R1_ram_block2a5_PORT_B_write_enable_reg = DFFE(R1_ram_block2a5_PORT_B_write_enable, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_clock_0 = M1__clk0;
R1_ram_block2a5_clock_1 = GND;
R1_ram_block2a5_clock_enable_0 = S3_w_anode2909w[3];
R1_ram_block2a5_clock_enable_1 = GND;
R1_ram_block2a5_PORT_A_data_out = MEMORY(R1_ram_block2a5_PORT_A_data_in_reg, R1_ram_block2a5_PORT_B_data_in_reg, R1_ram_block2a5_PORT_A_address_reg, R1_ram_block2a5_PORT_B_address_reg, R1_ram_block2a5_PORT_A_write_enable_reg, R1_ram_block2a5_PORT_B_write_enable_reg, , , R1_ram_block2a5_clock_0, R1_ram_block2a5_clock_1, R1_ram_block2a5_clock_enable_0, R1_ram_block2a5_clock_enable_1, , );
R1_ram_block2a5_PORT_A_data_out_reg = DFFE(R1_ram_block2a5_PORT_A_data_out, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1M292Q = R1_ram_block2a5_PORT_A_data_out_reg[1];

--R1M293Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT2
R1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a5_PORT_A_data_in_reg = DFFE(R1_ram_block2a5_PORT_A_data_in, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_data_in = ~GND;
R1_ram_block2a5_PORT_B_data_in_reg = DFFE(R1_ram_block2a5_PORT_B_data_in, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a5_PORT_A_address_reg = DFFE(R1_ram_block2a5_PORT_A_address, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a5_PORT_B_address_reg = DFFE(R1_ram_block2a5_PORT_B_address, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_write_enable = GND;
R1_ram_block2a5_PORT_A_write_enable_reg = DFFE(R1_ram_block2a5_PORT_A_write_enable, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_write_enable = GND;
R1_ram_block2a5_PORT_B_write_enable_reg = DFFE(R1_ram_block2a5_PORT_B_write_enable, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_clock_0 = M1__clk0;
R1_ram_block2a5_clock_1 = GND;
R1_ram_block2a5_clock_enable_0 = S3_w_anode2909w[3];
R1_ram_block2a5_clock_enable_1 = GND;
R1_ram_block2a5_PORT_A_data_out = MEMORY(R1_ram_block2a5_PORT_A_data_in_reg, R1_ram_block2a5_PORT_B_data_in_reg, R1_ram_block2a5_PORT_A_address_reg, R1_ram_block2a5_PORT_B_address_reg, R1_ram_block2a5_PORT_A_write_enable_reg, R1_ram_block2a5_PORT_B_write_enable_reg, , , R1_ram_block2a5_clock_0, R1_ram_block2a5_clock_1, R1_ram_block2a5_clock_enable_0, R1_ram_block2a5_clock_enable_1, , );
R1_ram_block2a5_PORT_A_data_out_reg = DFFE(R1_ram_block2a5_PORT_A_data_out, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1M293Q = R1_ram_block2a5_PORT_A_data_out_reg[2];

--R1M294Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT3
R1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a5_PORT_A_data_in_reg = DFFE(R1_ram_block2a5_PORT_A_data_in, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_data_in = ~GND;
R1_ram_block2a5_PORT_B_data_in_reg = DFFE(R1_ram_block2a5_PORT_B_data_in, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a5_PORT_A_address_reg = DFFE(R1_ram_block2a5_PORT_A_address, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a5_PORT_B_address_reg = DFFE(R1_ram_block2a5_PORT_B_address, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_write_enable = GND;
R1_ram_block2a5_PORT_A_write_enable_reg = DFFE(R1_ram_block2a5_PORT_A_write_enable, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_write_enable = GND;
R1_ram_block2a5_PORT_B_write_enable_reg = DFFE(R1_ram_block2a5_PORT_B_write_enable, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_clock_0 = M1__clk0;
R1_ram_block2a5_clock_1 = GND;
R1_ram_block2a5_clock_enable_0 = S3_w_anode2909w[3];
R1_ram_block2a5_clock_enable_1 = GND;
R1_ram_block2a5_PORT_A_data_out = MEMORY(R1_ram_block2a5_PORT_A_data_in_reg, R1_ram_block2a5_PORT_B_data_in_reg, R1_ram_block2a5_PORT_A_address_reg, R1_ram_block2a5_PORT_B_address_reg, R1_ram_block2a5_PORT_A_write_enable_reg, R1_ram_block2a5_PORT_B_write_enable_reg, , , R1_ram_block2a5_clock_0, R1_ram_block2a5_clock_1, R1_ram_block2a5_clock_enable_0, R1_ram_block2a5_clock_enable_1, , );
R1_ram_block2a5_PORT_A_data_out_reg = DFFE(R1_ram_block2a5_PORT_A_data_out, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1M294Q = R1_ram_block2a5_PORT_A_data_out_reg[3];

--R1M295Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT4
R1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a5_PORT_A_data_in_reg = DFFE(R1_ram_block2a5_PORT_A_data_in, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_data_in = ~GND;
R1_ram_block2a5_PORT_B_data_in_reg = DFFE(R1_ram_block2a5_PORT_B_data_in, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a5_PORT_A_address_reg = DFFE(R1_ram_block2a5_PORT_A_address, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a5_PORT_B_address_reg = DFFE(R1_ram_block2a5_PORT_B_address, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_write_enable = GND;
R1_ram_block2a5_PORT_A_write_enable_reg = DFFE(R1_ram_block2a5_PORT_A_write_enable, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_write_enable = GND;
R1_ram_block2a5_PORT_B_write_enable_reg = DFFE(R1_ram_block2a5_PORT_B_write_enable, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_clock_0 = M1__clk0;
R1_ram_block2a5_clock_1 = GND;
R1_ram_block2a5_clock_enable_0 = S3_w_anode2909w[3];
R1_ram_block2a5_clock_enable_1 = GND;
R1_ram_block2a5_PORT_A_data_out = MEMORY(R1_ram_block2a5_PORT_A_data_in_reg, R1_ram_block2a5_PORT_B_data_in_reg, R1_ram_block2a5_PORT_A_address_reg, R1_ram_block2a5_PORT_B_address_reg, R1_ram_block2a5_PORT_A_write_enable_reg, R1_ram_block2a5_PORT_B_write_enable_reg, , , R1_ram_block2a5_clock_0, R1_ram_block2a5_clock_1, R1_ram_block2a5_clock_enable_0, R1_ram_block2a5_clock_enable_1, , );
R1_ram_block2a5_PORT_A_data_out_reg = DFFE(R1_ram_block2a5_PORT_A_data_out, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1M295Q = R1_ram_block2a5_PORT_A_data_out_reg[4];

--R1M296Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT5
R1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a5_PORT_A_data_in_reg = DFFE(R1_ram_block2a5_PORT_A_data_in, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_data_in = ~GND;
R1_ram_block2a5_PORT_B_data_in_reg = DFFE(R1_ram_block2a5_PORT_B_data_in, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a5_PORT_A_address_reg = DFFE(R1_ram_block2a5_PORT_A_address, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a5_PORT_B_address_reg = DFFE(R1_ram_block2a5_PORT_B_address, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_write_enable = GND;
R1_ram_block2a5_PORT_A_write_enable_reg = DFFE(R1_ram_block2a5_PORT_A_write_enable, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_write_enable = GND;
R1_ram_block2a5_PORT_B_write_enable_reg = DFFE(R1_ram_block2a5_PORT_B_write_enable, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_clock_0 = M1__clk0;
R1_ram_block2a5_clock_1 = GND;
R1_ram_block2a5_clock_enable_0 = S3_w_anode2909w[3];
R1_ram_block2a5_clock_enable_1 = GND;
R1_ram_block2a5_PORT_A_data_out = MEMORY(R1_ram_block2a5_PORT_A_data_in_reg, R1_ram_block2a5_PORT_B_data_in_reg, R1_ram_block2a5_PORT_A_address_reg, R1_ram_block2a5_PORT_B_address_reg, R1_ram_block2a5_PORT_A_write_enable_reg, R1_ram_block2a5_PORT_B_write_enable_reg, , , R1_ram_block2a5_clock_0, R1_ram_block2a5_clock_1, R1_ram_block2a5_clock_enable_0, R1_ram_block2a5_clock_enable_1, , );
R1_ram_block2a5_PORT_A_data_out_reg = DFFE(R1_ram_block2a5_PORT_A_data_out, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1M296Q = R1_ram_block2a5_PORT_A_data_out_reg[5];

--R1M297Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT6
R1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a5_PORT_A_data_in_reg = DFFE(R1_ram_block2a5_PORT_A_data_in, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_data_in = ~GND;
R1_ram_block2a5_PORT_B_data_in_reg = DFFE(R1_ram_block2a5_PORT_B_data_in, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a5_PORT_A_address_reg = DFFE(R1_ram_block2a5_PORT_A_address, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a5_PORT_B_address_reg = DFFE(R1_ram_block2a5_PORT_B_address, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_write_enable = GND;
R1_ram_block2a5_PORT_A_write_enable_reg = DFFE(R1_ram_block2a5_PORT_A_write_enable, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_write_enable = GND;
R1_ram_block2a5_PORT_B_write_enable_reg = DFFE(R1_ram_block2a5_PORT_B_write_enable, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_clock_0 = M1__clk0;
R1_ram_block2a5_clock_1 = GND;
R1_ram_block2a5_clock_enable_0 = S3_w_anode2909w[3];
R1_ram_block2a5_clock_enable_1 = GND;
R1_ram_block2a5_PORT_A_data_out = MEMORY(R1_ram_block2a5_PORT_A_data_in_reg, R1_ram_block2a5_PORT_B_data_in_reg, R1_ram_block2a5_PORT_A_address_reg, R1_ram_block2a5_PORT_B_address_reg, R1_ram_block2a5_PORT_A_write_enable_reg, R1_ram_block2a5_PORT_B_write_enable_reg, , , R1_ram_block2a5_clock_0, R1_ram_block2a5_clock_1, R1_ram_block2a5_clock_enable_0, R1_ram_block2a5_clock_enable_1, , );
R1_ram_block2a5_PORT_A_data_out_reg = DFFE(R1_ram_block2a5_PORT_A_data_out, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1M297Q = R1_ram_block2a5_PORT_A_data_out_reg[6];

--R1M298Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT7
R1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a5_PORT_A_data_in_reg = DFFE(R1_ram_block2a5_PORT_A_data_in, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_data_in = ~GND;
R1_ram_block2a5_PORT_B_data_in_reg = DFFE(R1_ram_block2a5_PORT_B_data_in, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a5_PORT_A_address_reg = DFFE(R1_ram_block2a5_PORT_A_address, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a5_PORT_B_address_reg = DFFE(R1_ram_block2a5_PORT_B_address, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_write_enable = GND;
R1_ram_block2a5_PORT_A_write_enable_reg = DFFE(R1_ram_block2a5_PORT_A_write_enable, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_write_enable = GND;
R1_ram_block2a5_PORT_B_write_enable_reg = DFFE(R1_ram_block2a5_PORT_B_write_enable, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_clock_0 = M1__clk0;
R1_ram_block2a5_clock_1 = GND;
R1_ram_block2a5_clock_enable_0 = S3_w_anode2909w[3];
R1_ram_block2a5_clock_enable_1 = GND;
R1_ram_block2a5_PORT_A_data_out = MEMORY(R1_ram_block2a5_PORT_A_data_in_reg, R1_ram_block2a5_PORT_B_data_in_reg, R1_ram_block2a5_PORT_A_address_reg, R1_ram_block2a5_PORT_B_address_reg, R1_ram_block2a5_PORT_A_write_enable_reg, R1_ram_block2a5_PORT_B_write_enable_reg, , , R1_ram_block2a5_clock_0, R1_ram_block2a5_clock_1, R1_ram_block2a5_clock_enable_0, R1_ram_block2a5_clock_enable_1, , );
R1_ram_block2a5_PORT_A_data_out_reg = DFFE(R1_ram_block2a5_PORT_A_data_out, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1M298Q = R1_ram_block2a5_PORT_A_data_out_reg[7];


--R1_ram_block2a4 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a4_PORT_A_data_in_reg = DFFE(R1_ram_block2a4_PORT_A_data_in, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_data_in = ~GND;
R1_ram_block2a4_PORT_B_data_in_reg = DFFE(R1_ram_block2a4_PORT_B_data_in, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a4_PORT_A_address_reg = DFFE(R1_ram_block2a4_PORT_A_address, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a4_PORT_B_address_reg = DFFE(R1_ram_block2a4_PORT_B_address, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_write_enable = GND;
R1_ram_block2a4_PORT_A_write_enable_reg = DFFE(R1_ram_block2a4_PORT_A_write_enable, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_write_enable = GND;
R1_ram_block2a4_PORT_B_write_enable_reg = DFFE(R1_ram_block2a4_PORT_B_write_enable, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_clock_0 = M1__clk0;
R1_ram_block2a4_clock_1 = GND;
R1_ram_block2a4_clock_enable_0 = S3L10;
R1_ram_block2a4_clock_enable_1 = GND;
R1_ram_block2a4_PORT_A_data_out = MEMORY(R1_ram_block2a4_PORT_A_data_in_reg, R1_ram_block2a4_PORT_B_data_in_reg, R1_ram_block2a4_PORT_A_address_reg, R1_ram_block2a4_PORT_B_address_reg, R1_ram_block2a4_PORT_A_write_enable_reg, R1_ram_block2a4_PORT_B_write_enable_reg, , , R1_ram_block2a4_clock_0, R1_ram_block2a4_clock_1, R1_ram_block2a4_clock_enable_0, R1_ram_block2a4_clock_enable_1, , );
R1_ram_block2a4_PORT_A_data_out_reg = DFFE(R1_ram_block2a4_PORT_A_data_out, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4 = R1_ram_block2a4_PORT_A_data_out_reg[0];

--R1M242Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT1
R1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a4_PORT_A_data_in_reg = DFFE(R1_ram_block2a4_PORT_A_data_in, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_data_in = ~GND;
R1_ram_block2a4_PORT_B_data_in_reg = DFFE(R1_ram_block2a4_PORT_B_data_in, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a4_PORT_A_address_reg = DFFE(R1_ram_block2a4_PORT_A_address, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a4_PORT_B_address_reg = DFFE(R1_ram_block2a4_PORT_B_address, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_write_enable = GND;
R1_ram_block2a4_PORT_A_write_enable_reg = DFFE(R1_ram_block2a4_PORT_A_write_enable, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_write_enable = GND;
R1_ram_block2a4_PORT_B_write_enable_reg = DFFE(R1_ram_block2a4_PORT_B_write_enable, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_clock_0 = M1__clk0;
R1_ram_block2a4_clock_1 = GND;
R1_ram_block2a4_clock_enable_0 = S3L10;
R1_ram_block2a4_clock_enable_1 = GND;
R1_ram_block2a4_PORT_A_data_out = MEMORY(R1_ram_block2a4_PORT_A_data_in_reg, R1_ram_block2a4_PORT_B_data_in_reg, R1_ram_block2a4_PORT_A_address_reg, R1_ram_block2a4_PORT_B_address_reg, R1_ram_block2a4_PORT_A_write_enable_reg, R1_ram_block2a4_PORT_B_write_enable_reg, , , R1_ram_block2a4_clock_0, R1_ram_block2a4_clock_1, R1_ram_block2a4_clock_enable_0, R1_ram_block2a4_clock_enable_1, , );
R1_ram_block2a4_PORT_A_data_out_reg = DFFE(R1_ram_block2a4_PORT_A_data_out, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1M242Q = R1_ram_block2a4_PORT_A_data_out_reg[1];

--R1M243Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT2
R1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a4_PORT_A_data_in_reg = DFFE(R1_ram_block2a4_PORT_A_data_in, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_data_in = ~GND;
R1_ram_block2a4_PORT_B_data_in_reg = DFFE(R1_ram_block2a4_PORT_B_data_in, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a4_PORT_A_address_reg = DFFE(R1_ram_block2a4_PORT_A_address, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a4_PORT_B_address_reg = DFFE(R1_ram_block2a4_PORT_B_address, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_write_enable = GND;
R1_ram_block2a4_PORT_A_write_enable_reg = DFFE(R1_ram_block2a4_PORT_A_write_enable, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_write_enable = GND;
R1_ram_block2a4_PORT_B_write_enable_reg = DFFE(R1_ram_block2a4_PORT_B_write_enable, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_clock_0 = M1__clk0;
R1_ram_block2a4_clock_1 = GND;
R1_ram_block2a4_clock_enable_0 = S3L10;
R1_ram_block2a4_clock_enable_1 = GND;
R1_ram_block2a4_PORT_A_data_out = MEMORY(R1_ram_block2a4_PORT_A_data_in_reg, R1_ram_block2a4_PORT_B_data_in_reg, R1_ram_block2a4_PORT_A_address_reg, R1_ram_block2a4_PORT_B_address_reg, R1_ram_block2a4_PORT_A_write_enable_reg, R1_ram_block2a4_PORT_B_write_enable_reg, , , R1_ram_block2a4_clock_0, R1_ram_block2a4_clock_1, R1_ram_block2a4_clock_enable_0, R1_ram_block2a4_clock_enable_1, , );
R1_ram_block2a4_PORT_A_data_out_reg = DFFE(R1_ram_block2a4_PORT_A_data_out, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1M243Q = R1_ram_block2a4_PORT_A_data_out_reg[2];

--R1M244Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT3
R1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a4_PORT_A_data_in_reg = DFFE(R1_ram_block2a4_PORT_A_data_in, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_data_in = ~GND;
R1_ram_block2a4_PORT_B_data_in_reg = DFFE(R1_ram_block2a4_PORT_B_data_in, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a4_PORT_A_address_reg = DFFE(R1_ram_block2a4_PORT_A_address, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a4_PORT_B_address_reg = DFFE(R1_ram_block2a4_PORT_B_address, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_write_enable = GND;
R1_ram_block2a4_PORT_A_write_enable_reg = DFFE(R1_ram_block2a4_PORT_A_write_enable, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_write_enable = GND;
R1_ram_block2a4_PORT_B_write_enable_reg = DFFE(R1_ram_block2a4_PORT_B_write_enable, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_clock_0 = M1__clk0;
R1_ram_block2a4_clock_1 = GND;
R1_ram_block2a4_clock_enable_0 = S3L10;
R1_ram_block2a4_clock_enable_1 = GND;
R1_ram_block2a4_PORT_A_data_out = MEMORY(R1_ram_block2a4_PORT_A_data_in_reg, R1_ram_block2a4_PORT_B_data_in_reg, R1_ram_block2a4_PORT_A_address_reg, R1_ram_block2a4_PORT_B_address_reg, R1_ram_block2a4_PORT_A_write_enable_reg, R1_ram_block2a4_PORT_B_write_enable_reg, , , R1_ram_block2a4_clock_0, R1_ram_block2a4_clock_1, R1_ram_block2a4_clock_enable_0, R1_ram_block2a4_clock_enable_1, , );
R1_ram_block2a4_PORT_A_data_out_reg = DFFE(R1_ram_block2a4_PORT_A_data_out, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1M244Q = R1_ram_block2a4_PORT_A_data_out_reg[3];

--R1M245Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT4
R1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a4_PORT_A_data_in_reg = DFFE(R1_ram_block2a4_PORT_A_data_in, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_data_in = ~GND;
R1_ram_block2a4_PORT_B_data_in_reg = DFFE(R1_ram_block2a4_PORT_B_data_in, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a4_PORT_A_address_reg = DFFE(R1_ram_block2a4_PORT_A_address, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a4_PORT_B_address_reg = DFFE(R1_ram_block2a4_PORT_B_address, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_write_enable = GND;
R1_ram_block2a4_PORT_A_write_enable_reg = DFFE(R1_ram_block2a4_PORT_A_write_enable, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_write_enable = GND;
R1_ram_block2a4_PORT_B_write_enable_reg = DFFE(R1_ram_block2a4_PORT_B_write_enable, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_clock_0 = M1__clk0;
R1_ram_block2a4_clock_1 = GND;
R1_ram_block2a4_clock_enable_0 = S3L10;
R1_ram_block2a4_clock_enable_1 = GND;
R1_ram_block2a4_PORT_A_data_out = MEMORY(R1_ram_block2a4_PORT_A_data_in_reg, R1_ram_block2a4_PORT_B_data_in_reg, R1_ram_block2a4_PORT_A_address_reg, R1_ram_block2a4_PORT_B_address_reg, R1_ram_block2a4_PORT_A_write_enable_reg, R1_ram_block2a4_PORT_B_write_enable_reg, , , R1_ram_block2a4_clock_0, R1_ram_block2a4_clock_1, R1_ram_block2a4_clock_enable_0, R1_ram_block2a4_clock_enable_1, , );
R1_ram_block2a4_PORT_A_data_out_reg = DFFE(R1_ram_block2a4_PORT_A_data_out, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1M245Q = R1_ram_block2a4_PORT_A_data_out_reg[4];

--R1M246Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT5
R1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a4_PORT_A_data_in_reg = DFFE(R1_ram_block2a4_PORT_A_data_in, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_data_in = ~GND;
R1_ram_block2a4_PORT_B_data_in_reg = DFFE(R1_ram_block2a4_PORT_B_data_in, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a4_PORT_A_address_reg = DFFE(R1_ram_block2a4_PORT_A_address, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a4_PORT_B_address_reg = DFFE(R1_ram_block2a4_PORT_B_address, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_write_enable = GND;
R1_ram_block2a4_PORT_A_write_enable_reg = DFFE(R1_ram_block2a4_PORT_A_write_enable, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_write_enable = GND;
R1_ram_block2a4_PORT_B_write_enable_reg = DFFE(R1_ram_block2a4_PORT_B_write_enable, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_clock_0 = M1__clk0;
R1_ram_block2a4_clock_1 = GND;
R1_ram_block2a4_clock_enable_0 = S3L10;
R1_ram_block2a4_clock_enable_1 = GND;
R1_ram_block2a4_PORT_A_data_out = MEMORY(R1_ram_block2a4_PORT_A_data_in_reg, R1_ram_block2a4_PORT_B_data_in_reg, R1_ram_block2a4_PORT_A_address_reg, R1_ram_block2a4_PORT_B_address_reg, R1_ram_block2a4_PORT_A_write_enable_reg, R1_ram_block2a4_PORT_B_write_enable_reg, , , R1_ram_block2a4_clock_0, R1_ram_block2a4_clock_1, R1_ram_block2a4_clock_enable_0, R1_ram_block2a4_clock_enable_1, , );
R1_ram_block2a4_PORT_A_data_out_reg = DFFE(R1_ram_block2a4_PORT_A_data_out, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1M246Q = R1_ram_block2a4_PORT_A_data_out_reg[5];

--R1M247Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT6
R1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a4_PORT_A_data_in_reg = DFFE(R1_ram_block2a4_PORT_A_data_in, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_data_in = ~GND;
R1_ram_block2a4_PORT_B_data_in_reg = DFFE(R1_ram_block2a4_PORT_B_data_in, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a4_PORT_A_address_reg = DFFE(R1_ram_block2a4_PORT_A_address, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a4_PORT_B_address_reg = DFFE(R1_ram_block2a4_PORT_B_address, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_write_enable = GND;
R1_ram_block2a4_PORT_A_write_enable_reg = DFFE(R1_ram_block2a4_PORT_A_write_enable, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_write_enable = GND;
R1_ram_block2a4_PORT_B_write_enable_reg = DFFE(R1_ram_block2a4_PORT_B_write_enable, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_clock_0 = M1__clk0;
R1_ram_block2a4_clock_1 = GND;
R1_ram_block2a4_clock_enable_0 = S3L10;
R1_ram_block2a4_clock_enable_1 = GND;
R1_ram_block2a4_PORT_A_data_out = MEMORY(R1_ram_block2a4_PORT_A_data_in_reg, R1_ram_block2a4_PORT_B_data_in_reg, R1_ram_block2a4_PORT_A_address_reg, R1_ram_block2a4_PORT_B_address_reg, R1_ram_block2a4_PORT_A_write_enable_reg, R1_ram_block2a4_PORT_B_write_enable_reg, , , R1_ram_block2a4_clock_0, R1_ram_block2a4_clock_1, R1_ram_block2a4_clock_enable_0, R1_ram_block2a4_clock_enable_1, , );
R1_ram_block2a4_PORT_A_data_out_reg = DFFE(R1_ram_block2a4_PORT_A_data_out, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1M247Q = R1_ram_block2a4_PORT_A_data_out_reg[6];

--R1M248Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT7
R1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a4_PORT_A_data_in_reg = DFFE(R1_ram_block2a4_PORT_A_data_in, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_data_in = ~GND;
R1_ram_block2a4_PORT_B_data_in_reg = DFFE(R1_ram_block2a4_PORT_B_data_in, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a4_PORT_A_address_reg = DFFE(R1_ram_block2a4_PORT_A_address, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a4_PORT_B_address_reg = DFFE(R1_ram_block2a4_PORT_B_address, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_write_enable = GND;
R1_ram_block2a4_PORT_A_write_enable_reg = DFFE(R1_ram_block2a4_PORT_A_write_enable, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_write_enable = GND;
R1_ram_block2a4_PORT_B_write_enable_reg = DFFE(R1_ram_block2a4_PORT_B_write_enable, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_clock_0 = M1__clk0;
R1_ram_block2a4_clock_1 = GND;
R1_ram_block2a4_clock_enable_0 = S3L10;
R1_ram_block2a4_clock_enable_1 = GND;
R1_ram_block2a4_PORT_A_data_out = MEMORY(R1_ram_block2a4_PORT_A_data_in_reg, R1_ram_block2a4_PORT_B_data_in_reg, R1_ram_block2a4_PORT_A_address_reg, R1_ram_block2a4_PORT_B_address_reg, R1_ram_block2a4_PORT_A_write_enable_reg, R1_ram_block2a4_PORT_B_write_enable_reg, , , R1_ram_block2a4_clock_0, R1_ram_block2a4_clock_1, R1_ram_block2a4_clock_enable_0, R1_ram_block2a4_clock_enable_1, , );
R1_ram_block2a4_PORT_A_data_out_reg = DFFE(R1_ram_block2a4_PORT_A_data_out, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1M248Q = R1_ram_block2a4_PORT_A_data_out_reg[7];


--T1L214 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6388w~44
T1L214 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M296Q # !R1_address_reg_a[6] & (R1M246Q));


--R1_ram_block2a7 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a7_PORT_A_data_in_reg = DFFE(R1_ram_block2a7_PORT_A_data_in, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_data_in = ~GND;
R1_ram_block2a7_PORT_B_data_in_reg = DFFE(R1_ram_block2a7_PORT_B_data_in, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a7_PORT_A_address_reg = DFFE(R1_ram_block2a7_PORT_A_address, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a7_PORT_B_address_reg = DFFE(R1_ram_block2a7_PORT_B_address, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_write_enable = GND;
R1_ram_block2a7_PORT_A_write_enable_reg = DFFE(R1_ram_block2a7_PORT_A_write_enable, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_write_enable = GND;
R1_ram_block2a7_PORT_B_write_enable_reg = DFFE(R1_ram_block2a7_PORT_B_write_enable, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_clock_0 = M1__clk0;
R1_ram_block2a7_clock_1 = GND;
R1_ram_block2a7_clock_enable_0 = S3_w_anode2929w[3];
R1_ram_block2a7_clock_enable_1 = GND;
R1_ram_block2a7_PORT_A_data_out = MEMORY(R1_ram_block2a7_PORT_A_data_in_reg, R1_ram_block2a7_PORT_B_data_in_reg, R1_ram_block2a7_PORT_A_address_reg, R1_ram_block2a7_PORT_B_address_reg, R1_ram_block2a7_PORT_A_write_enable_reg, R1_ram_block2a7_PORT_B_write_enable_reg, , , R1_ram_block2a7_clock_0, R1_ram_block2a7_clock_1, R1_ram_block2a7_clock_enable_0, R1_ram_block2a7_clock_enable_1, , );
R1_ram_block2a7_PORT_A_data_out_reg = DFFE(R1_ram_block2a7_PORT_A_data_out, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7 = R1_ram_block2a7_PORT_A_data_out_reg[0];

--R1M392Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT1
R1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a7_PORT_A_data_in_reg = DFFE(R1_ram_block2a7_PORT_A_data_in, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_data_in = ~GND;
R1_ram_block2a7_PORT_B_data_in_reg = DFFE(R1_ram_block2a7_PORT_B_data_in, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a7_PORT_A_address_reg = DFFE(R1_ram_block2a7_PORT_A_address, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a7_PORT_B_address_reg = DFFE(R1_ram_block2a7_PORT_B_address, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_write_enable = GND;
R1_ram_block2a7_PORT_A_write_enable_reg = DFFE(R1_ram_block2a7_PORT_A_write_enable, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_write_enable = GND;
R1_ram_block2a7_PORT_B_write_enable_reg = DFFE(R1_ram_block2a7_PORT_B_write_enable, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_clock_0 = M1__clk0;
R1_ram_block2a7_clock_1 = GND;
R1_ram_block2a7_clock_enable_0 = S3_w_anode2929w[3];
R1_ram_block2a7_clock_enable_1 = GND;
R1_ram_block2a7_PORT_A_data_out = MEMORY(R1_ram_block2a7_PORT_A_data_in_reg, R1_ram_block2a7_PORT_B_data_in_reg, R1_ram_block2a7_PORT_A_address_reg, R1_ram_block2a7_PORT_B_address_reg, R1_ram_block2a7_PORT_A_write_enable_reg, R1_ram_block2a7_PORT_B_write_enable_reg, , , R1_ram_block2a7_clock_0, R1_ram_block2a7_clock_1, R1_ram_block2a7_clock_enable_0, R1_ram_block2a7_clock_enable_1, , );
R1_ram_block2a7_PORT_A_data_out_reg = DFFE(R1_ram_block2a7_PORT_A_data_out, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1M392Q = R1_ram_block2a7_PORT_A_data_out_reg[1];

--R1M393Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT2
R1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a7_PORT_A_data_in_reg = DFFE(R1_ram_block2a7_PORT_A_data_in, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_data_in = ~GND;
R1_ram_block2a7_PORT_B_data_in_reg = DFFE(R1_ram_block2a7_PORT_B_data_in, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a7_PORT_A_address_reg = DFFE(R1_ram_block2a7_PORT_A_address, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a7_PORT_B_address_reg = DFFE(R1_ram_block2a7_PORT_B_address, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_write_enable = GND;
R1_ram_block2a7_PORT_A_write_enable_reg = DFFE(R1_ram_block2a7_PORT_A_write_enable, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_write_enable = GND;
R1_ram_block2a7_PORT_B_write_enable_reg = DFFE(R1_ram_block2a7_PORT_B_write_enable, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_clock_0 = M1__clk0;
R1_ram_block2a7_clock_1 = GND;
R1_ram_block2a7_clock_enable_0 = S3_w_anode2929w[3];
R1_ram_block2a7_clock_enable_1 = GND;
R1_ram_block2a7_PORT_A_data_out = MEMORY(R1_ram_block2a7_PORT_A_data_in_reg, R1_ram_block2a7_PORT_B_data_in_reg, R1_ram_block2a7_PORT_A_address_reg, R1_ram_block2a7_PORT_B_address_reg, R1_ram_block2a7_PORT_A_write_enable_reg, R1_ram_block2a7_PORT_B_write_enable_reg, , , R1_ram_block2a7_clock_0, R1_ram_block2a7_clock_1, R1_ram_block2a7_clock_enable_0, R1_ram_block2a7_clock_enable_1, , );
R1_ram_block2a7_PORT_A_data_out_reg = DFFE(R1_ram_block2a7_PORT_A_data_out, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1M393Q = R1_ram_block2a7_PORT_A_data_out_reg[2];

--R1M394Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT3
R1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a7_PORT_A_data_in_reg = DFFE(R1_ram_block2a7_PORT_A_data_in, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_data_in = ~GND;
R1_ram_block2a7_PORT_B_data_in_reg = DFFE(R1_ram_block2a7_PORT_B_data_in, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a7_PORT_A_address_reg = DFFE(R1_ram_block2a7_PORT_A_address, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a7_PORT_B_address_reg = DFFE(R1_ram_block2a7_PORT_B_address, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_write_enable = GND;
R1_ram_block2a7_PORT_A_write_enable_reg = DFFE(R1_ram_block2a7_PORT_A_write_enable, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_write_enable = GND;
R1_ram_block2a7_PORT_B_write_enable_reg = DFFE(R1_ram_block2a7_PORT_B_write_enable, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_clock_0 = M1__clk0;
R1_ram_block2a7_clock_1 = GND;
R1_ram_block2a7_clock_enable_0 = S3_w_anode2929w[3];
R1_ram_block2a7_clock_enable_1 = GND;
R1_ram_block2a7_PORT_A_data_out = MEMORY(R1_ram_block2a7_PORT_A_data_in_reg, R1_ram_block2a7_PORT_B_data_in_reg, R1_ram_block2a7_PORT_A_address_reg, R1_ram_block2a7_PORT_B_address_reg, R1_ram_block2a7_PORT_A_write_enable_reg, R1_ram_block2a7_PORT_B_write_enable_reg, , , R1_ram_block2a7_clock_0, R1_ram_block2a7_clock_1, R1_ram_block2a7_clock_enable_0, R1_ram_block2a7_clock_enable_1, , );
R1_ram_block2a7_PORT_A_data_out_reg = DFFE(R1_ram_block2a7_PORT_A_data_out, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1M394Q = R1_ram_block2a7_PORT_A_data_out_reg[3];

--R1M395Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT4
R1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a7_PORT_A_data_in_reg = DFFE(R1_ram_block2a7_PORT_A_data_in, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_data_in = ~GND;
R1_ram_block2a7_PORT_B_data_in_reg = DFFE(R1_ram_block2a7_PORT_B_data_in, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a7_PORT_A_address_reg = DFFE(R1_ram_block2a7_PORT_A_address, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a7_PORT_B_address_reg = DFFE(R1_ram_block2a7_PORT_B_address, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_write_enable = GND;
R1_ram_block2a7_PORT_A_write_enable_reg = DFFE(R1_ram_block2a7_PORT_A_write_enable, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_write_enable = GND;
R1_ram_block2a7_PORT_B_write_enable_reg = DFFE(R1_ram_block2a7_PORT_B_write_enable, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_clock_0 = M1__clk0;
R1_ram_block2a7_clock_1 = GND;
R1_ram_block2a7_clock_enable_0 = S3_w_anode2929w[3];
R1_ram_block2a7_clock_enable_1 = GND;
R1_ram_block2a7_PORT_A_data_out = MEMORY(R1_ram_block2a7_PORT_A_data_in_reg, R1_ram_block2a7_PORT_B_data_in_reg, R1_ram_block2a7_PORT_A_address_reg, R1_ram_block2a7_PORT_B_address_reg, R1_ram_block2a7_PORT_A_write_enable_reg, R1_ram_block2a7_PORT_B_write_enable_reg, , , R1_ram_block2a7_clock_0, R1_ram_block2a7_clock_1, R1_ram_block2a7_clock_enable_0, R1_ram_block2a7_clock_enable_1, , );
R1_ram_block2a7_PORT_A_data_out_reg = DFFE(R1_ram_block2a7_PORT_A_data_out, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1M395Q = R1_ram_block2a7_PORT_A_data_out_reg[4];

--R1M396Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT5
R1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a7_PORT_A_data_in_reg = DFFE(R1_ram_block2a7_PORT_A_data_in, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_data_in = ~GND;
R1_ram_block2a7_PORT_B_data_in_reg = DFFE(R1_ram_block2a7_PORT_B_data_in, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a7_PORT_A_address_reg = DFFE(R1_ram_block2a7_PORT_A_address, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a7_PORT_B_address_reg = DFFE(R1_ram_block2a7_PORT_B_address, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_write_enable = GND;
R1_ram_block2a7_PORT_A_write_enable_reg = DFFE(R1_ram_block2a7_PORT_A_write_enable, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_write_enable = GND;
R1_ram_block2a7_PORT_B_write_enable_reg = DFFE(R1_ram_block2a7_PORT_B_write_enable, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_clock_0 = M1__clk0;
R1_ram_block2a7_clock_1 = GND;
R1_ram_block2a7_clock_enable_0 = S3_w_anode2929w[3];
R1_ram_block2a7_clock_enable_1 = GND;
R1_ram_block2a7_PORT_A_data_out = MEMORY(R1_ram_block2a7_PORT_A_data_in_reg, R1_ram_block2a7_PORT_B_data_in_reg, R1_ram_block2a7_PORT_A_address_reg, R1_ram_block2a7_PORT_B_address_reg, R1_ram_block2a7_PORT_A_write_enable_reg, R1_ram_block2a7_PORT_B_write_enable_reg, , , R1_ram_block2a7_clock_0, R1_ram_block2a7_clock_1, R1_ram_block2a7_clock_enable_0, R1_ram_block2a7_clock_enable_1, , );
R1_ram_block2a7_PORT_A_data_out_reg = DFFE(R1_ram_block2a7_PORT_A_data_out, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1M396Q = R1_ram_block2a7_PORT_A_data_out_reg[5];

--R1M397Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT6
R1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a7_PORT_A_data_in_reg = DFFE(R1_ram_block2a7_PORT_A_data_in, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_data_in = ~GND;
R1_ram_block2a7_PORT_B_data_in_reg = DFFE(R1_ram_block2a7_PORT_B_data_in, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a7_PORT_A_address_reg = DFFE(R1_ram_block2a7_PORT_A_address, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a7_PORT_B_address_reg = DFFE(R1_ram_block2a7_PORT_B_address, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_write_enable = GND;
R1_ram_block2a7_PORT_A_write_enable_reg = DFFE(R1_ram_block2a7_PORT_A_write_enable, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_write_enable = GND;
R1_ram_block2a7_PORT_B_write_enable_reg = DFFE(R1_ram_block2a7_PORT_B_write_enable, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_clock_0 = M1__clk0;
R1_ram_block2a7_clock_1 = GND;
R1_ram_block2a7_clock_enable_0 = S3_w_anode2929w[3];
R1_ram_block2a7_clock_enable_1 = GND;
R1_ram_block2a7_PORT_A_data_out = MEMORY(R1_ram_block2a7_PORT_A_data_in_reg, R1_ram_block2a7_PORT_B_data_in_reg, R1_ram_block2a7_PORT_A_address_reg, R1_ram_block2a7_PORT_B_address_reg, R1_ram_block2a7_PORT_A_write_enable_reg, R1_ram_block2a7_PORT_B_write_enable_reg, , , R1_ram_block2a7_clock_0, R1_ram_block2a7_clock_1, R1_ram_block2a7_clock_enable_0, R1_ram_block2a7_clock_enable_1, , );
R1_ram_block2a7_PORT_A_data_out_reg = DFFE(R1_ram_block2a7_PORT_A_data_out, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1M397Q = R1_ram_block2a7_PORT_A_data_out_reg[6];

--R1M398Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT7
R1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a7_PORT_A_data_in_reg = DFFE(R1_ram_block2a7_PORT_A_data_in, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_data_in = ~GND;
R1_ram_block2a7_PORT_B_data_in_reg = DFFE(R1_ram_block2a7_PORT_B_data_in, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a7_PORT_A_address_reg = DFFE(R1_ram_block2a7_PORT_A_address, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a7_PORT_B_address_reg = DFFE(R1_ram_block2a7_PORT_B_address, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_write_enable = GND;
R1_ram_block2a7_PORT_A_write_enable_reg = DFFE(R1_ram_block2a7_PORT_A_write_enable, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_write_enable = GND;
R1_ram_block2a7_PORT_B_write_enable_reg = DFFE(R1_ram_block2a7_PORT_B_write_enable, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_clock_0 = M1__clk0;
R1_ram_block2a7_clock_1 = GND;
R1_ram_block2a7_clock_enable_0 = S3_w_anode2929w[3];
R1_ram_block2a7_clock_enable_1 = GND;
R1_ram_block2a7_PORT_A_data_out = MEMORY(R1_ram_block2a7_PORT_A_data_in_reg, R1_ram_block2a7_PORT_B_data_in_reg, R1_ram_block2a7_PORT_A_address_reg, R1_ram_block2a7_PORT_B_address_reg, R1_ram_block2a7_PORT_A_write_enable_reg, R1_ram_block2a7_PORT_B_write_enable_reg, , , R1_ram_block2a7_clock_0, R1_ram_block2a7_clock_1, R1_ram_block2a7_clock_enable_0, R1_ram_block2a7_clock_enable_1, , );
R1_ram_block2a7_PORT_A_data_out_reg = DFFE(R1_ram_block2a7_PORT_A_data_out, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1M398Q = R1_ram_block2a7_PORT_A_data_out_reg[7];


--T1L215 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6388w~45
T1L215 = R1_address_reg_a[7] & (T1L214 & (R1M396Q) # !T1L214 & R1M346Q) # !R1_address_reg_a[7] & (T1L214);


--T1L234 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~575
T1L234 = !R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L227 # !R1_address_reg_a[11] & (T1L215));


--T1L235 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~576
T1L235 = T1L147 # T1L232 & (T1L233 # T1L234);


--T1L236 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~577
T1L236 = !R1_address_reg_a[9] & !R1_address_reg_a[10] & !R1_address_reg_a[8];


--R1_ram_block2a33 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a33_PORT_A_data_in_reg = DFFE(R1_ram_block2a33_PORT_A_data_in, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_data_in = ~GND;
R1_ram_block2a33_PORT_B_data_in_reg = DFFE(R1_ram_block2a33_PORT_B_data_in, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a33_PORT_A_address_reg = DFFE(R1_ram_block2a33_PORT_A_address, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a33_PORT_B_address_reg = DFFE(R1_ram_block2a33_PORT_B_address, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_write_enable = GND;
R1_ram_block2a33_PORT_A_write_enable_reg = DFFE(R1_ram_block2a33_PORT_A_write_enable, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_write_enable = GND;
R1_ram_block2a33_PORT_B_write_enable_reg = DFFE(R1_ram_block2a33_PORT_B_write_enable, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_clock_0 = M1__clk0;
R1_ram_block2a33_clock_1 = GND;
R1_ram_block2a33_clock_enable_0 = S3_w_anode3242w[3];
R1_ram_block2a33_clock_enable_1 = GND;
R1_ram_block2a33_PORT_A_data_out = MEMORY(R1_ram_block2a33_PORT_A_data_in_reg, R1_ram_block2a33_PORT_B_data_in_reg, R1_ram_block2a33_PORT_A_address_reg, R1_ram_block2a33_PORT_B_address_reg, R1_ram_block2a33_PORT_A_write_enable_reg, R1_ram_block2a33_PORT_B_write_enable_reg, , , R1_ram_block2a33_clock_0, R1_ram_block2a33_clock_1, R1_ram_block2a33_clock_enable_0, R1_ram_block2a33_clock_enable_1, , );
R1_ram_block2a33_PORT_A_data_out_reg = DFFE(R1_ram_block2a33_PORT_A_data_out, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33 = R1_ram_block2a33_PORT_A_data_out_reg[0];

--R1M1692Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT1
R1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a33_PORT_A_data_in_reg = DFFE(R1_ram_block2a33_PORT_A_data_in, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_data_in = ~GND;
R1_ram_block2a33_PORT_B_data_in_reg = DFFE(R1_ram_block2a33_PORT_B_data_in, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a33_PORT_A_address_reg = DFFE(R1_ram_block2a33_PORT_A_address, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a33_PORT_B_address_reg = DFFE(R1_ram_block2a33_PORT_B_address, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_write_enable = GND;
R1_ram_block2a33_PORT_A_write_enable_reg = DFFE(R1_ram_block2a33_PORT_A_write_enable, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_write_enable = GND;
R1_ram_block2a33_PORT_B_write_enable_reg = DFFE(R1_ram_block2a33_PORT_B_write_enable, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_clock_0 = M1__clk0;
R1_ram_block2a33_clock_1 = GND;
R1_ram_block2a33_clock_enable_0 = S3_w_anode3242w[3];
R1_ram_block2a33_clock_enable_1 = GND;
R1_ram_block2a33_PORT_A_data_out = MEMORY(R1_ram_block2a33_PORT_A_data_in_reg, R1_ram_block2a33_PORT_B_data_in_reg, R1_ram_block2a33_PORT_A_address_reg, R1_ram_block2a33_PORT_B_address_reg, R1_ram_block2a33_PORT_A_write_enable_reg, R1_ram_block2a33_PORT_B_write_enable_reg, , , R1_ram_block2a33_clock_0, R1_ram_block2a33_clock_1, R1_ram_block2a33_clock_enable_0, R1_ram_block2a33_clock_enable_1, , );
R1_ram_block2a33_PORT_A_data_out_reg = DFFE(R1_ram_block2a33_PORT_A_data_out, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1M1692Q = R1_ram_block2a33_PORT_A_data_out_reg[1];

--R1M1693Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT2
R1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a33_PORT_A_data_in_reg = DFFE(R1_ram_block2a33_PORT_A_data_in, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_data_in = ~GND;
R1_ram_block2a33_PORT_B_data_in_reg = DFFE(R1_ram_block2a33_PORT_B_data_in, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a33_PORT_A_address_reg = DFFE(R1_ram_block2a33_PORT_A_address, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a33_PORT_B_address_reg = DFFE(R1_ram_block2a33_PORT_B_address, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_write_enable = GND;
R1_ram_block2a33_PORT_A_write_enable_reg = DFFE(R1_ram_block2a33_PORT_A_write_enable, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_write_enable = GND;
R1_ram_block2a33_PORT_B_write_enable_reg = DFFE(R1_ram_block2a33_PORT_B_write_enable, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_clock_0 = M1__clk0;
R1_ram_block2a33_clock_1 = GND;
R1_ram_block2a33_clock_enable_0 = S3_w_anode3242w[3];
R1_ram_block2a33_clock_enable_1 = GND;
R1_ram_block2a33_PORT_A_data_out = MEMORY(R1_ram_block2a33_PORT_A_data_in_reg, R1_ram_block2a33_PORT_B_data_in_reg, R1_ram_block2a33_PORT_A_address_reg, R1_ram_block2a33_PORT_B_address_reg, R1_ram_block2a33_PORT_A_write_enable_reg, R1_ram_block2a33_PORT_B_write_enable_reg, , , R1_ram_block2a33_clock_0, R1_ram_block2a33_clock_1, R1_ram_block2a33_clock_enable_0, R1_ram_block2a33_clock_enable_1, , );
R1_ram_block2a33_PORT_A_data_out_reg = DFFE(R1_ram_block2a33_PORT_A_data_out, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1M1693Q = R1_ram_block2a33_PORT_A_data_out_reg[2];

--R1M1694Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT3
R1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a33_PORT_A_data_in_reg = DFFE(R1_ram_block2a33_PORT_A_data_in, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_data_in = ~GND;
R1_ram_block2a33_PORT_B_data_in_reg = DFFE(R1_ram_block2a33_PORT_B_data_in, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a33_PORT_A_address_reg = DFFE(R1_ram_block2a33_PORT_A_address, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a33_PORT_B_address_reg = DFFE(R1_ram_block2a33_PORT_B_address, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_write_enable = GND;
R1_ram_block2a33_PORT_A_write_enable_reg = DFFE(R1_ram_block2a33_PORT_A_write_enable, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_write_enable = GND;
R1_ram_block2a33_PORT_B_write_enable_reg = DFFE(R1_ram_block2a33_PORT_B_write_enable, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_clock_0 = M1__clk0;
R1_ram_block2a33_clock_1 = GND;
R1_ram_block2a33_clock_enable_0 = S3_w_anode3242w[3];
R1_ram_block2a33_clock_enable_1 = GND;
R1_ram_block2a33_PORT_A_data_out = MEMORY(R1_ram_block2a33_PORT_A_data_in_reg, R1_ram_block2a33_PORT_B_data_in_reg, R1_ram_block2a33_PORT_A_address_reg, R1_ram_block2a33_PORT_B_address_reg, R1_ram_block2a33_PORT_A_write_enable_reg, R1_ram_block2a33_PORT_B_write_enable_reg, , , R1_ram_block2a33_clock_0, R1_ram_block2a33_clock_1, R1_ram_block2a33_clock_enable_0, R1_ram_block2a33_clock_enable_1, , );
R1_ram_block2a33_PORT_A_data_out_reg = DFFE(R1_ram_block2a33_PORT_A_data_out, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1M1694Q = R1_ram_block2a33_PORT_A_data_out_reg[3];

--R1M1695Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT4
R1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a33_PORT_A_data_in_reg = DFFE(R1_ram_block2a33_PORT_A_data_in, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_data_in = ~GND;
R1_ram_block2a33_PORT_B_data_in_reg = DFFE(R1_ram_block2a33_PORT_B_data_in, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a33_PORT_A_address_reg = DFFE(R1_ram_block2a33_PORT_A_address, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a33_PORT_B_address_reg = DFFE(R1_ram_block2a33_PORT_B_address, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_write_enable = GND;
R1_ram_block2a33_PORT_A_write_enable_reg = DFFE(R1_ram_block2a33_PORT_A_write_enable, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_write_enable = GND;
R1_ram_block2a33_PORT_B_write_enable_reg = DFFE(R1_ram_block2a33_PORT_B_write_enable, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_clock_0 = M1__clk0;
R1_ram_block2a33_clock_1 = GND;
R1_ram_block2a33_clock_enable_0 = S3_w_anode3242w[3];
R1_ram_block2a33_clock_enable_1 = GND;
R1_ram_block2a33_PORT_A_data_out = MEMORY(R1_ram_block2a33_PORT_A_data_in_reg, R1_ram_block2a33_PORT_B_data_in_reg, R1_ram_block2a33_PORT_A_address_reg, R1_ram_block2a33_PORT_B_address_reg, R1_ram_block2a33_PORT_A_write_enable_reg, R1_ram_block2a33_PORT_B_write_enable_reg, , , R1_ram_block2a33_clock_0, R1_ram_block2a33_clock_1, R1_ram_block2a33_clock_enable_0, R1_ram_block2a33_clock_enable_1, , );
R1_ram_block2a33_PORT_A_data_out_reg = DFFE(R1_ram_block2a33_PORT_A_data_out, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1M1695Q = R1_ram_block2a33_PORT_A_data_out_reg[4];

--R1M1696Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT5
R1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a33_PORT_A_data_in_reg = DFFE(R1_ram_block2a33_PORT_A_data_in, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_data_in = ~GND;
R1_ram_block2a33_PORT_B_data_in_reg = DFFE(R1_ram_block2a33_PORT_B_data_in, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a33_PORT_A_address_reg = DFFE(R1_ram_block2a33_PORT_A_address, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a33_PORT_B_address_reg = DFFE(R1_ram_block2a33_PORT_B_address, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_write_enable = GND;
R1_ram_block2a33_PORT_A_write_enable_reg = DFFE(R1_ram_block2a33_PORT_A_write_enable, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_write_enable = GND;
R1_ram_block2a33_PORT_B_write_enable_reg = DFFE(R1_ram_block2a33_PORT_B_write_enable, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_clock_0 = M1__clk0;
R1_ram_block2a33_clock_1 = GND;
R1_ram_block2a33_clock_enable_0 = S3_w_anode3242w[3];
R1_ram_block2a33_clock_enable_1 = GND;
R1_ram_block2a33_PORT_A_data_out = MEMORY(R1_ram_block2a33_PORT_A_data_in_reg, R1_ram_block2a33_PORT_B_data_in_reg, R1_ram_block2a33_PORT_A_address_reg, R1_ram_block2a33_PORT_B_address_reg, R1_ram_block2a33_PORT_A_write_enable_reg, R1_ram_block2a33_PORT_B_write_enable_reg, , , R1_ram_block2a33_clock_0, R1_ram_block2a33_clock_1, R1_ram_block2a33_clock_enable_0, R1_ram_block2a33_clock_enable_1, , );
R1_ram_block2a33_PORT_A_data_out_reg = DFFE(R1_ram_block2a33_PORT_A_data_out, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1M1696Q = R1_ram_block2a33_PORT_A_data_out_reg[5];

--R1M1697Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT6
R1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a33_PORT_A_data_in_reg = DFFE(R1_ram_block2a33_PORT_A_data_in, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_data_in = ~GND;
R1_ram_block2a33_PORT_B_data_in_reg = DFFE(R1_ram_block2a33_PORT_B_data_in, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a33_PORT_A_address_reg = DFFE(R1_ram_block2a33_PORT_A_address, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a33_PORT_B_address_reg = DFFE(R1_ram_block2a33_PORT_B_address, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_write_enable = GND;
R1_ram_block2a33_PORT_A_write_enable_reg = DFFE(R1_ram_block2a33_PORT_A_write_enable, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_write_enable = GND;
R1_ram_block2a33_PORT_B_write_enable_reg = DFFE(R1_ram_block2a33_PORT_B_write_enable, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_clock_0 = M1__clk0;
R1_ram_block2a33_clock_1 = GND;
R1_ram_block2a33_clock_enable_0 = S3_w_anode3242w[3];
R1_ram_block2a33_clock_enable_1 = GND;
R1_ram_block2a33_PORT_A_data_out = MEMORY(R1_ram_block2a33_PORT_A_data_in_reg, R1_ram_block2a33_PORT_B_data_in_reg, R1_ram_block2a33_PORT_A_address_reg, R1_ram_block2a33_PORT_B_address_reg, R1_ram_block2a33_PORT_A_write_enable_reg, R1_ram_block2a33_PORT_B_write_enable_reg, , , R1_ram_block2a33_clock_0, R1_ram_block2a33_clock_1, R1_ram_block2a33_clock_enable_0, R1_ram_block2a33_clock_enable_1, , );
R1_ram_block2a33_PORT_A_data_out_reg = DFFE(R1_ram_block2a33_PORT_A_data_out, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1M1697Q = R1_ram_block2a33_PORT_A_data_out_reg[6];

--R1M1698Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT7
R1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a33_PORT_A_data_in_reg = DFFE(R1_ram_block2a33_PORT_A_data_in, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_data_in = ~GND;
R1_ram_block2a33_PORT_B_data_in_reg = DFFE(R1_ram_block2a33_PORT_B_data_in, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a33_PORT_A_address_reg = DFFE(R1_ram_block2a33_PORT_A_address, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a33_PORT_B_address_reg = DFFE(R1_ram_block2a33_PORT_B_address, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_write_enable = GND;
R1_ram_block2a33_PORT_A_write_enable_reg = DFFE(R1_ram_block2a33_PORT_A_write_enable, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_write_enable = GND;
R1_ram_block2a33_PORT_B_write_enable_reg = DFFE(R1_ram_block2a33_PORT_B_write_enable, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_clock_0 = M1__clk0;
R1_ram_block2a33_clock_1 = GND;
R1_ram_block2a33_clock_enable_0 = S3_w_anode3242w[3];
R1_ram_block2a33_clock_enable_1 = GND;
R1_ram_block2a33_PORT_A_data_out = MEMORY(R1_ram_block2a33_PORT_A_data_in_reg, R1_ram_block2a33_PORT_B_data_in_reg, R1_ram_block2a33_PORT_A_address_reg, R1_ram_block2a33_PORT_B_address_reg, R1_ram_block2a33_PORT_A_write_enable_reg, R1_ram_block2a33_PORT_B_write_enable_reg, , , R1_ram_block2a33_clock_0, R1_ram_block2a33_clock_1, R1_ram_block2a33_clock_enable_0, R1_ram_block2a33_clock_enable_1, , );
R1_ram_block2a33_PORT_A_data_out_reg = DFFE(R1_ram_block2a33_PORT_A_data_out, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1M1698Q = R1_ram_block2a33_PORT_A_data_out_reg[7];


--R1_ram_block2a34 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a34_PORT_A_data_in_reg = DFFE(R1_ram_block2a34_PORT_A_data_in, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_data_in = ~GND;
R1_ram_block2a34_PORT_B_data_in_reg = DFFE(R1_ram_block2a34_PORT_B_data_in, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a34_PORT_A_address_reg = DFFE(R1_ram_block2a34_PORT_A_address, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a34_PORT_B_address_reg = DFFE(R1_ram_block2a34_PORT_B_address, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_write_enable = GND;
R1_ram_block2a34_PORT_A_write_enable_reg = DFFE(R1_ram_block2a34_PORT_A_write_enable, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_write_enable = GND;
R1_ram_block2a34_PORT_B_write_enable_reg = DFFE(R1_ram_block2a34_PORT_B_write_enable, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_clock_0 = M1__clk0;
R1_ram_block2a34_clock_1 = GND;
R1_ram_block2a34_clock_enable_0 = S3_w_anode3252w[3];
R1_ram_block2a34_clock_enable_1 = GND;
R1_ram_block2a34_PORT_A_data_out = MEMORY(R1_ram_block2a34_PORT_A_data_in_reg, R1_ram_block2a34_PORT_B_data_in_reg, R1_ram_block2a34_PORT_A_address_reg, R1_ram_block2a34_PORT_B_address_reg, R1_ram_block2a34_PORT_A_write_enable_reg, R1_ram_block2a34_PORT_B_write_enable_reg, , , R1_ram_block2a34_clock_0, R1_ram_block2a34_clock_1, R1_ram_block2a34_clock_enable_0, R1_ram_block2a34_clock_enable_1, , );
R1_ram_block2a34_PORT_A_data_out_reg = DFFE(R1_ram_block2a34_PORT_A_data_out, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34 = R1_ram_block2a34_PORT_A_data_out_reg[0];

--R1M1742Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT1
R1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a34_PORT_A_data_in_reg = DFFE(R1_ram_block2a34_PORT_A_data_in, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_data_in = ~GND;
R1_ram_block2a34_PORT_B_data_in_reg = DFFE(R1_ram_block2a34_PORT_B_data_in, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a34_PORT_A_address_reg = DFFE(R1_ram_block2a34_PORT_A_address, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a34_PORT_B_address_reg = DFFE(R1_ram_block2a34_PORT_B_address, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_write_enable = GND;
R1_ram_block2a34_PORT_A_write_enable_reg = DFFE(R1_ram_block2a34_PORT_A_write_enable, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_write_enable = GND;
R1_ram_block2a34_PORT_B_write_enable_reg = DFFE(R1_ram_block2a34_PORT_B_write_enable, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_clock_0 = M1__clk0;
R1_ram_block2a34_clock_1 = GND;
R1_ram_block2a34_clock_enable_0 = S3_w_anode3252w[3];
R1_ram_block2a34_clock_enable_1 = GND;
R1_ram_block2a34_PORT_A_data_out = MEMORY(R1_ram_block2a34_PORT_A_data_in_reg, R1_ram_block2a34_PORT_B_data_in_reg, R1_ram_block2a34_PORT_A_address_reg, R1_ram_block2a34_PORT_B_address_reg, R1_ram_block2a34_PORT_A_write_enable_reg, R1_ram_block2a34_PORT_B_write_enable_reg, , , R1_ram_block2a34_clock_0, R1_ram_block2a34_clock_1, R1_ram_block2a34_clock_enable_0, R1_ram_block2a34_clock_enable_1, , );
R1_ram_block2a34_PORT_A_data_out_reg = DFFE(R1_ram_block2a34_PORT_A_data_out, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1M1742Q = R1_ram_block2a34_PORT_A_data_out_reg[1];

--R1M1743Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT2
R1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a34_PORT_A_data_in_reg = DFFE(R1_ram_block2a34_PORT_A_data_in, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_data_in = ~GND;
R1_ram_block2a34_PORT_B_data_in_reg = DFFE(R1_ram_block2a34_PORT_B_data_in, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a34_PORT_A_address_reg = DFFE(R1_ram_block2a34_PORT_A_address, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a34_PORT_B_address_reg = DFFE(R1_ram_block2a34_PORT_B_address, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_write_enable = GND;
R1_ram_block2a34_PORT_A_write_enable_reg = DFFE(R1_ram_block2a34_PORT_A_write_enable, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_write_enable = GND;
R1_ram_block2a34_PORT_B_write_enable_reg = DFFE(R1_ram_block2a34_PORT_B_write_enable, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_clock_0 = M1__clk0;
R1_ram_block2a34_clock_1 = GND;
R1_ram_block2a34_clock_enable_0 = S3_w_anode3252w[3];
R1_ram_block2a34_clock_enable_1 = GND;
R1_ram_block2a34_PORT_A_data_out = MEMORY(R1_ram_block2a34_PORT_A_data_in_reg, R1_ram_block2a34_PORT_B_data_in_reg, R1_ram_block2a34_PORT_A_address_reg, R1_ram_block2a34_PORT_B_address_reg, R1_ram_block2a34_PORT_A_write_enable_reg, R1_ram_block2a34_PORT_B_write_enable_reg, , , R1_ram_block2a34_clock_0, R1_ram_block2a34_clock_1, R1_ram_block2a34_clock_enable_0, R1_ram_block2a34_clock_enable_1, , );
R1_ram_block2a34_PORT_A_data_out_reg = DFFE(R1_ram_block2a34_PORT_A_data_out, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1M1743Q = R1_ram_block2a34_PORT_A_data_out_reg[2];

--R1M1744Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT3
R1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a34_PORT_A_data_in_reg = DFFE(R1_ram_block2a34_PORT_A_data_in, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_data_in = ~GND;
R1_ram_block2a34_PORT_B_data_in_reg = DFFE(R1_ram_block2a34_PORT_B_data_in, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a34_PORT_A_address_reg = DFFE(R1_ram_block2a34_PORT_A_address, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a34_PORT_B_address_reg = DFFE(R1_ram_block2a34_PORT_B_address, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_write_enable = GND;
R1_ram_block2a34_PORT_A_write_enable_reg = DFFE(R1_ram_block2a34_PORT_A_write_enable, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_write_enable = GND;
R1_ram_block2a34_PORT_B_write_enable_reg = DFFE(R1_ram_block2a34_PORT_B_write_enable, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_clock_0 = M1__clk0;
R1_ram_block2a34_clock_1 = GND;
R1_ram_block2a34_clock_enable_0 = S3_w_anode3252w[3];
R1_ram_block2a34_clock_enable_1 = GND;
R1_ram_block2a34_PORT_A_data_out = MEMORY(R1_ram_block2a34_PORT_A_data_in_reg, R1_ram_block2a34_PORT_B_data_in_reg, R1_ram_block2a34_PORT_A_address_reg, R1_ram_block2a34_PORT_B_address_reg, R1_ram_block2a34_PORT_A_write_enable_reg, R1_ram_block2a34_PORT_B_write_enable_reg, , , R1_ram_block2a34_clock_0, R1_ram_block2a34_clock_1, R1_ram_block2a34_clock_enable_0, R1_ram_block2a34_clock_enable_1, , );
R1_ram_block2a34_PORT_A_data_out_reg = DFFE(R1_ram_block2a34_PORT_A_data_out, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1M1744Q = R1_ram_block2a34_PORT_A_data_out_reg[3];

--R1M1745Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT4
R1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a34_PORT_A_data_in_reg = DFFE(R1_ram_block2a34_PORT_A_data_in, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_data_in = ~GND;
R1_ram_block2a34_PORT_B_data_in_reg = DFFE(R1_ram_block2a34_PORT_B_data_in, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a34_PORT_A_address_reg = DFFE(R1_ram_block2a34_PORT_A_address, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a34_PORT_B_address_reg = DFFE(R1_ram_block2a34_PORT_B_address, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_write_enable = GND;
R1_ram_block2a34_PORT_A_write_enable_reg = DFFE(R1_ram_block2a34_PORT_A_write_enable, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_write_enable = GND;
R1_ram_block2a34_PORT_B_write_enable_reg = DFFE(R1_ram_block2a34_PORT_B_write_enable, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_clock_0 = M1__clk0;
R1_ram_block2a34_clock_1 = GND;
R1_ram_block2a34_clock_enable_0 = S3_w_anode3252w[3];
R1_ram_block2a34_clock_enable_1 = GND;
R1_ram_block2a34_PORT_A_data_out = MEMORY(R1_ram_block2a34_PORT_A_data_in_reg, R1_ram_block2a34_PORT_B_data_in_reg, R1_ram_block2a34_PORT_A_address_reg, R1_ram_block2a34_PORT_B_address_reg, R1_ram_block2a34_PORT_A_write_enable_reg, R1_ram_block2a34_PORT_B_write_enable_reg, , , R1_ram_block2a34_clock_0, R1_ram_block2a34_clock_1, R1_ram_block2a34_clock_enable_0, R1_ram_block2a34_clock_enable_1, , );
R1_ram_block2a34_PORT_A_data_out_reg = DFFE(R1_ram_block2a34_PORT_A_data_out, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1M1745Q = R1_ram_block2a34_PORT_A_data_out_reg[4];

--R1M1746Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT5
R1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a34_PORT_A_data_in_reg = DFFE(R1_ram_block2a34_PORT_A_data_in, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_data_in = ~GND;
R1_ram_block2a34_PORT_B_data_in_reg = DFFE(R1_ram_block2a34_PORT_B_data_in, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a34_PORT_A_address_reg = DFFE(R1_ram_block2a34_PORT_A_address, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a34_PORT_B_address_reg = DFFE(R1_ram_block2a34_PORT_B_address, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_write_enable = GND;
R1_ram_block2a34_PORT_A_write_enable_reg = DFFE(R1_ram_block2a34_PORT_A_write_enable, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_write_enable = GND;
R1_ram_block2a34_PORT_B_write_enable_reg = DFFE(R1_ram_block2a34_PORT_B_write_enable, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_clock_0 = M1__clk0;
R1_ram_block2a34_clock_1 = GND;
R1_ram_block2a34_clock_enable_0 = S3_w_anode3252w[3];
R1_ram_block2a34_clock_enable_1 = GND;
R1_ram_block2a34_PORT_A_data_out = MEMORY(R1_ram_block2a34_PORT_A_data_in_reg, R1_ram_block2a34_PORT_B_data_in_reg, R1_ram_block2a34_PORT_A_address_reg, R1_ram_block2a34_PORT_B_address_reg, R1_ram_block2a34_PORT_A_write_enable_reg, R1_ram_block2a34_PORT_B_write_enable_reg, , , R1_ram_block2a34_clock_0, R1_ram_block2a34_clock_1, R1_ram_block2a34_clock_enable_0, R1_ram_block2a34_clock_enable_1, , );
R1_ram_block2a34_PORT_A_data_out_reg = DFFE(R1_ram_block2a34_PORT_A_data_out, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1M1746Q = R1_ram_block2a34_PORT_A_data_out_reg[5];

--R1M1747Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT6
R1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a34_PORT_A_data_in_reg = DFFE(R1_ram_block2a34_PORT_A_data_in, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_data_in = ~GND;
R1_ram_block2a34_PORT_B_data_in_reg = DFFE(R1_ram_block2a34_PORT_B_data_in, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a34_PORT_A_address_reg = DFFE(R1_ram_block2a34_PORT_A_address, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a34_PORT_B_address_reg = DFFE(R1_ram_block2a34_PORT_B_address, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_write_enable = GND;
R1_ram_block2a34_PORT_A_write_enable_reg = DFFE(R1_ram_block2a34_PORT_A_write_enable, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_write_enable = GND;
R1_ram_block2a34_PORT_B_write_enable_reg = DFFE(R1_ram_block2a34_PORT_B_write_enable, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_clock_0 = M1__clk0;
R1_ram_block2a34_clock_1 = GND;
R1_ram_block2a34_clock_enable_0 = S3_w_anode3252w[3];
R1_ram_block2a34_clock_enable_1 = GND;
R1_ram_block2a34_PORT_A_data_out = MEMORY(R1_ram_block2a34_PORT_A_data_in_reg, R1_ram_block2a34_PORT_B_data_in_reg, R1_ram_block2a34_PORT_A_address_reg, R1_ram_block2a34_PORT_B_address_reg, R1_ram_block2a34_PORT_A_write_enable_reg, R1_ram_block2a34_PORT_B_write_enable_reg, , , R1_ram_block2a34_clock_0, R1_ram_block2a34_clock_1, R1_ram_block2a34_clock_enable_0, R1_ram_block2a34_clock_enable_1, , );
R1_ram_block2a34_PORT_A_data_out_reg = DFFE(R1_ram_block2a34_PORT_A_data_out, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1M1747Q = R1_ram_block2a34_PORT_A_data_out_reg[6];

--R1M1748Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT7
R1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a34_PORT_A_data_in_reg = DFFE(R1_ram_block2a34_PORT_A_data_in, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_data_in = ~GND;
R1_ram_block2a34_PORT_B_data_in_reg = DFFE(R1_ram_block2a34_PORT_B_data_in, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a34_PORT_A_address_reg = DFFE(R1_ram_block2a34_PORT_A_address, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a34_PORT_B_address_reg = DFFE(R1_ram_block2a34_PORT_B_address, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_write_enable = GND;
R1_ram_block2a34_PORT_A_write_enable_reg = DFFE(R1_ram_block2a34_PORT_A_write_enable, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_write_enable = GND;
R1_ram_block2a34_PORT_B_write_enable_reg = DFFE(R1_ram_block2a34_PORT_B_write_enable, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_clock_0 = M1__clk0;
R1_ram_block2a34_clock_1 = GND;
R1_ram_block2a34_clock_enable_0 = S3_w_anode3252w[3];
R1_ram_block2a34_clock_enable_1 = GND;
R1_ram_block2a34_PORT_A_data_out = MEMORY(R1_ram_block2a34_PORT_A_data_in_reg, R1_ram_block2a34_PORT_B_data_in_reg, R1_ram_block2a34_PORT_A_address_reg, R1_ram_block2a34_PORT_B_address_reg, R1_ram_block2a34_PORT_A_write_enable_reg, R1_ram_block2a34_PORT_B_write_enable_reg, , , R1_ram_block2a34_clock_0, R1_ram_block2a34_clock_1, R1_ram_block2a34_clock_enable_0, R1_ram_block2a34_clock_enable_1, , );
R1_ram_block2a34_PORT_A_data_out_reg = DFFE(R1_ram_block2a34_PORT_A_data_out, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1M1748Q = R1_ram_block2a34_PORT_A_data_out_reg[7];


--R1_ram_block2a32 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a32_PORT_A_data_in_reg = DFFE(R1_ram_block2a32_PORT_A_data_in, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_data_in = ~GND;
R1_ram_block2a32_PORT_B_data_in_reg = DFFE(R1_ram_block2a32_PORT_B_data_in, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a32_PORT_A_address_reg = DFFE(R1_ram_block2a32_PORT_A_address, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a32_PORT_B_address_reg = DFFE(R1_ram_block2a32_PORT_B_address, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_write_enable = GND;
R1_ram_block2a32_PORT_A_write_enable_reg = DFFE(R1_ram_block2a32_PORT_A_write_enable, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_write_enable = GND;
R1_ram_block2a32_PORT_B_write_enable_reg = DFFE(R1_ram_block2a32_PORT_B_write_enable, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_clock_0 = M1__clk0;
R1_ram_block2a32_clock_1 = GND;
R1_ram_block2a32_clock_enable_0 = S3_w_anode3231w[3];
R1_ram_block2a32_clock_enable_1 = GND;
R1_ram_block2a32_PORT_A_data_out = MEMORY(R1_ram_block2a32_PORT_A_data_in_reg, R1_ram_block2a32_PORT_B_data_in_reg, R1_ram_block2a32_PORT_A_address_reg, R1_ram_block2a32_PORT_B_address_reg, R1_ram_block2a32_PORT_A_write_enable_reg, R1_ram_block2a32_PORT_B_write_enable_reg, , , R1_ram_block2a32_clock_0, R1_ram_block2a32_clock_1, R1_ram_block2a32_clock_enable_0, R1_ram_block2a32_clock_enable_1, , );
R1_ram_block2a32_PORT_A_data_out_reg = DFFE(R1_ram_block2a32_PORT_A_data_out, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32 = R1_ram_block2a32_PORT_A_data_out_reg[0];

--R1M1642Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT1
R1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a32_PORT_A_data_in_reg = DFFE(R1_ram_block2a32_PORT_A_data_in, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_data_in = ~GND;
R1_ram_block2a32_PORT_B_data_in_reg = DFFE(R1_ram_block2a32_PORT_B_data_in, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a32_PORT_A_address_reg = DFFE(R1_ram_block2a32_PORT_A_address, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a32_PORT_B_address_reg = DFFE(R1_ram_block2a32_PORT_B_address, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_write_enable = GND;
R1_ram_block2a32_PORT_A_write_enable_reg = DFFE(R1_ram_block2a32_PORT_A_write_enable, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_write_enable = GND;
R1_ram_block2a32_PORT_B_write_enable_reg = DFFE(R1_ram_block2a32_PORT_B_write_enable, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_clock_0 = M1__clk0;
R1_ram_block2a32_clock_1 = GND;
R1_ram_block2a32_clock_enable_0 = S3_w_anode3231w[3];
R1_ram_block2a32_clock_enable_1 = GND;
R1_ram_block2a32_PORT_A_data_out = MEMORY(R1_ram_block2a32_PORT_A_data_in_reg, R1_ram_block2a32_PORT_B_data_in_reg, R1_ram_block2a32_PORT_A_address_reg, R1_ram_block2a32_PORT_B_address_reg, R1_ram_block2a32_PORT_A_write_enable_reg, R1_ram_block2a32_PORT_B_write_enable_reg, , , R1_ram_block2a32_clock_0, R1_ram_block2a32_clock_1, R1_ram_block2a32_clock_enable_0, R1_ram_block2a32_clock_enable_1, , );
R1_ram_block2a32_PORT_A_data_out_reg = DFFE(R1_ram_block2a32_PORT_A_data_out, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1M1642Q = R1_ram_block2a32_PORT_A_data_out_reg[1];

--R1M1643Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT2
R1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a32_PORT_A_data_in_reg = DFFE(R1_ram_block2a32_PORT_A_data_in, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_data_in = ~GND;
R1_ram_block2a32_PORT_B_data_in_reg = DFFE(R1_ram_block2a32_PORT_B_data_in, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a32_PORT_A_address_reg = DFFE(R1_ram_block2a32_PORT_A_address, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a32_PORT_B_address_reg = DFFE(R1_ram_block2a32_PORT_B_address, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_write_enable = GND;
R1_ram_block2a32_PORT_A_write_enable_reg = DFFE(R1_ram_block2a32_PORT_A_write_enable, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_write_enable = GND;
R1_ram_block2a32_PORT_B_write_enable_reg = DFFE(R1_ram_block2a32_PORT_B_write_enable, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_clock_0 = M1__clk0;
R1_ram_block2a32_clock_1 = GND;
R1_ram_block2a32_clock_enable_0 = S3_w_anode3231w[3];
R1_ram_block2a32_clock_enable_1 = GND;
R1_ram_block2a32_PORT_A_data_out = MEMORY(R1_ram_block2a32_PORT_A_data_in_reg, R1_ram_block2a32_PORT_B_data_in_reg, R1_ram_block2a32_PORT_A_address_reg, R1_ram_block2a32_PORT_B_address_reg, R1_ram_block2a32_PORT_A_write_enable_reg, R1_ram_block2a32_PORT_B_write_enable_reg, , , R1_ram_block2a32_clock_0, R1_ram_block2a32_clock_1, R1_ram_block2a32_clock_enable_0, R1_ram_block2a32_clock_enable_1, , );
R1_ram_block2a32_PORT_A_data_out_reg = DFFE(R1_ram_block2a32_PORT_A_data_out, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1M1643Q = R1_ram_block2a32_PORT_A_data_out_reg[2];

--R1M1644Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT3
R1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a32_PORT_A_data_in_reg = DFFE(R1_ram_block2a32_PORT_A_data_in, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_data_in = ~GND;
R1_ram_block2a32_PORT_B_data_in_reg = DFFE(R1_ram_block2a32_PORT_B_data_in, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a32_PORT_A_address_reg = DFFE(R1_ram_block2a32_PORT_A_address, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a32_PORT_B_address_reg = DFFE(R1_ram_block2a32_PORT_B_address, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_write_enable = GND;
R1_ram_block2a32_PORT_A_write_enable_reg = DFFE(R1_ram_block2a32_PORT_A_write_enable, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_write_enable = GND;
R1_ram_block2a32_PORT_B_write_enable_reg = DFFE(R1_ram_block2a32_PORT_B_write_enable, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_clock_0 = M1__clk0;
R1_ram_block2a32_clock_1 = GND;
R1_ram_block2a32_clock_enable_0 = S3_w_anode3231w[3];
R1_ram_block2a32_clock_enable_1 = GND;
R1_ram_block2a32_PORT_A_data_out = MEMORY(R1_ram_block2a32_PORT_A_data_in_reg, R1_ram_block2a32_PORT_B_data_in_reg, R1_ram_block2a32_PORT_A_address_reg, R1_ram_block2a32_PORT_B_address_reg, R1_ram_block2a32_PORT_A_write_enable_reg, R1_ram_block2a32_PORT_B_write_enable_reg, , , R1_ram_block2a32_clock_0, R1_ram_block2a32_clock_1, R1_ram_block2a32_clock_enable_0, R1_ram_block2a32_clock_enable_1, , );
R1_ram_block2a32_PORT_A_data_out_reg = DFFE(R1_ram_block2a32_PORT_A_data_out, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1M1644Q = R1_ram_block2a32_PORT_A_data_out_reg[3];

--R1M1645Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT4
R1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a32_PORT_A_data_in_reg = DFFE(R1_ram_block2a32_PORT_A_data_in, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_data_in = ~GND;
R1_ram_block2a32_PORT_B_data_in_reg = DFFE(R1_ram_block2a32_PORT_B_data_in, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a32_PORT_A_address_reg = DFFE(R1_ram_block2a32_PORT_A_address, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a32_PORT_B_address_reg = DFFE(R1_ram_block2a32_PORT_B_address, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_write_enable = GND;
R1_ram_block2a32_PORT_A_write_enable_reg = DFFE(R1_ram_block2a32_PORT_A_write_enable, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_write_enable = GND;
R1_ram_block2a32_PORT_B_write_enable_reg = DFFE(R1_ram_block2a32_PORT_B_write_enable, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_clock_0 = M1__clk0;
R1_ram_block2a32_clock_1 = GND;
R1_ram_block2a32_clock_enable_0 = S3_w_anode3231w[3];
R1_ram_block2a32_clock_enable_1 = GND;
R1_ram_block2a32_PORT_A_data_out = MEMORY(R1_ram_block2a32_PORT_A_data_in_reg, R1_ram_block2a32_PORT_B_data_in_reg, R1_ram_block2a32_PORT_A_address_reg, R1_ram_block2a32_PORT_B_address_reg, R1_ram_block2a32_PORT_A_write_enable_reg, R1_ram_block2a32_PORT_B_write_enable_reg, , , R1_ram_block2a32_clock_0, R1_ram_block2a32_clock_1, R1_ram_block2a32_clock_enable_0, R1_ram_block2a32_clock_enable_1, , );
R1_ram_block2a32_PORT_A_data_out_reg = DFFE(R1_ram_block2a32_PORT_A_data_out, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1M1645Q = R1_ram_block2a32_PORT_A_data_out_reg[4];

--R1M1646Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT5
R1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a32_PORT_A_data_in_reg = DFFE(R1_ram_block2a32_PORT_A_data_in, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_data_in = ~GND;
R1_ram_block2a32_PORT_B_data_in_reg = DFFE(R1_ram_block2a32_PORT_B_data_in, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a32_PORT_A_address_reg = DFFE(R1_ram_block2a32_PORT_A_address, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a32_PORT_B_address_reg = DFFE(R1_ram_block2a32_PORT_B_address, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_write_enable = GND;
R1_ram_block2a32_PORT_A_write_enable_reg = DFFE(R1_ram_block2a32_PORT_A_write_enable, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_write_enable = GND;
R1_ram_block2a32_PORT_B_write_enable_reg = DFFE(R1_ram_block2a32_PORT_B_write_enable, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_clock_0 = M1__clk0;
R1_ram_block2a32_clock_1 = GND;
R1_ram_block2a32_clock_enable_0 = S3_w_anode3231w[3];
R1_ram_block2a32_clock_enable_1 = GND;
R1_ram_block2a32_PORT_A_data_out = MEMORY(R1_ram_block2a32_PORT_A_data_in_reg, R1_ram_block2a32_PORT_B_data_in_reg, R1_ram_block2a32_PORT_A_address_reg, R1_ram_block2a32_PORT_B_address_reg, R1_ram_block2a32_PORT_A_write_enable_reg, R1_ram_block2a32_PORT_B_write_enable_reg, , , R1_ram_block2a32_clock_0, R1_ram_block2a32_clock_1, R1_ram_block2a32_clock_enable_0, R1_ram_block2a32_clock_enable_1, , );
R1_ram_block2a32_PORT_A_data_out_reg = DFFE(R1_ram_block2a32_PORT_A_data_out, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1M1646Q = R1_ram_block2a32_PORT_A_data_out_reg[5];

--R1M1647Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT6
R1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a32_PORT_A_data_in_reg = DFFE(R1_ram_block2a32_PORT_A_data_in, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_data_in = ~GND;
R1_ram_block2a32_PORT_B_data_in_reg = DFFE(R1_ram_block2a32_PORT_B_data_in, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a32_PORT_A_address_reg = DFFE(R1_ram_block2a32_PORT_A_address, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a32_PORT_B_address_reg = DFFE(R1_ram_block2a32_PORT_B_address, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_write_enable = GND;
R1_ram_block2a32_PORT_A_write_enable_reg = DFFE(R1_ram_block2a32_PORT_A_write_enable, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_write_enable = GND;
R1_ram_block2a32_PORT_B_write_enable_reg = DFFE(R1_ram_block2a32_PORT_B_write_enable, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_clock_0 = M1__clk0;
R1_ram_block2a32_clock_1 = GND;
R1_ram_block2a32_clock_enable_0 = S3_w_anode3231w[3];
R1_ram_block2a32_clock_enable_1 = GND;
R1_ram_block2a32_PORT_A_data_out = MEMORY(R1_ram_block2a32_PORT_A_data_in_reg, R1_ram_block2a32_PORT_B_data_in_reg, R1_ram_block2a32_PORT_A_address_reg, R1_ram_block2a32_PORT_B_address_reg, R1_ram_block2a32_PORT_A_write_enable_reg, R1_ram_block2a32_PORT_B_write_enable_reg, , , R1_ram_block2a32_clock_0, R1_ram_block2a32_clock_1, R1_ram_block2a32_clock_enable_0, R1_ram_block2a32_clock_enable_1, , );
R1_ram_block2a32_PORT_A_data_out_reg = DFFE(R1_ram_block2a32_PORT_A_data_out, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1M1647Q = R1_ram_block2a32_PORT_A_data_out_reg[6];

--R1M1648Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT7
R1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a32_PORT_A_data_in_reg = DFFE(R1_ram_block2a32_PORT_A_data_in, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_data_in = ~GND;
R1_ram_block2a32_PORT_B_data_in_reg = DFFE(R1_ram_block2a32_PORT_B_data_in, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a32_PORT_A_address_reg = DFFE(R1_ram_block2a32_PORT_A_address, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a32_PORT_B_address_reg = DFFE(R1_ram_block2a32_PORT_B_address, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_write_enable = GND;
R1_ram_block2a32_PORT_A_write_enable_reg = DFFE(R1_ram_block2a32_PORT_A_write_enable, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_write_enable = GND;
R1_ram_block2a32_PORT_B_write_enable_reg = DFFE(R1_ram_block2a32_PORT_B_write_enable, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_clock_0 = M1__clk0;
R1_ram_block2a32_clock_1 = GND;
R1_ram_block2a32_clock_enable_0 = S3_w_anode3231w[3];
R1_ram_block2a32_clock_enable_1 = GND;
R1_ram_block2a32_PORT_A_data_out = MEMORY(R1_ram_block2a32_PORT_A_data_in_reg, R1_ram_block2a32_PORT_B_data_in_reg, R1_ram_block2a32_PORT_A_address_reg, R1_ram_block2a32_PORT_B_address_reg, R1_ram_block2a32_PORT_A_write_enable_reg, R1_ram_block2a32_PORT_B_write_enable_reg, , , R1_ram_block2a32_clock_0, R1_ram_block2a32_clock_1, R1_ram_block2a32_clock_enable_0, R1_ram_block2a32_clock_enable_1, , );
R1_ram_block2a32_PORT_A_data_out_reg = DFFE(R1_ram_block2a32_PORT_A_data_out, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1M1648Q = R1_ram_block2a32_PORT_A_data_out_reg[7];


--T1L230 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6673w~281
T1L230 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M1746Q # !R1_address_reg_a[7] & (R1M1646Q));


--R1_ram_block2a35 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a35_PORT_A_data_in_reg = DFFE(R1_ram_block2a35_PORT_A_data_in, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_data_in = ~GND;
R1_ram_block2a35_PORT_B_data_in_reg = DFFE(R1_ram_block2a35_PORT_B_data_in, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a35_PORT_A_address_reg = DFFE(R1_ram_block2a35_PORT_A_address, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a35_PORT_B_address_reg = DFFE(R1_ram_block2a35_PORT_B_address, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_write_enable = GND;
R1_ram_block2a35_PORT_A_write_enable_reg = DFFE(R1_ram_block2a35_PORT_A_write_enable, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_write_enable = GND;
R1_ram_block2a35_PORT_B_write_enable_reg = DFFE(R1_ram_block2a35_PORT_B_write_enable, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_clock_0 = M1__clk0;
R1_ram_block2a35_clock_1 = GND;
R1_ram_block2a35_clock_enable_0 = S3_w_anode3262w[3];
R1_ram_block2a35_clock_enable_1 = GND;
R1_ram_block2a35_PORT_A_data_out = MEMORY(R1_ram_block2a35_PORT_A_data_in_reg, R1_ram_block2a35_PORT_B_data_in_reg, R1_ram_block2a35_PORT_A_address_reg, R1_ram_block2a35_PORT_B_address_reg, R1_ram_block2a35_PORT_A_write_enable_reg, R1_ram_block2a35_PORT_B_write_enable_reg, , , R1_ram_block2a35_clock_0, R1_ram_block2a35_clock_1, R1_ram_block2a35_clock_enable_0, R1_ram_block2a35_clock_enable_1, , );
R1_ram_block2a35_PORT_A_data_out_reg = DFFE(R1_ram_block2a35_PORT_A_data_out, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35 = R1_ram_block2a35_PORT_A_data_out_reg[0];

--R1M1792Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT1
R1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a35_PORT_A_data_in_reg = DFFE(R1_ram_block2a35_PORT_A_data_in, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_data_in = ~GND;
R1_ram_block2a35_PORT_B_data_in_reg = DFFE(R1_ram_block2a35_PORT_B_data_in, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a35_PORT_A_address_reg = DFFE(R1_ram_block2a35_PORT_A_address, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a35_PORT_B_address_reg = DFFE(R1_ram_block2a35_PORT_B_address, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_write_enable = GND;
R1_ram_block2a35_PORT_A_write_enable_reg = DFFE(R1_ram_block2a35_PORT_A_write_enable, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_write_enable = GND;
R1_ram_block2a35_PORT_B_write_enable_reg = DFFE(R1_ram_block2a35_PORT_B_write_enable, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_clock_0 = M1__clk0;
R1_ram_block2a35_clock_1 = GND;
R1_ram_block2a35_clock_enable_0 = S3_w_anode3262w[3];
R1_ram_block2a35_clock_enable_1 = GND;
R1_ram_block2a35_PORT_A_data_out = MEMORY(R1_ram_block2a35_PORT_A_data_in_reg, R1_ram_block2a35_PORT_B_data_in_reg, R1_ram_block2a35_PORT_A_address_reg, R1_ram_block2a35_PORT_B_address_reg, R1_ram_block2a35_PORT_A_write_enable_reg, R1_ram_block2a35_PORT_B_write_enable_reg, , , R1_ram_block2a35_clock_0, R1_ram_block2a35_clock_1, R1_ram_block2a35_clock_enable_0, R1_ram_block2a35_clock_enable_1, , );
R1_ram_block2a35_PORT_A_data_out_reg = DFFE(R1_ram_block2a35_PORT_A_data_out, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1M1792Q = R1_ram_block2a35_PORT_A_data_out_reg[1];

--R1M1793Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT2
R1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a35_PORT_A_data_in_reg = DFFE(R1_ram_block2a35_PORT_A_data_in, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_data_in = ~GND;
R1_ram_block2a35_PORT_B_data_in_reg = DFFE(R1_ram_block2a35_PORT_B_data_in, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a35_PORT_A_address_reg = DFFE(R1_ram_block2a35_PORT_A_address, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a35_PORT_B_address_reg = DFFE(R1_ram_block2a35_PORT_B_address, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_write_enable = GND;
R1_ram_block2a35_PORT_A_write_enable_reg = DFFE(R1_ram_block2a35_PORT_A_write_enable, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_write_enable = GND;
R1_ram_block2a35_PORT_B_write_enable_reg = DFFE(R1_ram_block2a35_PORT_B_write_enable, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_clock_0 = M1__clk0;
R1_ram_block2a35_clock_1 = GND;
R1_ram_block2a35_clock_enable_0 = S3_w_anode3262w[3];
R1_ram_block2a35_clock_enable_1 = GND;
R1_ram_block2a35_PORT_A_data_out = MEMORY(R1_ram_block2a35_PORT_A_data_in_reg, R1_ram_block2a35_PORT_B_data_in_reg, R1_ram_block2a35_PORT_A_address_reg, R1_ram_block2a35_PORT_B_address_reg, R1_ram_block2a35_PORT_A_write_enable_reg, R1_ram_block2a35_PORT_B_write_enable_reg, , , R1_ram_block2a35_clock_0, R1_ram_block2a35_clock_1, R1_ram_block2a35_clock_enable_0, R1_ram_block2a35_clock_enable_1, , );
R1_ram_block2a35_PORT_A_data_out_reg = DFFE(R1_ram_block2a35_PORT_A_data_out, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1M1793Q = R1_ram_block2a35_PORT_A_data_out_reg[2];

--R1M1794Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT3
R1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a35_PORT_A_data_in_reg = DFFE(R1_ram_block2a35_PORT_A_data_in, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_data_in = ~GND;
R1_ram_block2a35_PORT_B_data_in_reg = DFFE(R1_ram_block2a35_PORT_B_data_in, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a35_PORT_A_address_reg = DFFE(R1_ram_block2a35_PORT_A_address, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a35_PORT_B_address_reg = DFFE(R1_ram_block2a35_PORT_B_address, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_write_enable = GND;
R1_ram_block2a35_PORT_A_write_enable_reg = DFFE(R1_ram_block2a35_PORT_A_write_enable, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_write_enable = GND;
R1_ram_block2a35_PORT_B_write_enable_reg = DFFE(R1_ram_block2a35_PORT_B_write_enable, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_clock_0 = M1__clk0;
R1_ram_block2a35_clock_1 = GND;
R1_ram_block2a35_clock_enable_0 = S3_w_anode3262w[3];
R1_ram_block2a35_clock_enable_1 = GND;
R1_ram_block2a35_PORT_A_data_out = MEMORY(R1_ram_block2a35_PORT_A_data_in_reg, R1_ram_block2a35_PORT_B_data_in_reg, R1_ram_block2a35_PORT_A_address_reg, R1_ram_block2a35_PORT_B_address_reg, R1_ram_block2a35_PORT_A_write_enable_reg, R1_ram_block2a35_PORT_B_write_enable_reg, , , R1_ram_block2a35_clock_0, R1_ram_block2a35_clock_1, R1_ram_block2a35_clock_enable_0, R1_ram_block2a35_clock_enable_1, , );
R1_ram_block2a35_PORT_A_data_out_reg = DFFE(R1_ram_block2a35_PORT_A_data_out, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1M1794Q = R1_ram_block2a35_PORT_A_data_out_reg[3];

--R1M1795Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT4
R1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a35_PORT_A_data_in_reg = DFFE(R1_ram_block2a35_PORT_A_data_in, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_data_in = ~GND;
R1_ram_block2a35_PORT_B_data_in_reg = DFFE(R1_ram_block2a35_PORT_B_data_in, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a35_PORT_A_address_reg = DFFE(R1_ram_block2a35_PORT_A_address, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a35_PORT_B_address_reg = DFFE(R1_ram_block2a35_PORT_B_address, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_write_enable = GND;
R1_ram_block2a35_PORT_A_write_enable_reg = DFFE(R1_ram_block2a35_PORT_A_write_enable, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_write_enable = GND;
R1_ram_block2a35_PORT_B_write_enable_reg = DFFE(R1_ram_block2a35_PORT_B_write_enable, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_clock_0 = M1__clk0;
R1_ram_block2a35_clock_1 = GND;
R1_ram_block2a35_clock_enable_0 = S3_w_anode3262w[3];
R1_ram_block2a35_clock_enable_1 = GND;
R1_ram_block2a35_PORT_A_data_out = MEMORY(R1_ram_block2a35_PORT_A_data_in_reg, R1_ram_block2a35_PORT_B_data_in_reg, R1_ram_block2a35_PORT_A_address_reg, R1_ram_block2a35_PORT_B_address_reg, R1_ram_block2a35_PORT_A_write_enable_reg, R1_ram_block2a35_PORT_B_write_enable_reg, , , R1_ram_block2a35_clock_0, R1_ram_block2a35_clock_1, R1_ram_block2a35_clock_enable_0, R1_ram_block2a35_clock_enable_1, , );
R1_ram_block2a35_PORT_A_data_out_reg = DFFE(R1_ram_block2a35_PORT_A_data_out, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1M1795Q = R1_ram_block2a35_PORT_A_data_out_reg[4];

--R1M1796Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT5
R1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a35_PORT_A_data_in_reg = DFFE(R1_ram_block2a35_PORT_A_data_in, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_data_in = ~GND;
R1_ram_block2a35_PORT_B_data_in_reg = DFFE(R1_ram_block2a35_PORT_B_data_in, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a35_PORT_A_address_reg = DFFE(R1_ram_block2a35_PORT_A_address, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a35_PORT_B_address_reg = DFFE(R1_ram_block2a35_PORT_B_address, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_write_enable = GND;
R1_ram_block2a35_PORT_A_write_enable_reg = DFFE(R1_ram_block2a35_PORT_A_write_enable, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_write_enable = GND;
R1_ram_block2a35_PORT_B_write_enable_reg = DFFE(R1_ram_block2a35_PORT_B_write_enable, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_clock_0 = M1__clk0;
R1_ram_block2a35_clock_1 = GND;
R1_ram_block2a35_clock_enable_0 = S3_w_anode3262w[3];
R1_ram_block2a35_clock_enable_1 = GND;
R1_ram_block2a35_PORT_A_data_out = MEMORY(R1_ram_block2a35_PORT_A_data_in_reg, R1_ram_block2a35_PORT_B_data_in_reg, R1_ram_block2a35_PORT_A_address_reg, R1_ram_block2a35_PORT_B_address_reg, R1_ram_block2a35_PORT_A_write_enable_reg, R1_ram_block2a35_PORT_B_write_enable_reg, , , R1_ram_block2a35_clock_0, R1_ram_block2a35_clock_1, R1_ram_block2a35_clock_enable_0, R1_ram_block2a35_clock_enable_1, , );
R1_ram_block2a35_PORT_A_data_out_reg = DFFE(R1_ram_block2a35_PORT_A_data_out, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1M1796Q = R1_ram_block2a35_PORT_A_data_out_reg[5];

--R1M1797Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT6
R1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a35_PORT_A_data_in_reg = DFFE(R1_ram_block2a35_PORT_A_data_in, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_data_in = ~GND;
R1_ram_block2a35_PORT_B_data_in_reg = DFFE(R1_ram_block2a35_PORT_B_data_in, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a35_PORT_A_address_reg = DFFE(R1_ram_block2a35_PORT_A_address, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a35_PORT_B_address_reg = DFFE(R1_ram_block2a35_PORT_B_address, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_write_enable = GND;
R1_ram_block2a35_PORT_A_write_enable_reg = DFFE(R1_ram_block2a35_PORT_A_write_enable, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_write_enable = GND;
R1_ram_block2a35_PORT_B_write_enable_reg = DFFE(R1_ram_block2a35_PORT_B_write_enable, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_clock_0 = M1__clk0;
R1_ram_block2a35_clock_1 = GND;
R1_ram_block2a35_clock_enable_0 = S3_w_anode3262w[3];
R1_ram_block2a35_clock_enable_1 = GND;
R1_ram_block2a35_PORT_A_data_out = MEMORY(R1_ram_block2a35_PORT_A_data_in_reg, R1_ram_block2a35_PORT_B_data_in_reg, R1_ram_block2a35_PORT_A_address_reg, R1_ram_block2a35_PORT_B_address_reg, R1_ram_block2a35_PORT_A_write_enable_reg, R1_ram_block2a35_PORT_B_write_enable_reg, , , R1_ram_block2a35_clock_0, R1_ram_block2a35_clock_1, R1_ram_block2a35_clock_enable_0, R1_ram_block2a35_clock_enable_1, , );
R1_ram_block2a35_PORT_A_data_out_reg = DFFE(R1_ram_block2a35_PORT_A_data_out, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1M1797Q = R1_ram_block2a35_PORT_A_data_out_reg[6];

--R1M1798Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT7
R1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a35_PORT_A_data_in_reg = DFFE(R1_ram_block2a35_PORT_A_data_in, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_data_in = ~GND;
R1_ram_block2a35_PORT_B_data_in_reg = DFFE(R1_ram_block2a35_PORT_B_data_in, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a35_PORT_A_address_reg = DFFE(R1_ram_block2a35_PORT_A_address, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a35_PORT_B_address_reg = DFFE(R1_ram_block2a35_PORT_B_address, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_write_enable = GND;
R1_ram_block2a35_PORT_A_write_enable_reg = DFFE(R1_ram_block2a35_PORT_A_write_enable, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_write_enable = GND;
R1_ram_block2a35_PORT_B_write_enable_reg = DFFE(R1_ram_block2a35_PORT_B_write_enable, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_clock_0 = M1__clk0;
R1_ram_block2a35_clock_1 = GND;
R1_ram_block2a35_clock_enable_0 = S3_w_anode3262w[3];
R1_ram_block2a35_clock_enable_1 = GND;
R1_ram_block2a35_PORT_A_data_out = MEMORY(R1_ram_block2a35_PORT_A_data_in_reg, R1_ram_block2a35_PORT_B_data_in_reg, R1_ram_block2a35_PORT_A_address_reg, R1_ram_block2a35_PORT_B_address_reg, R1_ram_block2a35_PORT_A_write_enable_reg, R1_ram_block2a35_PORT_B_write_enable_reg, , , R1_ram_block2a35_clock_0, R1_ram_block2a35_clock_1, R1_ram_block2a35_clock_enable_0, R1_ram_block2a35_clock_enable_1, , );
R1_ram_block2a35_PORT_A_data_out_reg = DFFE(R1_ram_block2a35_PORT_A_data_out, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1M1798Q = R1_ram_block2a35_PORT_A_data_out_reg[7];


--T1L231 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6673w~282
T1L231 = R1_address_reg_a[6] & (T1L230 & (R1M1796Q) # !T1L230 & R1M1696Q) # !R1_address_reg_a[6] & (T1L230);


--R1_ram_block2a2 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a2_PORT_A_data_in_reg = DFFE(R1_ram_block2a2_PORT_A_data_in, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_data_in = ~GND;
R1_ram_block2a2_PORT_B_data_in_reg = DFFE(R1_ram_block2a2_PORT_B_data_in, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a2_PORT_A_address_reg = DFFE(R1_ram_block2a2_PORT_A_address, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a2_PORT_B_address_reg = DFFE(R1_ram_block2a2_PORT_B_address, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_write_enable = GND;
R1_ram_block2a2_PORT_A_write_enable_reg = DFFE(R1_ram_block2a2_PORT_A_write_enable, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_write_enable = GND;
R1_ram_block2a2_PORT_B_write_enable_reg = DFFE(R1_ram_block2a2_PORT_B_write_enable, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_clock_0 = M1__clk0;
R1_ram_block2a2_clock_1 = GND;
R1_ram_block2a2_clock_enable_0 = S3L6;
R1_ram_block2a2_clock_enable_1 = GND;
R1_ram_block2a2_PORT_A_data_out = MEMORY(R1_ram_block2a2_PORT_A_data_in_reg, R1_ram_block2a2_PORT_B_data_in_reg, R1_ram_block2a2_PORT_A_address_reg, R1_ram_block2a2_PORT_B_address_reg, R1_ram_block2a2_PORT_A_write_enable_reg, R1_ram_block2a2_PORT_B_write_enable_reg, , , R1_ram_block2a2_clock_0, R1_ram_block2a2_clock_1, R1_ram_block2a2_clock_enable_0, R1_ram_block2a2_clock_enable_1, , );
R1_ram_block2a2_PORT_A_data_out_reg = DFFE(R1_ram_block2a2_PORT_A_data_out, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2 = R1_ram_block2a2_PORT_A_data_out_reg[0];

--R1M142Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT1
R1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a2_PORT_A_data_in_reg = DFFE(R1_ram_block2a2_PORT_A_data_in, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_data_in = ~GND;
R1_ram_block2a2_PORT_B_data_in_reg = DFFE(R1_ram_block2a2_PORT_B_data_in, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a2_PORT_A_address_reg = DFFE(R1_ram_block2a2_PORT_A_address, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a2_PORT_B_address_reg = DFFE(R1_ram_block2a2_PORT_B_address, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_write_enable = GND;
R1_ram_block2a2_PORT_A_write_enable_reg = DFFE(R1_ram_block2a2_PORT_A_write_enable, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_write_enable = GND;
R1_ram_block2a2_PORT_B_write_enable_reg = DFFE(R1_ram_block2a2_PORT_B_write_enable, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_clock_0 = M1__clk0;
R1_ram_block2a2_clock_1 = GND;
R1_ram_block2a2_clock_enable_0 = S3L6;
R1_ram_block2a2_clock_enable_1 = GND;
R1_ram_block2a2_PORT_A_data_out = MEMORY(R1_ram_block2a2_PORT_A_data_in_reg, R1_ram_block2a2_PORT_B_data_in_reg, R1_ram_block2a2_PORT_A_address_reg, R1_ram_block2a2_PORT_B_address_reg, R1_ram_block2a2_PORT_A_write_enable_reg, R1_ram_block2a2_PORT_B_write_enable_reg, , , R1_ram_block2a2_clock_0, R1_ram_block2a2_clock_1, R1_ram_block2a2_clock_enable_0, R1_ram_block2a2_clock_enable_1, , );
R1_ram_block2a2_PORT_A_data_out_reg = DFFE(R1_ram_block2a2_PORT_A_data_out, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1M142Q = R1_ram_block2a2_PORT_A_data_out_reg[1];

--R1M143Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT2
R1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a2_PORT_A_data_in_reg = DFFE(R1_ram_block2a2_PORT_A_data_in, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_data_in = ~GND;
R1_ram_block2a2_PORT_B_data_in_reg = DFFE(R1_ram_block2a2_PORT_B_data_in, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a2_PORT_A_address_reg = DFFE(R1_ram_block2a2_PORT_A_address, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a2_PORT_B_address_reg = DFFE(R1_ram_block2a2_PORT_B_address, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_write_enable = GND;
R1_ram_block2a2_PORT_A_write_enable_reg = DFFE(R1_ram_block2a2_PORT_A_write_enable, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_write_enable = GND;
R1_ram_block2a2_PORT_B_write_enable_reg = DFFE(R1_ram_block2a2_PORT_B_write_enable, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_clock_0 = M1__clk0;
R1_ram_block2a2_clock_1 = GND;
R1_ram_block2a2_clock_enable_0 = S3L6;
R1_ram_block2a2_clock_enable_1 = GND;
R1_ram_block2a2_PORT_A_data_out = MEMORY(R1_ram_block2a2_PORT_A_data_in_reg, R1_ram_block2a2_PORT_B_data_in_reg, R1_ram_block2a2_PORT_A_address_reg, R1_ram_block2a2_PORT_B_address_reg, R1_ram_block2a2_PORT_A_write_enable_reg, R1_ram_block2a2_PORT_B_write_enable_reg, , , R1_ram_block2a2_clock_0, R1_ram_block2a2_clock_1, R1_ram_block2a2_clock_enable_0, R1_ram_block2a2_clock_enable_1, , );
R1_ram_block2a2_PORT_A_data_out_reg = DFFE(R1_ram_block2a2_PORT_A_data_out, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1M143Q = R1_ram_block2a2_PORT_A_data_out_reg[2];

--R1M144Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT3
R1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a2_PORT_A_data_in_reg = DFFE(R1_ram_block2a2_PORT_A_data_in, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_data_in = ~GND;
R1_ram_block2a2_PORT_B_data_in_reg = DFFE(R1_ram_block2a2_PORT_B_data_in, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a2_PORT_A_address_reg = DFFE(R1_ram_block2a2_PORT_A_address, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a2_PORT_B_address_reg = DFFE(R1_ram_block2a2_PORT_B_address, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_write_enable = GND;
R1_ram_block2a2_PORT_A_write_enable_reg = DFFE(R1_ram_block2a2_PORT_A_write_enable, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_write_enable = GND;
R1_ram_block2a2_PORT_B_write_enable_reg = DFFE(R1_ram_block2a2_PORT_B_write_enable, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_clock_0 = M1__clk0;
R1_ram_block2a2_clock_1 = GND;
R1_ram_block2a2_clock_enable_0 = S3L6;
R1_ram_block2a2_clock_enable_1 = GND;
R1_ram_block2a2_PORT_A_data_out = MEMORY(R1_ram_block2a2_PORT_A_data_in_reg, R1_ram_block2a2_PORT_B_data_in_reg, R1_ram_block2a2_PORT_A_address_reg, R1_ram_block2a2_PORT_B_address_reg, R1_ram_block2a2_PORT_A_write_enable_reg, R1_ram_block2a2_PORT_B_write_enable_reg, , , R1_ram_block2a2_clock_0, R1_ram_block2a2_clock_1, R1_ram_block2a2_clock_enable_0, R1_ram_block2a2_clock_enable_1, , );
R1_ram_block2a2_PORT_A_data_out_reg = DFFE(R1_ram_block2a2_PORT_A_data_out, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1M144Q = R1_ram_block2a2_PORT_A_data_out_reg[3];

--R1M145Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT4
R1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a2_PORT_A_data_in_reg = DFFE(R1_ram_block2a2_PORT_A_data_in, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_data_in = ~GND;
R1_ram_block2a2_PORT_B_data_in_reg = DFFE(R1_ram_block2a2_PORT_B_data_in, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a2_PORT_A_address_reg = DFFE(R1_ram_block2a2_PORT_A_address, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a2_PORT_B_address_reg = DFFE(R1_ram_block2a2_PORT_B_address, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_write_enable = GND;
R1_ram_block2a2_PORT_A_write_enable_reg = DFFE(R1_ram_block2a2_PORT_A_write_enable, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_write_enable = GND;
R1_ram_block2a2_PORT_B_write_enable_reg = DFFE(R1_ram_block2a2_PORT_B_write_enable, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_clock_0 = M1__clk0;
R1_ram_block2a2_clock_1 = GND;
R1_ram_block2a2_clock_enable_0 = S3L6;
R1_ram_block2a2_clock_enable_1 = GND;
R1_ram_block2a2_PORT_A_data_out = MEMORY(R1_ram_block2a2_PORT_A_data_in_reg, R1_ram_block2a2_PORT_B_data_in_reg, R1_ram_block2a2_PORT_A_address_reg, R1_ram_block2a2_PORT_B_address_reg, R1_ram_block2a2_PORT_A_write_enable_reg, R1_ram_block2a2_PORT_B_write_enable_reg, , , R1_ram_block2a2_clock_0, R1_ram_block2a2_clock_1, R1_ram_block2a2_clock_enable_0, R1_ram_block2a2_clock_enable_1, , );
R1_ram_block2a2_PORT_A_data_out_reg = DFFE(R1_ram_block2a2_PORT_A_data_out, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1M145Q = R1_ram_block2a2_PORT_A_data_out_reg[4];

--R1M146Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT5
R1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a2_PORT_A_data_in_reg = DFFE(R1_ram_block2a2_PORT_A_data_in, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_data_in = ~GND;
R1_ram_block2a2_PORT_B_data_in_reg = DFFE(R1_ram_block2a2_PORT_B_data_in, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a2_PORT_A_address_reg = DFFE(R1_ram_block2a2_PORT_A_address, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a2_PORT_B_address_reg = DFFE(R1_ram_block2a2_PORT_B_address, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_write_enable = GND;
R1_ram_block2a2_PORT_A_write_enable_reg = DFFE(R1_ram_block2a2_PORT_A_write_enable, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_write_enable = GND;
R1_ram_block2a2_PORT_B_write_enable_reg = DFFE(R1_ram_block2a2_PORT_B_write_enable, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_clock_0 = M1__clk0;
R1_ram_block2a2_clock_1 = GND;
R1_ram_block2a2_clock_enable_0 = S3L6;
R1_ram_block2a2_clock_enable_1 = GND;
R1_ram_block2a2_PORT_A_data_out = MEMORY(R1_ram_block2a2_PORT_A_data_in_reg, R1_ram_block2a2_PORT_B_data_in_reg, R1_ram_block2a2_PORT_A_address_reg, R1_ram_block2a2_PORT_B_address_reg, R1_ram_block2a2_PORT_A_write_enable_reg, R1_ram_block2a2_PORT_B_write_enable_reg, , , R1_ram_block2a2_clock_0, R1_ram_block2a2_clock_1, R1_ram_block2a2_clock_enable_0, R1_ram_block2a2_clock_enable_1, , );
R1_ram_block2a2_PORT_A_data_out_reg = DFFE(R1_ram_block2a2_PORT_A_data_out, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1M146Q = R1_ram_block2a2_PORT_A_data_out_reg[5];

--R1M147Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT6
R1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a2_PORT_A_data_in_reg = DFFE(R1_ram_block2a2_PORT_A_data_in, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_data_in = ~GND;
R1_ram_block2a2_PORT_B_data_in_reg = DFFE(R1_ram_block2a2_PORT_B_data_in, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a2_PORT_A_address_reg = DFFE(R1_ram_block2a2_PORT_A_address, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a2_PORT_B_address_reg = DFFE(R1_ram_block2a2_PORT_B_address, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_write_enable = GND;
R1_ram_block2a2_PORT_A_write_enable_reg = DFFE(R1_ram_block2a2_PORT_A_write_enable, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_write_enable = GND;
R1_ram_block2a2_PORT_B_write_enable_reg = DFFE(R1_ram_block2a2_PORT_B_write_enable, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_clock_0 = M1__clk0;
R1_ram_block2a2_clock_1 = GND;
R1_ram_block2a2_clock_enable_0 = S3L6;
R1_ram_block2a2_clock_enable_1 = GND;
R1_ram_block2a2_PORT_A_data_out = MEMORY(R1_ram_block2a2_PORT_A_data_in_reg, R1_ram_block2a2_PORT_B_data_in_reg, R1_ram_block2a2_PORT_A_address_reg, R1_ram_block2a2_PORT_B_address_reg, R1_ram_block2a2_PORT_A_write_enable_reg, R1_ram_block2a2_PORT_B_write_enable_reg, , , R1_ram_block2a2_clock_0, R1_ram_block2a2_clock_1, R1_ram_block2a2_clock_enable_0, R1_ram_block2a2_clock_enable_1, , );
R1_ram_block2a2_PORT_A_data_out_reg = DFFE(R1_ram_block2a2_PORT_A_data_out, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1M147Q = R1_ram_block2a2_PORT_A_data_out_reg[6];

--R1M148Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT7
R1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a2_PORT_A_data_in_reg = DFFE(R1_ram_block2a2_PORT_A_data_in, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_data_in = ~GND;
R1_ram_block2a2_PORT_B_data_in_reg = DFFE(R1_ram_block2a2_PORT_B_data_in, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a2_PORT_A_address_reg = DFFE(R1_ram_block2a2_PORT_A_address, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a2_PORT_B_address_reg = DFFE(R1_ram_block2a2_PORT_B_address, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_write_enable = GND;
R1_ram_block2a2_PORT_A_write_enable_reg = DFFE(R1_ram_block2a2_PORT_A_write_enable, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_write_enable = GND;
R1_ram_block2a2_PORT_B_write_enable_reg = DFFE(R1_ram_block2a2_PORT_B_write_enable, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_clock_0 = M1__clk0;
R1_ram_block2a2_clock_1 = GND;
R1_ram_block2a2_clock_enable_0 = S3L6;
R1_ram_block2a2_clock_enable_1 = GND;
R1_ram_block2a2_PORT_A_data_out = MEMORY(R1_ram_block2a2_PORT_A_data_in_reg, R1_ram_block2a2_PORT_B_data_in_reg, R1_ram_block2a2_PORT_A_address_reg, R1_ram_block2a2_PORT_B_address_reg, R1_ram_block2a2_PORT_A_write_enable_reg, R1_ram_block2a2_PORT_B_write_enable_reg, , , R1_ram_block2a2_clock_0, R1_ram_block2a2_clock_1, R1_ram_block2a2_clock_enable_0, R1_ram_block2a2_clock_enable_1, , );
R1_ram_block2a2_PORT_A_data_out_reg = DFFE(R1_ram_block2a2_PORT_A_data_out, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1M148Q = R1_ram_block2a2_PORT_A_data_out_reg[7];


--R1_ram_block2a1 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a1_PORT_A_data_in_reg = DFFE(R1_ram_block2a1_PORT_A_data_in, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_data_in = ~GND;
R1_ram_block2a1_PORT_B_data_in_reg = DFFE(R1_ram_block2a1_PORT_B_data_in, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a1_PORT_A_address_reg = DFFE(R1_ram_block2a1_PORT_A_address, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a1_PORT_B_address_reg = DFFE(R1_ram_block2a1_PORT_B_address, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_write_enable = GND;
R1_ram_block2a1_PORT_A_write_enable_reg = DFFE(R1_ram_block2a1_PORT_A_write_enable, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_write_enable = GND;
R1_ram_block2a1_PORT_B_write_enable_reg = DFFE(R1_ram_block2a1_PORT_B_write_enable, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_clock_0 = M1__clk0;
R1_ram_block2a1_clock_1 = GND;
R1_ram_block2a1_clock_enable_0 = S3_w_anode2869w[3];
R1_ram_block2a1_clock_enable_1 = GND;
R1_ram_block2a1_PORT_A_data_out = MEMORY(R1_ram_block2a1_PORT_A_data_in_reg, R1_ram_block2a1_PORT_B_data_in_reg, R1_ram_block2a1_PORT_A_address_reg, R1_ram_block2a1_PORT_B_address_reg, R1_ram_block2a1_PORT_A_write_enable_reg, R1_ram_block2a1_PORT_B_write_enable_reg, , , R1_ram_block2a1_clock_0, R1_ram_block2a1_clock_1, R1_ram_block2a1_clock_enable_0, R1_ram_block2a1_clock_enable_1, , );
R1_ram_block2a1_PORT_A_data_out_reg = DFFE(R1_ram_block2a1_PORT_A_data_out, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1 = R1_ram_block2a1_PORT_A_data_out_reg[0];

--R1M92Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT1
R1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a1_PORT_A_data_in_reg = DFFE(R1_ram_block2a1_PORT_A_data_in, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_data_in = ~GND;
R1_ram_block2a1_PORT_B_data_in_reg = DFFE(R1_ram_block2a1_PORT_B_data_in, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a1_PORT_A_address_reg = DFFE(R1_ram_block2a1_PORT_A_address, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a1_PORT_B_address_reg = DFFE(R1_ram_block2a1_PORT_B_address, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_write_enable = GND;
R1_ram_block2a1_PORT_A_write_enable_reg = DFFE(R1_ram_block2a1_PORT_A_write_enable, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_write_enable = GND;
R1_ram_block2a1_PORT_B_write_enable_reg = DFFE(R1_ram_block2a1_PORT_B_write_enable, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_clock_0 = M1__clk0;
R1_ram_block2a1_clock_1 = GND;
R1_ram_block2a1_clock_enable_0 = S3_w_anode2869w[3];
R1_ram_block2a1_clock_enable_1 = GND;
R1_ram_block2a1_PORT_A_data_out = MEMORY(R1_ram_block2a1_PORT_A_data_in_reg, R1_ram_block2a1_PORT_B_data_in_reg, R1_ram_block2a1_PORT_A_address_reg, R1_ram_block2a1_PORT_B_address_reg, R1_ram_block2a1_PORT_A_write_enable_reg, R1_ram_block2a1_PORT_B_write_enable_reg, , , R1_ram_block2a1_clock_0, R1_ram_block2a1_clock_1, R1_ram_block2a1_clock_enable_0, R1_ram_block2a1_clock_enable_1, , );
R1_ram_block2a1_PORT_A_data_out_reg = DFFE(R1_ram_block2a1_PORT_A_data_out, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1M92Q = R1_ram_block2a1_PORT_A_data_out_reg[1];

--R1M93Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT2
R1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a1_PORT_A_data_in_reg = DFFE(R1_ram_block2a1_PORT_A_data_in, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_data_in = ~GND;
R1_ram_block2a1_PORT_B_data_in_reg = DFFE(R1_ram_block2a1_PORT_B_data_in, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a1_PORT_A_address_reg = DFFE(R1_ram_block2a1_PORT_A_address, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a1_PORT_B_address_reg = DFFE(R1_ram_block2a1_PORT_B_address, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_write_enable = GND;
R1_ram_block2a1_PORT_A_write_enable_reg = DFFE(R1_ram_block2a1_PORT_A_write_enable, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_write_enable = GND;
R1_ram_block2a1_PORT_B_write_enable_reg = DFFE(R1_ram_block2a1_PORT_B_write_enable, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_clock_0 = M1__clk0;
R1_ram_block2a1_clock_1 = GND;
R1_ram_block2a1_clock_enable_0 = S3_w_anode2869w[3];
R1_ram_block2a1_clock_enable_1 = GND;
R1_ram_block2a1_PORT_A_data_out = MEMORY(R1_ram_block2a1_PORT_A_data_in_reg, R1_ram_block2a1_PORT_B_data_in_reg, R1_ram_block2a1_PORT_A_address_reg, R1_ram_block2a1_PORT_B_address_reg, R1_ram_block2a1_PORT_A_write_enable_reg, R1_ram_block2a1_PORT_B_write_enable_reg, , , R1_ram_block2a1_clock_0, R1_ram_block2a1_clock_1, R1_ram_block2a1_clock_enable_0, R1_ram_block2a1_clock_enable_1, , );
R1_ram_block2a1_PORT_A_data_out_reg = DFFE(R1_ram_block2a1_PORT_A_data_out, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1M93Q = R1_ram_block2a1_PORT_A_data_out_reg[2];

--R1M94Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT3
R1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a1_PORT_A_data_in_reg = DFFE(R1_ram_block2a1_PORT_A_data_in, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_data_in = ~GND;
R1_ram_block2a1_PORT_B_data_in_reg = DFFE(R1_ram_block2a1_PORT_B_data_in, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a1_PORT_A_address_reg = DFFE(R1_ram_block2a1_PORT_A_address, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a1_PORT_B_address_reg = DFFE(R1_ram_block2a1_PORT_B_address, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_write_enable = GND;
R1_ram_block2a1_PORT_A_write_enable_reg = DFFE(R1_ram_block2a1_PORT_A_write_enable, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_write_enable = GND;
R1_ram_block2a1_PORT_B_write_enable_reg = DFFE(R1_ram_block2a1_PORT_B_write_enable, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_clock_0 = M1__clk0;
R1_ram_block2a1_clock_1 = GND;
R1_ram_block2a1_clock_enable_0 = S3_w_anode2869w[3];
R1_ram_block2a1_clock_enable_1 = GND;
R1_ram_block2a1_PORT_A_data_out = MEMORY(R1_ram_block2a1_PORT_A_data_in_reg, R1_ram_block2a1_PORT_B_data_in_reg, R1_ram_block2a1_PORT_A_address_reg, R1_ram_block2a1_PORT_B_address_reg, R1_ram_block2a1_PORT_A_write_enable_reg, R1_ram_block2a1_PORT_B_write_enable_reg, , , R1_ram_block2a1_clock_0, R1_ram_block2a1_clock_1, R1_ram_block2a1_clock_enable_0, R1_ram_block2a1_clock_enable_1, , );
R1_ram_block2a1_PORT_A_data_out_reg = DFFE(R1_ram_block2a1_PORT_A_data_out, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1M94Q = R1_ram_block2a1_PORT_A_data_out_reg[3];

--R1M95Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT4
R1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a1_PORT_A_data_in_reg = DFFE(R1_ram_block2a1_PORT_A_data_in, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_data_in = ~GND;
R1_ram_block2a1_PORT_B_data_in_reg = DFFE(R1_ram_block2a1_PORT_B_data_in, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a1_PORT_A_address_reg = DFFE(R1_ram_block2a1_PORT_A_address, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a1_PORT_B_address_reg = DFFE(R1_ram_block2a1_PORT_B_address, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_write_enable = GND;
R1_ram_block2a1_PORT_A_write_enable_reg = DFFE(R1_ram_block2a1_PORT_A_write_enable, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_write_enable = GND;
R1_ram_block2a1_PORT_B_write_enable_reg = DFFE(R1_ram_block2a1_PORT_B_write_enable, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_clock_0 = M1__clk0;
R1_ram_block2a1_clock_1 = GND;
R1_ram_block2a1_clock_enable_0 = S3_w_anode2869w[3];
R1_ram_block2a1_clock_enable_1 = GND;
R1_ram_block2a1_PORT_A_data_out = MEMORY(R1_ram_block2a1_PORT_A_data_in_reg, R1_ram_block2a1_PORT_B_data_in_reg, R1_ram_block2a1_PORT_A_address_reg, R1_ram_block2a1_PORT_B_address_reg, R1_ram_block2a1_PORT_A_write_enable_reg, R1_ram_block2a1_PORT_B_write_enable_reg, , , R1_ram_block2a1_clock_0, R1_ram_block2a1_clock_1, R1_ram_block2a1_clock_enable_0, R1_ram_block2a1_clock_enable_1, , );
R1_ram_block2a1_PORT_A_data_out_reg = DFFE(R1_ram_block2a1_PORT_A_data_out, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1M95Q = R1_ram_block2a1_PORT_A_data_out_reg[4];

--R1M96Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT5
R1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a1_PORT_A_data_in_reg = DFFE(R1_ram_block2a1_PORT_A_data_in, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_data_in = ~GND;
R1_ram_block2a1_PORT_B_data_in_reg = DFFE(R1_ram_block2a1_PORT_B_data_in, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a1_PORT_A_address_reg = DFFE(R1_ram_block2a1_PORT_A_address, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a1_PORT_B_address_reg = DFFE(R1_ram_block2a1_PORT_B_address, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_write_enable = GND;
R1_ram_block2a1_PORT_A_write_enable_reg = DFFE(R1_ram_block2a1_PORT_A_write_enable, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_write_enable = GND;
R1_ram_block2a1_PORT_B_write_enable_reg = DFFE(R1_ram_block2a1_PORT_B_write_enable, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_clock_0 = M1__clk0;
R1_ram_block2a1_clock_1 = GND;
R1_ram_block2a1_clock_enable_0 = S3_w_anode2869w[3];
R1_ram_block2a1_clock_enable_1 = GND;
R1_ram_block2a1_PORT_A_data_out = MEMORY(R1_ram_block2a1_PORT_A_data_in_reg, R1_ram_block2a1_PORT_B_data_in_reg, R1_ram_block2a1_PORT_A_address_reg, R1_ram_block2a1_PORT_B_address_reg, R1_ram_block2a1_PORT_A_write_enable_reg, R1_ram_block2a1_PORT_B_write_enable_reg, , , R1_ram_block2a1_clock_0, R1_ram_block2a1_clock_1, R1_ram_block2a1_clock_enable_0, R1_ram_block2a1_clock_enable_1, , );
R1_ram_block2a1_PORT_A_data_out_reg = DFFE(R1_ram_block2a1_PORT_A_data_out, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1M96Q = R1_ram_block2a1_PORT_A_data_out_reg[5];

--R1M97Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT6
R1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a1_PORT_A_data_in_reg = DFFE(R1_ram_block2a1_PORT_A_data_in, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_data_in = ~GND;
R1_ram_block2a1_PORT_B_data_in_reg = DFFE(R1_ram_block2a1_PORT_B_data_in, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a1_PORT_A_address_reg = DFFE(R1_ram_block2a1_PORT_A_address, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a1_PORT_B_address_reg = DFFE(R1_ram_block2a1_PORT_B_address, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_write_enable = GND;
R1_ram_block2a1_PORT_A_write_enable_reg = DFFE(R1_ram_block2a1_PORT_A_write_enable, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_write_enable = GND;
R1_ram_block2a1_PORT_B_write_enable_reg = DFFE(R1_ram_block2a1_PORT_B_write_enable, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_clock_0 = M1__clk0;
R1_ram_block2a1_clock_1 = GND;
R1_ram_block2a1_clock_enable_0 = S3_w_anode2869w[3];
R1_ram_block2a1_clock_enable_1 = GND;
R1_ram_block2a1_PORT_A_data_out = MEMORY(R1_ram_block2a1_PORT_A_data_in_reg, R1_ram_block2a1_PORT_B_data_in_reg, R1_ram_block2a1_PORT_A_address_reg, R1_ram_block2a1_PORT_B_address_reg, R1_ram_block2a1_PORT_A_write_enable_reg, R1_ram_block2a1_PORT_B_write_enable_reg, , , R1_ram_block2a1_clock_0, R1_ram_block2a1_clock_1, R1_ram_block2a1_clock_enable_0, R1_ram_block2a1_clock_enable_1, , );
R1_ram_block2a1_PORT_A_data_out_reg = DFFE(R1_ram_block2a1_PORT_A_data_out, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1M97Q = R1_ram_block2a1_PORT_A_data_out_reg[6];

--R1M98Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT7
R1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a1_PORT_A_data_in_reg = DFFE(R1_ram_block2a1_PORT_A_data_in, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_data_in = ~GND;
R1_ram_block2a1_PORT_B_data_in_reg = DFFE(R1_ram_block2a1_PORT_B_data_in, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a1_PORT_A_address_reg = DFFE(R1_ram_block2a1_PORT_A_address, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a1_PORT_B_address_reg = DFFE(R1_ram_block2a1_PORT_B_address, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_write_enable = GND;
R1_ram_block2a1_PORT_A_write_enable_reg = DFFE(R1_ram_block2a1_PORT_A_write_enable, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_write_enable = GND;
R1_ram_block2a1_PORT_B_write_enable_reg = DFFE(R1_ram_block2a1_PORT_B_write_enable, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_clock_0 = M1__clk0;
R1_ram_block2a1_clock_1 = GND;
R1_ram_block2a1_clock_enable_0 = S3_w_anode2869w[3];
R1_ram_block2a1_clock_enable_1 = GND;
R1_ram_block2a1_PORT_A_data_out = MEMORY(R1_ram_block2a1_PORT_A_data_in_reg, R1_ram_block2a1_PORT_B_data_in_reg, R1_ram_block2a1_PORT_A_address_reg, R1_ram_block2a1_PORT_B_address_reg, R1_ram_block2a1_PORT_A_write_enable_reg, R1_ram_block2a1_PORT_B_write_enable_reg, , , R1_ram_block2a1_clock_0, R1_ram_block2a1_clock_1, R1_ram_block2a1_clock_enable_0, R1_ram_block2a1_clock_enable_1, , );
R1_ram_block2a1_PORT_A_data_out_reg = DFFE(R1_ram_block2a1_PORT_A_data_out, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1M98Q = R1_ram_block2a1_PORT_A_data_out_reg[7];


--R1_ram_block2a0 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a0_PORT_A_data_in_reg = DFFE(R1_ram_block2a0_PORT_A_data_in, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_data_in = ~GND;
R1_ram_block2a0_PORT_B_data_in_reg = DFFE(R1_ram_block2a0_PORT_B_data_in, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a0_PORT_A_address_reg = DFFE(R1_ram_block2a0_PORT_A_address, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a0_PORT_B_address_reg = DFFE(R1_ram_block2a0_PORT_B_address, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_write_enable = GND;
R1_ram_block2a0_PORT_A_write_enable_reg = DFFE(R1_ram_block2a0_PORT_A_write_enable, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_write_enable = GND;
R1_ram_block2a0_PORT_B_write_enable_reg = DFFE(R1_ram_block2a0_PORT_B_write_enable, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_clock_0 = M1__clk0;
R1_ram_block2a0_clock_1 = GND;
R1_ram_block2a0_clock_enable_0 = S3_w_anode2852w[3];
R1_ram_block2a0_PORT_A_data_out = MEMORY(R1_ram_block2a0_PORT_A_data_in_reg, R1_ram_block2a0_PORT_B_data_in_reg, R1_ram_block2a0_PORT_A_address_reg, R1_ram_block2a0_PORT_B_address_reg, R1_ram_block2a0_PORT_A_write_enable_reg, R1_ram_block2a0_PORT_B_write_enable_reg, , , R1_ram_block2a0_clock_0, R1_ram_block2a0_clock_1, R1_ram_block2a0_clock_enable_0, , , );
R1_ram_block2a0_PORT_A_data_out_reg = DFFE(R1_ram_block2a0_PORT_A_data_out, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0 = R1_ram_block2a0_PORT_A_data_out_reg[0];

--R1M42Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT1
R1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a0_PORT_A_data_in_reg = DFFE(R1_ram_block2a0_PORT_A_data_in, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_data_in = ~GND;
R1_ram_block2a0_PORT_B_data_in_reg = DFFE(R1_ram_block2a0_PORT_B_data_in, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a0_PORT_A_address_reg = DFFE(R1_ram_block2a0_PORT_A_address, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a0_PORT_B_address_reg = DFFE(R1_ram_block2a0_PORT_B_address, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_write_enable = GND;
R1_ram_block2a0_PORT_A_write_enable_reg = DFFE(R1_ram_block2a0_PORT_A_write_enable, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_write_enable = GND;
R1_ram_block2a0_PORT_B_write_enable_reg = DFFE(R1_ram_block2a0_PORT_B_write_enable, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_clock_0 = M1__clk0;
R1_ram_block2a0_clock_1 = GND;
R1_ram_block2a0_clock_enable_0 = S3_w_anode2852w[3];
R1_ram_block2a0_PORT_A_data_out = MEMORY(R1_ram_block2a0_PORT_A_data_in_reg, R1_ram_block2a0_PORT_B_data_in_reg, R1_ram_block2a0_PORT_A_address_reg, R1_ram_block2a0_PORT_B_address_reg, R1_ram_block2a0_PORT_A_write_enable_reg, R1_ram_block2a0_PORT_B_write_enable_reg, , , R1_ram_block2a0_clock_0, R1_ram_block2a0_clock_1, R1_ram_block2a0_clock_enable_0, , , );
R1_ram_block2a0_PORT_A_data_out_reg = DFFE(R1_ram_block2a0_PORT_A_data_out, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1M42Q = R1_ram_block2a0_PORT_A_data_out_reg[1];

--R1M43Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT2
R1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a0_PORT_A_data_in_reg = DFFE(R1_ram_block2a0_PORT_A_data_in, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_data_in = ~GND;
R1_ram_block2a0_PORT_B_data_in_reg = DFFE(R1_ram_block2a0_PORT_B_data_in, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a0_PORT_A_address_reg = DFFE(R1_ram_block2a0_PORT_A_address, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a0_PORT_B_address_reg = DFFE(R1_ram_block2a0_PORT_B_address, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_write_enable = GND;
R1_ram_block2a0_PORT_A_write_enable_reg = DFFE(R1_ram_block2a0_PORT_A_write_enable, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_write_enable = GND;
R1_ram_block2a0_PORT_B_write_enable_reg = DFFE(R1_ram_block2a0_PORT_B_write_enable, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_clock_0 = M1__clk0;
R1_ram_block2a0_clock_1 = GND;
R1_ram_block2a0_clock_enable_0 = S3_w_anode2852w[3];
R1_ram_block2a0_PORT_A_data_out = MEMORY(R1_ram_block2a0_PORT_A_data_in_reg, R1_ram_block2a0_PORT_B_data_in_reg, R1_ram_block2a0_PORT_A_address_reg, R1_ram_block2a0_PORT_B_address_reg, R1_ram_block2a0_PORT_A_write_enable_reg, R1_ram_block2a0_PORT_B_write_enable_reg, , , R1_ram_block2a0_clock_0, R1_ram_block2a0_clock_1, R1_ram_block2a0_clock_enable_0, , , );
R1_ram_block2a0_PORT_A_data_out_reg = DFFE(R1_ram_block2a0_PORT_A_data_out, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1M43Q = R1_ram_block2a0_PORT_A_data_out_reg[2];

--R1M44Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT3
R1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a0_PORT_A_data_in_reg = DFFE(R1_ram_block2a0_PORT_A_data_in, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_data_in = ~GND;
R1_ram_block2a0_PORT_B_data_in_reg = DFFE(R1_ram_block2a0_PORT_B_data_in, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a0_PORT_A_address_reg = DFFE(R1_ram_block2a0_PORT_A_address, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a0_PORT_B_address_reg = DFFE(R1_ram_block2a0_PORT_B_address, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_write_enable = GND;
R1_ram_block2a0_PORT_A_write_enable_reg = DFFE(R1_ram_block2a0_PORT_A_write_enable, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_write_enable = GND;
R1_ram_block2a0_PORT_B_write_enable_reg = DFFE(R1_ram_block2a0_PORT_B_write_enable, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_clock_0 = M1__clk0;
R1_ram_block2a0_clock_1 = GND;
R1_ram_block2a0_clock_enable_0 = S3_w_anode2852w[3];
R1_ram_block2a0_PORT_A_data_out = MEMORY(R1_ram_block2a0_PORT_A_data_in_reg, R1_ram_block2a0_PORT_B_data_in_reg, R1_ram_block2a0_PORT_A_address_reg, R1_ram_block2a0_PORT_B_address_reg, R1_ram_block2a0_PORT_A_write_enable_reg, R1_ram_block2a0_PORT_B_write_enable_reg, , , R1_ram_block2a0_clock_0, R1_ram_block2a0_clock_1, R1_ram_block2a0_clock_enable_0, , , );
R1_ram_block2a0_PORT_A_data_out_reg = DFFE(R1_ram_block2a0_PORT_A_data_out, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1M44Q = R1_ram_block2a0_PORT_A_data_out_reg[3];

--R1M45Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT4
R1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a0_PORT_A_data_in_reg = DFFE(R1_ram_block2a0_PORT_A_data_in, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_data_in = ~GND;
R1_ram_block2a0_PORT_B_data_in_reg = DFFE(R1_ram_block2a0_PORT_B_data_in, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a0_PORT_A_address_reg = DFFE(R1_ram_block2a0_PORT_A_address, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a0_PORT_B_address_reg = DFFE(R1_ram_block2a0_PORT_B_address, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_write_enable = GND;
R1_ram_block2a0_PORT_A_write_enable_reg = DFFE(R1_ram_block2a0_PORT_A_write_enable, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_write_enable = GND;
R1_ram_block2a0_PORT_B_write_enable_reg = DFFE(R1_ram_block2a0_PORT_B_write_enable, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_clock_0 = M1__clk0;
R1_ram_block2a0_clock_1 = GND;
R1_ram_block2a0_clock_enable_0 = S3_w_anode2852w[3];
R1_ram_block2a0_PORT_A_data_out = MEMORY(R1_ram_block2a0_PORT_A_data_in_reg, R1_ram_block2a0_PORT_B_data_in_reg, R1_ram_block2a0_PORT_A_address_reg, R1_ram_block2a0_PORT_B_address_reg, R1_ram_block2a0_PORT_A_write_enable_reg, R1_ram_block2a0_PORT_B_write_enable_reg, , , R1_ram_block2a0_clock_0, R1_ram_block2a0_clock_1, R1_ram_block2a0_clock_enable_0, , , );
R1_ram_block2a0_PORT_A_data_out_reg = DFFE(R1_ram_block2a0_PORT_A_data_out, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1M45Q = R1_ram_block2a0_PORT_A_data_out_reg[4];

--R1M46Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT5
R1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a0_PORT_A_data_in_reg = DFFE(R1_ram_block2a0_PORT_A_data_in, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_data_in = ~GND;
R1_ram_block2a0_PORT_B_data_in_reg = DFFE(R1_ram_block2a0_PORT_B_data_in, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a0_PORT_A_address_reg = DFFE(R1_ram_block2a0_PORT_A_address, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a0_PORT_B_address_reg = DFFE(R1_ram_block2a0_PORT_B_address, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_write_enable = GND;
R1_ram_block2a0_PORT_A_write_enable_reg = DFFE(R1_ram_block2a0_PORT_A_write_enable, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_write_enable = GND;
R1_ram_block2a0_PORT_B_write_enable_reg = DFFE(R1_ram_block2a0_PORT_B_write_enable, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_clock_0 = M1__clk0;
R1_ram_block2a0_clock_1 = GND;
R1_ram_block2a0_clock_enable_0 = S3_w_anode2852w[3];
R1_ram_block2a0_PORT_A_data_out = MEMORY(R1_ram_block2a0_PORT_A_data_in_reg, R1_ram_block2a0_PORT_B_data_in_reg, R1_ram_block2a0_PORT_A_address_reg, R1_ram_block2a0_PORT_B_address_reg, R1_ram_block2a0_PORT_A_write_enable_reg, R1_ram_block2a0_PORT_B_write_enable_reg, , , R1_ram_block2a0_clock_0, R1_ram_block2a0_clock_1, R1_ram_block2a0_clock_enable_0, , , );
R1_ram_block2a0_PORT_A_data_out_reg = DFFE(R1_ram_block2a0_PORT_A_data_out, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1M46Q = R1_ram_block2a0_PORT_A_data_out_reg[5];

--R1M47Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT6
R1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a0_PORT_A_data_in_reg = DFFE(R1_ram_block2a0_PORT_A_data_in, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_data_in = ~GND;
R1_ram_block2a0_PORT_B_data_in_reg = DFFE(R1_ram_block2a0_PORT_B_data_in, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a0_PORT_A_address_reg = DFFE(R1_ram_block2a0_PORT_A_address, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a0_PORT_B_address_reg = DFFE(R1_ram_block2a0_PORT_B_address, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_write_enable = GND;
R1_ram_block2a0_PORT_A_write_enable_reg = DFFE(R1_ram_block2a0_PORT_A_write_enable, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_write_enable = GND;
R1_ram_block2a0_PORT_B_write_enable_reg = DFFE(R1_ram_block2a0_PORT_B_write_enable, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_clock_0 = M1__clk0;
R1_ram_block2a0_clock_1 = GND;
R1_ram_block2a0_clock_enable_0 = S3_w_anode2852w[3];
R1_ram_block2a0_PORT_A_data_out = MEMORY(R1_ram_block2a0_PORT_A_data_in_reg, R1_ram_block2a0_PORT_B_data_in_reg, R1_ram_block2a0_PORT_A_address_reg, R1_ram_block2a0_PORT_B_address_reg, R1_ram_block2a0_PORT_A_write_enable_reg, R1_ram_block2a0_PORT_B_write_enable_reg, , , R1_ram_block2a0_clock_0, R1_ram_block2a0_clock_1, R1_ram_block2a0_clock_enable_0, , , );
R1_ram_block2a0_PORT_A_data_out_reg = DFFE(R1_ram_block2a0_PORT_A_data_out, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1M47Q = R1_ram_block2a0_PORT_A_data_out_reg[6];

--R1M48Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT7
R1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a0_PORT_A_data_in_reg = DFFE(R1_ram_block2a0_PORT_A_data_in, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_data_in = ~GND;
R1_ram_block2a0_PORT_B_data_in_reg = DFFE(R1_ram_block2a0_PORT_B_data_in, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a0_PORT_A_address_reg = DFFE(R1_ram_block2a0_PORT_A_address, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a0_PORT_B_address_reg = DFFE(R1_ram_block2a0_PORT_B_address, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_write_enable = GND;
R1_ram_block2a0_PORT_A_write_enable_reg = DFFE(R1_ram_block2a0_PORT_A_write_enable, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_write_enable = GND;
R1_ram_block2a0_PORT_B_write_enable_reg = DFFE(R1_ram_block2a0_PORT_B_write_enable, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_clock_0 = M1__clk0;
R1_ram_block2a0_clock_1 = GND;
R1_ram_block2a0_clock_enable_0 = S3_w_anode2852w[3];
R1_ram_block2a0_PORT_A_data_out = MEMORY(R1_ram_block2a0_PORT_A_data_in_reg, R1_ram_block2a0_PORT_B_data_in_reg, R1_ram_block2a0_PORT_A_address_reg, R1_ram_block2a0_PORT_B_address_reg, R1_ram_block2a0_PORT_A_write_enable_reg, R1_ram_block2a0_PORT_B_write_enable_reg, , , R1_ram_block2a0_clock_0, R1_ram_block2a0_clock_1, R1_ram_block2a0_clock_enable_0, , , );
R1_ram_block2a0_PORT_A_data_out_reg = DFFE(R1_ram_block2a0_PORT_A_data_out, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1M48Q = R1_ram_block2a0_PORT_A_data_out_reg[7];


--T1L218 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6473w~281
T1L218 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M96Q # !R1_address_reg_a[6] & (R1M46Q));


--R1_ram_block2a3 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a3_PORT_A_data_in_reg = DFFE(R1_ram_block2a3_PORT_A_data_in, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_data_in = ~GND;
R1_ram_block2a3_PORT_B_data_in_reg = DFFE(R1_ram_block2a3_PORT_B_data_in, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a3_PORT_A_address_reg = DFFE(R1_ram_block2a3_PORT_A_address, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a3_PORT_B_address_reg = DFFE(R1_ram_block2a3_PORT_B_address, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_write_enable = GND;
R1_ram_block2a3_PORT_A_write_enable_reg = DFFE(R1_ram_block2a3_PORT_A_write_enable, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_write_enable = GND;
R1_ram_block2a3_PORT_B_write_enable_reg = DFFE(R1_ram_block2a3_PORT_B_write_enable, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_clock_0 = M1__clk0;
R1_ram_block2a3_clock_1 = GND;
R1_ram_block2a3_clock_enable_0 = S3_w_anode2889w[3];
R1_ram_block2a3_clock_enable_1 = GND;
R1_ram_block2a3_PORT_A_data_out = MEMORY(R1_ram_block2a3_PORT_A_data_in_reg, R1_ram_block2a3_PORT_B_data_in_reg, R1_ram_block2a3_PORT_A_address_reg, R1_ram_block2a3_PORT_B_address_reg, R1_ram_block2a3_PORT_A_write_enable_reg, R1_ram_block2a3_PORT_B_write_enable_reg, , , R1_ram_block2a3_clock_0, R1_ram_block2a3_clock_1, R1_ram_block2a3_clock_enable_0, R1_ram_block2a3_clock_enable_1, , );
R1_ram_block2a3_PORT_A_data_out_reg = DFFE(R1_ram_block2a3_PORT_A_data_out, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3 = R1_ram_block2a3_PORT_A_data_out_reg[0];

--R1M192Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT1
R1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a3_PORT_A_data_in_reg = DFFE(R1_ram_block2a3_PORT_A_data_in, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_data_in = ~GND;
R1_ram_block2a3_PORT_B_data_in_reg = DFFE(R1_ram_block2a3_PORT_B_data_in, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a3_PORT_A_address_reg = DFFE(R1_ram_block2a3_PORT_A_address, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a3_PORT_B_address_reg = DFFE(R1_ram_block2a3_PORT_B_address, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_write_enable = GND;
R1_ram_block2a3_PORT_A_write_enable_reg = DFFE(R1_ram_block2a3_PORT_A_write_enable, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_write_enable = GND;
R1_ram_block2a3_PORT_B_write_enable_reg = DFFE(R1_ram_block2a3_PORT_B_write_enable, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_clock_0 = M1__clk0;
R1_ram_block2a3_clock_1 = GND;
R1_ram_block2a3_clock_enable_0 = S3_w_anode2889w[3];
R1_ram_block2a3_clock_enable_1 = GND;
R1_ram_block2a3_PORT_A_data_out = MEMORY(R1_ram_block2a3_PORT_A_data_in_reg, R1_ram_block2a3_PORT_B_data_in_reg, R1_ram_block2a3_PORT_A_address_reg, R1_ram_block2a3_PORT_B_address_reg, R1_ram_block2a3_PORT_A_write_enable_reg, R1_ram_block2a3_PORT_B_write_enable_reg, , , R1_ram_block2a3_clock_0, R1_ram_block2a3_clock_1, R1_ram_block2a3_clock_enable_0, R1_ram_block2a3_clock_enable_1, , );
R1_ram_block2a3_PORT_A_data_out_reg = DFFE(R1_ram_block2a3_PORT_A_data_out, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1M192Q = R1_ram_block2a3_PORT_A_data_out_reg[1];

--R1M193Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT2
R1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a3_PORT_A_data_in_reg = DFFE(R1_ram_block2a3_PORT_A_data_in, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_data_in = ~GND;
R1_ram_block2a3_PORT_B_data_in_reg = DFFE(R1_ram_block2a3_PORT_B_data_in, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a3_PORT_A_address_reg = DFFE(R1_ram_block2a3_PORT_A_address, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a3_PORT_B_address_reg = DFFE(R1_ram_block2a3_PORT_B_address, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_write_enable = GND;
R1_ram_block2a3_PORT_A_write_enable_reg = DFFE(R1_ram_block2a3_PORT_A_write_enable, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_write_enable = GND;
R1_ram_block2a3_PORT_B_write_enable_reg = DFFE(R1_ram_block2a3_PORT_B_write_enable, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_clock_0 = M1__clk0;
R1_ram_block2a3_clock_1 = GND;
R1_ram_block2a3_clock_enable_0 = S3_w_anode2889w[3];
R1_ram_block2a3_clock_enable_1 = GND;
R1_ram_block2a3_PORT_A_data_out = MEMORY(R1_ram_block2a3_PORT_A_data_in_reg, R1_ram_block2a3_PORT_B_data_in_reg, R1_ram_block2a3_PORT_A_address_reg, R1_ram_block2a3_PORT_B_address_reg, R1_ram_block2a3_PORT_A_write_enable_reg, R1_ram_block2a3_PORT_B_write_enable_reg, , , R1_ram_block2a3_clock_0, R1_ram_block2a3_clock_1, R1_ram_block2a3_clock_enable_0, R1_ram_block2a3_clock_enable_1, , );
R1_ram_block2a3_PORT_A_data_out_reg = DFFE(R1_ram_block2a3_PORT_A_data_out, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1M193Q = R1_ram_block2a3_PORT_A_data_out_reg[2];

--R1M194Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT3
R1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a3_PORT_A_data_in_reg = DFFE(R1_ram_block2a3_PORT_A_data_in, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_data_in = ~GND;
R1_ram_block2a3_PORT_B_data_in_reg = DFFE(R1_ram_block2a3_PORT_B_data_in, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a3_PORT_A_address_reg = DFFE(R1_ram_block2a3_PORT_A_address, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a3_PORT_B_address_reg = DFFE(R1_ram_block2a3_PORT_B_address, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_write_enable = GND;
R1_ram_block2a3_PORT_A_write_enable_reg = DFFE(R1_ram_block2a3_PORT_A_write_enable, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_write_enable = GND;
R1_ram_block2a3_PORT_B_write_enable_reg = DFFE(R1_ram_block2a3_PORT_B_write_enable, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_clock_0 = M1__clk0;
R1_ram_block2a3_clock_1 = GND;
R1_ram_block2a3_clock_enable_0 = S3_w_anode2889w[3];
R1_ram_block2a3_clock_enable_1 = GND;
R1_ram_block2a3_PORT_A_data_out = MEMORY(R1_ram_block2a3_PORT_A_data_in_reg, R1_ram_block2a3_PORT_B_data_in_reg, R1_ram_block2a3_PORT_A_address_reg, R1_ram_block2a3_PORT_B_address_reg, R1_ram_block2a3_PORT_A_write_enable_reg, R1_ram_block2a3_PORT_B_write_enable_reg, , , R1_ram_block2a3_clock_0, R1_ram_block2a3_clock_1, R1_ram_block2a3_clock_enable_0, R1_ram_block2a3_clock_enable_1, , );
R1_ram_block2a3_PORT_A_data_out_reg = DFFE(R1_ram_block2a3_PORT_A_data_out, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1M194Q = R1_ram_block2a3_PORT_A_data_out_reg[3];

--R1M195Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT4
R1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a3_PORT_A_data_in_reg = DFFE(R1_ram_block2a3_PORT_A_data_in, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_data_in = ~GND;
R1_ram_block2a3_PORT_B_data_in_reg = DFFE(R1_ram_block2a3_PORT_B_data_in, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a3_PORT_A_address_reg = DFFE(R1_ram_block2a3_PORT_A_address, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a3_PORT_B_address_reg = DFFE(R1_ram_block2a3_PORT_B_address, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_write_enable = GND;
R1_ram_block2a3_PORT_A_write_enable_reg = DFFE(R1_ram_block2a3_PORT_A_write_enable, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_write_enable = GND;
R1_ram_block2a3_PORT_B_write_enable_reg = DFFE(R1_ram_block2a3_PORT_B_write_enable, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_clock_0 = M1__clk0;
R1_ram_block2a3_clock_1 = GND;
R1_ram_block2a3_clock_enable_0 = S3_w_anode2889w[3];
R1_ram_block2a3_clock_enable_1 = GND;
R1_ram_block2a3_PORT_A_data_out = MEMORY(R1_ram_block2a3_PORT_A_data_in_reg, R1_ram_block2a3_PORT_B_data_in_reg, R1_ram_block2a3_PORT_A_address_reg, R1_ram_block2a3_PORT_B_address_reg, R1_ram_block2a3_PORT_A_write_enable_reg, R1_ram_block2a3_PORT_B_write_enable_reg, , , R1_ram_block2a3_clock_0, R1_ram_block2a3_clock_1, R1_ram_block2a3_clock_enable_0, R1_ram_block2a3_clock_enable_1, , );
R1_ram_block2a3_PORT_A_data_out_reg = DFFE(R1_ram_block2a3_PORT_A_data_out, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1M195Q = R1_ram_block2a3_PORT_A_data_out_reg[4];

--R1M196Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT5
R1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a3_PORT_A_data_in_reg = DFFE(R1_ram_block2a3_PORT_A_data_in, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_data_in = ~GND;
R1_ram_block2a3_PORT_B_data_in_reg = DFFE(R1_ram_block2a3_PORT_B_data_in, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a3_PORT_A_address_reg = DFFE(R1_ram_block2a3_PORT_A_address, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a3_PORT_B_address_reg = DFFE(R1_ram_block2a3_PORT_B_address, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_write_enable = GND;
R1_ram_block2a3_PORT_A_write_enable_reg = DFFE(R1_ram_block2a3_PORT_A_write_enable, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_write_enable = GND;
R1_ram_block2a3_PORT_B_write_enable_reg = DFFE(R1_ram_block2a3_PORT_B_write_enable, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_clock_0 = M1__clk0;
R1_ram_block2a3_clock_1 = GND;
R1_ram_block2a3_clock_enable_0 = S3_w_anode2889w[3];
R1_ram_block2a3_clock_enable_1 = GND;
R1_ram_block2a3_PORT_A_data_out = MEMORY(R1_ram_block2a3_PORT_A_data_in_reg, R1_ram_block2a3_PORT_B_data_in_reg, R1_ram_block2a3_PORT_A_address_reg, R1_ram_block2a3_PORT_B_address_reg, R1_ram_block2a3_PORT_A_write_enable_reg, R1_ram_block2a3_PORT_B_write_enable_reg, , , R1_ram_block2a3_clock_0, R1_ram_block2a3_clock_1, R1_ram_block2a3_clock_enable_0, R1_ram_block2a3_clock_enable_1, , );
R1_ram_block2a3_PORT_A_data_out_reg = DFFE(R1_ram_block2a3_PORT_A_data_out, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1M196Q = R1_ram_block2a3_PORT_A_data_out_reg[5];

--R1M197Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT6
R1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a3_PORT_A_data_in_reg = DFFE(R1_ram_block2a3_PORT_A_data_in, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_data_in = ~GND;
R1_ram_block2a3_PORT_B_data_in_reg = DFFE(R1_ram_block2a3_PORT_B_data_in, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a3_PORT_A_address_reg = DFFE(R1_ram_block2a3_PORT_A_address, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a3_PORT_B_address_reg = DFFE(R1_ram_block2a3_PORT_B_address, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_write_enable = GND;
R1_ram_block2a3_PORT_A_write_enable_reg = DFFE(R1_ram_block2a3_PORT_A_write_enable, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_write_enable = GND;
R1_ram_block2a3_PORT_B_write_enable_reg = DFFE(R1_ram_block2a3_PORT_B_write_enable, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_clock_0 = M1__clk0;
R1_ram_block2a3_clock_1 = GND;
R1_ram_block2a3_clock_enable_0 = S3_w_anode2889w[3];
R1_ram_block2a3_clock_enable_1 = GND;
R1_ram_block2a3_PORT_A_data_out = MEMORY(R1_ram_block2a3_PORT_A_data_in_reg, R1_ram_block2a3_PORT_B_data_in_reg, R1_ram_block2a3_PORT_A_address_reg, R1_ram_block2a3_PORT_B_address_reg, R1_ram_block2a3_PORT_A_write_enable_reg, R1_ram_block2a3_PORT_B_write_enable_reg, , , R1_ram_block2a3_clock_0, R1_ram_block2a3_clock_1, R1_ram_block2a3_clock_enable_0, R1_ram_block2a3_clock_enable_1, , );
R1_ram_block2a3_PORT_A_data_out_reg = DFFE(R1_ram_block2a3_PORT_A_data_out, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1M197Q = R1_ram_block2a3_PORT_A_data_out_reg[6];

--R1M198Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT7
R1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a3_PORT_A_data_in_reg = DFFE(R1_ram_block2a3_PORT_A_data_in, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_data_in = ~GND;
R1_ram_block2a3_PORT_B_data_in_reg = DFFE(R1_ram_block2a3_PORT_B_data_in, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a3_PORT_A_address_reg = DFFE(R1_ram_block2a3_PORT_A_address, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a3_PORT_B_address_reg = DFFE(R1_ram_block2a3_PORT_B_address, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_write_enable = GND;
R1_ram_block2a3_PORT_A_write_enable_reg = DFFE(R1_ram_block2a3_PORT_A_write_enable, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_write_enable = GND;
R1_ram_block2a3_PORT_B_write_enable_reg = DFFE(R1_ram_block2a3_PORT_B_write_enable, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_clock_0 = M1__clk0;
R1_ram_block2a3_clock_1 = GND;
R1_ram_block2a3_clock_enable_0 = S3_w_anode2889w[3];
R1_ram_block2a3_clock_enable_1 = GND;
R1_ram_block2a3_PORT_A_data_out = MEMORY(R1_ram_block2a3_PORT_A_data_in_reg, R1_ram_block2a3_PORT_B_data_in_reg, R1_ram_block2a3_PORT_A_address_reg, R1_ram_block2a3_PORT_B_address_reg, R1_ram_block2a3_PORT_A_write_enable_reg, R1_ram_block2a3_PORT_B_write_enable_reg, , , R1_ram_block2a3_clock_0, R1_ram_block2a3_clock_1, R1_ram_block2a3_clock_enable_0, R1_ram_block2a3_clock_enable_1, , );
R1_ram_block2a3_PORT_A_data_out_reg = DFFE(R1_ram_block2a3_PORT_A_data_out, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1M198Q = R1_ram_block2a3_PORT_A_data_out_reg[7];


--T1L219 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6473w~282
T1L219 = R1_address_reg_a[7] & (T1L218 & (R1M196Q) # !T1L218 & R1M146Q) # !R1_address_reg_a[7] & (T1L218);


--T1L237 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~578
T1L237 = T1L236 & (R1_address_reg_a[11] & T1L231 # !R1_address_reg_a[11] & (T1L219));


--R1_ram_block2a41 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a41_PORT_A_data_in_reg = DFFE(R1_ram_block2a41_PORT_A_data_in, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_data_in = ~GND;
R1_ram_block2a41_PORT_B_data_in_reg = DFFE(R1_ram_block2a41_PORT_B_data_in, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a41_PORT_A_address_reg = DFFE(R1_ram_block2a41_PORT_A_address, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a41_PORT_B_address_reg = DFFE(R1_ram_block2a41_PORT_B_address, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_write_enable = GND;
R1_ram_block2a41_PORT_A_write_enable_reg = DFFE(R1_ram_block2a41_PORT_A_write_enable, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_write_enable = GND;
R1_ram_block2a41_PORT_B_write_enable_reg = DFFE(R1_ram_block2a41_PORT_B_write_enable, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_clock_0 = M1__clk0;
R1_ram_block2a41_clock_1 = GND;
R1_ram_block2a41_clock_enable_0 = S3_w_anode3335w[3];
R1_ram_block2a41_clock_enable_1 = GND;
R1_ram_block2a41_PORT_A_data_out = MEMORY(R1_ram_block2a41_PORT_A_data_in_reg, R1_ram_block2a41_PORT_B_data_in_reg, R1_ram_block2a41_PORT_A_address_reg, R1_ram_block2a41_PORT_B_address_reg, R1_ram_block2a41_PORT_A_write_enable_reg, R1_ram_block2a41_PORT_B_write_enable_reg, , , R1_ram_block2a41_clock_0, R1_ram_block2a41_clock_1, R1_ram_block2a41_clock_enable_0, R1_ram_block2a41_clock_enable_1, , );
R1_ram_block2a41_PORT_A_data_out_reg = DFFE(R1_ram_block2a41_PORT_A_data_out, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41 = R1_ram_block2a41_PORT_A_data_out_reg[0];

--R1M2092Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT1
R1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a41_PORT_A_data_in_reg = DFFE(R1_ram_block2a41_PORT_A_data_in, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_data_in = ~GND;
R1_ram_block2a41_PORT_B_data_in_reg = DFFE(R1_ram_block2a41_PORT_B_data_in, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a41_PORT_A_address_reg = DFFE(R1_ram_block2a41_PORT_A_address, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a41_PORT_B_address_reg = DFFE(R1_ram_block2a41_PORT_B_address, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_write_enable = GND;
R1_ram_block2a41_PORT_A_write_enable_reg = DFFE(R1_ram_block2a41_PORT_A_write_enable, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_write_enable = GND;
R1_ram_block2a41_PORT_B_write_enable_reg = DFFE(R1_ram_block2a41_PORT_B_write_enable, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_clock_0 = M1__clk0;
R1_ram_block2a41_clock_1 = GND;
R1_ram_block2a41_clock_enable_0 = S3_w_anode3335w[3];
R1_ram_block2a41_clock_enable_1 = GND;
R1_ram_block2a41_PORT_A_data_out = MEMORY(R1_ram_block2a41_PORT_A_data_in_reg, R1_ram_block2a41_PORT_B_data_in_reg, R1_ram_block2a41_PORT_A_address_reg, R1_ram_block2a41_PORT_B_address_reg, R1_ram_block2a41_PORT_A_write_enable_reg, R1_ram_block2a41_PORT_B_write_enable_reg, , , R1_ram_block2a41_clock_0, R1_ram_block2a41_clock_1, R1_ram_block2a41_clock_enable_0, R1_ram_block2a41_clock_enable_1, , );
R1_ram_block2a41_PORT_A_data_out_reg = DFFE(R1_ram_block2a41_PORT_A_data_out, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1M2092Q = R1_ram_block2a41_PORT_A_data_out_reg[1];

--R1M2093Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT2
R1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a41_PORT_A_data_in_reg = DFFE(R1_ram_block2a41_PORT_A_data_in, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_data_in = ~GND;
R1_ram_block2a41_PORT_B_data_in_reg = DFFE(R1_ram_block2a41_PORT_B_data_in, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a41_PORT_A_address_reg = DFFE(R1_ram_block2a41_PORT_A_address, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a41_PORT_B_address_reg = DFFE(R1_ram_block2a41_PORT_B_address, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_write_enable = GND;
R1_ram_block2a41_PORT_A_write_enable_reg = DFFE(R1_ram_block2a41_PORT_A_write_enable, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_write_enable = GND;
R1_ram_block2a41_PORT_B_write_enable_reg = DFFE(R1_ram_block2a41_PORT_B_write_enable, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_clock_0 = M1__clk0;
R1_ram_block2a41_clock_1 = GND;
R1_ram_block2a41_clock_enable_0 = S3_w_anode3335w[3];
R1_ram_block2a41_clock_enable_1 = GND;
R1_ram_block2a41_PORT_A_data_out = MEMORY(R1_ram_block2a41_PORT_A_data_in_reg, R1_ram_block2a41_PORT_B_data_in_reg, R1_ram_block2a41_PORT_A_address_reg, R1_ram_block2a41_PORT_B_address_reg, R1_ram_block2a41_PORT_A_write_enable_reg, R1_ram_block2a41_PORT_B_write_enable_reg, , , R1_ram_block2a41_clock_0, R1_ram_block2a41_clock_1, R1_ram_block2a41_clock_enable_0, R1_ram_block2a41_clock_enable_1, , );
R1_ram_block2a41_PORT_A_data_out_reg = DFFE(R1_ram_block2a41_PORT_A_data_out, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1M2093Q = R1_ram_block2a41_PORT_A_data_out_reg[2];

--R1M2094Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT3
R1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a41_PORT_A_data_in_reg = DFFE(R1_ram_block2a41_PORT_A_data_in, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_data_in = ~GND;
R1_ram_block2a41_PORT_B_data_in_reg = DFFE(R1_ram_block2a41_PORT_B_data_in, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a41_PORT_A_address_reg = DFFE(R1_ram_block2a41_PORT_A_address, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a41_PORT_B_address_reg = DFFE(R1_ram_block2a41_PORT_B_address, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_write_enable = GND;
R1_ram_block2a41_PORT_A_write_enable_reg = DFFE(R1_ram_block2a41_PORT_A_write_enable, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_write_enable = GND;
R1_ram_block2a41_PORT_B_write_enable_reg = DFFE(R1_ram_block2a41_PORT_B_write_enable, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_clock_0 = M1__clk0;
R1_ram_block2a41_clock_1 = GND;
R1_ram_block2a41_clock_enable_0 = S3_w_anode3335w[3];
R1_ram_block2a41_clock_enable_1 = GND;
R1_ram_block2a41_PORT_A_data_out = MEMORY(R1_ram_block2a41_PORT_A_data_in_reg, R1_ram_block2a41_PORT_B_data_in_reg, R1_ram_block2a41_PORT_A_address_reg, R1_ram_block2a41_PORT_B_address_reg, R1_ram_block2a41_PORT_A_write_enable_reg, R1_ram_block2a41_PORT_B_write_enable_reg, , , R1_ram_block2a41_clock_0, R1_ram_block2a41_clock_1, R1_ram_block2a41_clock_enable_0, R1_ram_block2a41_clock_enable_1, , );
R1_ram_block2a41_PORT_A_data_out_reg = DFFE(R1_ram_block2a41_PORT_A_data_out, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1M2094Q = R1_ram_block2a41_PORT_A_data_out_reg[3];

--R1M2095Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT4
R1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a41_PORT_A_data_in_reg = DFFE(R1_ram_block2a41_PORT_A_data_in, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_data_in = ~GND;
R1_ram_block2a41_PORT_B_data_in_reg = DFFE(R1_ram_block2a41_PORT_B_data_in, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a41_PORT_A_address_reg = DFFE(R1_ram_block2a41_PORT_A_address, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a41_PORT_B_address_reg = DFFE(R1_ram_block2a41_PORT_B_address, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_write_enable = GND;
R1_ram_block2a41_PORT_A_write_enable_reg = DFFE(R1_ram_block2a41_PORT_A_write_enable, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_write_enable = GND;
R1_ram_block2a41_PORT_B_write_enable_reg = DFFE(R1_ram_block2a41_PORT_B_write_enable, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_clock_0 = M1__clk0;
R1_ram_block2a41_clock_1 = GND;
R1_ram_block2a41_clock_enable_0 = S3_w_anode3335w[3];
R1_ram_block2a41_clock_enable_1 = GND;
R1_ram_block2a41_PORT_A_data_out = MEMORY(R1_ram_block2a41_PORT_A_data_in_reg, R1_ram_block2a41_PORT_B_data_in_reg, R1_ram_block2a41_PORT_A_address_reg, R1_ram_block2a41_PORT_B_address_reg, R1_ram_block2a41_PORT_A_write_enable_reg, R1_ram_block2a41_PORT_B_write_enable_reg, , , R1_ram_block2a41_clock_0, R1_ram_block2a41_clock_1, R1_ram_block2a41_clock_enable_0, R1_ram_block2a41_clock_enable_1, , );
R1_ram_block2a41_PORT_A_data_out_reg = DFFE(R1_ram_block2a41_PORT_A_data_out, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1M2095Q = R1_ram_block2a41_PORT_A_data_out_reg[4];

--R1M2096Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT5
R1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a41_PORT_A_data_in_reg = DFFE(R1_ram_block2a41_PORT_A_data_in, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_data_in = ~GND;
R1_ram_block2a41_PORT_B_data_in_reg = DFFE(R1_ram_block2a41_PORT_B_data_in, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a41_PORT_A_address_reg = DFFE(R1_ram_block2a41_PORT_A_address, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a41_PORT_B_address_reg = DFFE(R1_ram_block2a41_PORT_B_address, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_write_enable = GND;
R1_ram_block2a41_PORT_A_write_enable_reg = DFFE(R1_ram_block2a41_PORT_A_write_enable, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_write_enable = GND;
R1_ram_block2a41_PORT_B_write_enable_reg = DFFE(R1_ram_block2a41_PORT_B_write_enable, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_clock_0 = M1__clk0;
R1_ram_block2a41_clock_1 = GND;
R1_ram_block2a41_clock_enable_0 = S3_w_anode3335w[3];
R1_ram_block2a41_clock_enable_1 = GND;
R1_ram_block2a41_PORT_A_data_out = MEMORY(R1_ram_block2a41_PORT_A_data_in_reg, R1_ram_block2a41_PORT_B_data_in_reg, R1_ram_block2a41_PORT_A_address_reg, R1_ram_block2a41_PORT_B_address_reg, R1_ram_block2a41_PORT_A_write_enable_reg, R1_ram_block2a41_PORT_B_write_enable_reg, , , R1_ram_block2a41_clock_0, R1_ram_block2a41_clock_1, R1_ram_block2a41_clock_enable_0, R1_ram_block2a41_clock_enable_1, , );
R1_ram_block2a41_PORT_A_data_out_reg = DFFE(R1_ram_block2a41_PORT_A_data_out, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1M2096Q = R1_ram_block2a41_PORT_A_data_out_reg[5];

--R1M2097Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT6
R1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a41_PORT_A_data_in_reg = DFFE(R1_ram_block2a41_PORT_A_data_in, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_data_in = ~GND;
R1_ram_block2a41_PORT_B_data_in_reg = DFFE(R1_ram_block2a41_PORT_B_data_in, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a41_PORT_A_address_reg = DFFE(R1_ram_block2a41_PORT_A_address, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a41_PORT_B_address_reg = DFFE(R1_ram_block2a41_PORT_B_address, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_write_enable = GND;
R1_ram_block2a41_PORT_A_write_enable_reg = DFFE(R1_ram_block2a41_PORT_A_write_enable, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_write_enable = GND;
R1_ram_block2a41_PORT_B_write_enable_reg = DFFE(R1_ram_block2a41_PORT_B_write_enable, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_clock_0 = M1__clk0;
R1_ram_block2a41_clock_1 = GND;
R1_ram_block2a41_clock_enable_0 = S3_w_anode3335w[3];
R1_ram_block2a41_clock_enable_1 = GND;
R1_ram_block2a41_PORT_A_data_out = MEMORY(R1_ram_block2a41_PORT_A_data_in_reg, R1_ram_block2a41_PORT_B_data_in_reg, R1_ram_block2a41_PORT_A_address_reg, R1_ram_block2a41_PORT_B_address_reg, R1_ram_block2a41_PORT_A_write_enable_reg, R1_ram_block2a41_PORT_B_write_enable_reg, , , R1_ram_block2a41_clock_0, R1_ram_block2a41_clock_1, R1_ram_block2a41_clock_enable_0, R1_ram_block2a41_clock_enable_1, , );
R1_ram_block2a41_PORT_A_data_out_reg = DFFE(R1_ram_block2a41_PORT_A_data_out, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1M2097Q = R1_ram_block2a41_PORT_A_data_out_reg[6];

--R1M2098Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT7
R1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a41_PORT_A_data_in_reg = DFFE(R1_ram_block2a41_PORT_A_data_in, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_data_in = ~GND;
R1_ram_block2a41_PORT_B_data_in_reg = DFFE(R1_ram_block2a41_PORT_B_data_in, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a41_PORT_A_address_reg = DFFE(R1_ram_block2a41_PORT_A_address, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a41_PORT_B_address_reg = DFFE(R1_ram_block2a41_PORT_B_address, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_write_enable = GND;
R1_ram_block2a41_PORT_A_write_enable_reg = DFFE(R1_ram_block2a41_PORT_A_write_enable, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_write_enable = GND;
R1_ram_block2a41_PORT_B_write_enable_reg = DFFE(R1_ram_block2a41_PORT_B_write_enable, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_clock_0 = M1__clk0;
R1_ram_block2a41_clock_1 = GND;
R1_ram_block2a41_clock_enable_0 = S3_w_anode3335w[3];
R1_ram_block2a41_clock_enable_1 = GND;
R1_ram_block2a41_PORT_A_data_out = MEMORY(R1_ram_block2a41_PORT_A_data_in_reg, R1_ram_block2a41_PORT_B_data_in_reg, R1_ram_block2a41_PORT_A_address_reg, R1_ram_block2a41_PORT_B_address_reg, R1_ram_block2a41_PORT_A_write_enable_reg, R1_ram_block2a41_PORT_B_write_enable_reg, , , R1_ram_block2a41_clock_0, R1_ram_block2a41_clock_1, R1_ram_block2a41_clock_enable_0, R1_ram_block2a41_clock_enable_1, , );
R1_ram_block2a41_PORT_A_data_out_reg = DFFE(R1_ram_block2a41_PORT_A_data_out, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1M2098Q = R1_ram_block2a41_PORT_A_data_out_reg[7];


--R1_ram_block2a40 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a40_PORT_A_data_in_reg = DFFE(R1_ram_block2a40_PORT_A_data_in, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_data_in = ~GND;
R1_ram_block2a40_PORT_B_data_in_reg = DFFE(R1_ram_block2a40_PORT_B_data_in, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a40_PORT_A_address_reg = DFFE(R1_ram_block2a40_PORT_A_address, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a40_PORT_B_address_reg = DFFE(R1_ram_block2a40_PORT_B_address, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_write_enable = GND;
R1_ram_block2a40_PORT_A_write_enable_reg = DFFE(R1_ram_block2a40_PORT_A_write_enable, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_write_enable = GND;
R1_ram_block2a40_PORT_B_write_enable_reg = DFFE(R1_ram_block2a40_PORT_B_write_enable, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_clock_0 = M1__clk0;
R1_ram_block2a40_clock_1 = GND;
R1_ram_block2a40_clock_enable_0 = S3_w_anode3324w[3];
R1_ram_block2a40_clock_enable_1 = GND;
R1_ram_block2a40_PORT_A_data_out = MEMORY(R1_ram_block2a40_PORT_A_data_in_reg, R1_ram_block2a40_PORT_B_data_in_reg, R1_ram_block2a40_PORT_A_address_reg, R1_ram_block2a40_PORT_B_address_reg, R1_ram_block2a40_PORT_A_write_enable_reg, R1_ram_block2a40_PORT_B_write_enable_reg, , , R1_ram_block2a40_clock_0, R1_ram_block2a40_clock_1, R1_ram_block2a40_clock_enable_0, R1_ram_block2a40_clock_enable_1, , );
R1_ram_block2a40_PORT_A_data_out_reg = DFFE(R1_ram_block2a40_PORT_A_data_out, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40 = R1_ram_block2a40_PORT_A_data_out_reg[0];

--R1M2042Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT1
R1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a40_PORT_A_data_in_reg = DFFE(R1_ram_block2a40_PORT_A_data_in, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_data_in = ~GND;
R1_ram_block2a40_PORT_B_data_in_reg = DFFE(R1_ram_block2a40_PORT_B_data_in, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a40_PORT_A_address_reg = DFFE(R1_ram_block2a40_PORT_A_address, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a40_PORT_B_address_reg = DFFE(R1_ram_block2a40_PORT_B_address, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_write_enable = GND;
R1_ram_block2a40_PORT_A_write_enable_reg = DFFE(R1_ram_block2a40_PORT_A_write_enable, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_write_enable = GND;
R1_ram_block2a40_PORT_B_write_enable_reg = DFFE(R1_ram_block2a40_PORT_B_write_enable, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_clock_0 = M1__clk0;
R1_ram_block2a40_clock_1 = GND;
R1_ram_block2a40_clock_enable_0 = S3_w_anode3324w[3];
R1_ram_block2a40_clock_enable_1 = GND;
R1_ram_block2a40_PORT_A_data_out = MEMORY(R1_ram_block2a40_PORT_A_data_in_reg, R1_ram_block2a40_PORT_B_data_in_reg, R1_ram_block2a40_PORT_A_address_reg, R1_ram_block2a40_PORT_B_address_reg, R1_ram_block2a40_PORT_A_write_enable_reg, R1_ram_block2a40_PORT_B_write_enable_reg, , , R1_ram_block2a40_clock_0, R1_ram_block2a40_clock_1, R1_ram_block2a40_clock_enable_0, R1_ram_block2a40_clock_enable_1, , );
R1_ram_block2a40_PORT_A_data_out_reg = DFFE(R1_ram_block2a40_PORT_A_data_out, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1M2042Q = R1_ram_block2a40_PORT_A_data_out_reg[1];

--R1M2043Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT2
R1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a40_PORT_A_data_in_reg = DFFE(R1_ram_block2a40_PORT_A_data_in, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_data_in = ~GND;
R1_ram_block2a40_PORT_B_data_in_reg = DFFE(R1_ram_block2a40_PORT_B_data_in, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a40_PORT_A_address_reg = DFFE(R1_ram_block2a40_PORT_A_address, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a40_PORT_B_address_reg = DFFE(R1_ram_block2a40_PORT_B_address, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_write_enable = GND;
R1_ram_block2a40_PORT_A_write_enable_reg = DFFE(R1_ram_block2a40_PORT_A_write_enable, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_write_enable = GND;
R1_ram_block2a40_PORT_B_write_enable_reg = DFFE(R1_ram_block2a40_PORT_B_write_enable, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_clock_0 = M1__clk0;
R1_ram_block2a40_clock_1 = GND;
R1_ram_block2a40_clock_enable_0 = S3_w_anode3324w[3];
R1_ram_block2a40_clock_enable_1 = GND;
R1_ram_block2a40_PORT_A_data_out = MEMORY(R1_ram_block2a40_PORT_A_data_in_reg, R1_ram_block2a40_PORT_B_data_in_reg, R1_ram_block2a40_PORT_A_address_reg, R1_ram_block2a40_PORT_B_address_reg, R1_ram_block2a40_PORT_A_write_enable_reg, R1_ram_block2a40_PORT_B_write_enable_reg, , , R1_ram_block2a40_clock_0, R1_ram_block2a40_clock_1, R1_ram_block2a40_clock_enable_0, R1_ram_block2a40_clock_enable_1, , );
R1_ram_block2a40_PORT_A_data_out_reg = DFFE(R1_ram_block2a40_PORT_A_data_out, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1M2043Q = R1_ram_block2a40_PORT_A_data_out_reg[2];

--R1M2044Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT3
R1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a40_PORT_A_data_in_reg = DFFE(R1_ram_block2a40_PORT_A_data_in, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_data_in = ~GND;
R1_ram_block2a40_PORT_B_data_in_reg = DFFE(R1_ram_block2a40_PORT_B_data_in, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a40_PORT_A_address_reg = DFFE(R1_ram_block2a40_PORT_A_address, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a40_PORT_B_address_reg = DFFE(R1_ram_block2a40_PORT_B_address, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_write_enable = GND;
R1_ram_block2a40_PORT_A_write_enable_reg = DFFE(R1_ram_block2a40_PORT_A_write_enable, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_write_enable = GND;
R1_ram_block2a40_PORT_B_write_enable_reg = DFFE(R1_ram_block2a40_PORT_B_write_enable, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_clock_0 = M1__clk0;
R1_ram_block2a40_clock_1 = GND;
R1_ram_block2a40_clock_enable_0 = S3_w_anode3324w[3];
R1_ram_block2a40_clock_enable_1 = GND;
R1_ram_block2a40_PORT_A_data_out = MEMORY(R1_ram_block2a40_PORT_A_data_in_reg, R1_ram_block2a40_PORT_B_data_in_reg, R1_ram_block2a40_PORT_A_address_reg, R1_ram_block2a40_PORT_B_address_reg, R1_ram_block2a40_PORT_A_write_enable_reg, R1_ram_block2a40_PORT_B_write_enable_reg, , , R1_ram_block2a40_clock_0, R1_ram_block2a40_clock_1, R1_ram_block2a40_clock_enable_0, R1_ram_block2a40_clock_enable_1, , );
R1_ram_block2a40_PORT_A_data_out_reg = DFFE(R1_ram_block2a40_PORT_A_data_out, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1M2044Q = R1_ram_block2a40_PORT_A_data_out_reg[3];

--R1M2045Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT4
R1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a40_PORT_A_data_in_reg = DFFE(R1_ram_block2a40_PORT_A_data_in, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_data_in = ~GND;
R1_ram_block2a40_PORT_B_data_in_reg = DFFE(R1_ram_block2a40_PORT_B_data_in, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a40_PORT_A_address_reg = DFFE(R1_ram_block2a40_PORT_A_address, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a40_PORT_B_address_reg = DFFE(R1_ram_block2a40_PORT_B_address, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_write_enable = GND;
R1_ram_block2a40_PORT_A_write_enable_reg = DFFE(R1_ram_block2a40_PORT_A_write_enable, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_write_enable = GND;
R1_ram_block2a40_PORT_B_write_enable_reg = DFFE(R1_ram_block2a40_PORT_B_write_enable, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_clock_0 = M1__clk0;
R1_ram_block2a40_clock_1 = GND;
R1_ram_block2a40_clock_enable_0 = S3_w_anode3324w[3];
R1_ram_block2a40_clock_enable_1 = GND;
R1_ram_block2a40_PORT_A_data_out = MEMORY(R1_ram_block2a40_PORT_A_data_in_reg, R1_ram_block2a40_PORT_B_data_in_reg, R1_ram_block2a40_PORT_A_address_reg, R1_ram_block2a40_PORT_B_address_reg, R1_ram_block2a40_PORT_A_write_enable_reg, R1_ram_block2a40_PORT_B_write_enable_reg, , , R1_ram_block2a40_clock_0, R1_ram_block2a40_clock_1, R1_ram_block2a40_clock_enable_0, R1_ram_block2a40_clock_enable_1, , );
R1_ram_block2a40_PORT_A_data_out_reg = DFFE(R1_ram_block2a40_PORT_A_data_out, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1M2045Q = R1_ram_block2a40_PORT_A_data_out_reg[4];

--R1M2046Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT5
R1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a40_PORT_A_data_in_reg = DFFE(R1_ram_block2a40_PORT_A_data_in, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_data_in = ~GND;
R1_ram_block2a40_PORT_B_data_in_reg = DFFE(R1_ram_block2a40_PORT_B_data_in, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a40_PORT_A_address_reg = DFFE(R1_ram_block2a40_PORT_A_address, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a40_PORT_B_address_reg = DFFE(R1_ram_block2a40_PORT_B_address, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_write_enable = GND;
R1_ram_block2a40_PORT_A_write_enable_reg = DFFE(R1_ram_block2a40_PORT_A_write_enable, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_write_enable = GND;
R1_ram_block2a40_PORT_B_write_enable_reg = DFFE(R1_ram_block2a40_PORT_B_write_enable, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_clock_0 = M1__clk0;
R1_ram_block2a40_clock_1 = GND;
R1_ram_block2a40_clock_enable_0 = S3_w_anode3324w[3];
R1_ram_block2a40_clock_enable_1 = GND;
R1_ram_block2a40_PORT_A_data_out = MEMORY(R1_ram_block2a40_PORT_A_data_in_reg, R1_ram_block2a40_PORT_B_data_in_reg, R1_ram_block2a40_PORT_A_address_reg, R1_ram_block2a40_PORT_B_address_reg, R1_ram_block2a40_PORT_A_write_enable_reg, R1_ram_block2a40_PORT_B_write_enable_reg, , , R1_ram_block2a40_clock_0, R1_ram_block2a40_clock_1, R1_ram_block2a40_clock_enable_0, R1_ram_block2a40_clock_enable_1, , );
R1_ram_block2a40_PORT_A_data_out_reg = DFFE(R1_ram_block2a40_PORT_A_data_out, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1M2046Q = R1_ram_block2a40_PORT_A_data_out_reg[5];

--R1M2047Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT6
R1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a40_PORT_A_data_in_reg = DFFE(R1_ram_block2a40_PORT_A_data_in, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_data_in = ~GND;
R1_ram_block2a40_PORT_B_data_in_reg = DFFE(R1_ram_block2a40_PORT_B_data_in, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a40_PORT_A_address_reg = DFFE(R1_ram_block2a40_PORT_A_address, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a40_PORT_B_address_reg = DFFE(R1_ram_block2a40_PORT_B_address, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_write_enable = GND;
R1_ram_block2a40_PORT_A_write_enable_reg = DFFE(R1_ram_block2a40_PORT_A_write_enable, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_write_enable = GND;
R1_ram_block2a40_PORT_B_write_enable_reg = DFFE(R1_ram_block2a40_PORT_B_write_enable, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_clock_0 = M1__clk0;
R1_ram_block2a40_clock_1 = GND;
R1_ram_block2a40_clock_enable_0 = S3_w_anode3324w[3];
R1_ram_block2a40_clock_enable_1 = GND;
R1_ram_block2a40_PORT_A_data_out = MEMORY(R1_ram_block2a40_PORT_A_data_in_reg, R1_ram_block2a40_PORT_B_data_in_reg, R1_ram_block2a40_PORT_A_address_reg, R1_ram_block2a40_PORT_B_address_reg, R1_ram_block2a40_PORT_A_write_enable_reg, R1_ram_block2a40_PORT_B_write_enable_reg, , , R1_ram_block2a40_clock_0, R1_ram_block2a40_clock_1, R1_ram_block2a40_clock_enable_0, R1_ram_block2a40_clock_enable_1, , );
R1_ram_block2a40_PORT_A_data_out_reg = DFFE(R1_ram_block2a40_PORT_A_data_out, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1M2047Q = R1_ram_block2a40_PORT_A_data_out_reg[6];

--R1M2048Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT7
R1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a40_PORT_A_data_in_reg = DFFE(R1_ram_block2a40_PORT_A_data_in, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_data_in = ~GND;
R1_ram_block2a40_PORT_B_data_in_reg = DFFE(R1_ram_block2a40_PORT_B_data_in, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a40_PORT_A_address_reg = DFFE(R1_ram_block2a40_PORT_A_address, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a40_PORT_B_address_reg = DFFE(R1_ram_block2a40_PORT_B_address, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_write_enable = GND;
R1_ram_block2a40_PORT_A_write_enable_reg = DFFE(R1_ram_block2a40_PORT_A_write_enable, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_write_enable = GND;
R1_ram_block2a40_PORT_B_write_enable_reg = DFFE(R1_ram_block2a40_PORT_B_write_enable, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_clock_0 = M1__clk0;
R1_ram_block2a40_clock_1 = GND;
R1_ram_block2a40_clock_enable_0 = S3_w_anode3324w[3];
R1_ram_block2a40_clock_enable_1 = GND;
R1_ram_block2a40_PORT_A_data_out = MEMORY(R1_ram_block2a40_PORT_A_data_in_reg, R1_ram_block2a40_PORT_B_data_in_reg, R1_ram_block2a40_PORT_A_address_reg, R1_ram_block2a40_PORT_B_address_reg, R1_ram_block2a40_PORT_A_write_enable_reg, R1_ram_block2a40_PORT_B_write_enable_reg, , , R1_ram_block2a40_clock_0, R1_ram_block2a40_clock_1, R1_ram_block2a40_clock_enable_0, R1_ram_block2a40_clock_enable_1, , );
R1_ram_block2a40_PORT_A_data_out_reg = DFFE(R1_ram_block2a40_PORT_A_data_out, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1M2048Q = R1_ram_block2a40_PORT_A_data_out_reg[7];


--R1_ram_block2a43 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a43_PORT_A_data_in_reg = DFFE(R1_ram_block2a43_PORT_A_data_in, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_data_in = ~GND;
R1_ram_block2a43_PORT_B_data_in_reg = DFFE(R1_ram_block2a43_PORT_B_data_in, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a43_PORT_A_address_reg = DFFE(R1_ram_block2a43_PORT_A_address, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a43_PORT_B_address_reg = DFFE(R1_ram_block2a43_PORT_B_address, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_write_enable = GND;
R1_ram_block2a43_PORT_A_write_enable_reg = DFFE(R1_ram_block2a43_PORT_A_write_enable, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_write_enable = GND;
R1_ram_block2a43_PORT_B_write_enable_reg = DFFE(R1_ram_block2a43_PORT_B_write_enable, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_clock_0 = M1__clk0;
R1_ram_block2a43_clock_1 = GND;
R1_ram_block2a43_clock_enable_0 = S3_w_anode3355w[3];
R1_ram_block2a43_clock_enable_1 = GND;
R1_ram_block2a43_PORT_A_data_out = MEMORY(R1_ram_block2a43_PORT_A_data_in_reg, R1_ram_block2a43_PORT_B_data_in_reg, R1_ram_block2a43_PORT_A_address_reg, R1_ram_block2a43_PORT_B_address_reg, R1_ram_block2a43_PORT_A_write_enable_reg, R1_ram_block2a43_PORT_B_write_enable_reg, , , R1_ram_block2a43_clock_0, R1_ram_block2a43_clock_1, R1_ram_block2a43_clock_enable_0, R1_ram_block2a43_clock_enable_1, , );
R1_ram_block2a43_PORT_A_data_out_reg = DFFE(R1_ram_block2a43_PORT_A_data_out, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43 = R1_ram_block2a43_PORT_A_data_out_reg[0];

--R1M2192Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT1
R1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a43_PORT_A_data_in_reg = DFFE(R1_ram_block2a43_PORT_A_data_in, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_data_in = ~GND;
R1_ram_block2a43_PORT_B_data_in_reg = DFFE(R1_ram_block2a43_PORT_B_data_in, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a43_PORT_A_address_reg = DFFE(R1_ram_block2a43_PORT_A_address, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a43_PORT_B_address_reg = DFFE(R1_ram_block2a43_PORT_B_address, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_write_enable = GND;
R1_ram_block2a43_PORT_A_write_enable_reg = DFFE(R1_ram_block2a43_PORT_A_write_enable, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_write_enable = GND;
R1_ram_block2a43_PORT_B_write_enable_reg = DFFE(R1_ram_block2a43_PORT_B_write_enable, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_clock_0 = M1__clk0;
R1_ram_block2a43_clock_1 = GND;
R1_ram_block2a43_clock_enable_0 = S3_w_anode3355w[3];
R1_ram_block2a43_clock_enable_1 = GND;
R1_ram_block2a43_PORT_A_data_out = MEMORY(R1_ram_block2a43_PORT_A_data_in_reg, R1_ram_block2a43_PORT_B_data_in_reg, R1_ram_block2a43_PORT_A_address_reg, R1_ram_block2a43_PORT_B_address_reg, R1_ram_block2a43_PORT_A_write_enable_reg, R1_ram_block2a43_PORT_B_write_enable_reg, , , R1_ram_block2a43_clock_0, R1_ram_block2a43_clock_1, R1_ram_block2a43_clock_enable_0, R1_ram_block2a43_clock_enable_1, , );
R1_ram_block2a43_PORT_A_data_out_reg = DFFE(R1_ram_block2a43_PORT_A_data_out, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1M2192Q = R1_ram_block2a43_PORT_A_data_out_reg[1];

--R1M2193Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT2
R1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a43_PORT_A_data_in_reg = DFFE(R1_ram_block2a43_PORT_A_data_in, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_data_in = ~GND;
R1_ram_block2a43_PORT_B_data_in_reg = DFFE(R1_ram_block2a43_PORT_B_data_in, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a43_PORT_A_address_reg = DFFE(R1_ram_block2a43_PORT_A_address, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a43_PORT_B_address_reg = DFFE(R1_ram_block2a43_PORT_B_address, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_write_enable = GND;
R1_ram_block2a43_PORT_A_write_enable_reg = DFFE(R1_ram_block2a43_PORT_A_write_enable, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_write_enable = GND;
R1_ram_block2a43_PORT_B_write_enable_reg = DFFE(R1_ram_block2a43_PORT_B_write_enable, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_clock_0 = M1__clk0;
R1_ram_block2a43_clock_1 = GND;
R1_ram_block2a43_clock_enable_0 = S3_w_anode3355w[3];
R1_ram_block2a43_clock_enable_1 = GND;
R1_ram_block2a43_PORT_A_data_out = MEMORY(R1_ram_block2a43_PORT_A_data_in_reg, R1_ram_block2a43_PORT_B_data_in_reg, R1_ram_block2a43_PORT_A_address_reg, R1_ram_block2a43_PORT_B_address_reg, R1_ram_block2a43_PORT_A_write_enable_reg, R1_ram_block2a43_PORT_B_write_enable_reg, , , R1_ram_block2a43_clock_0, R1_ram_block2a43_clock_1, R1_ram_block2a43_clock_enable_0, R1_ram_block2a43_clock_enable_1, , );
R1_ram_block2a43_PORT_A_data_out_reg = DFFE(R1_ram_block2a43_PORT_A_data_out, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1M2193Q = R1_ram_block2a43_PORT_A_data_out_reg[2];

--R1M2194Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT3
R1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a43_PORT_A_data_in_reg = DFFE(R1_ram_block2a43_PORT_A_data_in, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_data_in = ~GND;
R1_ram_block2a43_PORT_B_data_in_reg = DFFE(R1_ram_block2a43_PORT_B_data_in, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a43_PORT_A_address_reg = DFFE(R1_ram_block2a43_PORT_A_address, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a43_PORT_B_address_reg = DFFE(R1_ram_block2a43_PORT_B_address, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_write_enable = GND;
R1_ram_block2a43_PORT_A_write_enable_reg = DFFE(R1_ram_block2a43_PORT_A_write_enable, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_write_enable = GND;
R1_ram_block2a43_PORT_B_write_enable_reg = DFFE(R1_ram_block2a43_PORT_B_write_enable, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_clock_0 = M1__clk0;
R1_ram_block2a43_clock_1 = GND;
R1_ram_block2a43_clock_enable_0 = S3_w_anode3355w[3];
R1_ram_block2a43_clock_enable_1 = GND;
R1_ram_block2a43_PORT_A_data_out = MEMORY(R1_ram_block2a43_PORT_A_data_in_reg, R1_ram_block2a43_PORT_B_data_in_reg, R1_ram_block2a43_PORT_A_address_reg, R1_ram_block2a43_PORT_B_address_reg, R1_ram_block2a43_PORT_A_write_enable_reg, R1_ram_block2a43_PORT_B_write_enable_reg, , , R1_ram_block2a43_clock_0, R1_ram_block2a43_clock_1, R1_ram_block2a43_clock_enable_0, R1_ram_block2a43_clock_enable_1, , );
R1_ram_block2a43_PORT_A_data_out_reg = DFFE(R1_ram_block2a43_PORT_A_data_out, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1M2194Q = R1_ram_block2a43_PORT_A_data_out_reg[3];

--R1M2195Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT4
R1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a43_PORT_A_data_in_reg = DFFE(R1_ram_block2a43_PORT_A_data_in, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_data_in = ~GND;
R1_ram_block2a43_PORT_B_data_in_reg = DFFE(R1_ram_block2a43_PORT_B_data_in, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a43_PORT_A_address_reg = DFFE(R1_ram_block2a43_PORT_A_address, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a43_PORT_B_address_reg = DFFE(R1_ram_block2a43_PORT_B_address, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_write_enable = GND;
R1_ram_block2a43_PORT_A_write_enable_reg = DFFE(R1_ram_block2a43_PORT_A_write_enable, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_write_enable = GND;
R1_ram_block2a43_PORT_B_write_enable_reg = DFFE(R1_ram_block2a43_PORT_B_write_enable, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_clock_0 = M1__clk0;
R1_ram_block2a43_clock_1 = GND;
R1_ram_block2a43_clock_enable_0 = S3_w_anode3355w[3];
R1_ram_block2a43_clock_enable_1 = GND;
R1_ram_block2a43_PORT_A_data_out = MEMORY(R1_ram_block2a43_PORT_A_data_in_reg, R1_ram_block2a43_PORT_B_data_in_reg, R1_ram_block2a43_PORT_A_address_reg, R1_ram_block2a43_PORT_B_address_reg, R1_ram_block2a43_PORT_A_write_enable_reg, R1_ram_block2a43_PORT_B_write_enable_reg, , , R1_ram_block2a43_clock_0, R1_ram_block2a43_clock_1, R1_ram_block2a43_clock_enable_0, R1_ram_block2a43_clock_enable_1, , );
R1_ram_block2a43_PORT_A_data_out_reg = DFFE(R1_ram_block2a43_PORT_A_data_out, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1M2195Q = R1_ram_block2a43_PORT_A_data_out_reg[4];

--R1M2196Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT5
R1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a43_PORT_A_data_in_reg = DFFE(R1_ram_block2a43_PORT_A_data_in, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_data_in = ~GND;
R1_ram_block2a43_PORT_B_data_in_reg = DFFE(R1_ram_block2a43_PORT_B_data_in, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a43_PORT_A_address_reg = DFFE(R1_ram_block2a43_PORT_A_address, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a43_PORT_B_address_reg = DFFE(R1_ram_block2a43_PORT_B_address, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_write_enable = GND;
R1_ram_block2a43_PORT_A_write_enable_reg = DFFE(R1_ram_block2a43_PORT_A_write_enable, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_write_enable = GND;
R1_ram_block2a43_PORT_B_write_enable_reg = DFFE(R1_ram_block2a43_PORT_B_write_enable, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_clock_0 = M1__clk0;
R1_ram_block2a43_clock_1 = GND;
R1_ram_block2a43_clock_enable_0 = S3_w_anode3355w[3];
R1_ram_block2a43_clock_enable_1 = GND;
R1_ram_block2a43_PORT_A_data_out = MEMORY(R1_ram_block2a43_PORT_A_data_in_reg, R1_ram_block2a43_PORT_B_data_in_reg, R1_ram_block2a43_PORT_A_address_reg, R1_ram_block2a43_PORT_B_address_reg, R1_ram_block2a43_PORT_A_write_enable_reg, R1_ram_block2a43_PORT_B_write_enable_reg, , , R1_ram_block2a43_clock_0, R1_ram_block2a43_clock_1, R1_ram_block2a43_clock_enable_0, R1_ram_block2a43_clock_enable_1, , );
R1_ram_block2a43_PORT_A_data_out_reg = DFFE(R1_ram_block2a43_PORT_A_data_out, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1M2196Q = R1_ram_block2a43_PORT_A_data_out_reg[5];

--R1M2197Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT6
R1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a43_PORT_A_data_in_reg = DFFE(R1_ram_block2a43_PORT_A_data_in, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_data_in = ~GND;
R1_ram_block2a43_PORT_B_data_in_reg = DFFE(R1_ram_block2a43_PORT_B_data_in, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a43_PORT_A_address_reg = DFFE(R1_ram_block2a43_PORT_A_address, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a43_PORT_B_address_reg = DFFE(R1_ram_block2a43_PORT_B_address, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_write_enable = GND;
R1_ram_block2a43_PORT_A_write_enable_reg = DFFE(R1_ram_block2a43_PORT_A_write_enable, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_write_enable = GND;
R1_ram_block2a43_PORT_B_write_enable_reg = DFFE(R1_ram_block2a43_PORT_B_write_enable, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_clock_0 = M1__clk0;
R1_ram_block2a43_clock_1 = GND;
R1_ram_block2a43_clock_enable_0 = S3_w_anode3355w[3];
R1_ram_block2a43_clock_enable_1 = GND;
R1_ram_block2a43_PORT_A_data_out = MEMORY(R1_ram_block2a43_PORT_A_data_in_reg, R1_ram_block2a43_PORT_B_data_in_reg, R1_ram_block2a43_PORT_A_address_reg, R1_ram_block2a43_PORT_B_address_reg, R1_ram_block2a43_PORT_A_write_enable_reg, R1_ram_block2a43_PORT_B_write_enable_reg, , , R1_ram_block2a43_clock_0, R1_ram_block2a43_clock_1, R1_ram_block2a43_clock_enable_0, R1_ram_block2a43_clock_enable_1, , );
R1_ram_block2a43_PORT_A_data_out_reg = DFFE(R1_ram_block2a43_PORT_A_data_out, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1M2197Q = R1_ram_block2a43_PORT_A_data_out_reg[6];

--R1M2198Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT7
R1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a43_PORT_A_data_in_reg = DFFE(R1_ram_block2a43_PORT_A_data_in, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_data_in = ~GND;
R1_ram_block2a43_PORT_B_data_in_reg = DFFE(R1_ram_block2a43_PORT_B_data_in, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a43_PORT_A_address_reg = DFFE(R1_ram_block2a43_PORT_A_address, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a43_PORT_B_address_reg = DFFE(R1_ram_block2a43_PORT_B_address, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_write_enable = GND;
R1_ram_block2a43_PORT_A_write_enable_reg = DFFE(R1_ram_block2a43_PORT_A_write_enable, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_write_enable = GND;
R1_ram_block2a43_PORT_B_write_enable_reg = DFFE(R1_ram_block2a43_PORT_B_write_enable, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_clock_0 = M1__clk0;
R1_ram_block2a43_clock_1 = GND;
R1_ram_block2a43_clock_enable_0 = S3_w_anode3355w[3];
R1_ram_block2a43_clock_enable_1 = GND;
R1_ram_block2a43_PORT_A_data_out = MEMORY(R1_ram_block2a43_PORT_A_data_in_reg, R1_ram_block2a43_PORT_B_data_in_reg, R1_ram_block2a43_PORT_A_address_reg, R1_ram_block2a43_PORT_B_address_reg, R1_ram_block2a43_PORT_A_write_enable_reg, R1_ram_block2a43_PORT_B_write_enable_reg, , , R1_ram_block2a43_clock_0, R1_ram_block2a43_clock_1, R1_ram_block2a43_clock_enable_0, R1_ram_block2a43_clock_enable_1, , );
R1_ram_block2a43_PORT_A_data_out_reg = DFFE(R1_ram_block2a43_PORT_A_data_out, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1M2198Q = R1_ram_block2a43_PORT_A_data_out_reg[7];


--R1_ram_block2a42 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a42_PORT_A_data_in_reg = DFFE(R1_ram_block2a42_PORT_A_data_in, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_data_in = ~GND;
R1_ram_block2a42_PORT_B_data_in_reg = DFFE(R1_ram_block2a42_PORT_B_data_in, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a42_PORT_A_address_reg = DFFE(R1_ram_block2a42_PORT_A_address, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a42_PORT_B_address_reg = DFFE(R1_ram_block2a42_PORT_B_address, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_write_enable = GND;
R1_ram_block2a42_PORT_A_write_enable_reg = DFFE(R1_ram_block2a42_PORT_A_write_enable, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_write_enable = GND;
R1_ram_block2a42_PORT_B_write_enable_reg = DFFE(R1_ram_block2a42_PORT_B_write_enable, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_clock_0 = M1__clk0;
R1_ram_block2a42_clock_1 = GND;
R1_ram_block2a42_clock_enable_0 = S3_w_anode3345w[3];
R1_ram_block2a42_clock_enable_1 = GND;
R1_ram_block2a42_PORT_A_data_out = MEMORY(R1_ram_block2a42_PORT_A_data_in_reg, R1_ram_block2a42_PORT_B_data_in_reg, R1_ram_block2a42_PORT_A_address_reg, R1_ram_block2a42_PORT_B_address_reg, R1_ram_block2a42_PORT_A_write_enable_reg, R1_ram_block2a42_PORT_B_write_enable_reg, , , R1_ram_block2a42_clock_0, R1_ram_block2a42_clock_1, R1_ram_block2a42_clock_enable_0, R1_ram_block2a42_clock_enable_1, , );
R1_ram_block2a42_PORT_A_data_out_reg = DFFE(R1_ram_block2a42_PORT_A_data_out, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42 = R1_ram_block2a42_PORT_A_data_out_reg[0];

--R1M2142Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT1
R1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a42_PORT_A_data_in_reg = DFFE(R1_ram_block2a42_PORT_A_data_in, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_data_in = ~GND;
R1_ram_block2a42_PORT_B_data_in_reg = DFFE(R1_ram_block2a42_PORT_B_data_in, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a42_PORT_A_address_reg = DFFE(R1_ram_block2a42_PORT_A_address, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a42_PORT_B_address_reg = DFFE(R1_ram_block2a42_PORT_B_address, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_write_enable = GND;
R1_ram_block2a42_PORT_A_write_enable_reg = DFFE(R1_ram_block2a42_PORT_A_write_enable, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_write_enable = GND;
R1_ram_block2a42_PORT_B_write_enable_reg = DFFE(R1_ram_block2a42_PORT_B_write_enable, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_clock_0 = M1__clk0;
R1_ram_block2a42_clock_1 = GND;
R1_ram_block2a42_clock_enable_0 = S3_w_anode3345w[3];
R1_ram_block2a42_clock_enable_1 = GND;
R1_ram_block2a42_PORT_A_data_out = MEMORY(R1_ram_block2a42_PORT_A_data_in_reg, R1_ram_block2a42_PORT_B_data_in_reg, R1_ram_block2a42_PORT_A_address_reg, R1_ram_block2a42_PORT_B_address_reg, R1_ram_block2a42_PORT_A_write_enable_reg, R1_ram_block2a42_PORT_B_write_enable_reg, , , R1_ram_block2a42_clock_0, R1_ram_block2a42_clock_1, R1_ram_block2a42_clock_enable_0, R1_ram_block2a42_clock_enable_1, , );
R1_ram_block2a42_PORT_A_data_out_reg = DFFE(R1_ram_block2a42_PORT_A_data_out, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1M2142Q = R1_ram_block2a42_PORT_A_data_out_reg[1];

--R1M2143Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT2
R1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a42_PORT_A_data_in_reg = DFFE(R1_ram_block2a42_PORT_A_data_in, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_data_in = ~GND;
R1_ram_block2a42_PORT_B_data_in_reg = DFFE(R1_ram_block2a42_PORT_B_data_in, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a42_PORT_A_address_reg = DFFE(R1_ram_block2a42_PORT_A_address, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a42_PORT_B_address_reg = DFFE(R1_ram_block2a42_PORT_B_address, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_write_enable = GND;
R1_ram_block2a42_PORT_A_write_enable_reg = DFFE(R1_ram_block2a42_PORT_A_write_enable, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_write_enable = GND;
R1_ram_block2a42_PORT_B_write_enable_reg = DFFE(R1_ram_block2a42_PORT_B_write_enable, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_clock_0 = M1__clk0;
R1_ram_block2a42_clock_1 = GND;
R1_ram_block2a42_clock_enable_0 = S3_w_anode3345w[3];
R1_ram_block2a42_clock_enable_1 = GND;
R1_ram_block2a42_PORT_A_data_out = MEMORY(R1_ram_block2a42_PORT_A_data_in_reg, R1_ram_block2a42_PORT_B_data_in_reg, R1_ram_block2a42_PORT_A_address_reg, R1_ram_block2a42_PORT_B_address_reg, R1_ram_block2a42_PORT_A_write_enable_reg, R1_ram_block2a42_PORT_B_write_enable_reg, , , R1_ram_block2a42_clock_0, R1_ram_block2a42_clock_1, R1_ram_block2a42_clock_enable_0, R1_ram_block2a42_clock_enable_1, , );
R1_ram_block2a42_PORT_A_data_out_reg = DFFE(R1_ram_block2a42_PORT_A_data_out, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1M2143Q = R1_ram_block2a42_PORT_A_data_out_reg[2];

--R1M2144Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT3
R1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a42_PORT_A_data_in_reg = DFFE(R1_ram_block2a42_PORT_A_data_in, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_data_in = ~GND;
R1_ram_block2a42_PORT_B_data_in_reg = DFFE(R1_ram_block2a42_PORT_B_data_in, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a42_PORT_A_address_reg = DFFE(R1_ram_block2a42_PORT_A_address, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a42_PORT_B_address_reg = DFFE(R1_ram_block2a42_PORT_B_address, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_write_enable = GND;
R1_ram_block2a42_PORT_A_write_enable_reg = DFFE(R1_ram_block2a42_PORT_A_write_enable, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_write_enable = GND;
R1_ram_block2a42_PORT_B_write_enable_reg = DFFE(R1_ram_block2a42_PORT_B_write_enable, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_clock_0 = M1__clk0;
R1_ram_block2a42_clock_1 = GND;
R1_ram_block2a42_clock_enable_0 = S3_w_anode3345w[3];
R1_ram_block2a42_clock_enable_1 = GND;
R1_ram_block2a42_PORT_A_data_out = MEMORY(R1_ram_block2a42_PORT_A_data_in_reg, R1_ram_block2a42_PORT_B_data_in_reg, R1_ram_block2a42_PORT_A_address_reg, R1_ram_block2a42_PORT_B_address_reg, R1_ram_block2a42_PORT_A_write_enable_reg, R1_ram_block2a42_PORT_B_write_enable_reg, , , R1_ram_block2a42_clock_0, R1_ram_block2a42_clock_1, R1_ram_block2a42_clock_enable_0, R1_ram_block2a42_clock_enable_1, , );
R1_ram_block2a42_PORT_A_data_out_reg = DFFE(R1_ram_block2a42_PORT_A_data_out, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1M2144Q = R1_ram_block2a42_PORT_A_data_out_reg[3];

--R1M2145Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT4
R1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a42_PORT_A_data_in_reg = DFFE(R1_ram_block2a42_PORT_A_data_in, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_data_in = ~GND;
R1_ram_block2a42_PORT_B_data_in_reg = DFFE(R1_ram_block2a42_PORT_B_data_in, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a42_PORT_A_address_reg = DFFE(R1_ram_block2a42_PORT_A_address, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a42_PORT_B_address_reg = DFFE(R1_ram_block2a42_PORT_B_address, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_write_enable = GND;
R1_ram_block2a42_PORT_A_write_enable_reg = DFFE(R1_ram_block2a42_PORT_A_write_enable, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_write_enable = GND;
R1_ram_block2a42_PORT_B_write_enable_reg = DFFE(R1_ram_block2a42_PORT_B_write_enable, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_clock_0 = M1__clk0;
R1_ram_block2a42_clock_1 = GND;
R1_ram_block2a42_clock_enable_0 = S3_w_anode3345w[3];
R1_ram_block2a42_clock_enable_1 = GND;
R1_ram_block2a42_PORT_A_data_out = MEMORY(R1_ram_block2a42_PORT_A_data_in_reg, R1_ram_block2a42_PORT_B_data_in_reg, R1_ram_block2a42_PORT_A_address_reg, R1_ram_block2a42_PORT_B_address_reg, R1_ram_block2a42_PORT_A_write_enable_reg, R1_ram_block2a42_PORT_B_write_enable_reg, , , R1_ram_block2a42_clock_0, R1_ram_block2a42_clock_1, R1_ram_block2a42_clock_enable_0, R1_ram_block2a42_clock_enable_1, , );
R1_ram_block2a42_PORT_A_data_out_reg = DFFE(R1_ram_block2a42_PORT_A_data_out, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1M2145Q = R1_ram_block2a42_PORT_A_data_out_reg[4];

--R1M2146Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT5
R1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a42_PORT_A_data_in_reg = DFFE(R1_ram_block2a42_PORT_A_data_in, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_data_in = ~GND;
R1_ram_block2a42_PORT_B_data_in_reg = DFFE(R1_ram_block2a42_PORT_B_data_in, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a42_PORT_A_address_reg = DFFE(R1_ram_block2a42_PORT_A_address, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a42_PORT_B_address_reg = DFFE(R1_ram_block2a42_PORT_B_address, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_write_enable = GND;
R1_ram_block2a42_PORT_A_write_enable_reg = DFFE(R1_ram_block2a42_PORT_A_write_enable, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_write_enable = GND;
R1_ram_block2a42_PORT_B_write_enable_reg = DFFE(R1_ram_block2a42_PORT_B_write_enable, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_clock_0 = M1__clk0;
R1_ram_block2a42_clock_1 = GND;
R1_ram_block2a42_clock_enable_0 = S3_w_anode3345w[3];
R1_ram_block2a42_clock_enable_1 = GND;
R1_ram_block2a42_PORT_A_data_out = MEMORY(R1_ram_block2a42_PORT_A_data_in_reg, R1_ram_block2a42_PORT_B_data_in_reg, R1_ram_block2a42_PORT_A_address_reg, R1_ram_block2a42_PORT_B_address_reg, R1_ram_block2a42_PORT_A_write_enable_reg, R1_ram_block2a42_PORT_B_write_enable_reg, , , R1_ram_block2a42_clock_0, R1_ram_block2a42_clock_1, R1_ram_block2a42_clock_enable_0, R1_ram_block2a42_clock_enable_1, , );
R1_ram_block2a42_PORT_A_data_out_reg = DFFE(R1_ram_block2a42_PORT_A_data_out, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1M2146Q = R1_ram_block2a42_PORT_A_data_out_reg[5];

--R1M2147Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT6
R1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a42_PORT_A_data_in_reg = DFFE(R1_ram_block2a42_PORT_A_data_in, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_data_in = ~GND;
R1_ram_block2a42_PORT_B_data_in_reg = DFFE(R1_ram_block2a42_PORT_B_data_in, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a42_PORT_A_address_reg = DFFE(R1_ram_block2a42_PORT_A_address, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a42_PORT_B_address_reg = DFFE(R1_ram_block2a42_PORT_B_address, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_write_enable = GND;
R1_ram_block2a42_PORT_A_write_enable_reg = DFFE(R1_ram_block2a42_PORT_A_write_enable, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_write_enable = GND;
R1_ram_block2a42_PORT_B_write_enable_reg = DFFE(R1_ram_block2a42_PORT_B_write_enable, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_clock_0 = M1__clk0;
R1_ram_block2a42_clock_1 = GND;
R1_ram_block2a42_clock_enable_0 = S3_w_anode3345w[3];
R1_ram_block2a42_clock_enable_1 = GND;
R1_ram_block2a42_PORT_A_data_out = MEMORY(R1_ram_block2a42_PORT_A_data_in_reg, R1_ram_block2a42_PORT_B_data_in_reg, R1_ram_block2a42_PORT_A_address_reg, R1_ram_block2a42_PORT_B_address_reg, R1_ram_block2a42_PORT_A_write_enable_reg, R1_ram_block2a42_PORT_B_write_enable_reg, , , R1_ram_block2a42_clock_0, R1_ram_block2a42_clock_1, R1_ram_block2a42_clock_enable_0, R1_ram_block2a42_clock_enable_1, , );
R1_ram_block2a42_PORT_A_data_out_reg = DFFE(R1_ram_block2a42_PORT_A_data_out, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1M2147Q = R1_ram_block2a42_PORT_A_data_out_reg[6];

--R1M2148Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT7
R1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a42_PORT_A_data_in_reg = DFFE(R1_ram_block2a42_PORT_A_data_in, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_data_in = ~GND;
R1_ram_block2a42_PORT_B_data_in_reg = DFFE(R1_ram_block2a42_PORT_B_data_in, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a42_PORT_A_address_reg = DFFE(R1_ram_block2a42_PORT_A_address, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a42_PORT_B_address_reg = DFFE(R1_ram_block2a42_PORT_B_address, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_write_enable = GND;
R1_ram_block2a42_PORT_A_write_enable_reg = DFFE(R1_ram_block2a42_PORT_A_write_enable, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_write_enable = GND;
R1_ram_block2a42_PORT_B_write_enable_reg = DFFE(R1_ram_block2a42_PORT_B_write_enable, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_clock_0 = M1__clk0;
R1_ram_block2a42_clock_1 = GND;
R1_ram_block2a42_clock_enable_0 = S3_w_anode3345w[3];
R1_ram_block2a42_clock_enable_1 = GND;
R1_ram_block2a42_PORT_A_data_out = MEMORY(R1_ram_block2a42_PORT_A_data_in_reg, R1_ram_block2a42_PORT_B_data_in_reg, R1_ram_block2a42_PORT_A_address_reg, R1_ram_block2a42_PORT_B_address_reg, R1_ram_block2a42_PORT_A_write_enable_reg, R1_ram_block2a42_PORT_B_write_enable_reg, , , R1_ram_block2a42_clock_0, R1_ram_block2a42_clock_1, R1_ram_block2a42_clock_enable_0, R1_ram_block2a42_clock_enable_1, , );
R1_ram_block2a42_PORT_A_data_out_reg = DFFE(R1_ram_block2a42_PORT_A_data_out, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1M2148Q = R1_ram_block2a42_PORT_A_data_out_reg[7];


--T1L238 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~579
T1L238 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M2196Q # !R1_address_reg_a[6] & (R1M2146Q)) # !R1_address_reg_a[7] & (R1_address_reg_a[6]);


--T1L239 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~580
T1L239 = R1_address_reg_a[7] & (T1L238) # !R1_address_reg_a[7] & (T1L238 & R1M2096Q # !T1L238 & (R1M2046Q));


--R1_ram_block2a10 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a10_PORT_A_data_in_reg = DFFE(R1_ram_block2a10_PORT_A_data_in, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_data_in = ~GND;
R1_ram_block2a10_PORT_B_data_in_reg = DFFE(R1_ram_block2a10_PORT_B_data_in, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a10_PORT_A_address_reg = DFFE(R1_ram_block2a10_PORT_A_address, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a10_PORT_B_address_reg = DFFE(R1_ram_block2a10_PORT_B_address, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_write_enable = GND;
R1_ram_block2a10_PORT_A_write_enable_reg = DFFE(R1_ram_block2a10_PORT_A_write_enable, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_write_enable = GND;
R1_ram_block2a10_PORT_B_write_enable_reg = DFFE(R1_ram_block2a10_PORT_B_write_enable, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_clock_0 = M1__clk0;
R1_ram_block2a10_clock_1 = GND;
R1_ram_block2a10_clock_enable_0 = S3_w_anode2973w[3];
R1_ram_block2a10_clock_enable_1 = GND;
R1_ram_block2a10_PORT_A_data_out = MEMORY(R1_ram_block2a10_PORT_A_data_in_reg, R1_ram_block2a10_PORT_B_data_in_reg, R1_ram_block2a10_PORT_A_address_reg, R1_ram_block2a10_PORT_B_address_reg, R1_ram_block2a10_PORT_A_write_enable_reg, R1_ram_block2a10_PORT_B_write_enable_reg, , , R1_ram_block2a10_clock_0, R1_ram_block2a10_clock_1, R1_ram_block2a10_clock_enable_0, R1_ram_block2a10_clock_enable_1, , );
R1_ram_block2a10_PORT_A_data_out_reg = DFFE(R1_ram_block2a10_PORT_A_data_out, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10 = R1_ram_block2a10_PORT_A_data_out_reg[0];

--R1M542Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT1
R1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a10_PORT_A_data_in_reg = DFFE(R1_ram_block2a10_PORT_A_data_in, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_data_in = ~GND;
R1_ram_block2a10_PORT_B_data_in_reg = DFFE(R1_ram_block2a10_PORT_B_data_in, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a10_PORT_A_address_reg = DFFE(R1_ram_block2a10_PORT_A_address, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a10_PORT_B_address_reg = DFFE(R1_ram_block2a10_PORT_B_address, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_write_enable = GND;
R1_ram_block2a10_PORT_A_write_enable_reg = DFFE(R1_ram_block2a10_PORT_A_write_enable, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_write_enable = GND;
R1_ram_block2a10_PORT_B_write_enable_reg = DFFE(R1_ram_block2a10_PORT_B_write_enable, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_clock_0 = M1__clk0;
R1_ram_block2a10_clock_1 = GND;
R1_ram_block2a10_clock_enable_0 = S3_w_anode2973w[3];
R1_ram_block2a10_clock_enable_1 = GND;
R1_ram_block2a10_PORT_A_data_out = MEMORY(R1_ram_block2a10_PORT_A_data_in_reg, R1_ram_block2a10_PORT_B_data_in_reg, R1_ram_block2a10_PORT_A_address_reg, R1_ram_block2a10_PORT_B_address_reg, R1_ram_block2a10_PORT_A_write_enable_reg, R1_ram_block2a10_PORT_B_write_enable_reg, , , R1_ram_block2a10_clock_0, R1_ram_block2a10_clock_1, R1_ram_block2a10_clock_enable_0, R1_ram_block2a10_clock_enable_1, , );
R1_ram_block2a10_PORT_A_data_out_reg = DFFE(R1_ram_block2a10_PORT_A_data_out, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1M542Q = R1_ram_block2a10_PORT_A_data_out_reg[1];

--R1M543Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT2
R1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a10_PORT_A_data_in_reg = DFFE(R1_ram_block2a10_PORT_A_data_in, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_data_in = ~GND;
R1_ram_block2a10_PORT_B_data_in_reg = DFFE(R1_ram_block2a10_PORT_B_data_in, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a10_PORT_A_address_reg = DFFE(R1_ram_block2a10_PORT_A_address, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a10_PORT_B_address_reg = DFFE(R1_ram_block2a10_PORT_B_address, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_write_enable = GND;
R1_ram_block2a10_PORT_A_write_enable_reg = DFFE(R1_ram_block2a10_PORT_A_write_enable, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_write_enable = GND;
R1_ram_block2a10_PORT_B_write_enable_reg = DFFE(R1_ram_block2a10_PORT_B_write_enable, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_clock_0 = M1__clk0;
R1_ram_block2a10_clock_1 = GND;
R1_ram_block2a10_clock_enable_0 = S3_w_anode2973w[3];
R1_ram_block2a10_clock_enable_1 = GND;
R1_ram_block2a10_PORT_A_data_out = MEMORY(R1_ram_block2a10_PORT_A_data_in_reg, R1_ram_block2a10_PORT_B_data_in_reg, R1_ram_block2a10_PORT_A_address_reg, R1_ram_block2a10_PORT_B_address_reg, R1_ram_block2a10_PORT_A_write_enable_reg, R1_ram_block2a10_PORT_B_write_enable_reg, , , R1_ram_block2a10_clock_0, R1_ram_block2a10_clock_1, R1_ram_block2a10_clock_enable_0, R1_ram_block2a10_clock_enable_1, , );
R1_ram_block2a10_PORT_A_data_out_reg = DFFE(R1_ram_block2a10_PORT_A_data_out, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1M543Q = R1_ram_block2a10_PORT_A_data_out_reg[2];

--R1M544Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT3
R1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a10_PORT_A_data_in_reg = DFFE(R1_ram_block2a10_PORT_A_data_in, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_data_in = ~GND;
R1_ram_block2a10_PORT_B_data_in_reg = DFFE(R1_ram_block2a10_PORT_B_data_in, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a10_PORT_A_address_reg = DFFE(R1_ram_block2a10_PORT_A_address, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a10_PORT_B_address_reg = DFFE(R1_ram_block2a10_PORT_B_address, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_write_enable = GND;
R1_ram_block2a10_PORT_A_write_enable_reg = DFFE(R1_ram_block2a10_PORT_A_write_enable, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_write_enable = GND;
R1_ram_block2a10_PORT_B_write_enable_reg = DFFE(R1_ram_block2a10_PORT_B_write_enable, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_clock_0 = M1__clk0;
R1_ram_block2a10_clock_1 = GND;
R1_ram_block2a10_clock_enable_0 = S3_w_anode2973w[3];
R1_ram_block2a10_clock_enable_1 = GND;
R1_ram_block2a10_PORT_A_data_out = MEMORY(R1_ram_block2a10_PORT_A_data_in_reg, R1_ram_block2a10_PORT_B_data_in_reg, R1_ram_block2a10_PORT_A_address_reg, R1_ram_block2a10_PORT_B_address_reg, R1_ram_block2a10_PORT_A_write_enable_reg, R1_ram_block2a10_PORT_B_write_enable_reg, , , R1_ram_block2a10_clock_0, R1_ram_block2a10_clock_1, R1_ram_block2a10_clock_enable_0, R1_ram_block2a10_clock_enable_1, , );
R1_ram_block2a10_PORT_A_data_out_reg = DFFE(R1_ram_block2a10_PORT_A_data_out, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1M544Q = R1_ram_block2a10_PORT_A_data_out_reg[3];

--R1M545Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT4
R1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a10_PORT_A_data_in_reg = DFFE(R1_ram_block2a10_PORT_A_data_in, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_data_in = ~GND;
R1_ram_block2a10_PORT_B_data_in_reg = DFFE(R1_ram_block2a10_PORT_B_data_in, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a10_PORT_A_address_reg = DFFE(R1_ram_block2a10_PORT_A_address, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a10_PORT_B_address_reg = DFFE(R1_ram_block2a10_PORT_B_address, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_write_enable = GND;
R1_ram_block2a10_PORT_A_write_enable_reg = DFFE(R1_ram_block2a10_PORT_A_write_enable, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_write_enable = GND;
R1_ram_block2a10_PORT_B_write_enable_reg = DFFE(R1_ram_block2a10_PORT_B_write_enable, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_clock_0 = M1__clk0;
R1_ram_block2a10_clock_1 = GND;
R1_ram_block2a10_clock_enable_0 = S3_w_anode2973w[3];
R1_ram_block2a10_clock_enable_1 = GND;
R1_ram_block2a10_PORT_A_data_out = MEMORY(R1_ram_block2a10_PORT_A_data_in_reg, R1_ram_block2a10_PORT_B_data_in_reg, R1_ram_block2a10_PORT_A_address_reg, R1_ram_block2a10_PORT_B_address_reg, R1_ram_block2a10_PORT_A_write_enable_reg, R1_ram_block2a10_PORT_B_write_enable_reg, , , R1_ram_block2a10_clock_0, R1_ram_block2a10_clock_1, R1_ram_block2a10_clock_enable_0, R1_ram_block2a10_clock_enable_1, , );
R1_ram_block2a10_PORT_A_data_out_reg = DFFE(R1_ram_block2a10_PORT_A_data_out, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1M545Q = R1_ram_block2a10_PORT_A_data_out_reg[4];

--R1M546Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT5
R1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a10_PORT_A_data_in_reg = DFFE(R1_ram_block2a10_PORT_A_data_in, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_data_in = ~GND;
R1_ram_block2a10_PORT_B_data_in_reg = DFFE(R1_ram_block2a10_PORT_B_data_in, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a10_PORT_A_address_reg = DFFE(R1_ram_block2a10_PORT_A_address, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a10_PORT_B_address_reg = DFFE(R1_ram_block2a10_PORT_B_address, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_write_enable = GND;
R1_ram_block2a10_PORT_A_write_enable_reg = DFFE(R1_ram_block2a10_PORT_A_write_enable, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_write_enable = GND;
R1_ram_block2a10_PORT_B_write_enable_reg = DFFE(R1_ram_block2a10_PORT_B_write_enable, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_clock_0 = M1__clk0;
R1_ram_block2a10_clock_1 = GND;
R1_ram_block2a10_clock_enable_0 = S3_w_anode2973w[3];
R1_ram_block2a10_clock_enable_1 = GND;
R1_ram_block2a10_PORT_A_data_out = MEMORY(R1_ram_block2a10_PORT_A_data_in_reg, R1_ram_block2a10_PORT_B_data_in_reg, R1_ram_block2a10_PORT_A_address_reg, R1_ram_block2a10_PORT_B_address_reg, R1_ram_block2a10_PORT_A_write_enable_reg, R1_ram_block2a10_PORT_B_write_enable_reg, , , R1_ram_block2a10_clock_0, R1_ram_block2a10_clock_1, R1_ram_block2a10_clock_enable_0, R1_ram_block2a10_clock_enable_1, , );
R1_ram_block2a10_PORT_A_data_out_reg = DFFE(R1_ram_block2a10_PORT_A_data_out, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1M546Q = R1_ram_block2a10_PORT_A_data_out_reg[5];

--R1M547Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT6
R1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a10_PORT_A_data_in_reg = DFFE(R1_ram_block2a10_PORT_A_data_in, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_data_in = ~GND;
R1_ram_block2a10_PORT_B_data_in_reg = DFFE(R1_ram_block2a10_PORT_B_data_in, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a10_PORT_A_address_reg = DFFE(R1_ram_block2a10_PORT_A_address, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a10_PORT_B_address_reg = DFFE(R1_ram_block2a10_PORT_B_address, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_write_enable = GND;
R1_ram_block2a10_PORT_A_write_enable_reg = DFFE(R1_ram_block2a10_PORT_A_write_enable, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_write_enable = GND;
R1_ram_block2a10_PORT_B_write_enable_reg = DFFE(R1_ram_block2a10_PORT_B_write_enable, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_clock_0 = M1__clk0;
R1_ram_block2a10_clock_1 = GND;
R1_ram_block2a10_clock_enable_0 = S3_w_anode2973w[3];
R1_ram_block2a10_clock_enable_1 = GND;
R1_ram_block2a10_PORT_A_data_out = MEMORY(R1_ram_block2a10_PORT_A_data_in_reg, R1_ram_block2a10_PORT_B_data_in_reg, R1_ram_block2a10_PORT_A_address_reg, R1_ram_block2a10_PORT_B_address_reg, R1_ram_block2a10_PORT_A_write_enable_reg, R1_ram_block2a10_PORT_B_write_enable_reg, , , R1_ram_block2a10_clock_0, R1_ram_block2a10_clock_1, R1_ram_block2a10_clock_enable_0, R1_ram_block2a10_clock_enable_1, , );
R1_ram_block2a10_PORT_A_data_out_reg = DFFE(R1_ram_block2a10_PORT_A_data_out, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1M547Q = R1_ram_block2a10_PORT_A_data_out_reg[6];

--R1M548Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT7
R1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a10_PORT_A_data_in_reg = DFFE(R1_ram_block2a10_PORT_A_data_in, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_data_in = ~GND;
R1_ram_block2a10_PORT_B_data_in_reg = DFFE(R1_ram_block2a10_PORT_B_data_in, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a10_PORT_A_address_reg = DFFE(R1_ram_block2a10_PORT_A_address, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a10_PORT_B_address_reg = DFFE(R1_ram_block2a10_PORT_B_address, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_write_enable = GND;
R1_ram_block2a10_PORT_A_write_enable_reg = DFFE(R1_ram_block2a10_PORT_A_write_enable, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_write_enable = GND;
R1_ram_block2a10_PORT_B_write_enable_reg = DFFE(R1_ram_block2a10_PORT_B_write_enable, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_clock_0 = M1__clk0;
R1_ram_block2a10_clock_1 = GND;
R1_ram_block2a10_clock_enable_0 = S3_w_anode2973w[3];
R1_ram_block2a10_clock_enable_1 = GND;
R1_ram_block2a10_PORT_A_data_out = MEMORY(R1_ram_block2a10_PORT_A_data_in_reg, R1_ram_block2a10_PORT_B_data_in_reg, R1_ram_block2a10_PORT_A_address_reg, R1_ram_block2a10_PORT_B_address_reg, R1_ram_block2a10_PORT_A_write_enable_reg, R1_ram_block2a10_PORT_B_write_enable_reg, , , R1_ram_block2a10_clock_0, R1_ram_block2a10_clock_1, R1_ram_block2a10_clock_enable_0, R1_ram_block2a10_clock_enable_1, , );
R1_ram_block2a10_PORT_A_data_out_reg = DFFE(R1_ram_block2a10_PORT_A_data_out, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1M548Q = R1_ram_block2a10_PORT_A_data_out_reg[7];


--R1_ram_block2a8 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a8_PORT_A_data_in_reg = DFFE(R1_ram_block2a8_PORT_A_data_in, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_data_in = ~GND;
R1_ram_block2a8_PORT_B_data_in_reg = DFFE(R1_ram_block2a8_PORT_B_data_in, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a8_PORT_A_address_reg = DFFE(R1_ram_block2a8_PORT_A_address, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a8_PORT_B_address_reg = DFFE(R1_ram_block2a8_PORT_B_address, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_write_enable = GND;
R1_ram_block2a8_PORT_A_write_enable_reg = DFFE(R1_ram_block2a8_PORT_A_write_enable, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_write_enable = GND;
R1_ram_block2a8_PORT_B_write_enable_reg = DFFE(R1_ram_block2a8_PORT_B_write_enable, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_clock_0 = M1__clk0;
R1_ram_block2a8_clock_1 = GND;
R1_ram_block2a8_clock_enable_0 = S3_w_anode2952w[3];
R1_ram_block2a8_clock_enable_1 = GND;
R1_ram_block2a8_PORT_A_data_out = MEMORY(R1_ram_block2a8_PORT_A_data_in_reg, R1_ram_block2a8_PORT_B_data_in_reg, R1_ram_block2a8_PORT_A_address_reg, R1_ram_block2a8_PORT_B_address_reg, R1_ram_block2a8_PORT_A_write_enable_reg, R1_ram_block2a8_PORT_B_write_enable_reg, , , R1_ram_block2a8_clock_0, R1_ram_block2a8_clock_1, R1_ram_block2a8_clock_enable_0, R1_ram_block2a8_clock_enable_1, , );
R1_ram_block2a8_PORT_A_data_out_reg = DFFE(R1_ram_block2a8_PORT_A_data_out, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8 = R1_ram_block2a8_PORT_A_data_out_reg[0];

--R1M442Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT1
R1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a8_PORT_A_data_in_reg = DFFE(R1_ram_block2a8_PORT_A_data_in, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_data_in = ~GND;
R1_ram_block2a8_PORT_B_data_in_reg = DFFE(R1_ram_block2a8_PORT_B_data_in, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a8_PORT_A_address_reg = DFFE(R1_ram_block2a8_PORT_A_address, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a8_PORT_B_address_reg = DFFE(R1_ram_block2a8_PORT_B_address, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_write_enable = GND;
R1_ram_block2a8_PORT_A_write_enable_reg = DFFE(R1_ram_block2a8_PORT_A_write_enable, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_write_enable = GND;
R1_ram_block2a8_PORT_B_write_enable_reg = DFFE(R1_ram_block2a8_PORT_B_write_enable, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_clock_0 = M1__clk0;
R1_ram_block2a8_clock_1 = GND;
R1_ram_block2a8_clock_enable_0 = S3_w_anode2952w[3];
R1_ram_block2a8_clock_enable_1 = GND;
R1_ram_block2a8_PORT_A_data_out = MEMORY(R1_ram_block2a8_PORT_A_data_in_reg, R1_ram_block2a8_PORT_B_data_in_reg, R1_ram_block2a8_PORT_A_address_reg, R1_ram_block2a8_PORT_B_address_reg, R1_ram_block2a8_PORT_A_write_enable_reg, R1_ram_block2a8_PORT_B_write_enable_reg, , , R1_ram_block2a8_clock_0, R1_ram_block2a8_clock_1, R1_ram_block2a8_clock_enable_0, R1_ram_block2a8_clock_enable_1, , );
R1_ram_block2a8_PORT_A_data_out_reg = DFFE(R1_ram_block2a8_PORT_A_data_out, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1M442Q = R1_ram_block2a8_PORT_A_data_out_reg[1];

--R1M443Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT2
R1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a8_PORT_A_data_in_reg = DFFE(R1_ram_block2a8_PORT_A_data_in, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_data_in = ~GND;
R1_ram_block2a8_PORT_B_data_in_reg = DFFE(R1_ram_block2a8_PORT_B_data_in, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a8_PORT_A_address_reg = DFFE(R1_ram_block2a8_PORT_A_address, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a8_PORT_B_address_reg = DFFE(R1_ram_block2a8_PORT_B_address, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_write_enable = GND;
R1_ram_block2a8_PORT_A_write_enable_reg = DFFE(R1_ram_block2a8_PORT_A_write_enable, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_write_enable = GND;
R1_ram_block2a8_PORT_B_write_enable_reg = DFFE(R1_ram_block2a8_PORT_B_write_enable, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_clock_0 = M1__clk0;
R1_ram_block2a8_clock_1 = GND;
R1_ram_block2a8_clock_enable_0 = S3_w_anode2952w[3];
R1_ram_block2a8_clock_enable_1 = GND;
R1_ram_block2a8_PORT_A_data_out = MEMORY(R1_ram_block2a8_PORT_A_data_in_reg, R1_ram_block2a8_PORT_B_data_in_reg, R1_ram_block2a8_PORT_A_address_reg, R1_ram_block2a8_PORT_B_address_reg, R1_ram_block2a8_PORT_A_write_enable_reg, R1_ram_block2a8_PORT_B_write_enable_reg, , , R1_ram_block2a8_clock_0, R1_ram_block2a8_clock_1, R1_ram_block2a8_clock_enable_0, R1_ram_block2a8_clock_enable_1, , );
R1_ram_block2a8_PORT_A_data_out_reg = DFFE(R1_ram_block2a8_PORT_A_data_out, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1M443Q = R1_ram_block2a8_PORT_A_data_out_reg[2];

--R1M444Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT3
R1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a8_PORT_A_data_in_reg = DFFE(R1_ram_block2a8_PORT_A_data_in, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_data_in = ~GND;
R1_ram_block2a8_PORT_B_data_in_reg = DFFE(R1_ram_block2a8_PORT_B_data_in, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a8_PORT_A_address_reg = DFFE(R1_ram_block2a8_PORT_A_address, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a8_PORT_B_address_reg = DFFE(R1_ram_block2a8_PORT_B_address, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_write_enable = GND;
R1_ram_block2a8_PORT_A_write_enable_reg = DFFE(R1_ram_block2a8_PORT_A_write_enable, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_write_enable = GND;
R1_ram_block2a8_PORT_B_write_enable_reg = DFFE(R1_ram_block2a8_PORT_B_write_enable, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_clock_0 = M1__clk0;
R1_ram_block2a8_clock_1 = GND;
R1_ram_block2a8_clock_enable_0 = S3_w_anode2952w[3];
R1_ram_block2a8_clock_enable_1 = GND;
R1_ram_block2a8_PORT_A_data_out = MEMORY(R1_ram_block2a8_PORT_A_data_in_reg, R1_ram_block2a8_PORT_B_data_in_reg, R1_ram_block2a8_PORT_A_address_reg, R1_ram_block2a8_PORT_B_address_reg, R1_ram_block2a8_PORT_A_write_enable_reg, R1_ram_block2a8_PORT_B_write_enable_reg, , , R1_ram_block2a8_clock_0, R1_ram_block2a8_clock_1, R1_ram_block2a8_clock_enable_0, R1_ram_block2a8_clock_enable_1, , );
R1_ram_block2a8_PORT_A_data_out_reg = DFFE(R1_ram_block2a8_PORT_A_data_out, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1M444Q = R1_ram_block2a8_PORT_A_data_out_reg[3];

--R1M445Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT4
R1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a8_PORT_A_data_in_reg = DFFE(R1_ram_block2a8_PORT_A_data_in, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_data_in = ~GND;
R1_ram_block2a8_PORT_B_data_in_reg = DFFE(R1_ram_block2a8_PORT_B_data_in, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a8_PORT_A_address_reg = DFFE(R1_ram_block2a8_PORT_A_address, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a8_PORT_B_address_reg = DFFE(R1_ram_block2a8_PORT_B_address, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_write_enable = GND;
R1_ram_block2a8_PORT_A_write_enable_reg = DFFE(R1_ram_block2a8_PORT_A_write_enable, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_write_enable = GND;
R1_ram_block2a8_PORT_B_write_enable_reg = DFFE(R1_ram_block2a8_PORT_B_write_enable, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_clock_0 = M1__clk0;
R1_ram_block2a8_clock_1 = GND;
R1_ram_block2a8_clock_enable_0 = S3_w_anode2952w[3];
R1_ram_block2a8_clock_enable_1 = GND;
R1_ram_block2a8_PORT_A_data_out = MEMORY(R1_ram_block2a8_PORT_A_data_in_reg, R1_ram_block2a8_PORT_B_data_in_reg, R1_ram_block2a8_PORT_A_address_reg, R1_ram_block2a8_PORT_B_address_reg, R1_ram_block2a8_PORT_A_write_enable_reg, R1_ram_block2a8_PORT_B_write_enable_reg, , , R1_ram_block2a8_clock_0, R1_ram_block2a8_clock_1, R1_ram_block2a8_clock_enable_0, R1_ram_block2a8_clock_enable_1, , );
R1_ram_block2a8_PORT_A_data_out_reg = DFFE(R1_ram_block2a8_PORT_A_data_out, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1M445Q = R1_ram_block2a8_PORT_A_data_out_reg[4];

--R1M446Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT5
R1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a8_PORT_A_data_in_reg = DFFE(R1_ram_block2a8_PORT_A_data_in, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_data_in = ~GND;
R1_ram_block2a8_PORT_B_data_in_reg = DFFE(R1_ram_block2a8_PORT_B_data_in, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a8_PORT_A_address_reg = DFFE(R1_ram_block2a8_PORT_A_address, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a8_PORT_B_address_reg = DFFE(R1_ram_block2a8_PORT_B_address, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_write_enable = GND;
R1_ram_block2a8_PORT_A_write_enable_reg = DFFE(R1_ram_block2a8_PORT_A_write_enable, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_write_enable = GND;
R1_ram_block2a8_PORT_B_write_enable_reg = DFFE(R1_ram_block2a8_PORT_B_write_enable, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_clock_0 = M1__clk0;
R1_ram_block2a8_clock_1 = GND;
R1_ram_block2a8_clock_enable_0 = S3_w_anode2952w[3];
R1_ram_block2a8_clock_enable_1 = GND;
R1_ram_block2a8_PORT_A_data_out = MEMORY(R1_ram_block2a8_PORT_A_data_in_reg, R1_ram_block2a8_PORT_B_data_in_reg, R1_ram_block2a8_PORT_A_address_reg, R1_ram_block2a8_PORT_B_address_reg, R1_ram_block2a8_PORT_A_write_enable_reg, R1_ram_block2a8_PORT_B_write_enable_reg, , , R1_ram_block2a8_clock_0, R1_ram_block2a8_clock_1, R1_ram_block2a8_clock_enable_0, R1_ram_block2a8_clock_enable_1, , );
R1_ram_block2a8_PORT_A_data_out_reg = DFFE(R1_ram_block2a8_PORT_A_data_out, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1M446Q = R1_ram_block2a8_PORT_A_data_out_reg[5];

--R1M447Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT6
R1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a8_PORT_A_data_in_reg = DFFE(R1_ram_block2a8_PORT_A_data_in, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_data_in = ~GND;
R1_ram_block2a8_PORT_B_data_in_reg = DFFE(R1_ram_block2a8_PORT_B_data_in, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a8_PORT_A_address_reg = DFFE(R1_ram_block2a8_PORT_A_address, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a8_PORT_B_address_reg = DFFE(R1_ram_block2a8_PORT_B_address, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_write_enable = GND;
R1_ram_block2a8_PORT_A_write_enable_reg = DFFE(R1_ram_block2a8_PORT_A_write_enable, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_write_enable = GND;
R1_ram_block2a8_PORT_B_write_enable_reg = DFFE(R1_ram_block2a8_PORT_B_write_enable, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_clock_0 = M1__clk0;
R1_ram_block2a8_clock_1 = GND;
R1_ram_block2a8_clock_enable_0 = S3_w_anode2952w[3];
R1_ram_block2a8_clock_enable_1 = GND;
R1_ram_block2a8_PORT_A_data_out = MEMORY(R1_ram_block2a8_PORT_A_data_in_reg, R1_ram_block2a8_PORT_B_data_in_reg, R1_ram_block2a8_PORT_A_address_reg, R1_ram_block2a8_PORT_B_address_reg, R1_ram_block2a8_PORT_A_write_enable_reg, R1_ram_block2a8_PORT_B_write_enable_reg, , , R1_ram_block2a8_clock_0, R1_ram_block2a8_clock_1, R1_ram_block2a8_clock_enable_0, R1_ram_block2a8_clock_enable_1, , );
R1_ram_block2a8_PORT_A_data_out_reg = DFFE(R1_ram_block2a8_PORT_A_data_out, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1M447Q = R1_ram_block2a8_PORT_A_data_out_reg[6];

--R1M448Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT7
R1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a8_PORT_A_data_in_reg = DFFE(R1_ram_block2a8_PORT_A_data_in, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_data_in = ~GND;
R1_ram_block2a8_PORT_B_data_in_reg = DFFE(R1_ram_block2a8_PORT_B_data_in, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a8_PORT_A_address_reg = DFFE(R1_ram_block2a8_PORT_A_address, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a8_PORT_B_address_reg = DFFE(R1_ram_block2a8_PORT_B_address, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_write_enable = GND;
R1_ram_block2a8_PORT_A_write_enable_reg = DFFE(R1_ram_block2a8_PORT_A_write_enable, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_write_enable = GND;
R1_ram_block2a8_PORT_B_write_enable_reg = DFFE(R1_ram_block2a8_PORT_B_write_enable, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_clock_0 = M1__clk0;
R1_ram_block2a8_clock_1 = GND;
R1_ram_block2a8_clock_enable_0 = S3_w_anode2952w[3];
R1_ram_block2a8_clock_enable_1 = GND;
R1_ram_block2a8_PORT_A_data_out = MEMORY(R1_ram_block2a8_PORT_A_data_in_reg, R1_ram_block2a8_PORT_B_data_in_reg, R1_ram_block2a8_PORT_A_address_reg, R1_ram_block2a8_PORT_B_address_reg, R1_ram_block2a8_PORT_A_write_enable_reg, R1_ram_block2a8_PORT_B_write_enable_reg, , , R1_ram_block2a8_clock_0, R1_ram_block2a8_clock_1, R1_ram_block2a8_clock_enable_0, R1_ram_block2a8_clock_enable_1, , );
R1_ram_block2a8_PORT_A_data_out_reg = DFFE(R1_ram_block2a8_PORT_A_data_out, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1M448Q = R1_ram_block2a8_PORT_A_data_out_reg[7];


--T1L240 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~581
T1L240 = !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M546Q # !R1_address_reg_a[7] & (R1M446Q));


--R1_ram_block2a11 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a11_PORT_A_data_in_reg = DFFE(R1_ram_block2a11_PORT_A_data_in, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_data_in = ~GND;
R1_ram_block2a11_PORT_B_data_in_reg = DFFE(R1_ram_block2a11_PORT_B_data_in, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a11_PORT_A_address_reg = DFFE(R1_ram_block2a11_PORT_A_address, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a11_PORT_B_address_reg = DFFE(R1_ram_block2a11_PORT_B_address, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_write_enable = GND;
R1_ram_block2a11_PORT_A_write_enable_reg = DFFE(R1_ram_block2a11_PORT_A_write_enable, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_write_enable = GND;
R1_ram_block2a11_PORT_B_write_enable_reg = DFFE(R1_ram_block2a11_PORT_B_write_enable, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_clock_0 = M1__clk0;
R1_ram_block2a11_clock_1 = GND;
R1_ram_block2a11_clock_enable_0 = S3_w_anode2983w[3];
R1_ram_block2a11_clock_enable_1 = GND;
R1_ram_block2a11_PORT_A_data_out = MEMORY(R1_ram_block2a11_PORT_A_data_in_reg, R1_ram_block2a11_PORT_B_data_in_reg, R1_ram_block2a11_PORT_A_address_reg, R1_ram_block2a11_PORT_B_address_reg, R1_ram_block2a11_PORT_A_write_enable_reg, R1_ram_block2a11_PORT_B_write_enable_reg, , , R1_ram_block2a11_clock_0, R1_ram_block2a11_clock_1, R1_ram_block2a11_clock_enable_0, R1_ram_block2a11_clock_enable_1, , );
R1_ram_block2a11_PORT_A_data_out_reg = DFFE(R1_ram_block2a11_PORT_A_data_out, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11 = R1_ram_block2a11_PORT_A_data_out_reg[0];

--R1M592Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT1
R1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a11_PORT_A_data_in_reg = DFFE(R1_ram_block2a11_PORT_A_data_in, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_data_in = ~GND;
R1_ram_block2a11_PORT_B_data_in_reg = DFFE(R1_ram_block2a11_PORT_B_data_in, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a11_PORT_A_address_reg = DFFE(R1_ram_block2a11_PORT_A_address, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a11_PORT_B_address_reg = DFFE(R1_ram_block2a11_PORT_B_address, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_write_enable = GND;
R1_ram_block2a11_PORT_A_write_enable_reg = DFFE(R1_ram_block2a11_PORT_A_write_enable, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_write_enable = GND;
R1_ram_block2a11_PORT_B_write_enable_reg = DFFE(R1_ram_block2a11_PORT_B_write_enable, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_clock_0 = M1__clk0;
R1_ram_block2a11_clock_1 = GND;
R1_ram_block2a11_clock_enable_0 = S3_w_anode2983w[3];
R1_ram_block2a11_clock_enable_1 = GND;
R1_ram_block2a11_PORT_A_data_out = MEMORY(R1_ram_block2a11_PORT_A_data_in_reg, R1_ram_block2a11_PORT_B_data_in_reg, R1_ram_block2a11_PORT_A_address_reg, R1_ram_block2a11_PORT_B_address_reg, R1_ram_block2a11_PORT_A_write_enable_reg, R1_ram_block2a11_PORT_B_write_enable_reg, , , R1_ram_block2a11_clock_0, R1_ram_block2a11_clock_1, R1_ram_block2a11_clock_enable_0, R1_ram_block2a11_clock_enable_1, , );
R1_ram_block2a11_PORT_A_data_out_reg = DFFE(R1_ram_block2a11_PORT_A_data_out, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1M592Q = R1_ram_block2a11_PORT_A_data_out_reg[1];

--R1M593Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT2
R1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a11_PORT_A_data_in_reg = DFFE(R1_ram_block2a11_PORT_A_data_in, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_data_in = ~GND;
R1_ram_block2a11_PORT_B_data_in_reg = DFFE(R1_ram_block2a11_PORT_B_data_in, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a11_PORT_A_address_reg = DFFE(R1_ram_block2a11_PORT_A_address, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a11_PORT_B_address_reg = DFFE(R1_ram_block2a11_PORT_B_address, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_write_enable = GND;
R1_ram_block2a11_PORT_A_write_enable_reg = DFFE(R1_ram_block2a11_PORT_A_write_enable, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_write_enable = GND;
R1_ram_block2a11_PORT_B_write_enable_reg = DFFE(R1_ram_block2a11_PORT_B_write_enable, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_clock_0 = M1__clk0;
R1_ram_block2a11_clock_1 = GND;
R1_ram_block2a11_clock_enable_0 = S3_w_anode2983w[3];
R1_ram_block2a11_clock_enable_1 = GND;
R1_ram_block2a11_PORT_A_data_out = MEMORY(R1_ram_block2a11_PORT_A_data_in_reg, R1_ram_block2a11_PORT_B_data_in_reg, R1_ram_block2a11_PORT_A_address_reg, R1_ram_block2a11_PORT_B_address_reg, R1_ram_block2a11_PORT_A_write_enable_reg, R1_ram_block2a11_PORT_B_write_enable_reg, , , R1_ram_block2a11_clock_0, R1_ram_block2a11_clock_1, R1_ram_block2a11_clock_enable_0, R1_ram_block2a11_clock_enable_1, , );
R1_ram_block2a11_PORT_A_data_out_reg = DFFE(R1_ram_block2a11_PORT_A_data_out, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1M593Q = R1_ram_block2a11_PORT_A_data_out_reg[2];

--R1M594Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT3
R1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a11_PORT_A_data_in_reg = DFFE(R1_ram_block2a11_PORT_A_data_in, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_data_in = ~GND;
R1_ram_block2a11_PORT_B_data_in_reg = DFFE(R1_ram_block2a11_PORT_B_data_in, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a11_PORT_A_address_reg = DFFE(R1_ram_block2a11_PORT_A_address, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a11_PORT_B_address_reg = DFFE(R1_ram_block2a11_PORT_B_address, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_write_enable = GND;
R1_ram_block2a11_PORT_A_write_enable_reg = DFFE(R1_ram_block2a11_PORT_A_write_enable, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_write_enable = GND;
R1_ram_block2a11_PORT_B_write_enable_reg = DFFE(R1_ram_block2a11_PORT_B_write_enable, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_clock_0 = M1__clk0;
R1_ram_block2a11_clock_1 = GND;
R1_ram_block2a11_clock_enable_0 = S3_w_anode2983w[3];
R1_ram_block2a11_clock_enable_1 = GND;
R1_ram_block2a11_PORT_A_data_out = MEMORY(R1_ram_block2a11_PORT_A_data_in_reg, R1_ram_block2a11_PORT_B_data_in_reg, R1_ram_block2a11_PORT_A_address_reg, R1_ram_block2a11_PORT_B_address_reg, R1_ram_block2a11_PORT_A_write_enable_reg, R1_ram_block2a11_PORT_B_write_enable_reg, , , R1_ram_block2a11_clock_0, R1_ram_block2a11_clock_1, R1_ram_block2a11_clock_enable_0, R1_ram_block2a11_clock_enable_1, , );
R1_ram_block2a11_PORT_A_data_out_reg = DFFE(R1_ram_block2a11_PORT_A_data_out, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1M594Q = R1_ram_block2a11_PORT_A_data_out_reg[3];

--R1M595Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT4
R1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a11_PORT_A_data_in_reg = DFFE(R1_ram_block2a11_PORT_A_data_in, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_data_in = ~GND;
R1_ram_block2a11_PORT_B_data_in_reg = DFFE(R1_ram_block2a11_PORT_B_data_in, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a11_PORT_A_address_reg = DFFE(R1_ram_block2a11_PORT_A_address, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a11_PORT_B_address_reg = DFFE(R1_ram_block2a11_PORT_B_address, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_write_enable = GND;
R1_ram_block2a11_PORT_A_write_enable_reg = DFFE(R1_ram_block2a11_PORT_A_write_enable, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_write_enable = GND;
R1_ram_block2a11_PORT_B_write_enable_reg = DFFE(R1_ram_block2a11_PORT_B_write_enable, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_clock_0 = M1__clk0;
R1_ram_block2a11_clock_1 = GND;
R1_ram_block2a11_clock_enable_0 = S3_w_anode2983w[3];
R1_ram_block2a11_clock_enable_1 = GND;
R1_ram_block2a11_PORT_A_data_out = MEMORY(R1_ram_block2a11_PORT_A_data_in_reg, R1_ram_block2a11_PORT_B_data_in_reg, R1_ram_block2a11_PORT_A_address_reg, R1_ram_block2a11_PORT_B_address_reg, R1_ram_block2a11_PORT_A_write_enable_reg, R1_ram_block2a11_PORT_B_write_enable_reg, , , R1_ram_block2a11_clock_0, R1_ram_block2a11_clock_1, R1_ram_block2a11_clock_enable_0, R1_ram_block2a11_clock_enable_1, , );
R1_ram_block2a11_PORT_A_data_out_reg = DFFE(R1_ram_block2a11_PORT_A_data_out, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1M595Q = R1_ram_block2a11_PORT_A_data_out_reg[4];

--R1M596Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT5
R1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a11_PORT_A_data_in_reg = DFFE(R1_ram_block2a11_PORT_A_data_in, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_data_in = ~GND;
R1_ram_block2a11_PORT_B_data_in_reg = DFFE(R1_ram_block2a11_PORT_B_data_in, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a11_PORT_A_address_reg = DFFE(R1_ram_block2a11_PORT_A_address, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a11_PORT_B_address_reg = DFFE(R1_ram_block2a11_PORT_B_address, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_write_enable = GND;
R1_ram_block2a11_PORT_A_write_enable_reg = DFFE(R1_ram_block2a11_PORT_A_write_enable, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_write_enable = GND;
R1_ram_block2a11_PORT_B_write_enable_reg = DFFE(R1_ram_block2a11_PORT_B_write_enable, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_clock_0 = M1__clk0;
R1_ram_block2a11_clock_1 = GND;
R1_ram_block2a11_clock_enable_0 = S3_w_anode2983w[3];
R1_ram_block2a11_clock_enable_1 = GND;
R1_ram_block2a11_PORT_A_data_out = MEMORY(R1_ram_block2a11_PORT_A_data_in_reg, R1_ram_block2a11_PORT_B_data_in_reg, R1_ram_block2a11_PORT_A_address_reg, R1_ram_block2a11_PORT_B_address_reg, R1_ram_block2a11_PORT_A_write_enable_reg, R1_ram_block2a11_PORT_B_write_enable_reg, , , R1_ram_block2a11_clock_0, R1_ram_block2a11_clock_1, R1_ram_block2a11_clock_enable_0, R1_ram_block2a11_clock_enable_1, , );
R1_ram_block2a11_PORT_A_data_out_reg = DFFE(R1_ram_block2a11_PORT_A_data_out, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1M596Q = R1_ram_block2a11_PORT_A_data_out_reg[5];

--R1M597Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT6
R1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a11_PORT_A_data_in_reg = DFFE(R1_ram_block2a11_PORT_A_data_in, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_data_in = ~GND;
R1_ram_block2a11_PORT_B_data_in_reg = DFFE(R1_ram_block2a11_PORT_B_data_in, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a11_PORT_A_address_reg = DFFE(R1_ram_block2a11_PORT_A_address, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a11_PORT_B_address_reg = DFFE(R1_ram_block2a11_PORT_B_address, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_write_enable = GND;
R1_ram_block2a11_PORT_A_write_enable_reg = DFFE(R1_ram_block2a11_PORT_A_write_enable, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_write_enable = GND;
R1_ram_block2a11_PORT_B_write_enable_reg = DFFE(R1_ram_block2a11_PORT_B_write_enable, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_clock_0 = M1__clk0;
R1_ram_block2a11_clock_1 = GND;
R1_ram_block2a11_clock_enable_0 = S3_w_anode2983w[3];
R1_ram_block2a11_clock_enable_1 = GND;
R1_ram_block2a11_PORT_A_data_out = MEMORY(R1_ram_block2a11_PORT_A_data_in_reg, R1_ram_block2a11_PORT_B_data_in_reg, R1_ram_block2a11_PORT_A_address_reg, R1_ram_block2a11_PORT_B_address_reg, R1_ram_block2a11_PORT_A_write_enable_reg, R1_ram_block2a11_PORT_B_write_enable_reg, , , R1_ram_block2a11_clock_0, R1_ram_block2a11_clock_1, R1_ram_block2a11_clock_enable_0, R1_ram_block2a11_clock_enable_1, , );
R1_ram_block2a11_PORT_A_data_out_reg = DFFE(R1_ram_block2a11_PORT_A_data_out, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1M597Q = R1_ram_block2a11_PORT_A_data_out_reg[6];

--R1M598Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT7
R1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a11_PORT_A_data_in_reg = DFFE(R1_ram_block2a11_PORT_A_data_in, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_data_in = ~GND;
R1_ram_block2a11_PORT_B_data_in_reg = DFFE(R1_ram_block2a11_PORT_B_data_in, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a11_PORT_A_address_reg = DFFE(R1_ram_block2a11_PORT_A_address, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a11_PORT_B_address_reg = DFFE(R1_ram_block2a11_PORT_B_address, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_write_enable = GND;
R1_ram_block2a11_PORT_A_write_enable_reg = DFFE(R1_ram_block2a11_PORT_A_write_enable, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_write_enable = GND;
R1_ram_block2a11_PORT_B_write_enable_reg = DFFE(R1_ram_block2a11_PORT_B_write_enable, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_clock_0 = M1__clk0;
R1_ram_block2a11_clock_1 = GND;
R1_ram_block2a11_clock_enable_0 = S3_w_anode2983w[3];
R1_ram_block2a11_clock_enable_1 = GND;
R1_ram_block2a11_PORT_A_data_out = MEMORY(R1_ram_block2a11_PORT_A_data_in_reg, R1_ram_block2a11_PORT_B_data_in_reg, R1_ram_block2a11_PORT_A_address_reg, R1_ram_block2a11_PORT_B_address_reg, R1_ram_block2a11_PORT_A_write_enable_reg, R1_ram_block2a11_PORT_B_write_enable_reg, , , R1_ram_block2a11_clock_0, R1_ram_block2a11_clock_1, R1_ram_block2a11_clock_enable_0, R1_ram_block2a11_clock_enable_1, , );
R1_ram_block2a11_PORT_A_data_out_reg = DFFE(R1_ram_block2a11_PORT_A_data_out, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1M598Q = R1_ram_block2a11_PORT_A_data_out_reg[7];


--R1_ram_block2a9 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a9_PORT_A_data_in_reg = DFFE(R1_ram_block2a9_PORT_A_data_in, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_data_in = ~GND;
R1_ram_block2a9_PORT_B_data_in_reg = DFFE(R1_ram_block2a9_PORT_B_data_in, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a9_PORT_A_address_reg = DFFE(R1_ram_block2a9_PORT_A_address, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a9_PORT_B_address_reg = DFFE(R1_ram_block2a9_PORT_B_address, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_write_enable = GND;
R1_ram_block2a9_PORT_A_write_enable_reg = DFFE(R1_ram_block2a9_PORT_A_write_enable, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_write_enable = GND;
R1_ram_block2a9_PORT_B_write_enable_reg = DFFE(R1_ram_block2a9_PORT_B_write_enable, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_clock_0 = M1__clk0;
R1_ram_block2a9_clock_1 = GND;
R1_ram_block2a9_clock_enable_0 = S3_w_anode2963w[3];
R1_ram_block2a9_clock_enable_1 = GND;
R1_ram_block2a9_PORT_A_data_out = MEMORY(R1_ram_block2a9_PORT_A_data_in_reg, R1_ram_block2a9_PORT_B_data_in_reg, R1_ram_block2a9_PORT_A_address_reg, R1_ram_block2a9_PORT_B_address_reg, R1_ram_block2a9_PORT_A_write_enable_reg, R1_ram_block2a9_PORT_B_write_enable_reg, , , R1_ram_block2a9_clock_0, R1_ram_block2a9_clock_1, R1_ram_block2a9_clock_enable_0, R1_ram_block2a9_clock_enable_1, , );
R1_ram_block2a9_PORT_A_data_out_reg = DFFE(R1_ram_block2a9_PORT_A_data_out, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9 = R1_ram_block2a9_PORT_A_data_out_reg[0];

--R1M492Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT1
R1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a9_PORT_A_data_in_reg = DFFE(R1_ram_block2a9_PORT_A_data_in, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_data_in = ~GND;
R1_ram_block2a9_PORT_B_data_in_reg = DFFE(R1_ram_block2a9_PORT_B_data_in, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a9_PORT_A_address_reg = DFFE(R1_ram_block2a9_PORT_A_address, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a9_PORT_B_address_reg = DFFE(R1_ram_block2a9_PORT_B_address, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_write_enable = GND;
R1_ram_block2a9_PORT_A_write_enable_reg = DFFE(R1_ram_block2a9_PORT_A_write_enable, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_write_enable = GND;
R1_ram_block2a9_PORT_B_write_enable_reg = DFFE(R1_ram_block2a9_PORT_B_write_enable, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_clock_0 = M1__clk0;
R1_ram_block2a9_clock_1 = GND;
R1_ram_block2a9_clock_enable_0 = S3_w_anode2963w[3];
R1_ram_block2a9_clock_enable_1 = GND;
R1_ram_block2a9_PORT_A_data_out = MEMORY(R1_ram_block2a9_PORT_A_data_in_reg, R1_ram_block2a9_PORT_B_data_in_reg, R1_ram_block2a9_PORT_A_address_reg, R1_ram_block2a9_PORT_B_address_reg, R1_ram_block2a9_PORT_A_write_enable_reg, R1_ram_block2a9_PORT_B_write_enable_reg, , , R1_ram_block2a9_clock_0, R1_ram_block2a9_clock_1, R1_ram_block2a9_clock_enable_0, R1_ram_block2a9_clock_enable_1, , );
R1_ram_block2a9_PORT_A_data_out_reg = DFFE(R1_ram_block2a9_PORT_A_data_out, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1M492Q = R1_ram_block2a9_PORT_A_data_out_reg[1];

--R1M493Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT2
R1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a9_PORT_A_data_in_reg = DFFE(R1_ram_block2a9_PORT_A_data_in, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_data_in = ~GND;
R1_ram_block2a9_PORT_B_data_in_reg = DFFE(R1_ram_block2a9_PORT_B_data_in, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a9_PORT_A_address_reg = DFFE(R1_ram_block2a9_PORT_A_address, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a9_PORT_B_address_reg = DFFE(R1_ram_block2a9_PORT_B_address, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_write_enable = GND;
R1_ram_block2a9_PORT_A_write_enable_reg = DFFE(R1_ram_block2a9_PORT_A_write_enable, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_write_enable = GND;
R1_ram_block2a9_PORT_B_write_enable_reg = DFFE(R1_ram_block2a9_PORT_B_write_enable, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_clock_0 = M1__clk0;
R1_ram_block2a9_clock_1 = GND;
R1_ram_block2a9_clock_enable_0 = S3_w_anode2963w[3];
R1_ram_block2a9_clock_enable_1 = GND;
R1_ram_block2a9_PORT_A_data_out = MEMORY(R1_ram_block2a9_PORT_A_data_in_reg, R1_ram_block2a9_PORT_B_data_in_reg, R1_ram_block2a9_PORT_A_address_reg, R1_ram_block2a9_PORT_B_address_reg, R1_ram_block2a9_PORT_A_write_enable_reg, R1_ram_block2a9_PORT_B_write_enable_reg, , , R1_ram_block2a9_clock_0, R1_ram_block2a9_clock_1, R1_ram_block2a9_clock_enable_0, R1_ram_block2a9_clock_enable_1, , );
R1_ram_block2a9_PORT_A_data_out_reg = DFFE(R1_ram_block2a9_PORT_A_data_out, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1M493Q = R1_ram_block2a9_PORT_A_data_out_reg[2];

--R1M494Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT3
R1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a9_PORT_A_data_in_reg = DFFE(R1_ram_block2a9_PORT_A_data_in, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_data_in = ~GND;
R1_ram_block2a9_PORT_B_data_in_reg = DFFE(R1_ram_block2a9_PORT_B_data_in, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a9_PORT_A_address_reg = DFFE(R1_ram_block2a9_PORT_A_address, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a9_PORT_B_address_reg = DFFE(R1_ram_block2a9_PORT_B_address, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_write_enable = GND;
R1_ram_block2a9_PORT_A_write_enable_reg = DFFE(R1_ram_block2a9_PORT_A_write_enable, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_write_enable = GND;
R1_ram_block2a9_PORT_B_write_enable_reg = DFFE(R1_ram_block2a9_PORT_B_write_enable, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_clock_0 = M1__clk0;
R1_ram_block2a9_clock_1 = GND;
R1_ram_block2a9_clock_enable_0 = S3_w_anode2963w[3];
R1_ram_block2a9_clock_enable_1 = GND;
R1_ram_block2a9_PORT_A_data_out = MEMORY(R1_ram_block2a9_PORT_A_data_in_reg, R1_ram_block2a9_PORT_B_data_in_reg, R1_ram_block2a9_PORT_A_address_reg, R1_ram_block2a9_PORT_B_address_reg, R1_ram_block2a9_PORT_A_write_enable_reg, R1_ram_block2a9_PORT_B_write_enable_reg, , , R1_ram_block2a9_clock_0, R1_ram_block2a9_clock_1, R1_ram_block2a9_clock_enable_0, R1_ram_block2a9_clock_enable_1, , );
R1_ram_block2a9_PORT_A_data_out_reg = DFFE(R1_ram_block2a9_PORT_A_data_out, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1M494Q = R1_ram_block2a9_PORT_A_data_out_reg[3];

--R1M495Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT4
R1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a9_PORT_A_data_in_reg = DFFE(R1_ram_block2a9_PORT_A_data_in, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_data_in = ~GND;
R1_ram_block2a9_PORT_B_data_in_reg = DFFE(R1_ram_block2a9_PORT_B_data_in, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a9_PORT_A_address_reg = DFFE(R1_ram_block2a9_PORT_A_address, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a9_PORT_B_address_reg = DFFE(R1_ram_block2a9_PORT_B_address, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_write_enable = GND;
R1_ram_block2a9_PORT_A_write_enable_reg = DFFE(R1_ram_block2a9_PORT_A_write_enable, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_write_enable = GND;
R1_ram_block2a9_PORT_B_write_enable_reg = DFFE(R1_ram_block2a9_PORT_B_write_enable, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_clock_0 = M1__clk0;
R1_ram_block2a9_clock_1 = GND;
R1_ram_block2a9_clock_enable_0 = S3_w_anode2963w[3];
R1_ram_block2a9_clock_enable_1 = GND;
R1_ram_block2a9_PORT_A_data_out = MEMORY(R1_ram_block2a9_PORT_A_data_in_reg, R1_ram_block2a9_PORT_B_data_in_reg, R1_ram_block2a9_PORT_A_address_reg, R1_ram_block2a9_PORT_B_address_reg, R1_ram_block2a9_PORT_A_write_enable_reg, R1_ram_block2a9_PORT_B_write_enable_reg, , , R1_ram_block2a9_clock_0, R1_ram_block2a9_clock_1, R1_ram_block2a9_clock_enable_0, R1_ram_block2a9_clock_enable_1, , );
R1_ram_block2a9_PORT_A_data_out_reg = DFFE(R1_ram_block2a9_PORT_A_data_out, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1M495Q = R1_ram_block2a9_PORT_A_data_out_reg[4];

--R1M496Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT5
R1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a9_PORT_A_data_in_reg = DFFE(R1_ram_block2a9_PORT_A_data_in, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_data_in = ~GND;
R1_ram_block2a9_PORT_B_data_in_reg = DFFE(R1_ram_block2a9_PORT_B_data_in, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a9_PORT_A_address_reg = DFFE(R1_ram_block2a9_PORT_A_address, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a9_PORT_B_address_reg = DFFE(R1_ram_block2a9_PORT_B_address, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_write_enable = GND;
R1_ram_block2a9_PORT_A_write_enable_reg = DFFE(R1_ram_block2a9_PORT_A_write_enable, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_write_enable = GND;
R1_ram_block2a9_PORT_B_write_enable_reg = DFFE(R1_ram_block2a9_PORT_B_write_enable, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_clock_0 = M1__clk0;
R1_ram_block2a9_clock_1 = GND;
R1_ram_block2a9_clock_enable_0 = S3_w_anode2963w[3];
R1_ram_block2a9_clock_enable_1 = GND;
R1_ram_block2a9_PORT_A_data_out = MEMORY(R1_ram_block2a9_PORT_A_data_in_reg, R1_ram_block2a9_PORT_B_data_in_reg, R1_ram_block2a9_PORT_A_address_reg, R1_ram_block2a9_PORT_B_address_reg, R1_ram_block2a9_PORT_A_write_enable_reg, R1_ram_block2a9_PORT_B_write_enable_reg, , , R1_ram_block2a9_clock_0, R1_ram_block2a9_clock_1, R1_ram_block2a9_clock_enable_0, R1_ram_block2a9_clock_enable_1, , );
R1_ram_block2a9_PORT_A_data_out_reg = DFFE(R1_ram_block2a9_PORT_A_data_out, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1M496Q = R1_ram_block2a9_PORT_A_data_out_reg[5];

--R1M497Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT6
R1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a9_PORT_A_data_in_reg = DFFE(R1_ram_block2a9_PORT_A_data_in, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_data_in = ~GND;
R1_ram_block2a9_PORT_B_data_in_reg = DFFE(R1_ram_block2a9_PORT_B_data_in, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a9_PORT_A_address_reg = DFFE(R1_ram_block2a9_PORT_A_address, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a9_PORT_B_address_reg = DFFE(R1_ram_block2a9_PORT_B_address, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_write_enable = GND;
R1_ram_block2a9_PORT_A_write_enable_reg = DFFE(R1_ram_block2a9_PORT_A_write_enable, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_write_enable = GND;
R1_ram_block2a9_PORT_B_write_enable_reg = DFFE(R1_ram_block2a9_PORT_B_write_enable, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_clock_0 = M1__clk0;
R1_ram_block2a9_clock_1 = GND;
R1_ram_block2a9_clock_enable_0 = S3_w_anode2963w[3];
R1_ram_block2a9_clock_enable_1 = GND;
R1_ram_block2a9_PORT_A_data_out = MEMORY(R1_ram_block2a9_PORT_A_data_in_reg, R1_ram_block2a9_PORT_B_data_in_reg, R1_ram_block2a9_PORT_A_address_reg, R1_ram_block2a9_PORT_B_address_reg, R1_ram_block2a9_PORT_A_write_enable_reg, R1_ram_block2a9_PORT_B_write_enable_reg, , , R1_ram_block2a9_clock_0, R1_ram_block2a9_clock_1, R1_ram_block2a9_clock_enable_0, R1_ram_block2a9_clock_enable_1, , );
R1_ram_block2a9_PORT_A_data_out_reg = DFFE(R1_ram_block2a9_PORT_A_data_out, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1M497Q = R1_ram_block2a9_PORT_A_data_out_reg[6];

--R1M498Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT7
R1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a9_PORT_A_data_in_reg = DFFE(R1_ram_block2a9_PORT_A_data_in, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_data_in = ~GND;
R1_ram_block2a9_PORT_B_data_in_reg = DFFE(R1_ram_block2a9_PORT_B_data_in, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_address = BUS(H1L104, H1L106, H1L108, H1L110, H1L112, H1L114, H1L116, H1L118, H1L120);
R1_ram_block2a9_PORT_A_address_reg = DFFE(R1_ram_block2a9_PORT_A_address, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a9_PORT_B_address_reg = DFFE(R1_ram_block2a9_PORT_B_address, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_write_enable = GND;
R1_ram_block2a9_PORT_A_write_enable_reg = DFFE(R1_ram_block2a9_PORT_A_write_enable, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_write_enable = GND;
R1_ram_block2a9_PORT_B_write_enable_reg = DFFE(R1_ram_block2a9_PORT_B_write_enable, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_clock_0 = M1__clk0;
R1_ram_block2a9_clock_1 = GND;
R1_ram_block2a9_clock_enable_0 = S3_w_anode2963w[3];
R1_ram_block2a9_clock_enable_1 = GND;
R1_ram_block2a9_PORT_A_data_out = MEMORY(R1_ram_block2a9_PORT_A_data_in_reg, R1_ram_block2a9_PORT_B_data_in_reg, R1_ram_block2a9_PORT_A_address_reg, R1_ram_block2a9_PORT_B_address_reg, R1_ram_block2a9_PORT_A_write_enable_reg, R1_ram_block2a9_PORT_B_write_enable_reg, , , R1_ram_block2a9_clock_0, R1_ram_block2a9_clock_1, R1_ram_block2a9_clock_enable_0, R1_ram_block2a9_clock_enable_1, , );
R1_ram_block2a9_PORT_A_data_out_reg = DFFE(R1_ram_block2a9_PORT_A_data_out, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1M498Q = R1_ram_block2a9_PORT_A_data_out_reg[7];


--T1L241 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~582
T1L241 = R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M596Q # !R1_address_reg_a[7] & (R1M496Q));


--T1L242 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~583
T1L242 = R1_address_reg_a[11] & T1L239 # !R1_address_reg_a[11] & (T1L240 # T1L241);


--T1L243 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~584
T1L243 = R1_address_reg_a[9] & !R1_address_reg_a[10] & !R1_address_reg_a[8];


--T1L244 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~585
T1L244 = T1L235 # T1L237 # T1L242 & T1L243;


--T1L54 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5039
T1L54 = T1L244 & (T1L48 # !R1_address_reg_a[10]) # !T1L244 & (T1L53 & R1_address_reg_a[10]);


--H1_ADDR_dd[0] is VGA_OSD_RAM:u6|ADDR_dd[0]
H1_ADDR_dd[0] = DFFEAS(H1L7, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--T1L55 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5040
T1L55 = R1_address_reg_a[8] & !R1_address_reg_a[7] # !R1_address_reg_a[8] & R1_address_reg_a[7] & R1M2547Q;


--T1L56 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5041
T1L56 = R1_address_reg_a[6] & (R1M2497Q # R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1M2447Q & !R1_address_reg_a[7]);


--T1L57 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5042
T1L57 = !R1_address_reg_a[9] & (T1L55 & R1_address_reg_a[7] & !T1L56 # !T1L55 & !R1_address_reg_a[7] & T1L56);


--T1L253 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7024w~49
T1L253 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M1547Q # !R1_address_reg_a[7] & (R1M1447Q));


--T1L254 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7024w~50
T1L254 = R1_address_reg_a[6] & (T1L253 & (R1M1597Q) # !T1L253 & R1M1497Q) # !R1_address_reg_a[6] & (T1L253);


--T1L251 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7022w~44
T1L251 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1097Q # !R1_address_reg_a[6] & (R1M1047Q));


--T1L252 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7022w~45
T1L252 = R1_address_reg_a[7] & (T1L251 & (R1M1197Q) # !T1L251 & R1M1147Q) # !R1_address_reg_a[7] & (T1L251);


--T1L58 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5043
T1L58 = R1_address_reg_a[9] & T1L254 # !R1_address_reg_a[9] & (T1L252);


--T1L255 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7106w~407
T1L255 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M897Q # !R1_address_reg_a[6] & (R1M847Q));


--T1L256 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7106w~408
T1L256 = R1_address_reg_a[7] & (T1L255 & (R1M997Q) # !T1L255 & R1M947Q) # !R1_address_reg_a[7] & (T1L255);


--T1L59 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5044
T1L59 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1397Q # !R1_address_reg_a[6] & (R1M1347Q));


--T1L60 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5045
T1L60 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1297Q # !R1_address_reg_a[6] & (R1M1247Q));


--T1L61 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5046
T1L61 = R1_address_reg_a[9] & (T1L59 # T1L60) # !R1_address_reg_a[9] & T1L256;


--T1L62 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5047
T1L62 = R1_address_reg_a[8] & T1L58 # !R1_address_reg_a[8] & (T1L61);


--T1L259 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7122w~47
T1L259 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M2347Q # !R1_address_reg_a[7] & (R1M2247Q));


--T1L260 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7122w~48
T1L260 = R1_address_reg_a[6] & (T1L259 & (R1M2397Q) # !T1L259 & R1M2297Q) # !R1_address_reg_a[6] & (T1L259);


--T1L247 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6921w~47
T1L247 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M697Q # !R1_address_reg_a[6] & (R1M647Q));


--T1L248 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6921w~48
T1L248 = R1_address_reg_a[7] & (T1L247 & (R1M797Q) # !T1L247 & R1M747Q) # !R1_address_reg_a[7] & (T1L247);


--T1L263 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~566
T1L263 = R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L260 # !R1_address_reg_a[11] & (T1L248));


--T1L257 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7120w~44
T1L257 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1897Q # !R1_address_reg_a[6] & (R1M1847Q));


--T1L258 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7120w~45
T1L258 = R1_address_reg_a[7] & (T1L257 & (R1M1997Q) # !T1L257 & R1M1947Q) # !R1_address_reg_a[7] & (T1L257);


--T1L245 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6919w~44
T1L245 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M347Q # !R1_address_reg_a[7] & (R1M247Q));


--T1L246 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6919w~45
T1L246 = R1_address_reg_a[6] & (T1L245 & (R1M397Q) # !T1L245 & R1M297Q) # !R1_address_reg_a[6] & (T1L245);


--T1L264 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~567
T1L264 = !R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L258 # !R1_address_reg_a[11] & (T1L246));


--T1L265 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~568
T1L265 = T1L147 # T1L232 & (T1L263 # T1L264);


--T1L261 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7204w~281
T1L261 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1697Q # !R1_address_reg_a[6] & (R1M1647Q));


--T1L262 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7204w~282
T1L262 = R1_address_reg_a[7] & (T1L261 & (R1M1797Q) # !T1L261 & R1M1747Q) # !R1_address_reg_a[7] & (T1L261);


--T1L249 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7004w~281
T1L249 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M147Q # !R1_address_reg_a[7] & (R1M47Q));


--T1L250 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7004w~282
T1L250 = R1_address_reg_a[6] & (T1L249 & (R1M197Q) # !T1L249 & R1M97Q) # !R1_address_reg_a[6] & (T1L249);


--T1L266 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~569
T1L266 = T1L236 & (R1_address_reg_a[11] & T1L262 # !R1_address_reg_a[11] & (T1L250));


--T1L267 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~570
T1L267 = R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M2197Q # !R1_address_reg_a[7] & (R1M2097Q)) # !R1_address_reg_a[6] & (R1_address_reg_a[7]);


--T1L268 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~571
T1L268 = R1_address_reg_a[6] & (T1L267) # !R1_address_reg_a[6] & (T1L267 & R1M2147Q # !T1L267 & (R1M2047Q));


--T1L269 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~572
T1L269 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M497Q # !R1_address_reg_a[6] & (R1M447Q));


--T1L270 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~573
T1L270 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M597Q # !R1_address_reg_a[6] & (R1M547Q));


--T1L271 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~574
T1L271 = R1_address_reg_a[11] & T1L268 # !R1_address_reg_a[11] & (T1L269 # T1L270);


--T1L272 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~575
T1L272 = T1L265 # T1L266 # T1L243 & T1L271;


--T1L63 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5048
T1L63 = T1L272 & (T1L57 # !R1_address_reg_a[10]) # !T1L272 & (T1L62 & R1_address_reg_a[10]);


--H1_ADDR_dd[1] is VGA_OSD_RAM:u6|ADDR_dd[1]
H1_ADDR_dd[1] = DFFEAS(H1L9, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--T1L37 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5049
T1L37 = R1_address_reg_a[8] & !R1_address_reg_a[7] # !R1_address_reg_a[8] & R1_address_reg_a[7] & R1M2545Q;


--T1L38 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5050
T1L38 = R1_address_reg_a[6] & (R1M2495Q # R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1M2445Q & !R1_address_reg_a[7]);


--T1L39 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5051
T1L39 = !R1_address_reg_a[9] & (T1L37 & R1_address_reg_a[7] & !T1L38 # !T1L37 & !R1_address_reg_a[7] & T1L38);


--T1L194 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5962w~49
T1L194 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M1545Q # !R1_address_reg_a[7] & (R1M1445Q));


--T1L195 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5962w~50
T1L195 = R1_address_reg_a[6] & (T1L194 & (R1M1595Q) # !T1L194 & R1M1495Q) # !R1_address_reg_a[6] & (T1L194);


--T1L192 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5960w~44
T1L192 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1095Q # !R1_address_reg_a[6] & (R1M1045Q));


--T1L193 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5960w~45
T1L193 = R1_address_reg_a[7] & (T1L192 & (R1M1195Q) # !T1L192 & R1M1145Q) # !R1_address_reg_a[7] & (T1L192);


--T1L40 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5052
T1L40 = R1_address_reg_a[9] & T1L195 # !R1_address_reg_a[9] & (T1L193);


--T1L196 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6044w~407
T1L196 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M895Q # !R1_address_reg_a[6] & (R1M845Q));


--T1L197 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6044w~408
T1L197 = R1_address_reg_a[7] & (T1L196 & (R1M995Q) # !T1L196 & R1M945Q) # !R1_address_reg_a[7] & (T1L196);


--T1L41 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5053
T1L41 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1395Q # !R1_address_reg_a[6] & (R1M1345Q));


--T1L42 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5054
T1L42 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1295Q # !R1_address_reg_a[6] & (R1M1245Q));


--T1L43 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5055
T1L43 = R1_address_reg_a[9] & (T1L41 # T1L42) # !R1_address_reg_a[9] & T1L197;


--T1L44 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5056
T1L44 = R1_address_reg_a[8] & T1L40 # !R1_address_reg_a[8] & (T1L43);


--T1L200 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6060w~47
T1L200 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M2345Q # !R1_address_reg_a[7] & (R1M2245Q));


--T1L201 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6060w~48
T1L201 = R1_address_reg_a[6] & (T1L200 & (R1M2395Q) # !T1L200 & R1M2295Q) # !R1_address_reg_a[6] & (T1L200);


--T1L188 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5859w~47
T1L188 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M695Q # !R1_address_reg_a[6] & (R1M645Q));


--T1L189 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5859w~48
T1L189 = R1_address_reg_a[7] & (T1L188 & (R1M795Q) # !T1L188 & R1M745Q) # !R1_address_reg_a[7] & (T1L188);


--T1L204 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~566
T1L204 = R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L201 # !R1_address_reg_a[11] & (T1L189));


--T1L198 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6058w~44
T1L198 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1895Q # !R1_address_reg_a[6] & (R1M1845Q));


--T1L199 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6058w~45
T1L199 = R1_address_reg_a[7] & (T1L198 & (R1M1995Q) # !T1L198 & R1M1945Q) # !R1_address_reg_a[7] & (T1L198);


--T1L186 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5857w~44
T1L186 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M345Q # !R1_address_reg_a[7] & (R1M245Q));


--T1L187 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5857w~45
T1L187 = R1_address_reg_a[6] & (T1L186 & (R1M395Q) # !T1L186 & R1M295Q) # !R1_address_reg_a[6] & (T1L186);


--T1L205 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~567
T1L205 = !R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L199 # !R1_address_reg_a[11] & (T1L187));


--T1L206 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~568
T1L206 = T1L147 # T1L232 & (T1L204 # T1L205);


--T1L202 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6142w~281
T1L202 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1695Q # !R1_address_reg_a[6] & (R1M1645Q));


--T1L203 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6142w~282
T1L203 = R1_address_reg_a[7] & (T1L202 & (R1M1795Q) # !T1L202 & R1M1745Q) # !R1_address_reg_a[7] & (T1L202);


--T1L190 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5942w~281
T1L190 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M145Q # !R1_address_reg_a[7] & (R1M45Q));


--T1L191 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5942w~282
T1L191 = R1_address_reg_a[6] & (T1L190 & (R1M195Q) # !T1L190 & R1M95Q) # !R1_address_reg_a[6] & (T1L190);


--T1L207 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~569
T1L207 = T1L236 & (R1_address_reg_a[11] & T1L203 # !R1_address_reg_a[11] & (T1L191));


--T1L208 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~570
T1L208 = R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M2195Q # !R1_address_reg_a[7] & (R1M2095Q)) # !R1_address_reg_a[6] & (R1_address_reg_a[7]);


--T1L209 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~571
T1L209 = R1_address_reg_a[6] & (T1L208) # !R1_address_reg_a[6] & (T1L208 & R1M2145Q # !T1L208 & (R1M2045Q));


--T1L210 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~572
T1L210 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M495Q # !R1_address_reg_a[6] & (R1M445Q));


--T1L211 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~573
T1L211 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M595Q # !R1_address_reg_a[6] & (R1M545Q));


--T1L212 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~574
T1L212 = R1_address_reg_a[11] & T1L209 # !R1_address_reg_a[11] & (T1L210 # T1L211);


--T1L213 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~575
T1L213 = T1L206 # T1L207 # T1L243 & T1L212;


--T1L45 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5057
T1L45 = T1L213 & (T1L39 # !R1_address_reg_a[10]) # !T1L213 & (T1L44 & R1_address_reg_a[10]);


--H1L20 is VGA_OSD_RAM:u6|Mux~32
H1L20 = H1_ADDR_dd[0] & (H1_ADDR_dd[1]) # !H1_ADDR_dd[0] & (H1_ADDR_dd[1] & T1L63 # !H1_ADDR_dd[1] & (T1L45));


--T1L64 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5058
T1L64 = R1_address_reg_a[8] & !R1_address_reg_a[7] # !R1_address_reg_a[8] & R1_address_reg_a[7] & R1M2548Q;


--T1L65 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5059
T1L65 = R1_address_reg_a[6] & (R1M2498Q # R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1M2448Q & !R1_address_reg_a[7]);


--T1L66 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5060
T1L66 = !R1_address_reg_a[9] & (T1L64 & R1_address_reg_a[7] & !T1L65 # !T1L64 & !R1_address_reg_a[7] & T1L65);


--T1L281 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7555w~49
T1L281 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1498Q # !R1_address_reg_a[6] & (R1M1448Q));


--T1L282 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7555w~50
T1L282 = R1_address_reg_a[7] & (T1L281 & (R1M1598Q) # !T1L281 & R1M1548Q) # !R1_address_reg_a[7] & (T1L281);


--T1L279 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7553w~44
T1L279 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M1148Q # !R1_address_reg_a[7] & (R1M1048Q));


--T1L280 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7553w~45
T1L280 = R1_address_reg_a[6] & (T1L279 & (R1M1198Q) # !T1L279 & R1M1098Q) # !R1_address_reg_a[6] & (T1L279);


--T1L67 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5061
T1L67 = R1_address_reg_a[9] & T1L282 # !R1_address_reg_a[9] & (T1L280);


--T1L283 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7637w~407
T1L283 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M948Q # !R1_address_reg_a[7] & (R1M848Q));


--T1L284 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7637w~408
T1L284 = R1_address_reg_a[6] & (T1L283 & (R1M998Q) # !T1L283 & R1M898Q) # !R1_address_reg_a[6] & (T1L283);


--T1L68 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5062
T1L68 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1398Q # !R1_address_reg_a[6] & (R1M1348Q));


--T1L69 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5063
T1L69 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1298Q # !R1_address_reg_a[6] & (R1M1248Q));


--T1L70 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5064
T1L70 = R1_address_reg_a[9] & (T1L68 # T1L69) # !R1_address_reg_a[9] & T1L284;


--T1L71 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5065
T1L71 = R1_address_reg_a[8] & T1L67 # !R1_address_reg_a[8] & (T1L70);


--T1L287 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7653w~47
T1L287 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M2298Q # !R1_address_reg_a[6] & (R1M2248Q));


--T1L288 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7653w~48
T1L288 = R1_address_reg_a[7] & (T1L287 & (R1M2398Q) # !T1L287 & R1M2348Q) # !R1_address_reg_a[7] & (T1L287);


--T1L275 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7452w~47
T1L275 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M748Q # !R1_address_reg_a[7] & (R1M648Q));


--T1L276 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7452w~48
T1L276 = R1_address_reg_a[6] & (T1L275 & (R1M798Q) # !T1L275 & R1M698Q) # !R1_address_reg_a[6] & (T1L275);


--T1L291 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~545
T1L291 = R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L288 # !R1_address_reg_a[11] & (T1L276));


--T1L285 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7651w~44
T1L285 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M1948Q # !R1_address_reg_a[7] & (R1M1848Q));


--T1L286 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7651w~45
T1L286 = R1_address_reg_a[6] & (T1L285 & (R1M1998Q) # !T1L285 & R1M1898Q) # !R1_address_reg_a[6] & (T1L285);


--T1L273 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7450w~44
T1L273 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M298Q # !R1_address_reg_a[6] & (R1M248Q));


--T1L274 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7450w~45
T1L274 = R1_address_reg_a[7] & (T1L273 & (R1M398Q) # !T1L273 & R1M348Q) # !R1_address_reg_a[7] & (T1L273);


--T1L292 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~546
T1L292 = !R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L286 # !R1_address_reg_a[11] & (T1L274));


--T1L293 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~547
T1L293 = T1L147 # T1L232 & (T1L291 # T1L292);


--T1L289 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7735w~281
T1L289 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M1748Q # !R1_address_reg_a[7] & (R1M1648Q));


--T1L290 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7735w~282
T1L290 = R1_address_reg_a[6] & (T1L289 & (R1M1798Q) # !T1L289 & R1M1698Q) # !R1_address_reg_a[6] & (T1L289);


--T1L277 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7535w~281
T1L277 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M98Q # !R1_address_reg_a[6] & (R1M48Q));


--T1L278 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7535w~282
T1L278 = R1_address_reg_a[7] & (T1L277 & (R1M198Q) # !T1L277 & R1M148Q) # !R1_address_reg_a[7] & (T1L277);


--T1L294 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~548
T1L294 = T1L236 & (R1_address_reg_a[11] & T1L290 # !R1_address_reg_a[11] & (T1L278));


--T1L295 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~549
T1L295 = R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M2198Q # !R1_address_reg_a[7] & (R1M2098Q)) # !R1_address_reg_a[6] & (R1_address_reg_a[7]);


--T1L296 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~550
T1L296 = R1_address_reg_a[6] & (T1L295) # !R1_address_reg_a[6] & (T1L295 & R1M2148Q # !T1L295 & (R1M2048Q));


--T1L297 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~551
T1L297 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M498Q # !R1_address_reg_a[6] & (R1M448Q));


--T1L298 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~552
T1L298 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M598Q # !R1_address_reg_a[6] & (R1M548Q));


--T1L299 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~553
T1L299 = R1_address_reg_a[11] & T1L296 # !R1_address_reg_a[11] & (T1L297 # T1L298);


--T1L300 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~554
T1L300 = T1L293 # T1L294 # T1L243 & T1L299;


--T1L72 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5066
T1L72 = T1L300 & (T1L66 # !R1_address_reg_a[10]) # !T1L300 & (T1L71 & R1_address_reg_a[10]);


--H1L21 is VGA_OSD_RAM:u6|Mux~33
H1L21 = H1_ADDR_dd[0] & (H1L20 & (T1L72) # !H1L20 & T1L54) # !H1_ADDR_dd[0] & (H1L20);


--T1L19 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5067
T1L19 = R1_address_reg_a[8] & !R1_address_reg_a[7] # !R1_address_reg_a[8] & R1_address_reg_a[7] & R1M2543Q;


--T1L20 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5068
T1L20 = R1_address_reg_a[6] & (R1M2493Q # R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1M2443Q & !R1_address_reg_a[7]);


--T1L21 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5069
T1L21 = !R1_address_reg_a[9] & (T1L19 & R1_address_reg_a[7] & !T1L20 # !T1L19 & !R1_address_reg_a[7] & T1L20);


--T1L137 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4900w~49
T1L137 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M1543Q # !R1_address_reg_a[7] & (R1M1443Q));


--T1L138 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4900w~50
T1L138 = R1_address_reg_a[6] & (T1L137 & (R1M1593Q) # !T1L137 & R1M1493Q) # !R1_address_reg_a[6] & (T1L137);


--T1L135 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4898w~44
T1L135 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1093Q # !R1_address_reg_a[6] & (R1M1043Q));


--T1L136 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4898w~45
T1L136 = R1_address_reg_a[7] & (T1L135 & (R1M1193Q) # !T1L135 & R1M1143Q) # !R1_address_reg_a[7] & (T1L135);


--T1L22 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5070
T1L22 = R1_address_reg_a[9] & T1L138 # !R1_address_reg_a[9] & (T1L136);


--T1L139 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4982w~407
T1L139 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M893Q # !R1_address_reg_a[6] & (R1M843Q));


--T1L140 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4982w~408
T1L140 = R1_address_reg_a[7] & (T1L139 & (R1M993Q) # !T1L139 & R1M943Q) # !R1_address_reg_a[7] & (T1L139);


--T1L23 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5071
T1L23 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1393Q # !R1_address_reg_a[6] & (R1M1343Q));


--T1L24 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5072
T1L24 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1293Q # !R1_address_reg_a[6] & (R1M1243Q));


--T1L25 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5073
T1L25 = R1_address_reg_a[9] & (T1L23 # T1L24) # !R1_address_reg_a[9] & T1L140;


--T1L26 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5074
T1L26 = R1_address_reg_a[8] & T1L22 # !R1_address_reg_a[8] & (T1L25);


--T1L143 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4998w~47
T1L143 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M2343Q # !R1_address_reg_a[7] & (R1M2243Q));


--T1L144 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4998w~48
T1L144 = R1_address_reg_a[6] & (T1L143 & (R1M2393Q) # !T1L143 & R1M2293Q) # !R1_address_reg_a[6] & (T1L143);


--T1L131 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4797w~47
T1L131 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M693Q # !R1_address_reg_a[6] & (R1M643Q));


--T1L132 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4797w~48
T1L132 = R1_address_reg_a[7] & (T1L131 & (R1M793Q) # !T1L131 & R1M743Q) # !R1_address_reg_a[7] & (T1L131);


--T1L148 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~609
T1L148 = R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L144 # !R1_address_reg_a[11] & (T1L132));


--T1L141 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4996w~44
T1L141 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1893Q # !R1_address_reg_a[6] & (R1M1843Q));


--T1L142 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4996w~45
T1L142 = R1_address_reg_a[7] & (T1L141 & (R1M1993Q) # !T1L141 & R1M1943Q) # !R1_address_reg_a[7] & (T1L141);


--T1L129 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4795w~44
T1L129 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M343Q # !R1_address_reg_a[7] & (R1M243Q));


--T1L130 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4795w~45
T1L130 = R1_address_reg_a[6] & (T1L129 & (R1M393Q) # !T1L129 & R1M293Q) # !R1_address_reg_a[6] & (T1L129);


--T1L149 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~610
T1L149 = !R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L142 # !R1_address_reg_a[11] & (T1L130));


--T1L150 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~611
T1L150 = T1L147 # T1L232 & (T1L148 # T1L149);


--T1L145 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5080w~281
T1L145 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1693Q # !R1_address_reg_a[6] & (R1M1643Q));


--T1L146 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5080w~282
T1L146 = R1_address_reg_a[7] & (T1L145 & (R1M1793Q) # !T1L145 & R1M1743Q) # !R1_address_reg_a[7] & (T1L145);


--T1L133 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4880w~281
T1L133 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M143Q # !R1_address_reg_a[7] & (R1M43Q));


--T1L134 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4880w~282
T1L134 = R1_address_reg_a[6] & (T1L133 & (R1M193Q) # !T1L133 & R1M93Q) # !R1_address_reg_a[6] & (T1L133);


--T1L151 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~612
T1L151 = T1L236 & (R1_address_reg_a[11] & T1L146 # !R1_address_reg_a[11] & (T1L134));


--T1L152 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~613
T1L152 = R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M2193Q # !R1_address_reg_a[7] & (R1M2093Q)) # !R1_address_reg_a[6] & (R1_address_reg_a[7]);


--T1L153 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~614
T1L153 = R1_address_reg_a[6] & (T1L152) # !R1_address_reg_a[6] & (T1L152 & R1M2143Q # !T1L152 & (R1M2043Q));


--T1L154 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~615
T1L154 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M493Q # !R1_address_reg_a[6] & (R1M443Q));


--T1L155 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~616
T1L155 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M593Q # !R1_address_reg_a[6] & (R1M543Q));


--T1L156 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~617
T1L156 = R1_address_reg_a[11] & T1L153 # !R1_address_reg_a[11] & (T1L154 # T1L155);


--T1L157 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~618
T1L157 = T1L150 # T1L151 # T1L243 & T1L156;


--T1L27 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5075
T1L27 = T1L157 & (T1L21 # !R1_address_reg_a[10]) # !T1L157 & (T1L26 & R1_address_reg_a[10]);


--T1L10 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5076
T1L10 = R1_address_reg_a[8] & !R1_address_reg_a[7] # !R1_address_reg_a[8] & R1_address_reg_a[7] & R1M2542Q;


--T1L11 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5077
T1L11 = R1_address_reg_a[6] & (R1M2492Q # R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1M2442Q & !R1_address_reg_a[7]);


--T1L12 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5078
T1L12 = !R1_address_reg_a[9] & (T1L10 & R1_address_reg_a[7] & !T1L11 # !T1L10 & !R1_address_reg_a[7] & T1L11);


--T1L109 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4369w~49
T1L109 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1492Q # !R1_address_reg_a[6] & (R1M1442Q));


--T1L110 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4369w~50
T1L110 = R1_address_reg_a[7] & (T1L109 & (R1M1592Q) # !T1L109 & R1M1542Q) # !R1_address_reg_a[7] & (T1L109);


--T1L107 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4367w~44
T1L107 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M1142Q # !R1_address_reg_a[7] & (R1M1042Q));


--T1L108 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4367w~45
T1L108 = R1_address_reg_a[6] & (T1L107 & (R1M1192Q) # !T1L107 & R1M1092Q) # !R1_address_reg_a[6] & (T1L107);


--T1L13 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5079
T1L13 = R1_address_reg_a[9] & T1L110 # !R1_address_reg_a[9] & (T1L108);


--T1L111 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4451w~407
T1L111 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M942Q # !R1_address_reg_a[7] & (R1M842Q));


--T1L112 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4451w~408
T1L112 = R1_address_reg_a[6] & (T1L111 & (R1M992Q) # !T1L111 & R1M892Q) # !R1_address_reg_a[6] & (T1L111);


--T1L14 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5080
T1L14 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1392Q # !R1_address_reg_a[6] & (R1M1342Q));


--T1L15 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5081
T1L15 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1292Q # !R1_address_reg_a[6] & (R1M1242Q));


--T1L16 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5082
T1L16 = R1_address_reg_a[9] & (T1L14 # T1L15) # !R1_address_reg_a[9] & T1L112;


--T1L17 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5083
T1L17 = R1_address_reg_a[8] & T1L13 # !R1_address_reg_a[8] & (T1L16);


--T1L115 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4467w~47
T1L115 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M2292Q # !R1_address_reg_a[6] & (R1M2242Q));


--T1L116 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4467w~48
T1L116 = R1_address_reg_a[7] & (T1L115 & (R1M2392Q) # !T1L115 & R1M2342Q) # !R1_address_reg_a[7] & (T1L115);


--T1L103 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4266w~47
T1L103 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M742Q # !R1_address_reg_a[7] & (R1M642Q));


--T1L104 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4266w~48
T1L104 = R1_address_reg_a[6] & (T1L103 & (R1M792Q) # !T1L103 & R1M692Q) # !R1_address_reg_a[6] & (T1L103);


--T1L119 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~566
T1L119 = R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L116 # !R1_address_reg_a[11] & (T1L104));


--T1L113 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4465w~44
T1L113 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M1942Q # !R1_address_reg_a[7] & (R1M1842Q));


--T1L114 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4465w~45
T1L114 = R1_address_reg_a[6] & (T1L113 & (R1M1992Q) # !T1L113 & R1M1892Q) # !R1_address_reg_a[6] & (T1L113);


--T1L101 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4264w~44
T1L101 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M292Q # !R1_address_reg_a[6] & (R1M242Q));


--T1L102 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4264w~45
T1L102 = R1_address_reg_a[7] & (T1L101 & (R1M392Q) # !T1L101 & R1M342Q) # !R1_address_reg_a[7] & (T1L101);


--T1L120 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~567
T1L120 = !R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L114 # !R1_address_reg_a[11] & (T1L102));


--T1L121 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~568
T1L121 = T1L147 # T1L232 & (T1L119 # T1L120);


--T1L117 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4549w~281
T1L117 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M1742Q # !R1_address_reg_a[7] & (R1M1642Q));


--T1L118 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4549w~282
T1L118 = R1_address_reg_a[6] & (T1L117 & (R1M1792Q) # !T1L117 & R1M1692Q) # !R1_address_reg_a[6] & (T1L117);


--T1L105 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4349w~281
T1L105 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M92Q # !R1_address_reg_a[6] & (R1M42Q));


--T1L106 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4349w~282
T1L106 = R1_address_reg_a[7] & (T1L105 & (R1M192Q) # !T1L105 & R1M142Q) # !R1_address_reg_a[7] & (T1L105);


--T1L122 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~569
T1L122 = T1L236 & (R1_address_reg_a[11] & T1L118 # !R1_address_reg_a[11] & (T1L106));


--T1L123 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~570
T1L123 = R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M2192Q # !R1_address_reg_a[7] & (R1M2092Q)) # !R1_address_reg_a[6] & (R1_address_reg_a[7]);


--T1L124 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~571
T1L124 = R1_address_reg_a[6] & (T1L123) # !R1_address_reg_a[6] & (T1L123 & R1M2142Q # !T1L123 & (R1M2042Q));


--T1L125 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~572
T1L125 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M492Q # !R1_address_reg_a[6] & (R1M442Q));


--T1L126 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~573
T1L126 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M592Q # !R1_address_reg_a[6] & (R1M542Q));


--T1L127 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~574
T1L127 = R1_address_reg_a[11] & T1L124 # !R1_address_reg_a[11] & (T1L125 # T1L126);


--T1L128 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~575
T1L128 = T1L121 # T1L122 # T1L243 & T1L127;


--T1L18 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5084
T1L18 = T1L128 & (T1L12 # !R1_address_reg_a[10]) # !T1L128 & (T1L17 & R1_address_reg_a[10]);


--T1L1 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5085
T1L1 = R1_address_reg_a[8] & !R1_address_reg_a[7] # !R1_address_reg_a[8] & R1_address_reg_a[7] & R1_ram_block2a50;


--T1L2 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5086
T1L2 = R1_address_reg_a[6] & (R1_ram_block2a49 # R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_ram_block2a48 & !R1_address_reg_a[7]);


--T1L3 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5087
T1L3 = !R1_address_reg_a[9] & (T1L1 & R1_address_reg_a[7] & !T1L2 # !T1L1 & !R1_address_reg_a[7] & T1L2);


--T1L81 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3833w~49
T1L81 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1_ram_block2a30 # !R1_address_reg_a[7] & (R1_ram_block2a28));


--T1L82 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3833w~50
T1L82 = R1_address_reg_a[6] & (T1L81 & (R1_ram_block2a31) # !T1L81 & R1_ram_block2a29) # !R1_address_reg_a[6] & (T1L81);


--T1L79 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3831w~44
T1L79 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1_ram_block2a21 # !R1_address_reg_a[6] & (R1_ram_block2a20));


--T1L80 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3831w~45
T1L80 = R1_address_reg_a[7] & (T1L79 & (R1_ram_block2a23) # !T1L79 & R1_ram_block2a22) # !R1_address_reg_a[7] & (T1L79);


--T1L4 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5088
T1L4 = R1_address_reg_a[9] & T1L82 # !R1_address_reg_a[9] & (T1L80);


--T1L83 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3915w~407
T1L83 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1_ram_block2a17 # !R1_address_reg_a[6] & (R1_ram_block2a16));


--T1L84 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3915w~408
T1L84 = R1_address_reg_a[7] & (T1L83 & (R1_ram_block2a19) # !T1L83 & R1_ram_block2a18) # !R1_address_reg_a[7] & (T1L83);


--T1L5 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5089
T1L5 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1_ram_block2a27 # !R1_address_reg_a[6] & (R1_ram_block2a26));


--T1L6 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5090
T1L6 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1_ram_block2a25 # !R1_address_reg_a[6] & (R1_ram_block2a24));


--T1L7 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5091
T1L7 = R1_address_reg_a[9] & (T1L5 # T1L6) # !R1_address_reg_a[9] & T1L84;


--T1L8 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5092
T1L8 = R1_address_reg_a[8] & T1L4 # !R1_address_reg_a[8] & (T1L7);


--T1L87 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3931w~47
T1L87 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1_ram_block2a46 # !R1_address_reg_a[7] & (R1_ram_block2a44));


--T1L88 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3931w~48
T1L88 = R1_address_reg_a[6] & (T1L87 & (R1_ram_block2a47) # !T1L87 & R1_ram_block2a45) # !R1_address_reg_a[6] & (T1L87);


--T1L75 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3730w~47
T1L75 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1_ram_block2a13 # !R1_address_reg_a[6] & (R1_ram_block2a12));


--T1L76 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3730w~48
T1L76 = R1_address_reg_a[7] & (T1L75 & (R1_ram_block2a15) # !T1L75 & R1_ram_block2a14) # !R1_address_reg_a[7] & (T1L75);


--T1L91 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~566
T1L91 = R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L88 # !R1_address_reg_a[11] & (T1L76));


--T1L85 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3929w~44
T1L85 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1_ram_block2a37 # !R1_address_reg_a[6] & (R1_ram_block2a36));


--T1L86 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3929w~45
T1L86 = R1_address_reg_a[7] & (T1L85 & (R1_ram_block2a39) # !T1L85 & R1_ram_block2a38) # !R1_address_reg_a[7] & (T1L85);


--T1L73 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3728w~44
T1L73 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1_ram_block2a6 # !R1_address_reg_a[7] & (R1_ram_block2a4));


--T1L74 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3728w~45
T1L74 = R1_address_reg_a[6] & (T1L73 & (R1_ram_block2a7) # !T1L73 & R1_ram_block2a5) # !R1_address_reg_a[6] & (T1L73);


--T1L92 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~567
T1L92 = !R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L86 # !R1_address_reg_a[11] & (T1L74));


--T1L93 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~568
T1L93 = T1L147 # T1L232 & (T1L91 # T1L92);


--T1L89 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4013w~281
T1L89 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1_ram_block2a33 # !R1_address_reg_a[6] & (R1_ram_block2a32));


--T1L90 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4013w~282
T1L90 = R1_address_reg_a[7] & (T1L89 & (R1_ram_block2a35) # !T1L89 & R1_ram_block2a34) # !R1_address_reg_a[7] & (T1L89);


--T1L77 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3813w~281
T1L77 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1_ram_block2a2 # !R1_address_reg_a[7] & (R1_ram_block2a0));


--T1L78 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3813w~282
T1L78 = R1_address_reg_a[6] & (T1L77 & (R1_ram_block2a3) # !T1L77 & R1_ram_block2a1) # !R1_address_reg_a[6] & (T1L77);


--T1L94 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~569
T1L94 = T1L236 & (R1_address_reg_a[11] & T1L90 # !R1_address_reg_a[11] & (T1L78));


--T1L95 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~570
T1L95 = R1_address_reg_a[6] & (R1_address_reg_a[7] & R1_ram_block2a43 # !R1_address_reg_a[7] & (R1_ram_block2a41)) # !R1_address_reg_a[6] & (R1_address_reg_a[7]);


--T1L96 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~571
T1L96 = R1_address_reg_a[6] & (T1L95) # !R1_address_reg_a[6] & (T1L95 & R1_ram_block2a42 # !T1L95 & (R1_ram_block2a40));


--T1L97 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~572
T1L97 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1_ram_block2a9 # !R1_address_reg_a[6] & (R1_ram_block2a8));


--T1L98 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~573
T1L98 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1_ram_block2a11 # !R1_address_reg_a[6] & (R1_ram_block2a10));


--T1L99 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~574
T1L99 = R1_address_reg_a[11] & T1L96 # !R1_address_reg_a[11] & (T1L97 # T1L98);


--T1L100 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~575
T1L100 = T1L93 # T1L94 # T1L243 & T1L99;


--T1L9 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5093
T1L9 = T1L100 & (T1L3 # !R1_address_reg_a[10]) # !T1L100 & (T1L8 & R1_address_reg_a[10]);


--H1L22 is VGA_OSD_RAM:u6|Mux~34
H1L22 = H1_ADDR_dd[1] & (H1_ADDR_dd[0]) # !H1_ADDR_dd[1] & (H1_ADDR_dd[0] & T1L18 # !H1_ADDR_dd[0] & (T1L9));


--T1L28 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5094
T1L28 = R1_address_reg_a[8] & !R1_address_reg_a[7] # !R1_address_reg_a[8] & R1_address_reg_a[7] & R1M2544Q;


--T1L29 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5095
T1L29 = R1_address_reg_a[6] & (R1M2494Q # R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1M2444Q & !R1_address_reg_a[7]);


--T1L30 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5096
T1L30 = !R1_address_reg_a[9] & (T1L28 & R1_address_reg_a[7] & !T1L29 # !T1L28 & !R1_address_reg_a[7] & T1L29);


--T1L166 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5431w~49
T1L166 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1494Q # !R1_address_reg_a[6] & (R1M1444Q));


--T1L167 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5431w~50
T1L167 = R1_address_reg_a[7] & (T1L166 & (R1M1594Q) # !T1L166 & R1M1544Q) # !R1_address_reg_a[7] & (T1L166);


--T1L164 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5429w~44
T1L164 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M1144Q # !R1_address_reg_a[7] & (R1M1044Q));


--T1L165 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5429w~45
T1L165 = R1_address_reg_a[6] & (T1L164 & (R1M1194Q) # !T1L164 & R1M1094Q) # !R1_address_reg_a[6] & (T1L164);


--T1L31 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5097
T1L31 = R1_address_reg_a[9] & T1L167 # !R1_address_reg_a[9] & (T1L165);


--T1L168 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5513w~407
T1L168 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M944Q # !R1_address_reg_a[7] & (R1M844Q));


--T1L169 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5513w~408
T1L169 = R1_address_reg_a[6] & (T1L168 & (R1M994Q) # !T1L168 & R1M894Q) # !R1_address_reg_a[6] & (T1L168);


--T1L32 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5098
T1L32 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1394Q # !R1_address_reg_a[6] & (R1M1344Q));


--T1L33 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5099
T1L33 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1294Q # !R1_address_reg_a[6] & (R1M1244Q));


--T1L34 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5100
T1L34 = R1_address_reg_a[9] & (T1L32 # T1L33) # !R1_address_reg_a[9] & T1L169;


--T1L35 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5101
T1L35 = R1_address_reg_a[8] & T1L31 # !R1_address_reg_a[8] & (T1L34);


--T1L172 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5529w~47
T1L172 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M2294Q # !R1_address_reg_a[6] & (R1M2244Q));


--T1L173 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5529w~48
T1L173 = R1_address_reg_a[7] & (T1L172 & (R1M2394Q) # !T1L172 & R1M2344Q) # !R1_address_reg_a[7] & (T1L172);


--T1L160 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5328w~47
T1L160 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M744Q # !R1_address_reg_a[7] & (R1M644Q));


--T1L161 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5328w~48
T1L161 = R1_address_reg_a[6] & (T1L160 & (R1M794Q) # !T1L160 & R1M694Q) # !R1_address_reg_a[6] & (T1L160);


--T1L176 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~545
T1L176 = R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L173 # !R1_address_reg_a[11] & (T1L161));


--T1L170 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5527w~44
T1L170 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M1944Q # !R1_address_reg_a[7] & (R1M1844Q));


--T1L171 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5527w~45
T1L171 = R1_address_reg_a[6] & (T1L170 & (R1M1994Q) # !T1L170 & R1M1894Q) # !R1_address_reg_a[6] & (T1L170);


--T1L158 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5326w~44
T1L158 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M294Q # !R1_address_reg_a[6] & (R1M244Q));


--T1L159 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5326w~45
T1L159 = R1_address_reg_a[7] & (T1L158 & (R1M394Q) # !T1L158 & R1M344Q) # !R1_address_reg_a[7] & (T1L158);


--T1L177 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~546
T1L177 = !R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L171 # !R1_address_reg_a[11] & (T1L159));


--T1L178 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~547
T1L178 = T1L147 # T1L232 & (T1L176 # T1L177);


--T1L174 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5611w~281
T1L174 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M1744Q # !R1_address_reg_a[7] & (R1M1644Q));


--T1L175 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5611w~282
T1L175 = R1_address_reg_a[6] & (T1L174 & (R1M1794Q) # !T1L174 & R1M1694Q) # !R1_address_reg_a[6] & (T1L174);


--T1L162 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5411w~281
T1L162 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M94Q # !R1_address_reg_a[6] & (R1M44Q));


--T1L163 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5411w~282
T1L163 = R1_address_reg_a[7] & (T1L162 & (R1M194Q) # !T1L162 & R1M144Q) # !R1_address_reg_a[7] & (T1L162);


--T1L179 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~548
T1L179 = T1L236 & (R1_address_reg_a[11] & T1L175 # !R1_address_reg_a[11] & (T1L163));


--T1L180 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~549
T1L180 = R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M2194Q # !R1_address_reg_a[7] & (R1M2094Q)) # !R1_address_reg_a[6] & (R1_address_reg_a[7]);


--T1L181 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~550
T1L181 = R1_address_reg_a[6] & (T1L180) # !R1_address_reg_a[6] & (T1L180 & R1M2144Q # !T1L180 & (R1M2044Q));


--T1L182 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~551
T1L182 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M494Q # !R1_address_reg_a[6] & (R1M444Q));


--T1L183 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~552
T1L183 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M594Q # !R1_address_reg_a[6] & (R1M544Q));


--T1L184 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~553
T1L184 = R1_address_reg_a[11] & T1L181 # !R1_address_reg_a[11] & (T1L182 # T1L183);


--T1L185 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~554
T1L185 = T1L178 # T1L179 # T1L243 & T1L184;


--T1L36 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5102
T1L36 = T1L185 & (T1L30 # !R1_address_reg_a[10]) # !T1L185 & (T1L35 & R1_address_reg_a[10]);


--H1L23 is VGA_OSD_RAM:u6|Mux~35
H1L23 = H1_ADDR_dd[1] & (H1L22 & (T1L36) # !H1L22 & T1L27) # !H1_ADDR_dd[1] & (H1L22);


--H1_ADDR_dd[2] is VGA_OSD_RAM:u6|ADDR_dd[2]
H1_ADDR_dd[2] = DFFEAS(H1L11, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--H1L140 is VGA_OSD_RAM:u6|oRed~83
H1L140 = H1L139 & (H1_ADDR_dd[2] & H1L21 # !H1_ADDR_dd[2] & (H1L23));


--G1L3 is VGA_Pattern:u5|LessThan~2785
G1L3 = F1_oCoord_Y[4] & F1_oCoord_Y[6] & F1_oCoord_Y[5];


--G1L4 is VGA_Pattern:u5|LessThan~2786
G1L4 = !F1_oCoord_Y[9] & !F1_oCoord_Y[8];


--G1L50 is VGA_Pattern:u5|oRed~95
G1L50 = G1L3 & (F1_oCoord_Y[7] # !F1_oCoord_Y[3]) # !G1L3 & !F1_oCoord_Y[7] # !G1L4;


--G1L5 is VGA_Pattern:u5|LessThan~2787
G1L5 = F1_oCoord_Y[7] # F1_oCoord_Y[3] & G1L3 # !G1L4;


--G1L41 is VGA_Pattern:u5|oGreen~1205
G1L41 = F1_oCoord_X[9] & (F1_oCoord_X[6] # G1L40 # !H1L12);


--G1L6 is VGA_Pattern:u5|LessThan~2788
G1L6 = !F1_oCoord_X[8] & (!G1L40 # !F1_oCoord_X[6] # !F1_oCoord_X[7]);


--G1L42 is VGA_Pattern:u5|oGreen~1206
G1L42 = F1_oCoord_X[9] # !G1L6;


--G1L7 is VGA_Pattern:u5|LessThan~2789
G1L7 = F1_oCoord_Y[3] & F1_oCoord_Y[2];


--G1L8 is VGA_Pattern:u5|LessThan~2790
G1L8 = G1L13 & !F1_oCoord_Y[9] & !F1_oCoord_Y[8] & !F1_oCoord_Y[7];


--G1L21 is VGA_Pattern:u5|oBlue~1287
G1L21 = F1_oCoord_Y[6] # F1_oCoord_Y[5] & (F1_oCoord_Y[4] # !F1L225);


--G1L51 is VGA_Pattern:u5|oRed~96
G1L51 = F1_oCoord_Y[8] & (F1_oCoord_Y[7] # !G1L1);


--G1L22 is VGA_Pattern:u5|oBlue~1288
G1L22 = F1_oCoord_Y[9] # F1_oCoord_Y[7] & G1L21 # !G1L51;


--G1L9 is VGA_Pattern:u5|LessThan~2791
G1L9 = F1_oCoord_Y[7] & (F1_oCoord_Y[6] # G1L2 & !F1L225);


--G1L10 is VGA_Pattern:u5|LessThan~2792
G1L10 = F1_oCoord_Y[7] # F1_oCoord_Y[3] & F1_oCoord_Y[6] & G1L2;


--G1L23 is VGA_Pattern:u5|oBlue~1289
G1L23 = F1_oCoord_Y[9] # F1_oCoord_Y[8] # G1L9 # !G1L10;


--G1L11 is VGA_Pattern:u5|LessThan~2793
G1L11 = F1_oCoord_Y[5] & (F1_oCoord_Y[4] # G1L7) # !H1L15;


--G1L24 is VGA_Pattern:u5|oBlue~1290
G1L24 = F1_oCoord_Y[8] & G1L11 # !F1_oCoord_Y[8] & (!G1L3 # !F1_oCoord_Y[7]);


--G1L12 is VGA_Pattern:u5|LessThan~2794
G1L12 = G1L9 & !F1_oCoord_Y[8] & !G1L3;


--G1L25 is VGA_Pattern:u5|oBlue~1291
G1L25 = G1L23 & (F1_oCoord_Y[9] # G1L24 # G1L12);


--G1L17 is VGA_Pattern:u5|oBlue[7]~1292
G1L17 = !F1_oCoord_Y[8] & !G1L10 & !G1L9;


--G1L18 is VGA_Pattern:u5|oBlue[7]~1293
G1L18 = F1_oCoord_Y[9] # G1L17 # G1L51 & G1L11;


--G1L26 is VGA_Pattern:u5|oBlue~1294
G1L26 = G1L13 & F1_oCoord_Y[7] # !G1L13 & (G1L10) # !G1L4;


--G1L27 is VGA_Pattern:u5|oBlue~1295
G1L27 = G1L18 & G1L22 # !G1L18 & (G1L25) # !G1L26;


--G1L28 is VGA_Pattern:u5|oBlue~1296
G1L28 = F1_oCoord_Y[9] # G1L24 & !G1L12 # !G1L23;


--G1L29 is VGA_Pattern:u5|oBlue~1297
G1L29 = G1L18 & (!G1L22) # !G1L18 & G1L28 # !G1L26;


--G1L30 is VGA_Pattern:u5|oBlue~1298
G1L30 = !F1_oCoord_Y[8] & (!G1L9 # !G1L3) # !G1L24;


--K1L11 is AUDIO_DAC:u8|LRCK_1X_DIV[0]~145
K1L11 = K1_LRCK_1X_DIV[0] $ VCC;

--K1L12 is AUDIO_DAC:u8|LRCK_1X_DIV[0]~146
K1L12 = CARRY(K1_LRCK_1X_DIV[0]);


--K1L14 is AUDIO_DAC:u8|LRCK_1X_DIV[1]~147
K1L14 = K1_LRCK_1X_DIV[1] & !K1L12 # !K1_LRCK_1X_DIV[1] & (K1L12 # GND);

--K1L15 is AUDIO_DAC:u8|LRCK_1X_DIV[1]~148
K1L15 = CARRY(!K1L12 # !K1_LRCK_1X_DIV[1]);


--K1L17 is AUDIO_DAC:u8|LRCK_1X_DIV[2]~149
K1L17 = K1_LRCK_1X_DIV[2] & (K1L15 $ GND) # !K1_LRCK_1X_DIV[2] & !K1L15 & VCC;

--K1L18 is AUDIO_DAC:u8|LRCK_1X_DIV[2]~150
K1L18 = CARRY(K1_LRCK_1X_DIV[2] & !K1L15);


--K1L20 is AUDIO_DAC:u8|LRCK_1X_DIV[3]~151
K1L20 = K1_LRCK_1X_DIV[3] & !K1L18 # !K1_LRCK_1X_DIV[3] & (K1L18 # GND);

--K1L21 is AUDIO_DAC:u8|LRCK_1X_DIV[3]~152
K1L21 = CARRY(!K1L18 # !K1_LRCK_1X_DIV[3]);


--K1L23 is AUDIO_DAC:u8|LRCK_1X_DIV[4]~153
K1L23 = K1_LRCK_1X_DIV[4] & (K1L21 $ GND) # !K1_LRCK_1X_DIV[4] & !K1L21 & VCC;

--K1L24 is AUDIO_DAC:u8|LRCK_1X_DIV[4]~154
K1L24 = CARRY(K1_LRCK_1X_DIV[4] & !K1L21);


--K1L26 is AUDIO_DAC:u8|LRCK_1X_DIV[5]~155
K1L26 = K1_LRCK_1X_DIV[5] & !K1L24 # !K1_LRCK_1X_DIV[5] & (K1L24 # GND);

--K1L27 is AUDIO_DAC:u8|LRCK_1X_DIV[5]~156
K1L27 = CARRY(!K1L24 # !K1_LRCK_1X_DIV[5]);


--K1L29 is AUDIO_DAC:u8|LRCK_1X_DIV[6]~157
K1L29 = K1_LRCK_1X_DIV[6] & (K1L27 $ GND) # !K1_LRCK_1X_DIV[6] & !K1L27 & VCC;

--K1L30 is AUDIO_DAC:u8|LRCK_1X_DIV[6]~158
K1L30 = CARRY(K1_LRCK_1X_DIV[6] & !K1L27);


--K1L32 is AUDIO_DAC:u8|LRCK_1X_DIV[7]~159
K1L32 = K1_LRCK_1X_DIV[7] & !K1L30 # !K1_LRCK_1X_DIV[7] & (K1L30 # GND);

--K1L33 is AUDIO_DAC:u8|LRCK_1X_DIV[7]~160
K1L33 = CARRY(!K1L30 # !K1_LRCK_1X_DIV[7]);


--K1L35 is AUDIO_DAC:u8|LRCK_1X_DIV[8]~161
K1L35 = K1_LRCK_1X_DIV[8] $ !K1L33;


--K1_BCK_DIV[2] is AUDIO_DAC:u8|BCK_DIV[2]
K1_BCK_DIV[2] = DFFEAS(K1L5, M1__clk1, KEY[0],  ,  ,  ,  ,  ,  );


--K1_BCK_DIV[1] is AUDIO_DAC:u8|BCK_DIV[1]
K1_BCK_DIV[1] = DFFEAS(K1L6, M1__clk1, KEY[0],  ,  ,  ,  ,  ,  );


--K1_BCK_DIV[0] is AUDIO_DAC:u8|BCK_DIV[0]
K1_BCK_DIV[0] = DFFEAS(K1L7, M1__clk1, KEY[0],  ,  ,  ,  ,  ,  );


--K1L124 is AUDIO_DAC:u8|oAUD_BCK~37
K1L124 = K1_oAUD_BCK $ (K1_BCK_DIV[2] & (K1_BCK_DIV[1] # K1_BCK_DIV[0]));


--V1L25Q is I2C_AV_Config:u7|I2C_Controller:u0|SDO~reg0
V1L25Q = DFFEAS(V1L70, J1_mI2C_CTRL_CLK, KEY[0],  ,  ,  ,  ,  ,  );


--V1L13 is I2C_AV_Config:u7|I2C_Controller:u0|END~124
V1L13 = V1L52Q & V1L40Q & V1L46Q & V1L49Q;


--V1L14 is I2C_AV_Config:u7|I2C_Controller:u0|END~125
V1L14 = V1L43Q & (V1L13 & (V1L55Q) # !V1L13 & V1_END) # !V1L43Q & (V1_END);


--V1_ACK3 is I2C_AV_Config:u7|I2C_Controller:u0|ACK3
V1_ACK3 = DFFEAS(V1L11, J1_mI2C_CTRL_CLK, KEY[0],  ,  ,  ,  ,  ,  );


--V1_ACK1 is I2C_AV_Config:u7|I2C_Controller:u0|ACK1
V1_ACK1 = DFFEAS(V1L3, J1_mI2C_CTRL_CLK, KEY[0],  ,  ,  ,  ,  ,  );


--V1_ACK2 is I2C_AV_Config:u7|I2C_Controller:u0|ACK2
V1_ACK2 = DFFEAS(V1L8, J1_mI2C_CTRL_CLK, KEY[0],  ,  ,  ,  ,  ,  );


--J1L89 is I2C_AV_Config:u7|mSetup_ST~58
J1L89 = !V1_ACK3 & !V1_ACK1 & !V1_ACK2;


--J1L90 is I2C_AV_Config:u7|mSetup_ST~59
J1L90 = J1_mSetup_ST.01 & J1L89 & !V1_END;


--J1_mSetup_ST.00 is I2C_AV_Config:u7|mSetup_ST.00
J1_mSetup_ST.00 = DFFEAS(J1L21, J1_mI2C_CTRL_CLK, KEY[0],  ,  ,  ,  ,  ,  );


--J1L20 is I2C_AV_Config:u7|Select~136
J1L20 = J1_mSetup_ST.01 & V1_END # !J1_mSetup_ST.00;


--F1L222 is VGA_Controller:u4|oCoord_Y[1]~477
F1L222 = F1_V_Cont[1] $ VCC;

--F1L223 is VGA_Controller:u4|oCoord_Y[1]~478
F1L223 = CARRY(F1_V_Cont[1]);


--F1L227 is VGA_Controller:u4|oCoord_Y[2]~479
F1L227 = F1_V_Cont[2] & F1L223 & VCC # !F1_V_Cont[2] & !F1L223;

--F1L228 is VGA_Controller:u4|oCoord_Y[2]~480
F1L228 = CARRY(!F1_V_Cont[2] & !F1L223);


--F1L230 is VGA_Controller:u4|oCoord_Y[3]~481
F1L230 = F1_V_Cont[3] & (GND # !F1L228) # !F1_V_Cont[3] & (F1L228 $ GND);

--F1L231 is VGA_Controller:u4|oCoord_Y[3]~482
F1L231 = CARRY(F1_V_Cont[3] # !F1L228);


--F1L233 is VGA_Controller:u4|oCoord_Y[4]~483
F1L233 = F1_V_Cont[4] & F1L231 & VCC # !F1_V_Cont[4] & !F1L231;

--F1L234 is VGA_Controller:u4|oCoord_Y[4]~484
F1L234 = CARRY(!F1_V_Cont[4] & !F1L231);


--F1L236 is VGA_Controller:u4|oCoord_Y[5]~485
F1L236 = F1_V_Cont[5] & (F1L234 $ GND) # !F1_V_Cont[5] & !F1L234 & VCC;

--F1L237 is VGA_Controller:u4|oCoord_Y[5]~486
F1L237 = CARRY(F1_V_Cont[5] & !F1L234);


--F1L239 is VGA_Controller:u4|oCoord_Y[6]~487
F1L239 = F1_V_Cont[6] & F1L237 & VCC # !F1_V_Cont[6] & !F1L237;

--F1L240 is VGA_Controller:u4|oCoord_Y[6]~488
F1L240 = CARRY(!F1_V_Cont[6] & !F1L237);


--F1L242 is VGA_Controller:u4|oCoord_Y[7]~489
F1L242 = F1_V_Cont[7] & (GND # !F1L240) # !F1_V_Cont[7] & (F1L240 $ GND);

--F1L243 is VGA_Controller:u4|oCoord_Y[7]~490
F1L243 = CARRY(F1_V_Cont[7] # !F1L240);


--F1L245 is VGA_Controller:u4|oCoord_Y[8]~491
F1L245 = F1_V_Cont[8] & F1L243 & VCC # !F1_V_Cont[8] & !F1L243;

--F1L246 is VGA_Controller:u4|oCoord_Y[8]~492
F1L246 = CARRY(!F1_V_Cont[8] & !F1L243);


--F1L248 is VGA_Controller:u4|oCoord_Y[9]~493
F1L248 = F1_V_Cont[9] $ F1L246;


--F1L135 is VGA_Controller:u4|always0~249
F1L135 = F1_H_Cont[8] & (F1L63 & !F1_H_Cont[7] # !F1_H_Cont[9]) # !F1_H_Cont[8] & (F1_H_Cont[9] # !F1L63 & F1_H_Cont[7]);


--F1L136 is VGA_Controller:u4|always0~250
F1L136 = F1L263 & F1L135;


--F1L196 is VGA_Controller:u4|oCoord_X[2]~1422
F1L196 = F1_H_Cont[2] $ VCC;

--F1L197 is VGA_Controller:u4|oCoord_X[2]~1423
F1L197 = CARRY(F1_H_Cont[2]);


--F1L199 is VGA_Controller:u4|oCoord_X[3]~1424
F1L199 = F1_H_Cont[3] & F1L197 & VCC # !F1_H_Cont[3] & !F1L197;

--F1L200 is VGA_Controller:u4|oCoord_X[3]~1425
F1L200 = CARRY(!F1_H_Cont[3] & !F1L197);


--F1L202 is VGA_Controller:u4|oCoord_X[4]~1426
F1L202 = F1_H_Cont[4] & (F1L200 $ GND) # !F1_H_Cont[4] & !F1L200 & VCC;

--F1L203 is VGA_Controller:u4|oCoord_X[4]~1427
F1L203 = CARRY(F1_H_Cont[4] & !F1L200);


--F1L205 is VGA_Controller:u4|oCoord_X[5]~1428
F1L205 = F1_H_Cont[5] & F1L203 & VCC # !F1_H_Cont[5] & !F1L203;

--F1L206 is VGA_Controller:u4|oCoord_X[5]~1429
F1L206 = CARRY(!F1_H_Cont[5] & !F1L203);


--F1L208 is VGA_Controller:u4|oCoord_X[6]~1430
F1L208 = F1_H_Cont[6] & (GND # !F1L206) # !F1_H_Cont[6] & (F1L206 $ GND);

--F1L209 is VGA_Controller:u4|oCoord_X[6]~1431
F1L209 = CARRY(F1_H_Cont[6] # !F1L206);


--F1L211 is VGA_Controller:u4|oCoord_X[7]~1432
F1L211 = F1_H_Cont[7] & !F1L209 # !F1_H_Cont[7] & (F1L209 # GND);

--F1L212 is VGA_Controller:u4|oCoord_X[7]~1433
F1L212 = CARRY(!F1L209 # !F1_H_Cont[7]);


--F1L214 is VGA_Controller:u4|oCoord_X[8]~1434
F1L214 = F1_H_Cont[8] & (GND # !F1L212) # !F1_H_Cont[8] & (F1L212 $ GND);

--F1L215 is VGA_Controller:u4|oCoord_X[8]~1435
F1L215 = CARRY(F1_H_Cont[8] # !F1L212);


--F1L217 is VGA_Controller:u4|oCoord_X[9]~1436
F1L217 = F1_H_Cont[9] $ !F1L215;


--R1_address_reg_a[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[3]
R1_address_reg_a[3] = DFFEAS(H1L128, M1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1_address_reg_a[2] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[2]
R1_address_reg_a[2] = DFFEAS(H1L126, M1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1_address_reg_a[1] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[1]
R1_address_reg_a[1] = DFFEAS(H1L124, M1__clk0,  ,  ,  ,  ,  ,  ,  );


--F1_oCoord_Y[0] is VGA_Controller:u4|oCoord_Y[0]
F1_oCoord_Y[0] = DFFEAS(F1_V_Cont[0], M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--H1L25 is VGA_OSD_RAM:u6|add~1377
H1L25 = CARRY(!F1_oCoord_Y[0]);


--H1L26 is VGA_OSD_RAM:u6|add~1378
H1L26 = F1_oCoord_Y[1] & (H1L25 # GND) # !F1_oCoord_Y[1] & !H1L25;

--H1L27 is VGA_OSD_RAM:u6|add~1379
H1L27 = CARRY(F1_oCoord_Y[1] # !H1L25);


--H1L28 is VGA_OSD_RAM:u6|add~1380
H1L28 = F1_oCoord_Y[2] & !H1L27 & VCC # !F1_oCoord_Y[2] & (H1L27 $ GND);

--H1L29 is VGA_OSD_RAM:u6|add~1381
H1L29 = CARRY(!F1_oCoord_Y[2] & !H1L27);


--H1L30 is VGA_OSD_RAM:u6|add~1382
H1L30 = F1_oCoord_Y[3] & (H1L29 # GND) # !F1_oCoord_Y[3] & !H1L29;

--H1L31 is VGA_OSD_RAM:u6|add~1383
H1L31 = CARRY(F1_oCoord_Y[3] # !H1L29);


--H1L32 is VGA_OSD_RAM:u6|add~1384
H1L32 = F1_oCoord_Y[4] & !H1L31 & VCC # !F1_oCoord_Y[4] & (H1L31 $ GND);

--H1L33 is VGA_OSD_RAM:u6|add~1385
H1L33 = CARRY(!F1_oCoord_Y[4] & !H1L31);


--H1L34 is VGA_OSD_RAM:u6|add~1386
H1L34 = F1_oCoord_Y[5] & (H1L33 # GND) # !F1_oCoord_Y[5] & !H1L33;

--H1L35 is VGA_OSD_RAM:u6|add~1387
H1L35 = CARRY(F1_oCoord_Y[5] # !H1L33);


--H1L36 is VGA_OSD_RAM:u6|add~1388
H1L36 = F1_oCoord_Y[6] & !H1L35 & VCC # !F1_oCoord_Y[6] & (H1L35 $ GND);

--H1L37 is VGA_OSD_RAM:u6|add~1389
H1L37 = CARRY(!F1_oCoord_Y[6] & !H1L35);


--H1L38 is VGA_OSD_RAM:u6|add~1390
H1L38 = F1_oCoord_Y[7] & (H1L37 # GND) # !F1_oCoord_Y[7] & !H1L37;

--H1L39 is VGA_OSD_RAM:u6|add~1391
H1L39 = CARRY(F1_oCoord_Y[7] # !H1L37);


--H1L40 is VGA_OSD_RAM:u6|add~1392
H1L40 = F1_oCoord_Y[8] & !H1L39 & VCC # !F1_oCoord_Y[8] & (H1L39 $ GND);

--H1L41 is VGA_OSD_RAM:u6|add~1393
H1L41 = CARRY(!F1_oCoord_Y[8] & !H1L39);


--H1L42 is VGA_OSD_RAM:u6|add~1394
H1L42 = F1_oCoord_Y[9] & (H1L41 # GND) # !F1_oCoord_Y[9] & !H1L41;

--H1L43 is VGA_OSD_RAM:u6|add~1395
H1L43 = CARRY(F1_oCoord_Y[9] # !H1L41);


--H1L44 is VGA_OSD_RAM:u6|add~1396
H1L44 = H1L43 $ GND;

--H1L45 is VGA_OSD_RAM:u6|add~1397
H1L45 = CARRY(!H1L43);


--H1L46 is VGA_OSD_RAM:u6|add~1398
H1L46 = !H1L45;


--H1L48 is VGA_OSD_RAM:u6|add~1400
H1L48 = H1L32 & (F1_oCoord_Y[0] $ VCC) # !H1L32 & F1_oCoord_Y[0] & VCC;

--H1L49 is VGA_OSD_RAM:u6|add~1401
H1L49 = CARRY(H1L32 & F1_oCoord_Y[0]);


--H1L50 is VGA_OSD_RAM:u6|add~1402
H1L50 = H1L34 & (F1_oCoord_Y[1] & H1L49 & VCC # !F1_oCoord_Y[1] & !H1L49) # !H1L34 & (F1_oCoord_Y[1] & !H1L49 # !F1_oCoord_Y[1] & (H1L49 # GND));

--H1L51 is VGA_OSD_RAM:u6|add~1403
H1L51 = CARRY(H1L34 & !F1_oCoord_Y[1] & !H1L49 # !H1L34 & (!H1L49 # !F1_oCoord_Y[1]));


--H1L52 is VGA_OSD_RAM:u6|add~1404
H1L52 = (H1L36 $ F1_oCoord_Y[2] $ !H1L51) # GND;

--H1L53 is VGA_OSD_RAM:u6|add~1405
H1L53 = CARRY(H1L36 & (F1_oCoord_Y[2] # !H1L51) # !H1L36 & F1_oCoord_Y[2] & !H1L51);


--H1L54 is VGA_OSD_RAM:u6|add~1406
H1L54 = H1L38 & (F1_oCoord_Y[3] & H1L53 & VCC # !F1_oCoord_Y[3] & !H1L53) # !H1L38 & (F1_oCoord_Y[3] & !H1L53 # !F1_oCoord_Y[3] & (H1L53 # GND));

--H1L55 is VGA_OSD_RAM:u6|add~1407
H1L55 = CARRY(H1L38 & !F1_oCoord_Y[3] & !H1L53 # !H1L38 & (!H1L53 # !F1_oCoord_Y[3]));


--H1L56 is VGA_OSD_RAM:u6|add~1408
H1L56 = (H1L40 $ F1_oCoord_Y[4] $ !H1L55) # GND;

--H1L57 is VGA_OSD_RAM:u6|add~1409
H1L57 = CARRY(H1L40 & (F1_oCoord_Y[4] # !H1L55) # !H1L40 & F1_oCoord_Y[4] & !H1L55);


--H1L58 is VGA_OSD_RAM:u6|add~1410
H1L58 = H1L42 & (F1_oCoord_Y[5] & H1L57 & VCC # !F1_oCoord_Y[5] & !H1L57) # !H1L42 & (F1_oCoord_Y[5] & !H1L57 # !F1_oCoord_Y[5] & (H1L57 # GND));

--H1L59 is VGA_OSD_RAM:u6|add~1411
H1L59 = CARRY(H1L42 & !F1_oCoord_Y[5] & !H1L57 # !H1L42 & (!H1L57 # !F1_oCoord_Y[5]));


--H1L60 is VGA_OSD_RAM:u6|add~1412
H1L60 = (H1L44 $ F1_oCoord_Y[6] $ !H1L59) # GND;

--H1L61 is VGA_OSD_RAM:u6|add~1413
H1L61 = CARRY(H1L44 & (F1_oCoord_Y[6] # !H1L59) # !H1L44 & F1_oCoord_Y[6] & !H1L59);


--H1L62 is VGA_OSD_RAM:u6|add~1414
H1L62 = H1L46 & (F1_oCoord_Y[7] & H1L61 & VCC # !F1_oCoord_Y[7] & !H1L61) # !H1L46 & (F1_oCoord_Y[7] & !H1L61 # !F1_oCoord_Y[7] & (H1L61 # GND));

--H1L63 is VGA_OSD_RAM:u6|add~1415
H1L63 = CARRY(H1L46 & !F1_oCoord_Y[7] & !H1L61 # !H1L46 & (!H1L61 # !F1_oCoord_Y[7]));


--H1L64 is VGA_OSD_RAM:u6|add~1416
H1L64 = (H1L46 $ F1_oCoord_Y[8] $ !H1L63) # GND;

--H1L65 is VGA_OSD_RAM:u6|add~1417
H1L65 = CARRY(H1L46 & (F1_oCoord_Y[8] # !H1L63) # !H1L46 & F1_oCoord_Y[8] & !H1L63);


--H1L66 is VGA_OSD_RAM:u6|add~1418
H1L66 = H1L46 & (F1_oCoord_Y[9] & H1L65 & VCC # !F1_oCoord_Y[9] & !H1L65) # !H1L46 & (F1_oCoord_Y[9] & !H1L65 # !F1_oCoord_Y[9] & (H1L65 # GND));

--H1L67 is VGA_OSD_RAM:u6|add~1419
H1L67 = CARRY(H1L46 & !F1_oCoord_Y[9] & !H1L65 # !H1L46 & (!H1L65 # !F1_oCoord_Y[9]));


--H1L68 is VGA_OSD_RAM:u6|add~1420
H1L68 = H1L46 $ !H1L67;


--F1_oAddress[17] is VGA_Controller:u4|oAddress[17]
F1_oAddress[17] = DFFEAS(F1L190, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[16] is VGA_Controller:u4|oAddress[16]
F1_oAddress[16] = DFFEAS(F1L187, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[15] is VGA_Controller:u4|oAddress[15]
F1_oAddress[15] = DFFEAS(F1L184, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[14] is VGA_Controller:u4|oAddress[14]
F1_oAddress[14] = DFFEAS(F1L181, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[13] is VGA_Controller:u4|oAddress[13]
F1_oAddress[13] = DFFEAS(F1L178, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[12] is VGA_Controller:u4|oAddress[12]
F1_oAddress[12] = DFFEAS(F1L175, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[11] is VGA_Controller:u4|oAddress[11]
F1_oAddress[11] = DFFEAS(F1L172, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[10] is VGA_Controller:u4|oAddress[10]
F1_oAddress[10] = DFFEAS(F1L169, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[9] is VGA_Controller:u4|oAddress[9]
F1_oAddress[9] = DFFEAS(F1L166, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[8] is VGA_Controller:u4|oAddress[8]
F1_oAddress[8] = DFFEAS(F1L163, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[7] is VGA_Controller:u4|oAddress[7]
F1_oAddress[7] = DFFEAS(F1L160, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[6] is VGA_Controller:u4|oAddress[6]
F1_oAddress[6] = DFFEAS(F1L157, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[5] is VGA_Controller:u4|oAddress[5]
F1_oAddress[5] = DFFEAS(F1L154, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[4] is VGA_Controller:u4|oAddress[4]
F1_oAddress[4] = DFFEAS(F1L151, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[3] is VGA_Controller:u4|oAddress[3]
F1_oAddress[3] = DFFEAS(F1L148, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--H1L70 is VGA_OSD_RAM:u6|add~1422
H1L70 = F1_oCoord_Y[0] & (F1_oAddress[3] $ VCC) # !F1_oCoord_Y[0] & (F1_oAddress[3] # GND);

--H1L71 is VGA_OSD_RAM:u6|add~1423
H1L71 = CARRY(F1_oAddress[3] # !F1_oCoord_Y[0]);


--H1L72 is VGA_OSD_RAM:u6|add~1424
H1L72 = H1L26 & (F1_oAddress[4] & !H1L71 # !F1_oAddress[4] & (H1L71 # GND)) # !H1L26 & (F1_oAddress[4] & H1L71 & VCC # !F1_oAddress[4] & !H1L71);

--H1L73 is VGA_OSD_RAM:u6|add~1425
H1L73 = CARRY(H1L26 & (!H1L71 # !F1_oAddress[4]) # !H1L26 & !F1_oAddress[4] & !H1L71);


--H1L74 is VGA_OSD_RAM:u6|add~1426
H1L74 = (H1L28 $ F1_oAddress[5] $ H1L73) # GND;

--H1L75 is VGA_OSD_RAM:u6|add~1427
H1L75 = CARRY(H1L28 & F1_oAddress[5] & !H1L73 # !H1L28 & (F1_oAddress[5] # !H1L73));


--H1L76 is VGA_OSD_RAM:u6|add~1428
H1L76 = H1L30 & (F1_oAddress[6] & !H1L75 # !F1_oAddress[6] & (H1L75 # GND)) # !H1L30 & (F1_oAddress[6] & H1L75 & VCC # !F1_oAddress[6] & !H1L75);

--H1L77 is VGA_OSD_RAM:u6|add~1429
H1L77 = CARRY(H1L30 & (!H1L75 # !F1_oAddress[6]) # !H1L30 & !F1_oAddress[6] & !H1L75);


--H1L78 is VGA_OSD_RAM:u6|add~1430
H1L78 = (H1L48 $ F1_oAddress[7] $ H1L77) # GND;

--H1L79 is VGA_OSD_RAM:u6|add~1431
H1L79 = CARRY(H1L48 & F1_oAddress[7] & !H1L77 # !H1L48 & (F1_oAddress[7] # !H1L77));


--H1L80 is VGA_OSD_RAM:u6|add~1432
H1L80 = H1L50 & (F1_oAddress[8] & !H1L79 # !F1_oAddress[8] & (H1L79 # GND)) # !H1L50 & (F1_oAddress[8] & H1L79 & VCC # !F1_oAddress[8] & !H1L79);

--H1L81 is VGA_OSD_RAM:u6|add~1433
H1L81 = CARRY(H1L50 & (!H1L79 # !F1_oAddress[8]) # !H1L50 & !F1_oAddress[8] & !H1L79);


--H1L82 is VGA_OSD_RAM:u6|add~1434
H1L82 = (H1L52 $ F1_oAddress[9] $ H1L81) # GND;

--H1L83 is VGA_OSD_RAM:u6|add~1435
H1L83 = CARRY(H1L52 & F1_oAddress[9] & !H1L81 # !H1L52 & (F1_oAddress[9] # !H1L81));


--H1L84 is VGA_OSD_RAM:u6|add~1436
H1L84 = H1L54 & (F1_oAddress[10] & !H1L83 # !F1_oAddress[10] & (H1L83 # GND)) # !H1L54 & (F1_oAddress[10] & H1L83 & VCC # !F1_oAddress[10] & !H1L83);

--H1L85 is VGA_OSD_RAM:u6|add~1437
H1L85 = CARRY(H1L54 & (!H1L83 # !F1_oAddress[10]) # !H1L54 & !F1_oAddress[10] & !H1L83);


--H1L86 is VGA_OSD_RAM:u6|add~1438
H1L86 = (H1L56 $ F1_oAddress[11] $ H1L85) # GND;

--H1L87 is VGA_OSD_RAM:u6|add~1439
H1L87 = CARRY(H1L56 & F1_oAddress[11] & !H1L85 # !H1L56 & (F1_oAddress[11] # !H1L85));


--H1L88 is VGA_OSD_RAM:u6|add~1440
H1L88 = H1L58 & (F1_oAddress[12] & !H1L87 # !F1_oAddress[12] & (H1L87 # GND)) # !H1L58 & (F1_oAddress[12] & H1L87 & VCC # !F1_oAddress[12] & !H1L87);

--H1L89 is VGA_OSD_RAM:u6|add~1441
H1L89 = CARRY(H1L58 & (!H1L87 # !F1_oAddress[12]) # !H1L58 & !F1_oAddress[12] & !H1L87);


--H1L90 is VGA_OSD_RAM:u6|add~1442
H1L90 = (H1L60 $ F1_oAddress[13] $ H1L89) # GND;

--H1L91 is VGA_OSD_RAM:u6|add~1443
H1L91 = CARRY(H1L60 & F1_oAddress[13] & !H1L89 # !H1L60 & (F1_oAddress[13] # !H1L89));


--H1L92 is VGA_OSD_RAM:u6|add~1444
H1L92 = H1L62 & (F1_oAddress[14] & !H1L91 # !F1_oAddress[14] & (H1L91 # GND)) # !H1L62 & (F1_oAddress[14] & H1L91 & VCC # !F1_oAddress[14] & !H1L91);

--H1L93 is VGA_OSD_RAM:u6|add~1445
H1L93 = CARRY(H1L62 & (!H1L91 # !F1_oAddress[14]) # !H1L62 & !F1_oAddress[14] & !H1L91);


--H1L94 is VGA_OSD_RAM:u6|add~1446
H1L94 = (H1L64 $ F1_oAddress[15] $ H1L93) # GND;

--H1L95 is VGA_OSD_RAM:u6|add~1447
H1L95 = CARRY(H1L64 & F1_oAddress[15] & !H1L93 # !H1L64 & (F1_oAddress[15] # !H1L93));


--H1L96 is VGA_OSD_RAM:u6|add~1448
H1L96 = H1L66 & (F1_oAddress[16] & !H1L95 # !F1_oAddress[16] & (H1L95 # GND)) # !H1L66 & (F1_oAddress[16] & H1L95 & VCC # !F1_oAddress[16] & !H1L95);

--H1L97 is VGA_OSD_RAM:u6|add~1449
H1L97 = CARRY(H1L66 & (!H1L95 # !F1_oAddress[16]) # !H1L66 & !F1_oAddress[16] & !H1L95);


--H1L98 is VGA_OSD_RAM:u6|add~1450
H1L98 = H1L68 $ F1_oAddress[17] $ H1L97;


--F1_oAddress[2] is VGA_Controller:u4|oAddress[2]
F1_oAddress[2] = DFFEAS(F1L145, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[1] is VGA_Controller:u4|oAddress[1]
F1_oAddress[1] = DFFEAS(F1L142, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--H1L100 is VGA_OSD_RAM:u6|add~1452
H1L100 = F1_oAddress[1] $ VCC;

--H1L101 is VGA_OSD_RAM:u6|add~1453
H1L101 = CARRY(F1_oAddress[1]);


--H1L102 is VGA_OSD_RAM:u6|add~1454
H1L102 = F1_oAddress[2] & H1L101 & VCC # !F1_oAddress[2] & !H1L101;

--H1L103 is VGA_OSD_RAM:u6|add~1455
H1L103 = CARRY(!F1_oAddress[2] & !H1L101);


--H1L104 is VGA_OSD_RAM:u6|add~1456
H1L104 = H1L70 & (GND # !H1L103) # !H1L70 & (H1L103 $ GND);

--H1L105 is VGA_OSD_RAM:u6|add~1457
H1L105 = CARRY(H1L70 # !H1L103);


--H1L106 is VGA_OSD_RAM:u6|add~1458
H1L106 = H1L72 & H1L105 & VCC # !H1L72 & !H1L105;

--H1L107 is VGA_OSD_RAM:u6|add~1459
H1L107 = CARRY(!H1L72 & !H1L105);


--H1L108 is VGA_OSD_RAM:u6|add~1460
H1L108 = H1L74 & (GND # !H1L107) # !H1L74 & (H1L107 $ GND);

--H1L109 is VGA_OSD_RAM:u6|add~1461
H1L109 = CARRY(H1L74 # !H1L107);


--H1L110 is VGA_OSD_RAM:u6|add~1462
H1L110 = H1L76 & !H1L109 # !H1L76 & (H1L109 # GND);

--H1L111 is VGA_OSD_RAM:u6|add~1463
H1L111 = CARRY(!H1L109 # !H1L76);


--H1L112 is VGA_OSD_RAM:u6|add~1464
H1L112 = H1L78 & (H1L111 $ GND) # !H1L78 & !H1L111 & VCC;

--H1L113 is VGA_OSD_RAM:u6|add~1465
H1L113 = CARRY(H1L78 & !H1L111);


--H1L114 is VGA_OSD_RAM:u6|add~1466
H1L114 = H1L80 & !H1L113 # !H1L80 & (H1L113 # GND);

--H1L115 is VGA_OSD_RAM:u6|add~1467
H1L115 = CARRY(!H1L113 # !H1L80);


--H1L116 is VGA_OSD_RAM:u6|add~1468
H1L116 = H1L82 & (GND # !H1L115) # !H1L82 & (H1L115 $ GND);

--H1L117 is VGA_OSD_RAM:u6|add~1469
H1L117 = CARRY(H1L82 # !H1L115);


--H1L118 is VGA_OSD_RAM:u6|add~1470
H1L118 = H1L84 & !H1L117 # !H1L84 & (H1L117 # GND);

--H1L119 is VGA_OSD_RAM:u6|add~1471
H1L119 = CARRY(!H1L117 # !H1L84);


--H1L120 is VGA_OSD_RAM:u6|add~1472
H1L120 = H1L86 & (GND # !H1L119) # !H1L86 & (H1L119 $ GND);

--H1L121 is VGA_OSD_RAM:u6|add~1473
H1L121 = CARRY(H1L86 # !H1L119);


--H1L122 is VGA_OSD_RAM:u6|add~1474
H1L122 = H1L88 & H1L121 & VCC # !H1L88 & !H1L121;

--H1L123 is VGA_OSD_RAM:u6|add~1475
H1L123 = CARRY(!H1L88 & !H1L121);


--H1L124 is VGA_OSD_RAM:u6|add~1476
H1L124 = H1L90 & (H1L123 $ GND) # !H1L90 & !H1L123 & VCC;

--H1L125 is VGA_OSD_RAM:u6|add~1477
H1L125 = CARRY(H1L90 & !H1L123);


--H1L126 is VGA_OSD_RAM:u6|add~1478
H1L126 = H1L92 & !H1L125 # !H1L92 & (H1L125 # GND);

--H1L127 is VGA_OSD_RAM:u6|add~1479
H1L127 = CARRY(!H1L125 # !H1L92);


--H1L128 is VGA_OSD_RAM:u6|add~1480
H1L128 = H1L94 & (GND # !H1L127) # !H1L94 & (H1L127 $ GND);

--H1L129 is VGA_OSD_RAM:u6|add~1481
H1L129 = CARRY(H1L94 # !H1L127);


--H1L130 is VGA_OSD_RAM:u6|add~1482
H1L130 = H1L96 & H1L129 & VCC # !H1L96 & !H1L129;

--H1L131 is VGA_OSD_RAM:u6|add~1483
H1L131 = CARRY(!H1L96 & !H1L129);


--H1L132 is VGA_OSD_RAM:u6|add~1484
H1L132 = H1L98 $ H1L131;


--S3L93 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3345w[3]~15
S3L93 = H1L124 & !H1L122 & !H1L126;


--S3L106 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3438w[3]~24
S3L106 = H1L132 & H1L130 & S3L93 & !H1L128;


--S3L23 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2963w[3]~14
S3L23 = H1L122 & !H1L124 & !H1L126;


--S3L105 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3428w[3]~10
S3L105 = H1L132 & H1L130 & S3L23 & !H1L128;


--S3L88 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3324w[3]~15
S3L88 = !H1L122 & !H1L124 & !H1L126;


--S3L104 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3417w[3]~11
S3L104 = H1L132 & H1L130 & S3L88 & !H1L128;


--R1_address_reg_a[0] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[0]
R1_address_reg_a[0] = DFFEAS(H1L122, M1__clk0,  ,  ,  ,  ,  ,  ,  );


--S3L17 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2929w[3]~21
S3L17 = H1L124 & H1L126;


--S3L52 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3127w[3]~18
S3L52 = H1L130 & !H1L132;


--S3_w_anode3199w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3199w[3]
S3_w_anode3199w[3] = H1L128 & S3L17 & S3L52 & !H1L122;


--S3L13 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2909w[3]~22
S3L13 = H1L126 & !H1L124;


--S3_w_anode3189w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3189w[3]
S3_w_anode3189w[3] = H1L122 & H1L128 & S3L13 & S3L52;


--S3_w_anode3179w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3179w[3]
S3_w_anode3179w[3] = H1L128 & S3L13 & S3L52 & !H1L122;


--S3_w_anode3209w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3209w[3]
S3_w_anode3209w[3] = H1L122 & H1L128 & S3L17 & S3L52;


--S3_w_anode3096w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3096w[3]
S3_w_anode3096w[3] = H1L122 & S3L13 & S3L52 & !H1L128;


--S3_w_anode3106w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3106w[3]
S3_w_anode3106w[3] = S3L17 & S3L52 & !H1L122 & !H1L128;


--S3_w_anode3086w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3086w[3]
S3_w_anode3086w[3] = S3L13 & S3L52 & !H1L122 & !H1L128;


--S3_w_anode3116w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3116w[3]
S3_w_anode3116w[3] = H1L122 & S3L17 & S3L52 & !H1L128;


--S3L9 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2889w[3]~16
S3L9 = H1L124 & !H1L126;


--S3_w_anode3076w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3076w[3]
S3_w_anode3076w[3] = H1L122 & S3L9 & S3L52 & !H1L128;


--S3_w_anode3169w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3169w[3]
S3_w_anode3169w[3] = H1L122 & H1L128 & S3L9 & S3L52;


--R1_address_reg_a[5] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[5]
R1_address_reg_a[5] = DFFEAS(H1L132, M1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1_address_reg_a[4] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[4]
R1_address_reg_a[4] = DFFEAS(H1L130, M1__clk0,  ,  ,  ,  ,  ,  ,  );


--S3L18 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2941w[3]~20
S3L18 = H1L128 & !H1L130;


--S3_w_anode3385w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3385w[3]
S3_w_anode3385w[3] = H1L132 & S3L18 & S3L17 & !H1L122;


--S3_w_anode3375w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3375w[3]
S3_w_anode3375w[3] = H1L132 & H1L122 & S3L18 & S3L13;


--S3_w_anode3365w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3365w[3]
S3_w_anode3365w[3] = H1L132 & S3L18 & S3L13 & !H1L122;


--S3_w_anode3395w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3395w[3]
S3_w_anode3395w[3] = H1L132 & H1L122 & S3L18 & S3L17;


--S3_w_anode3003w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3003w[3]
S3_w_anode3003w[3] = H1L122 & S3L18 & S3L13 & !H1L132;


--S3_w_anode3013w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3013w[3]
S3_w_anode3013w[3] = S3L18 & S3L17 & !H1L132 & !H1L122;


--S3_w_anode2993w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2993w[3]
S3_w_anode2993w[3] = S3L18 & S3L13 & !H1L132 & !H1L122;


--S3_w_anode3023w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3023w[3]
S3_w_anode3023w[3] = H1L122 & S3L18 & S3L17 & !H1L132;


--S3L69 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3220w[3]~28
S3L69 = !H1L128 & !H1L130;


--S3_w_anode3282w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3282w[3]
S3_w_anode3282w[3] = H1L132 & H1L122 & S3L13 & S3L69;


--S3_w_anode3292w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3292w[3]
S3_w_anode3292w[3] = H1L132 & S3L17 & S3L69 & !H1L122;


--S3_w_anode3272w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3272w[3]
S3_w_anode3272w[3] = H1L132 & S3L13 & S3L69 & !H1L122;


--S3_w_anode3302w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3302w[3]
S3_w_anode3302w[3] = H1L132 & H1L122 & S3L17 & S3L69;


--S3L14 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2919w[3]~16
S3L14 = S3L17 & S3L69 & !H1L132 & !H1L122;


--S3_w_anode2909w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2909w[3]
S3_w_anode2909w[3] = H1L122 & S3L13 & S3L69 & !H1L132;


--S3L10 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2899w[3]~25
S3L10 = S3L13 & S3L69 & !H1L132 & !H1L122;


--S3_w_anode2929w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2929w[3]
S3_w_anode2929w[3] = H1L122 & S3L17 & S3L69 & !H1L132;


--S3_w_anode3262w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3262w[3]
S3_w_anode3262w[3] = H1L132 & H1L122 & S3L9 & S3L69;


--S3L5 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2869w[3]~21
S3L5 = !H1L124 & !H1L126;


--S3_w_anode2869w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2869w[3]
S3_w_anode2869w[3] = H1L122 & S3L5 & S3L69 & !H1L132;


--S3_w_anode2889w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2889w[3]
S3_w_anode2889w[3] = H1L122 & S3L9 & S3L69 & !H1L132;


--S3_w_anode3355w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3355w[3]
S3_w_anode3355w[3] = H1L132 & H1L122 & S3L18 & S3L9;


--S3_w_anode2983w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2983w[3]
S3_w_anode2983w[3] = H1L122 & S3L18 & S3L9 & !H1L132;


--H1_ADDR_d[0] is VGA_OSD_RAM:u6|ADDR_d[0]
H1_ADDR_d[0] = DFFEAS(F1_oAddress[0], M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--H1_ADDR_d[1] is VGA_OSD_RAM:u6|ADDR_d[1]
H1_ADDR_d[1] = DFFEAS(H1L100, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--H1_ADDR_d[2] is VGA_OSD_RAM:u6|ADDR_d[2]
H1_ADDR_d[2] = DFFEAS(H1L102, M1__clk0, KEY[0],  ,  ,  ,  ,  ,  );


--K1L5 is AUDIO_DAC:u8|BCK_DIV~127
K1L5 = K1_BCK_DIV[1] & K1_BCK_DIV[0] & !K1_BCK_DIV[2] # !K1_BCK_DIV[1] & !K1_BCK_DIV[0] & K1_BCK_DIV[2];


--K1L6 is AUDIO_DAC:u8|BCK_DIV~128
K1L6 = !K1_BCK_DIV[2] & (K1_BCK_DIV[1] $ K1_BCK_DIV[0]);


--K1L7 is AUDIO_DAC:u8|BCK_DIV~129
K1L7 = !K1_BCK_DIV[0] & (!K1_BCK_DIV[1] # !K1_BCK_DIV[2]);


--V1L57 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1104
V1L57 = V1L40Q & V1L46Q & V1L49Q & V1L43Q;


--V1_SD[9] is I2C_AV_Config:u7|I2C_Controller:u0|SD[9]
V1_SD[9] = DFFEAS(J1_mI2C_DATA[9], J1_mI2C_CTRL_CLK,  ,  , V1L36,  ,  ,  ,  );


--V1_SD[2] is I2C_AV_Config:u7|I2C_Controller:u0|SD[2]
V1_SD[2] = DFFEAS(J1_mI2C_DATA[2], J1_mI2C_CTRL_CLK,  ,  , V1L36,  ,  ,  ,  );


--V1L58 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1105
V1L58 = V1L49Q & V1_SD[9] # !V1L49Q & (V1_SD[2]);


--V1_SD[1] is I2C_AV_Config:u7|I2C_Controller:u0|SD[1]
V1_SD[1] = DFFEAS(J1_mI2C_DATA[1], J1_mI2C_CTRL_CLK,  ,  , V1L36,  ,  ,  ,  );


--V1L59 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1106
V1L59 = V1L40Q & V1L58 # !V1L40Q & (V1_SD[1] & !V1L49Q);


--V1_SD[7] is I2C_AV_Config:u7|I2C_Controller:u0|SD[7]
V1_SD[7] = DFFEAS(J1_mI2C_DATA[7], J1_mI2C_CTRL_CLK,  ,  , V1L36,  ,  ,  ,  );


--V1_SD[0] is I2C_AV_Config:u7|I2C_Controller:u0|SD[0]
V1_SD[0] = DFFEAS(J1_mI2C_DATA[0], J1_mI2C_CTRL_CLK,  ,  , V1L36,  ,  ,  ,  );


--V1L60 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1107
V1L60 = V1L40Q & (V1_SD[0] # V1L49Q) # !V1L40Q & (V1_SD[7] # !V1L49Q);


--V1_SD[11] is I2C_AV_Config:u7|I2C_Controller:u0|SD[11]
V1_SD[11] = DFFEAS(J1_mI2C_DATA[11], J1_mI2C_CTRL_CLK,  ,  , V1L36,  ,  ,  ,  );


--V1_SD[10] is I2C_AV_Config:u7|I2C_Controller:u0|SD[10]
V1_SD[10] = DFFEAS(J1_mI2C_DATA[10], J1_mI2C_CTRL_CLK,  ,  , V1L36,  ,  ,  ,  );


--V1L61 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1108
V1L61 = V1L40Q & V1_SD[11] # !V1L40Q & (V1_SD[10]);


--V1_SD[4] is I2C_AV_Config:u7|I2C_Controller:u0|SD[4]
V1_SD[4] = DFFEAS(J1_mI2C_DATA[4], J1_mI2C_CTRL_CLK,  ,  , V1L36,  ,  ,  ,  );


--V1L62 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1109
V1L62 = V1L49Q & V1L61 # !V1L49Q & (V1_SD[4]);


--V1L63 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1110
V1L63 = V1L43Q & (V1L46Q & (V1L62) # !V1L46Q & V1L60) # !V1L43Q & (!V1L46Q);


--V1_SD[6] is I2C_AV_Config:u7|I2C_Controller:u0|SD[6]
V1_SD[6] = DFFEAS(J1_mI2C_DATA[6], J1_mI2C_CTRL_CLK,  ,  , V1L36,  ,  ,  ,  );


--V1L64 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1111
V1L64 = V1L49Q & V1_SD[6] # !V1L49Q & (!V1L40Q & !V1L25Q);


--V1L65 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1112
V1L65 = V1L43Q & (V1L63) # !V1L43Q & (V1L63 & (V1L64) # !V1L63 & V1L59);


--V1_SD[12] is I2C_AV_Config:u7|I2C_Controller:u0|SD[12]
V1_SD[12] = DFFEAS(J1_mI2C_DATA[12], J1_mI2C_CTRL_CLK,  ,  , V1L36,  ,  ,  ,  );


--V1L66 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1113
V1L66 = V1L40Q & (V1L46Q & (!V1L43Q) # !V1L46Q & (V1L43Q # !V1L49Q)) # !V1L40Q & (V1L49Q & (V1L46Q # !V1L43Q) # !V1L49Q & (V1L43Q));


--V1L67 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1114
V1L67 = V1L49Q & (V1L40Q $ (!V1L46Q & V1L43Q)) # !V1L49Q & V1L46Q & (V1L40Q $ !V1L43Q);


--V1L68 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1115
V1L68 = V1L66 & !V1L25Q & (V1L67) # !V1L66 & (V1_SD[12] # V1L67);


--V1L69 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1116
V1L69 = V1L55Q & (V1L52Q & (V1L68) # !V1L52Q & V1L65) # !V1L55Q & (!V1L52Q);


--V1L70 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1117
V1L70 = V1L55Q & (!V1L69) # !V1L55Q & V1L25Q & (V1L69 # !V1L57);


--V1L10 is I2C_AV_Config:u7|I2C_Controller:u0|ACK3~215
V1L10 = V1L40Q & V1L55Q & (V1L37 # V1L56);


--V1L71 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1118
V1L71 = V1L40Q & (A1L284 & !V1L46Q) # !V1L40Q & V1_ACK1;


--V1L2 is I2C_AV_Config:u7|I2C_Controller:u0|ACK1~170
V1L2 = V1L52Q & V1L55Q & (V1L46Q $ !V1L49Q);


--V1L3 is I2C_AV_Config:u7|I2C_Controller:u0|ACK1~171
V1L3 = V1L43Q & (V1L2 & V1L71 # !V1L2 & (V1_ACK1)) # !V1L43Q & (V1_ACK1);


--V1L6 is I2C_AV_Config:u7|I2C_Controller:u0|ACK2~251
V1L6 = V1L52Q & (!V1L46Q # !V1L40Q) # !V1L52Q & (V1L40Q # V1L46Q) # !V1L55Q;


--J1L21 is I2C_AV_Config:u7|Select~137
J1L21 = !J1_mSetup_ST.10 & (V1_END # J1L89 # !J1_mSetup_ST.01);


--F1L95 is VGA_Controller:u4|add~1144
F1L95 = F1_oCoord_Y[0] & (F1_oCoord_Y[2] $ VCC) # !F1_oCoord_Y[0] & F1_oCoord_Y[2] & VCC;

--F1L96 is VGA_Controller:u4|add~1145
F1L96 = CARRY(F1_oCoord_Y[0] & F1_oCoord_Y[2]);


--F1L97 is VGA_Controller:u4|add~1146
F1L97 = F1_oCoord_Y[1] & (F1_oCoord_Y[3] & F1L96 & VCC # !F1_oCoord_Y[3] & !F1L96) # !F1_oCoord_Y[1] & (F1_oCoord_Y[3] & !F1L96 # !F1_oCoord_Y[3] & (F1L96 # GND));

--F1L98 is VGA_Controller:u4|add~1147
F1L98 = CARRY(F1_oCoord_Y[1] & !F1_oCoord_Y[3] & !F1L96 # !F1_oCoord_Y[1] & (!F1L96 # !F1_oCoord_Y[3]));


--F1L99 is VGA_Controller:u4|add~1148
F1L99 = (F1_oCoord_Y[2] $ F1_oCoord_Y[4] $ !F1L98) # GND;

--F1L100 is VGA_Controller:u4|add~1149
F1L100 = CARRY(F1_oCoord_Y[2] & (F1_oCoord_Y[4] # !F1L98) # !F1_oCoord_Y[2] & F1_oCoord_Y[4] & !F1L98);


--F1L101 is VGA_Controller:u4|add~1150
F1L101 = F1_oCoord_Y[3] & (F1_oCoord_Y[5] & F1L100 & VCC # !F1_oCoord_Y[5] & !F1L100) # !F1_oCoord_Y[3] & (F1_oCoord_Y[5] & !F1L100 # !F1_oCoord_Y[5] & (F1L100 # GND));

--F1L102 is VGA_Controller:u4|add~1151
F1L102 = CARRY(F1_oCoord_Y[3] & !F1_oCoord_Y[5] & !F1L100 # !F1_oCoord_Y[3] & (!F1L100 # !F1_oCoord_Y[5]));


--F1L103 is VGA_Controller:u4|add~1152
F1L103 = (F1_oCoord_Y[4] $ F1_oCoord_Y[6] $ !F1L102) # GND;

--F1L104 is VGA_Controller:u4|add~1153
F1L104 = CARRY(F1_oCoord_Y[4] & (F1_oCoord_Y[6] # !F1L102) # !F1_oCoord_Y[4] & F1_oCoord_Y[6] & !F1L102);


--F1L105 is VGA_Controller:u4|add~1154
F1L105 = F1_oCoord_Y[5] & (F1_oCoord_Y[7] & F1L104 & VCC # !F1_oCoord_Y[7] & !F1L104) # !F1_oCoord_Y[5] & (F1_oCoord_Y[7] & !F1L104 # !F1_oCoord_Y[7] & (F1L104 # GND));

--F1L106 is VGA_Controller:u4|add~1155
F1L106 = CARRY(F1_oCoord_Y[5] & !F1_oCoord_Y[7] & !F1L104 # !F1_oCoord_Y[5] & (!F1L104 # !F1_oCoord_Y[7]));


--F1L107 is VGA_Controller:u4|add~1156
F1L107 = (F1_oCoord_Y[6] $ F1_oCoord_Y[8] $ !F1L106) # GND;

--F1L108 is VGA_Controller:u4|add~1157
F1L108 = CARRY(F1_oCoord_Y[6] & (F1_oCoord_Y[8] # !F1L106) # !F1_oCoord_Y[6] & F1_oCoord_Y[8] & !F1L106);


--F1L109 is VGA_Controller:u4|add~1158
F1L109 = F1_oCoord_Y[7] & (F1_oCoord_Y[9] & F1L108 & VCC # !F1_oCoord_Y[9] & !F1L108) # !F1_oCoord_Y[7] & (F1_oCoord_Y[9] & !F1L108 # !F1_oCoord_Y[9] & (F1L108 # GND));

--F1L110 is VGA_Controller:u4|add~1159
F1L110 = CARRY(F1_oCoord_Y[7] & !F1_oCoord_Y[9] & !F1L108 # !F1_oCoord_Y[7] & (!F1L108 # !F1_oCoord_Y[9]));


--F1L111 is VGA_Controller:u4|add~1160
F1L111 = F1_oCoord_Y[8] $ !F1L110;


--F1L113 is VGA_Controller:u4|add~1162
F1L113 = F1_oCoord_Y[0] & (F1_oCoord_X[7] $ VCC) # !F1_oCoord_Y[0] & F1_oCoord_X[7] & VCC;

--F1L114 is VGA_Controller:u4|add~1163
F1L114 = CARRY(F1_oCoord_Y[0] & F1_oCoord_X[7]);


--F1L115 is VGA_Controller:u4|add~1164
F1L115 = F1_oCoord_Y[1] & (F1_oCoord_X[8] & F1L114 & VCC # !F1_oCoord_X[8] & !F1L114) # !F1_oCoord_Y[1] & (F1_oCoord_X[8] & !F1L114 # !F1_oCoord_X[8] & (F1L114 # GND));

--F1L116 is VGA_Controller:u4|add~1165
F1L116 = CARRY(F1_oCoord_Y[1] & !F1_oCoord_X[8] & !F1L114 # !F1_oCoord_Y[1] & (!F1L114 # !F1_oCoord_X[8]));


--F1L117 is VGA_Controller:u4|add~1166
F1L117 = (F1L95 $ F1_oCoord_X[9] $ !F1L116) # GND;

--F1L118 is VGA_Controller:u4|add~1167
F1L118 = CARRY(F1L95 & (F1_oCoord_X[9] # !F1L116) # !F1L95 & F1_oCoord_X[9] & !F1L116);


--F1L119 is VGA_Controller:u4|add~1168
F1L119 = F1L97 & !F1L118 # !F1L97 & (F1L118 # GND);

--F1L120 is VGA_Controller:u4|add~1169
F1L120 = CARRY(!F1L118 # !F1L97);


--F1L121 is VGA_Controller:u4|add~1170
F1L121 = F1L99 & (F1L120 $ GND) # !F1L99 & !F1L120 & VCC;

--F1L122 is VGA_Controller:u4|add~1171
F1L122 = CARRY(F1L99 & !F1L120);


--F1L123 is VGA_Controller:u4|add~1172
F1L123 = F1L101 & !F1L122 # !F1L101 & (F1L122 # GND);

--F1L124 is VGA_Controller:u4|add~1173
F1L124 = CARRY(!F1L122 # !F1L101);


--F1L125 is VGA_Controller:u4|add~1174
F1L125 = F1L103 & (F1L124 $ GND) # !F1L103 & !F1L124 & VCC;

--F1L126 is VGA_Controller:u4|add~1175
F1L126 = CARRY(F1L103 & !F1L124);


--F1L127 is VGA_Controller:u4|add~1176
F1L127 = F1L105 & !F1L126 # !F1L105 & (F1L126 # GND);

--F1L128 is VGA_Controller:u4|add~1177
F1L128 = CARRY(!F1L126 # !F1L105);


--F1L129 is VGA_Controller:u4|add~1178
F1L129 = F1L107 & (F1L128 $ GND) # !F1L107 & !F1L128 & VCC;

--F1L130 is VGA_Controller:u4|add~1179
F1L130 = CARRY(F1L107 & !F1L128);


--F1L131 is VGA_Controller:u4|add~1180
F1L131 = F1L109 & !F1L130 # !F1L109 & (F1L130 # GND);

--F1L132 is VGA_Controller:u4|add~1181
F1L132 = CARRY(!F1L130 # !F1L109);


--F1L133 is VGA_Controller:u4|add~1182
F1L133 = F1L111 $ !F1L132;


--F1_oCoord_X[1] is VGA_Controller:u4|oCoord_X[1]
F1_oCoord_X[1] = DFFEAS(F1_H_Cont[1], M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_X[0] is VGA_Controller:u4|oCoord_X[0]
F1_oCoord_X[0] = DFFEAS(F1_H_Cont[0], M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--F1L139 is VGA_Controller:u4|oAddress[0]~163
F1L139 = F1_oCoord_X[0] $ VCC;

--F1L140 is VGA_Controller:u4|oAddress[0]~164
F1L140 = CARRY(F1_oCoord_X[0]);


--F1L142 is VGA_Controller:u4|oAddress[1]~165
F1L142 = F1_oCoord_X[1] & !F1L140 # !F1_oCoord_X[1] & (F1L140 # GND);

--F1L143 is VGA_Controller:u4|oAddress[1]~166
F1L143 = CARRY(!F1L140 # !F1_oCoord_X[1]);


--F1L145 is VGA_Controller:u4|oAddress[2]~167
F1L145 = F1_oCoord_X[2] & (GND # !F1L143) # !F1_oCoord_X[2] & (F1L143 $ GND);

--F1L146 is VGA_Controller:u4|oAddress[2]~168
F1L146 = CARRY(F1_oCoord_X[2] # !F1L143);


--F1L148 is VGA_Controller:u4|oAddress[3]~169
F1L148 = F1_oCoord_X[3] & F1L146 & VCC # !F1_oCoord_X[3] & !F1L146;

--F1L149 is VGA_Controller:u4|oAddress[3]~170
F1L149 = CARRY(!F1_oCoord_X[3] & !F1L146);


--F1L151 is VGA_Controller:u4|oAddress[4]~171
F1L151 = F1_oCoord_X[4] & (GND # !F1L149) # !F1_oCoord_X[4] & (F1L149 $ GND);

--F1L152 is VGA_Controller:u4|oAddress[4]~172
F1L152 = CARRY(F1_oCoord_X[4] # !F1L149);


--F1L154 is VGA_Controller:u4|oAddress[5]~173
F1L154 = F1_oCoord_X[5] & F1L152 & VCC # !F1_oCoord_X[5] & !F1L152;

--F1L155 is VGA_Controller:u4|oAddress[5]~174
F1L155 = CARRY(!F1_oCoord_X[5] & !F1L152);


--F1L157 is VGA_Controller:u4|oAddress[6]~175
F1L157 = F1_oCoord_X[6] & (GND # !F1L155) # !F1_oCoord_X[6] & (F1L155 $ GND);

--F1L158 is VGA_Controller:u4|oAddress[6]~176
F1L158 = CARRY(F1_oCoord_X[6] # !F1L155);


--F1L160 is VGA_Controller:u4|oAddress[7]~177
F1L160 = F1L113 & F1L158 & VCC # !F1L113 & !F1L158;

--F1L161 is VGA_Controller:u4|oAddress[7]~178
F1L161 = CARRY(!F1L113 & !F1L158);


--F1L163 is VGA_Controller:u4|oAddress[8]~179
F1L163 = F1L115 & (GND # !F1L161) # !F1L115 & (F1L161 $ GND);

--F1L164 is VGA_Controller:u4|oAddress[8]~180
F1L164 = CARRY(F1L115 # !F1L161);


--F1L166 is VGA_Controller:u4|oAddress[9]~181
F1L166 = F1L117 & F1L164 & VCC # !F1L117 & !F1L164;

--F1L167 is VGA_Controller:u4|oAddress[9]~182
F1L167 = CARRY(!F1L117 & !F1L164);


--F1L169 is VGA_Controller:u4|oAddress[10]~183
F1L169 = F1L119 & (GND # !F1L167) # !F1L119 & (F1L167 $ GND);

--F1L170 is VGA_Controller:u4|oAddress[10]~184
F1L170 = CARRY(F1L119 # !F1L167);


--F1L172 is VGA_Controller:u4|oAddress[11]~185
F1L172 = F1L121 & F1L170 & VCC # !F1L121 & !F1L170;

--F1L173 is VGA_Controller:u4|oAddress[11]~186
F1L173 = CARRY(!F1L121 & !F1L170);


--F1L175 is VGA_Controller:u4|oAddress[12]~187
F1L175 = F1L123 & (GND # !F1L173) # !F1L123 & (F1L173 $ GND);

--F1L176 is VGA_Controller:u4|oAddress[12]~188
F1L176 = CARRY(F1L123 # !F1L173);


--F1L178 is VGA_Controller:u4|oAddress[13]~189
F1L178 = F1L125 & F1L176 & VCC # !F1L125 & !F1L176;

--F1L179 is VGA_Controller:u4|oAddress[13]~190
F1L179 = CARRY(!F1L125 & !F1L176);


--F1L181 is VGA_Controller:u4|oAddress[14]~191
F1L181 = F1L127 & (GND # !F1L179) # !F1L127 & (F1L179 $ GND);

--F1L182 is VGA_Controller:u4|oAddress[14]~192
F1L182 = CARRY(F1L127 # !F1L179);


--F1L184 is VGA_Controller:u4|oAddress[15]~193
F1L184 = F1L129 & F1L182 & VCC # !F1L129 & !F1L182;

--F1L185 is VGA_Controller:u4|oAddress[15]~194
F1L185 = CARRY(!F1L129 & !F1L182);


--F1L187 is VGA_Controller:u4|oAddress[16]~195
F1L187 = F1L131 & (GND # !F1L185) # !F1L131 & (F1L185 $ GND);

--F1L188 is VGA_Controller:u4|oAddress[16]~196
F1L188 = CARRY(F1L131 # !F1L185);


--F1L190 is VGA_Controller:u4|oAddress[17]~197
F1L190 = F1L133 $ !F1L188;


--F1_oAddress[0] is VGA_Controller:u4|oAddress[0]
F1_oAddress[0] = DFFEAS(F1L139, M1__clk0, KEY[0],  , F1L136,  ,  ,  ,  );


--J1_mI2C_DATA[9] is I2C_AV_Config:u7|mI2C_DATA[9]
J1_mI2C_DATA[9] = DFFEAS(J1L91, J1_mI2C_CTRL_CLK,  ,  , J1L84,  ,  ,  ,  );


--J1_mI2C_DATA[2] is I2C_AV_Config:u7|mI2C_DATA[2]
J1_mI2C_DATA[2] = DFFEAS(J1L1, J1_mI2C_CTRL_CLK,  ,  , J1L84,  ,  ,  ,  );


--J1_mI2C_DATA[1] is I2C_AV_Config:u7|mI2C_DATA[1]
J1_mI2C_DATA[1] = DFFEAS(J1L92, J1_mI2C_CTRL_CLK,  ,  , J1L84,  ,  ,  ,  );


--J1_mI2C_DATA[7] is I2C_AV_Config:u7|mI2C_DATA[7]
J1_mI2C_DATA[7] = DFFEAS(J1L2, J1_mI2C_CTRL_CLK,  ,  , J1L84,  ,  ,  ,  );


--J1_mI2C_DATA[0] is I2C_AV_Config:u7|mI2C_DATA[0]
J1_mI2C_DATA[0] = DFFEAS(J1L93, J1_mI2C_CTRL_CLK,  ,  , J1L84,  ,  ,  ,  );


--J1_mI2C_DATA[11] is I2C_AV_Config:u7|mI2C_DATA[11]
J1_mI2C_DATA[11] = DFFEAS(J1L94, J1_mI2C_CTRL_CLK,  ,  , J1L84,  ,  ,  ,  );


--J1_mI2C_DATA[10] is I2C_AV_Config:u7|mI2C_DATA[10]
J1_mI2C_DATA[10] = DFFEAS(J1L95, J1_mI2C_CTRL_CLK,  ,  , J1L84,  ,  ,  ,  );


--J1_mI2C_DATA[4] is I2C_AV_Config:u7|mI2C_DATA[4]
J1_mI2C_DATA[4] = DFFEAS(J1L96, J1_mI2C_CTRL_CLK,  ,  , J1L84,  ,  ,  ,  );


--J1_mI2C_DATA[6] is I2C_AV_Config:u7|mI2C_DATA[6]
J1_mI2C_DATA[6] = DFFEAS(J1L97, J1_mI2C_CTRL_CLK,  ,  , J1L84,  ,  ,  ,  );


--J1_mI2C_DATA[12] is I2C_AV_Config:u7|mI2C_DATA[12]
J1_mI2C_DATA[12] = DFFEAS(J1L3, J1_mI2C_CTRL_CLK,  ,  , J1L84,  ,  ,  ,  );


--J1_LUT_INDEX[0] is I2C_AV_Config:u7|LUT_INDEX[0]
J1_LUT_INDEX[0] = DFFEAS(J1L6, J1_mI2C_CTRL_CLK, KEY[0],  ,  ,  ,  ,  ,  );


--J1_LUT_INDEX[1] is I2C_AV_Config:u7|LUT_INDEX[1]
J1_LUT_INDEX[1] = DFFEAS(J1L8, J1_mI2C_CTRL_CLK, KEY[0],  ,  ,  ,  ,  ,  );


--J1_LUT_INDEX[2] is I2C_AV_Config:u7|LUT_INDEX[2]
J1_LUT_INDEX[2] = DFFEAS(J1L11, J1_mI2C_CTRL_CLK, KEY[0],  ,  ,  ,  ,  ,  );


--J1_LUT_INDEX[3] is I2C_AV_Config:u7|LUT_INDEX[3]
J1_LUT_INDEX[3] = DFFEAS(J1L13, J1_mI2C_CTRL_CLK, KEY[0],  ,  ,  ,  ,  ,  );


--J1L91 is I2C_AV_Config:u7|reduce_or~73
J1L91 = !J1_LUT_INDEX[0] & (J1_LUT_INDEX[2] & (!J1_LUT_INDEX[3]) # !J1_LUT_INDEX[2] & (J1_LUT_INDEX[1] # J1_LUT_INDEX[3]));


--J1L84 is I2C_AV_Config:u7|mI2C_DATA[12]~871
J1L84 = KEY[0] & !J1_mSetup_ST.00;


--J1L1 is I2C_AV_Config:u7|Decoder~138
J1L1 = J1_LUT_INDEX[1] & J1_LUT_INDEX[2] & !J1_LUT_INDEX[0] & !J1_LUT_INDEX[3];


--J1L92 is I2C_AV_Config:u7|reduce_or~74
J1L92 = J1_LUT_INDEX[2] & !J1_LUT_INDEX[0] & (!J1_LUT_INDEX[3]) # !J1_LUT_INDEX[2] & (J1_LUT_INDEX[1] & (!J1_LUT_INDEX[3]) # !J1_LUT_INDEX[1] & J1_LUT_INDEX[0]);


--J1L2 is I2C_AV_Config:u7|Decoder~139
J1L2 = J1_LUT_INDEX[0] & J1_LUT_INDEX[2] & !J1_LUT_INDEX[1] & !J1_LUT_INDEX[3];


--J1L93 is I2C_AV_Config:u7|reduce_or~75
J1L93 = J1_LUT_INDEX[1] & !J1_LUT_INDEX[2] & (J1_LUT_INDEX[0] $ J1_LUT_INDEX[3]) # !J1_LUT_INDEX[1] & !J1_LUT_INDEX[0] & (J1_LUT_INDEX[2] $ J1_LUT_INDEX[3]);


--J1L94 is I2C_AV_Config:u7|reduce_or~76
J1L94 = J1_LUT_INDEX[2] & !J1_LUT_INDEX[3] & (J1_LUT_INDEX[0] # J1_LUT_INDEX[1]) # !J1_LUT_INDEX[2] & !J1_LUT_INDEX[0] & !J1_LUT_INDEX[1] & J1_LUT_INDEX[3];


--J1L95 is I2C_AV_Config:u7|reduce_or~77
J1L95 = J1_LUT_INDEX[0] & J1_LUT_INDEX[1] & (!J1_LUT_INDEX[3]) # !J1_LUT_INDEX[0] & !J1_LUT_INDEX[1] & (J1_LUT_INDEX[2] $ J1_LUT_INDEX[3]);


--J1L96 is I2C_AV_Config:u7|reduce_or~78
J1L96 = !J1_LUT_INDEX[3] & (J1_LUT_INDEX[1] & (!J1_LUT_INDEX[2]) # !J1_LUT_INDEX[1] & (J1_LUT_INDEX[0] # J1_LUT_INDEX[2]));


--J1L97 is I2C_AV_Config:u7|reduce_or~79
J1L97 = !J1_LUT_INDEX[3] & (J1_LUT_INDEX[1] & J1_LUT_INDEX[0] & !J1_LUT_INDEX[2] # !J1_LUT_INDEX[1] & (J1_LUT_INDEX[2]));


--J1L3 is I2C_AV_Config:u7|LUT_DATA~8
J1L3 = !J1_LUT_INDEX[2] & J1_LUT_INDEX[3] & (J1_LUT_INDEX[0] $ J1_LUT_INDEX[1]);


--J1L6 is I2C_AV_Config:u7|LUT_INDEX[0]~680
J1L6 = J1_mSetup_ST.10 $ J1_LUT_INDEX[0];


--J1L8 is I2C_AV_Config:u7|LUT_INDEX[1]~681
J1L8 = J1_LUT_INDEX[1] $ (J1_mSetup_ST.10 & J1_LUT_INDEX[0]);


--J1L11 is I2C_AV_Config:u7|LUT_INDEX[2]~682
J1L11 = J1_LUT_INDEX[2] $ (J1_mSetup_ST.10 & J1_LUT_INDEX[0] & J1_LUT_INDEX[1]);


--J1L9 is I2C_AV_Config:u7|LUT_INDEX[1]~683
J1L9 = J1_mSetup_ST.10 & J1_LUT_INDEX[0];


--J1L13 is I2C_AV_Config:u7|LUT_INDEX[3]~684
J1L13 = J1_LUT_INDEX[3] $ (J1_LUT_INDEX[1] & J1_LUT_INDEX[2] & J1L9);


--F1L61 is VGA_Controller:u4|LessThan~1175
F1L61 = !F1_H_Cont[5] & !F1_H_Cont[6] & (F1L51 # !F1_H_Cont[4]);


--F1L62 is VGA_Controller:u4|LessThan~1176
F1L62 = !F1_H_Cont[8] & !F1_H_Cont[9] & (F1L61 # !F1_H_Cont[7]);


--H1L19 is VGA_OSD_RAM:u6|LessThan~457
H1L19 = !F1_oCoord_Y[3] & !F1_oCoord_Y[2] & !F1_oCoord_Y[1] # !G1L2;


--G1L13 is VGA_Pattern:u5|LessThan~2795
G1L13 = !F1_oCoord_Y[6] & (!G1L7 # !F1_oCoord_Y[5] # !F1_oCoord_Y[4]);


--F1L63 is VGA_Controller:u4|LessThan~1177
F1L63 = !F1_H_Cont[5] & !F1_H_Cont[6] & (F1L17 # !F1_H_Cont[4]);


--S3_w_anode3056w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3056w[3]
S3_w_anode3056w[3] = H1L130 & !H1L132 & S3L23 & !H1L128;


--S3_w_anode3066w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3066w[3]
S3_w_anode3066w[3] = H1L130 & !H1L132 & S3L93 & !H1L128;


--S3_w_anode3045w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3045w[3]
S3_w_anode3045w[3] = H1L130 & !H1L132 & S3L88 & !H1L128;


--S3_w_anode3159w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3159w[3]
S3_w_anode3159w[3] = H1L130 & !H1L132 & H1L128 & S3L93;


--S3_w_anode3149w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3149w[3]
S3_w_anode3149w[3] = H1L130 & !H1L132 & H1L128 & S3L23;


--S3_w_anode3138w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3138w[3]
S3_w_anode3138w[3] = H1L130 & !H1L132 & H1L128 & S3L88;


--S3_w_anode3242w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3242w[3]
S3_w_anode3242w[3] = !H1L128 & !H1L130 & H1L132 & S3L23;


--S3_w_anode3252w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3252w[3]
S3_w_anode3252w[3] = !H1L128 & !H1L130 & H1L132 & S3L93;


--S3_w_anode3231w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3231w[3]
S3_w_anode3231w[3] = !H1L128 & !H1L130 & H1L132 & S3L88;


--S3L6 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2879w[3]~12
S3L6 = !H1L128 & !H1L130 & S3L93 & !H1L132;


--S3_w_anode2852w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2852w[3]
S3_w_anode2852w[3] = !H1L128 & !H1L130 & !H1L132 & S3L88;


--S3_w_anode3335w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3335w[3]
S3_w_anode3335w[3] = H1L128 & !H1L130 & H1L132 & S3L23;


--S3_w_anode3324w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3324w[3]
S3_w_anode3324w[3] = H1L128 & !H1L130 & H1L132 & S3L88;


--S3_w_anode3345w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3345w[3]
S3_w_anode3345w[3] = H1L128 & !H1L130 & H1L132 & S3L93;


--S3_w_anode2973w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2973w[3]
S3_w_anode2973w[3] = H1L128 & !H1L130 & S3L93 & !H1L132;


--S3_w_anode2952w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2952w[3]
S3_w_anode2952w[3] = H1L128 & !H1L130 & S3L88 & !H1L132;


--S3_w_anode2963w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2963w[3]
S3_w_anode2963w[3] = H1L128 & !H1L130 & S3L23 & !H1L132;


--V1L11 is I2C_AV_Config:u7|I2C_Controller:u0|ACK3~216
V1L11 = V1L10 & A1L284 & !V1L52Q # !V1L10 & (V1_ACK3);


--V1L36 is I2C_AV_Config:u7|I2C_Controller:u0|SD[12]~11
V1L36 = V1L55Q & !V1L40Q & KEY[0] & V1L37;


--G1L36 is VGA_Pattern:u5|oGreen~1193
G1L36 = F1_oCoord_X[5] & (!F1_oCoord_X[4] & F1_oCoord_X[7] # !F1_oCoord_X[6]) # !F1_oCoord_X[5] & (F1_oCoord_X[6] & (F1_oCoord_X[7] # !F1_oCoord_X[4]) # !F1_oCoord_X[6] & (!F1_oCoord_X[7]));


--G1L37 is VGA_Pattern:u5|oGreen~1194
G1L37 = F1_oCoord_X[5] & (F1_oCoord_X[6]) # !F1_oCoord_X[5] & (F1_oCoord_X[6] & (!F1_oCoord_X[7]) # !F1_oCoord_X[6] & !F1_oCoord_X[4] & F1_oCoord_X[7]);


--G1L43 is VGA_Pattern:u5|oGreen~1207
G1L43 = F1_oCoord_X[9] # F1_oCoord_X[8] & (G1L37) # !F1_oCoord_X[8] & G1L36;


--G1L38 is VGA_Pattern:u5|oGreen~1200
G1L38 = F1_oCoord_X[7] & (!F1_oCoord_X[5] # !F1_oCoord_X[4] # !F1_oCoord_X[6]) # !F1_oCoord_X[7] & F1_oCoord_X[6] & (F1_oCoord_X[4] # F1_oCoord_X[5]);


--G1L39 is VGA_Pattern:u5|oGreen~1201
G1L39 = F1_oCoord_X[7] & (F1_oCoord_X[6] # F1_oCoord_X[4] # F1_oCoord_X[5]);


--G1L44 is VGA_Pattern:u5|oGreen~1208
G1L44 = F1_oCoord_X[9] # F1_oCoord_X[8] & (G1L39) # !F1_oCoord_X[8] & G1L38;


--V1L5 is I2C_AV_Config:u7|I2C_Controller:u0|ACK2~237
V1L5 = !V1L46Q & !V1L40Q & V1L55Q & !V1L52Q;


--V1L7 is I2C_AV_Config:u7|I2C_Controller:u0|ACK2~252
V1L7 = V1_ACK2 & (V1L6 # A1L284 & V1L5) # !V1_ACK2 & A1L284 & V1L5;


--V1L8 is I2C_AV_Config:u7|I2C_Controller:u0|ACK2~253
V1L8 = V1L49Q & (V1L43Q & (V1L7) # !V1L43Q & V1_ACK2) # !V1L49Q & V1_ACK2;


--K1L125 is AUDIO_DAC:u8|oAUD_DATA~94
K1L125 = K1L131Q & (!K1L132Q) # !K1L131Q & (K1L132Q & K1L88 # !K1L132Q & (K1L113));


--K1L126 is AUDIO_DAC:u8|oAUD_DATA~95
K1L126 = K1L125 & !SW[9] & (K1L66 # !K1L131Q);


--K1L116 is AUDIO_DAC:u8|SEL_Cont[0]~53
K1L116 = !K1_SEL_Cont[0];


--H1L7 is VGA_OSD_RAM:u6|ADDR_dd[0]~6
H1L7 = !H1_ADDR_d[0];


--H1L9 is VGA_OSD_RAM:u6|ADDR_dd[1]~7
H1L9 = !H1_ADDR_d[1];


--H1L11 is VGA_OSD_RAM:u6|ADDR_dd[2]~8
H1L11 = !H1_ADDR_d[2];


--~GND is ~GND
~GND = GND;


--CLOCK_24[1] is CLOCK_24[1]
--operation mode is input

CLOCK_24[1] = INPUT();


--CLOCK_27[1] is CLOCK_27[1]
--operation mode is input

CLOCK_27[1] = INPUT();


--EXT_CLOCK is EXT_CLOCK
--operation mode is input

EXT_CLOCK = INPUT();


--KEY[1] is KEY[1]
--operation mode is input

KEY[1] = INPUT();


--KEY[2] is KEY[2]
--operation mode is input

KEY[2] = INPUT();


--KEY[3] is KEY[3]
--operation mode is input

KEY[3] = INPUT();


--SW[1] is SW[1]
--operation mode is input

SW[1] = INPUT();


--SW[2] is SW[2]
--operation mode is input

SW[2] = INPUT();


--SW[3] is SW[3]
--operation mode is input

SW[3] = INPUT();


--SW[4] is SW[4]
--operation mode is input

SW[4] = INPUT();


--SW[5] is SW[5]
--operation mode is input

SW[5] = INPUT();


--SW[6] is SW[6]
--operation mode is input

SW[6] = INPUT();


--SW[7] is SW[7]
--operation mode is input

SW[7] = INPUT();


--SW[8] is SW[8]
--operation mode is input

SW[8] = INPUT();


--UART_RXD is UART_RXD
--operation mode is input

UART_RXD = INPUT();


--TDI is TDI
--operation mode is input

TDI = INPUT();


--TCK is TCK
--operation mode is input

TCK = INPUT();


--TCS is TCS
--operation mode is input

TCS = INPUT();


--PS2_DAT is PS2_DAT
--operation mode is input

PS2_DAT = INPUT();


--PS2_CLK is PS2_CLK
--operation mode is input

PS2_CLK = INPUT();


--AUD_ADCDAT is AUD_ADCDAT
--operation mode is input

AUD_ADCDAT = INPUT();


--SW[9] is SW[9]
--operation mode is input

SW[9] = INPUT();


--CLOCK_50 is CLOCK_50
--operation mode is input

CLOCK_50 = INPUT();


--KEY[0] is KEY[0]
--operation mode is input

KEY[0] = INPUT();


--SW[0] is SW[0]
--operation mode is input

SW[0] = INPUT();


--CLOCK_27[0] is CLOCK_27[0]
--operation mode is input

CLOCK_27[0] = INPUT();


--CLOCK_24[0] is CLOCK_24[0]
--operation mode is input

CLOCK_24[0] = INPUT();


--HEX0[0] is HEX0[0]
--operation mode is output

HEX0[0] = OUTPUT(L1L1);


--HEX0[1] is HEX0[1]
--operation mode is output

HEX0[1] = OUTPUT(L1L2);


--HEX0[2] is HEX0[2]
--operation mode is output

HEX0[2] = OUTPUT(L1L3);


--HEX0[3] is HEX0[3]
--operation mode is output

HEX0[3] = OUTPUT(L1L4);


--HEX0[4] is HEX0[4]
--operation mode is output

HEX0[4] = OUTPUT(L1L5);


--HEX0[5] is HEX0[5]
--operation mode is output

HEX0[5] = OUTPUT(L1L6);


--HEX0[6] is HEX0[6]
--operation mode is output

HEX0[6] = OUTPUT(!L1L7);


--HEX1[0] is HEX1[0]
--operation mode is output

HEX1[0] = OUTPUT(L1L1);


--HEX1[1] is HEX1[1]
--operation mode is output

HEX1[1] = OUTPUT(L1L2);


--HEX1[2] is HEX1[2]
--operation mode is output

HEX1[2] = OUTPUT(L1L3);


--HEX1[3] is HEX1[3]
--operation mode is output

HEX1[3] = OUTPUT(L1L4);


--HEX1[4] is HEX1[4]
--operation mode is output

HEX1[4] = OUTPUT(L1L5);


--HEX1[5] is HEX1[5]
--operation mode is output

HEX1[5] = OUTPUT(L1L6);


--HEX1[6] is HEX1[6]
--operation mode is output

HEX1[6] = OUTPUT(!L1L7);


--HEX2[0] is HEX2[0]
--operation mode is output

HEX2[0] = OUTPUT(L1L1);


--HEX2[1] is HEX2[1]
--operation mode is output

HEX2[1] = OUTPUT(L1L2);


--HEX2[2] is HEX2[2]
--operation mode is output

HEX2[2] = OUTPUT(L1L3);


--HEX2[3] is HEX2[3]
--operation mode is output

HEX2[3] = OUTPUT(L1L4);


--HEX2[4] is HEX2[4]
--operation mode is output

HEX2[4] = OUTPUT(L1L5);


--HEX2[5] is HEX2[5]
--operation mode is output

HEX2[5] = OUTPUT(L1L6);


--HEX2[6] is HEX2[6]
--operation mode is output

HEX2[6] = OUTPUT(!L1L7);


--HEX3[0] is HEX3[0]
--operation mode is output

HEX3[0] = OUTPUT(L1L1);


--HEX3[1] is HEX3[1]
--operation mode is output

HEX3[1] = OUTPUT(L1L2);


--HEX3[2] is HEX3[2]
--operation mode is output

HEX3[2] = OUTPUT(L1L3);


--HEX3[3] is HEX3[3]
--operation mode is output

HEX3[3] = OUTPUT(L1L4);


--HEX3[4] is HEX3[4]
--operation mode is output

HEX3[4] = OUTPUT(L1L5);


--HEX3[5] is HEX3[5]
--operation mode is output

HEX3[5] = OUTPUT(L1L6);


--HEX3[6] is HEX3[6]
--operation mode is output

HEX3[6] = OUTPUT(!L1L7);


--LEDG[0] is LEDG[0]
--operation mode is output

LEDG[0] = OUTPUT(!D1_mLED[0]);


--LEDG[1] is LEDG[1]
--operation mode is output

LEDG[1] = OUTPUT(!D1_mLED[1]);


--LEDG[2] is LEDG[2]
--operation mode is output

LEDG[2] = OUTPUT(!D1_mLED[2]);


--LEDG[3] is LEDG[3]
--operation mode is output

LEDG[3] = OUTPUT(D1_mLED[3]);


--LEDG[4] is LEDG[4]
--operation mode is output

LEDG[4] = OUTPUT(D1_mLED[4]);


--LEDG[5] is LEDG[5]
--operation mode is output

LEDG[5] = OUTPUT(D1_mLED[5]);


--LEDG[6] is LEDG[6]
--operation mode is output

LEDG[6] = OUTPUT(D1_mLED[6]);


--LEDG[7] is LEDG[7]
--operation mode is output

LEDG[7] = OUTPUT(D1_mLED[7]);


--LEDR[0] is LEDR[0]
--operation mode is output

LEDR[0] = OUTPUT(!C1_mLED[0]);


--LEDR[1] is LEDR[1]
--operation mode is output

LEDR[1] = OUTPUT(!C1_mLED[1]);


--LEDR[2] is LEDR[2]
--operation mode is output

LEDR[2] = OUTPUT(!C1_mLED[2]);


--LEDR[3] is LEDR[3]
--operation mode is output

LEDR[3] = OUTPUT(C1_mLED[3]);


--LEDR[4] is LEDR[4]
--operation mode is output

LEDR[4] = OUTPUT(C1_mLED[4]);


--LEDR[5] is LEDR[5]
--operation mode is output

LEDR[5] = OUTPUT(C1_mLED[5]);


--LEDR[6] is LEDR[6]
--operation mode is output

LEDR[6] = OUTPUT(C1_mLED[6]);


--LEDR[7] is LEDR[7]
--operation mode is output

LEDR[7] = OUTPUT(C1_mLED[7]);


--LEDR[8] is LEDR[8]
--operation mode is output

LEDR[8] = OUTPUT(C1_mLED[8]);


--LEDR[9] is LEDR[9]
--operation mode is output

LEDR[9] = OUTPUT(C1_mLED[9]);


--UART_TXD is UART_TXD
--operation mode is output

UART_TXD = OUTPUT(GND);


--DRAM_ADDR[0] is DRAM_ADDR[0]
--operation mode is output

DRAM_ADDR[0] = OUTPUT(GND);


--DRAM_ADDR[1] is DRAM_ADDR[1]
--operation mode is output

DRAM_ADDR[1] = OUTPUT(GND);


--DRAM_ADDR[2] is DRAM_ADDR[2]
--operation mode is output

DRAM_ADDR[2] = OUTPUT(GND);


--DRAM_ADDR[3] is DRAM_ADDR[3]
--operation mode is output

DRAM_ADDR[3] = OUTPUT(GND);


--DRAM_ADDR[4] is DRAM_ADDR[4]
--operation mode is output

DRAM_ADDR[4] = OUTPUT(GND);


--DRAM_ADDR[5] is DRAM_ADDR[5]
--operation mode is output

DRAM_ADDR[5] = OUTPUT(GND);


--DRAM_ADDR[6] is DRAM_ADDR[6]
--operation mode is output

DRAM_ADDR[6] = OUTPUT(GND);


--DRAM_ADDR[7] is DRAM_ADDR[7]
--operation mode is output

DRAM_ADDR[7] = OUTPUT(GND);


--DRAM_ADDR[8] is DRAM_ADDR[8]
--operation mode is output

DRAM_ADDR[8] = OUTPUT(GND);


--DRAM_ADDR[9] is DRAM_ADDR[9]
--operation mode is output

DRAM_ADDR[9] = OUTPUT(GND);


--DRAM_ADDR[10] is DRAM_ADDR[10]
--operation mode is output

DRAM_ADDR[10] = OUTPUT(GND);


--DRAM_ADDR[11] is DRAM_ADDR[11]
--operation mode is output

DRAM_ADDR[11] = OUTPUT(GND);


--DRAM_LDQM is DRAM_LDQM
--operation mode is output

DRAM_LDQM = OUTPUT(GND);


--DRAM_UDQM is DRAM_UDQM
--operation mode is output

DRAM_UDQM = OUTPUT(GND);


--DRAM_WE_N is DRAM_WE_N
--operation mode is output

DRAM_WE_N = OUTPUT(GND);


--DRAM_CAS_N is DRAM_CAS_N
--operation mode is output

DRAM_CAS_N = OUTPUT(GND);


--DRAM_RAS_N is DRAM_RAS_N
--operation mode is output

DRAM_RAS_N = OUTPUT(GND);


--DRAM_CS_N is DRAM_CS_N
--operation mode is output

DRAM_CS_N = OUTPUT(GND);


--DRAM_BA_0 is DRAM_BA_0
--operation mode is output

DRAM_BA_0 = OUTPUT(GND);


--DRAM_BA_1 is DRAM_BA_1
--operation mode is output

DRAM_BA_1 = OUTPUT(GND);


--DRAM_CLK is DRAM_CLK
--operation mode is output

DRAM_CLK = OUTPUT(GND);


--DRAM_CKE is DRAM_CKE
--operation mode is output

DRAM_CKE = OUTPUT(GND);


--FL_ADDR[0] is FL_ADDR[0]
--operation mode is output

FL_ADDR[0] = OUTPUT(GND);


--FL_ADDR[1] is FL_ADDR[1]
--operation mode is output

FL_ADDR[1] = OUTPUT(GND);


--FL_ADDR[2] is FL_ADDR[2]
--operation mode is output

FL_ADDR[2] = OUTPUT(GND);


--FL_ADDR[3] is FL_ADDR[3]
--operation mode is output

FL_ADDR[3] = OUTPUT(GND);


--FL_ADDR[4] is FL_ADDR[4]
--operation mode is output

FL_ADDR[4] = OUTPUT(GND);


--FL_ADDR[5] is FL_ADDR[5]
--operation mode is output

FL_ADDR[5] = OUTPUT(GND);


--FL_ADDR[6] is FL_ADDR[6]
--operation mode is output

FL_ADDR[6] = OUTPUT(GND);


--FL_ADDR[7] is FL_ADDR[7]
--operation mode is output

FL_ADDR[7] = OUTPUT(GND);


--FL_ADDR[8] is FL_ADDR[8]
--operation mode is output

FL_ADDR[8] = OUTPUT(GND);


--FL_ADDR[9] is FL_ADDR[9]
--operation mode is output

FL_ADDR[9] = OUTPUT(GND);


--FL_ADDR[10] is FL_ADDR[10]
--operation mode is output

FL_ADDR[10] = OUTPUT(GND);


--FL_ADDR[11] is FL_ADDR[11]
--operation mode is output

FL_ADDR[11] = OUTPUT(GND);


--FL_ADDR[12] is FL_ADDR[12]
--operation mode is output

FL_ADDR[12] = OUTPUT(GND);


--FL_ADDR[13] is FL_ADDR[13]
--operation mode is output

FL_ADDR[13] = OUTPUT(GND);


--FL_ADDR[14] is FL_ADDR[14]
--operation mode is output

FL_ADDR[14] = OUTPUT(GND);


--FL_ADDR[15] is FL_ADDR[15]
--operation mode is output

FL_ADDR[15] = OUTPUT(GND);


--FL_ADDR[16] is FL_ADDR[16]
--operation mode is output

FL_ADDR[16] = OUTPUT(GND);


--FL_ADDR[17] is FL_ADDR[17]
--operation mode is output

FL_ADDR[17] = OUTPUT(GND);


--FL_ADDR[18] is FL_ADDR[18]
--operation mode is output

FL_ADDR[18] = OUTPUT(GND);


--FL_ADDR[19] is FL_ADDR[19]
--operation mode is output

FL_ADDR[19] = OUTPUT(GND);


--FL_ADDR[20] is FL_ADDR[20]
--operation mode is output

FL_ADDR[20] = OUTPUT(GND);


--FL_ADDR[21] is FL_ADDR[21]
--operation mode is output

FL_ADDR[21] = OUTPUT(GND);


--FL_WE_N is FL_WE_N
--operation mode is output

FL_WE_N = OUTPUT(GND);


--FL_RST_N is FL_RST_N
--operation mode is output

FL_RST_N = OUTPUT(GND);


--FL_OE_N is FL_OE_N
--operation mode is output

FL_OE_N = OUTPUT(GND);


--FL_CE_N is FL_CE_N
--operation mode is output

FL_CE_N = OUTPUT(GND);


--SRAM_ADDR[0] is SRAM_ADDR[0]
--operation mode is output

SRAM_ADDR[0] = OUTPUT(GND);


--SRAM_ADDR[1] is SRAM_ADDR[1]
--operation mode is output

SRAM_ADDR[1] = OUTPUT(GND);


--SRAM_ADDR[2] is SRAM_ADDR[2]
--operation mode is output

SRAM_ADDR[2] = OUTPUT(GND);


--SRAM_ADDR[3] is SRAM_ADDR[3]
--operation mode is output

SRAM_ADDR[3] = OUTPUT(GND);


--SRAM_ADDR[4] is SRAM_ADDR[4]
--operation mode is output

SRAM_ADDR[4] = OUTPUT(GND);


--SRAM_ADDR[5] is SRAM_ADDR[5]
--operation mode is output

SRAM_ADDR[5] = OUTPUT(GND);


--SRAM_ADDR[6] is SRAM_ADDR[6]
--operation mode is output

SRAM_ADDR[6] = OUTPUT(GND);


--SRAM_ADDR[7] is SRAM_ADDR[7]
--operation mode is output

SRAM_ADDR[7] = OUTPUT(GND);


--SRAM_ADDR[8] is SRAM_ADDR[8]
--operation mode is output

SRAM_ADDR[8] = OUTPUT(GND);


--SRAM_ADDR[9] is SRAM_ADDR[9]
--operation mode is output

SRAM_ADDR[9] = OUTPUT(GND);


--SRAM_ADDR[10] is SRAM_ADDR[10]
--operation mode is output

SRAM_ADDR[10] = OUTPUT(GND);


--SRAM_ADDR[11] is SRAM_ADDR[11]
--operation mode is output

SRAM_ADDR[11] = OUTPUT(GND);


--SRAM_ADDR[12] is SRAM_ADDR[12]
--operation mode is output

SRAM_ADDR[12] = OUTPUT(GND);


--SRAM_ADDR[13] is SRAM_ADDR[13]
--operation mode is output

SRAM_ADDR[13] = OUTPUT(GND);


--SRAM_ADDR[14] is SRAM_ADDR[14]
--operation mode is output

SRAM_ADDR[14] = OUTPUT(GND);


--SRAM_ADDR[15] is SRAM_ADDR[15]
--operation mode is output

SRAM_ADDR[15] = OUTPUT(GND);


--SRAM_ADDR[16] is SRAM_ADDR[16]
--operation mode is output

SRAM_ADDR[16] = OUTPUT(GND);


--SRAM_ADDR[17] is SRAM_ADDR[17]
--operation mode is output

SRAM_ADDR[17] = OUTPUT(GND);


--SRAM_UB_N is SRAM_UB_N
--operation mode is output

SRAM_UB_N = OUTPUT(GND);


--SRAM_LB_N is SRAM_LB_N
--operation mode is output

SRAM_LB_N = OUTPUT(GND);


--SRAM_WE_N is SRAM_WE_N
--operation mode is output

SRAM_WE_N = OUTPUT(GND);


--SRAM_CE_N is SRAM_CE_N
--operation mode is output

SRAM_CE_N = OUTPUT(GND);


--SRAM_OE_N is SRAM_OE_N
--operation mode is output

SRAM_OE_N = OUTPUT(GND);


--SD_CLK is SD_CLK
--operation mode is output

SD_CLK = OUTPUT(GND);


--TDO is TDO
--operation mode is output

TDO = OUTPUT(GND);


--I2C_SCLK is I2C_SCLK
--operation mode is output

I2C_SCLK = OUTPUT(V1L17);


--VGA_HS is VGA_HS
--operation mode is output

VGA_HS = OUTPUT(F1_oVGA_H_SYNC);


--VGA_VS is VGA_VS
--operation mode is output

VGA_VS = OUTPUT(F1_oVGA_V_SYNC);


--VGA_R[0] is VGA_R[0]
--operation mode is output

VGA_R[0] = OUTPUT(F1L259);


--VGA_R[1] is VGA_R[1]
--operation mode is output

VGA_R[1] = OUTPUT(F1L259);


--VGA_R[2] is VGA_R[2]
--operation mode is output

VGA_R[2] = OUTPUT(F1L260);


--VGA_R[3] is VGA_R[3]
--operation mode is output

VGA_R[3] = OUTPUT(F1L261);


--VGA_G[0] is VGA_G[0]
--operation mode is output

VGA_G[0] = OUTPUT(F1L254);


--VGA_G[1] is VGA_G[1]
--operation mode is output

VGA_G[1] = OUTPUT(F1L255);


--VGA_G[2] is VGA_G[2]
--operation mode is output

VGA_G[2] = OUTPUT(F1L256);


--VGA_G[3] is VGA_G[3]
--operation mode is output

VGA_G[3] = OUTPUT(F1L257);


--VGA_B[0] is VGA_B[0]
--operation mode is output

VGA_B[0] = OUTPUT(F1L250);


--VGA_B[1] is VGA_B[1]
--operation mode is output

VGA_B[1] = OUTPUT(F1L251);


--VGA_B[2] is VGA_B[2]
--operation mode is output

VGA_B[2] = OUTPUT(F1L252);


--VGA_B[3] is VGA_B[3]
--operation mode is output

VGA_B[3] = OUTPUT(F1L253);


--AUD_ADCLRCK is AUD_ADCLRCK
--operation mode is output

AUD_ADCLRCK = OUTPUT(K1_LRCK_1X);


--AUD_DACLRCK is AUD_DACLRCK
--operation mode is output

AUD_DACLRCK = OUTPUT(K1_LRCK_1X);


--AUD_DACDAT is AUD_DACDAT
--operation mode is output

AUD_DACDAT = OUTPUT(K1L126);


--AUD_XCK is AUD_XCK
--operation mode is output

AUD_XCK = OUTPUT(M1__clk1);


--SD_DAT3 is SD_DAT3
--operation mode is bidir

SD_DAT3 = BIDIR(OPNDRN(VCC));


--SD_CMD is SD_CMD
--operation mode is bidir

SD_CMD = BIDIR(OPNDRN(VCC));


--DRAM_DQ[0] is DRAM_DQ[0]
--operation mode is bidir

DRAM_DQ[0] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[1] is DRAM_DQ[1]
--operation mode is bidir

DRAM_DQ[1] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[2] is DRAM_DQ[2]
--operation mode is bidir

DRAM_DQ[2] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[3] is DRAM_DQ[3]
--operation mode is bidir

DRAM_DQ[3] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[4] is DRAM_DQ[4]
--operation mode is bidir

DRAM_DQ[4] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[5] is DRAM_DQ[5]
--operation mode is bidir

DRAM_DQ[5] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[6] is DRAM_DQ[6]
--operation mode is bidir

DRAM_DQ[6] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[7] is DRAM_DQ[7]
--operation mode is bidir

DRAM_DQ[7] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[8] is DRAM_DQ[8]
--operation mode is bidir

DRAM_DQ[8] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[9] is DRAM_DQ[9]
--operation mode is bidir

DRAM_DQ[9] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[10] is DRAM_DQ[10]
--operation mode is bidir

DRAM_DQ[10] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[11] is DRAM_DQ[11]
--operation mode is bidir

DRAM_DQ[11] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[12] is DRAM_DQ[12]
--operation mode is bidir

DRAM_DQ[12] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[13] is DRAM_DQ[13]
--operation mode is bidir

DRAM_DQ[13] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[14] is DRAM_DQ[14]
--operation mode is bidir

DRAM_DQ[14] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[15] is DRAM_DQ[15]
--operation mode is bidir

DRAM_DQ[15] = BIDIR(OPNDRN(VCC));


--FL_DQ[0] is FL_DQ[0]
--operation mode is bidir

FL_DQ[0] = BIDIR(OPNDRN(VCC));


--FL_DQ[1] is FL_DQ[1]
--operation mode is bidir

FL_DQ[1] = BIDIR(OPNDRN(VCC));


--FL_DQ[2] is FL_DQ[2]
--operation mode is bidir

FL_DQ[2] = BIDIR(OPNDRN(VCC));


--FL_DQ[3] is FL_DQ[3]
--operation mode is bidir

FL_DQ[3] = BIDIR(OPNDRN(VCC));


--FL_DQ[4] is FL_DQ[4]
--operation mode is bidir

FL_DQ[4] = BIDIR(OPNDRN(VCC));


--FL_DQ[5] is FL_DQ[5]
--operation mode is bidir

FL_DQ[5] = BIDIR(OPNDRN(VCC));


--FL_DQ[6] is FL_DQ[6]
--operation mode is bidir

FL_DQ[6] = BIDIR(OPNDRN(VCC));


--FL_DQ[7] is FL_DQ[7]
--operation mode is bidir

FL_DQ[7] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[0] is SRAM_DQ[0]
--operation mode is bidir

SRAM_DQ[0] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[1] is SRAM_DQ[1]
--operation mode is bidir

SRAM_DQ[1] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[2] is SRAM_DQ[2]
--operation mode is bidir

SRAM_DQ[2] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[3] is SRAM_DQ[3]
--operation mode is bidir

SRAM_DQ[3] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[4] is SRAM_DQ[4]
--operation mode is bidir

SRAM_DQ[4] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[5] is SRAM_DQ[5]
--operation mode is bidir

SRAM_DQ[5] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[6] is SRAM_DQ[6]
--operation mode is bidir

SRAM_DQ[6] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[7] is SRAM_DQ[7]
--operation mode is bidir

SRAM_DQ[7] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[8] is SRAM_DQ[8]
--operation mode is bidir

SRAM_DQ[8] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[9] is SRAM_DQ[9]
--operation mode is bidir

SRAM_DQ[9] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[10] is SRAM_DQ[10]
--operation mode is bidir

SRAM_DQ[10] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[11] is SRAM_DQ[11]
--operation mode is bidir

SRAM_DQ[11] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[12] is SRAM_DQ[12]
--operation mode is bidir

SRAM_DQ[12] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[13] is SRAM_DQ[13]
--operation mode is bidir

SRAM_DQ[13] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[14] is SRAM_DQ[14]
--operation mode is bidir

SRAM_DQ[14] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[15] is SRAM_DQ[15]
--operation mode is bidir

SRAM_DQ[15] = BIDIR(OPNDRN(VCC));


--SD_DAT is SD_DAT
--operation mode is bidir

SD_DAT = BIDIR(OPNDRN(VCC));


--A1L284 is I2C_SDAT~1
--operation mode is bidir

A1L284 = I2C_SDAT;

--I2C_SDAT is I2C_SDAT
--operation mode is bidir

I2C_SDAT = BIDIR(OPNDRN(!V1L25Q));


--AUD_BCLK is AUD_BCLK
--operation mode is bidir

AUD_BCLK_tri_out = TRI(K1_oAUD_BCK, VCC);
AUD_BCLK = BIDIR(AUD_BCLK_tri_out);


--GPIO_0[0] is GPIO_0[0]
--operation mode is bidir

GPIO_0[0] = BIDIR(OPNDRN(VCC));


--GPIO_0[1] is GPIO_0[1]
--operation mode is bidir

GPIO_0[1] = BIDIR(OPNDRN(VCC));


--GPIO_0[2] is GPIO_0[2]
--operation mode is bidir

GPIO_0[2] = BIDIR(OPNDRN(VCC));


--GPIO_0[3] is GPIO_0[3]
--operation mode is bidir

GPIO_0[3] = BIDIR(OPNDRN(VCC));


--GPIO_0[4] is GPIO_0[4]
--operation mode is bidir

GPIO_0[4] = BIDIR(OPNDRN(VCC));


--GPIO_0[5] is GPIO_0[5]
--operation mode is bidir

GPIO_0[5] = BIDIR(OPNDRN(VCC));


--GPIO_0[6] is GPIO_0[6]
--operation mode is bidir

GPIO_0[6] = BIDIR(OPNDRN(VCC));


--GPIO_0[7] is GPIO_0[7]
--operation mode is bidir

GPIO_0[7] = BIDIR(OPNDRN(VCC));


--GPIO_0[8] is GPIO_0[8]
--operation mode is bidir

GPIO_0[8] = BIDIR(OPNDRN(VCC));


--GPIO_0[9] is GPIO_0[9]
--operation mode is bidir

GPIO_0[9] = BIDIR(OPNDRN(VCC));


--GPIO_0[10] is GPIO_0[10]
--operation mode is bidir

GPIO_0[10] = BIDIR(OPNDRN(VCC));


--GPIO_0[11] is GPIO_0[11]
--operation mode is bidir

GPIO_0[11] = BIDIR(OPNDRN(VCC));


--GPIO_0[12] is GPIO_0[12]
--operation mode is bidir

GPIO_0[12] = BIDIR(OPNDRN(VCC));


--GPIO_0[13] is GPIO_0[13]
--operation mode is bidir

GPIO_0[13] = BIDIR(OPNDRN(VCC));


--GPIO_0[14] is GPIO_0[14]
--operation mode is bidir

GPIO_0[14] = BIDIR(OPNDRN(VCC));


--GPIO_0[15] is GPIO_0[15]
--operation mode is bidir

GPIO_0[15] = BIDIR(OPNDRN(VCC));


--GPIO_0[16] is GPIO_0[16]
--operation mode is bidir

GPIO_0[16] = BIDIR(OPNDRN(VCC));


--GPIO_0[17] is GPIO_0[17]
--operation mode is bidir

GPIO_0[17] = BIDIR(OPNDRN(VCC));


--GPIO_0[18] is GPIO_0[18]
--operation mode is bidir

GPIO_0[18] = BIDIR(OPNDRN(VCC));


--GPIO_0[19] is GPIO_0[19]
--operation mode is bidir

GPIO_0[19] = BIDIR(OPNDRN(VCC));


--GPIO_0[20] is GPIO_0[20]
--operation mode is bidir

GPIO_0[20] = BIDIR(OPNDRN(VCC));


--GPIO_0[21] is GPIO_0[21]
--operation mode is bidir

GPIO_0[21] = BIDIR(OPNDRN(VCC));


--GPIO_0[22] is GPIO_0[22]
--operation mode is bidir

GPIO_0[22] = BIDIR(OPNDRN(VCC));


--GPIO_0[23] is GPIO_0[23]
--operation mode is bidir

GPIO_0[23] = BIDIR(OPNDRN(VCC));


--GPIO_0[24] is GPIO_0[24]
--operation mode is bidir

GPIO_0[24] = BIDIR(OPNDRN(VCC));


--GPIO_0[25] is GPIO_0[25]
--operation mode is bidir

GPIO_0[25] = BIDIR(OPNDRN(VCC));


--GPIO_0[26] is GPIO_0[26]
--operation mode is bidir

GPIO_0[26] = BIDIR(OPNDRN(VCC));


--GPIO_0[27] is GPIO_0[27]
--operation mode is bidir

GPIO_0[27] = BIDIR(OPNDRN(VCC));


--GPIO_0[28] is GPIO_0[28]
--operation mode is bidir

GPIO_0[28] = BIDIR(OPNDRN(VCC));


--GPIO_0[29] is GPIO_0[29]
--operation mode is bidir

GPIO_0[29] = BIDIR(OPNDRN(VCC));


--GPIO_0[30] is GPIO_0[30]
--operation mode is bidir

GPIO_0[30] = BIDIR(OPNDRN(VCC));


--GPIO_0[31] is GPIO_0[31]
--operation mode is bidir

GPIO_0[31] = BIDIR(OPNDRN(VCC));


--GPIO_0[32] is GPIO_0[32]
--operation mode is bidir

GPIO_0[32] = BIDIR(OPNDRN(VCC));


--GPIO_0[33] is GPIO_0[33]
--operation mode is bidir

GPIO_0[33] = BIDIR(OPNDRN(VCC));


--GPIO_0[34] is GPIO_0[34]
--operation mode is bidir

GPIO_0[34] = BIDIR(OPNDRN(VCC));


--GPIO_0[35] is GPIO_0[35]
--operation mode is bidir

GPIO_0[35] = BIDIR(OPNDRN(VCC));


--GPIO_1[0] is GPIO_1[0]
--operation mode is bidir

GPIO_1[0] = BIDIR(OPNDRN(VCC));


--GPIO_1[1] is GPIO_1[1]
--operation mode is bidir

GPIO_1[1] = BIDIR(OPNDRN(VCC));


--GPIO_1[2] is GPIO_1[2]
--operation mode is bidir

GPIO_1[2] = BIDIR(OPNDRN(VCC));


--GPIO_1[3] is GPIO_1[3]
--operation mode is bidir

GPIO_1[3] = BIDIR(OPNDRN(VCC));


--GPIO_1[4] is GPIO_1[4]
--operation mode is bidir

GPIO_1[4] = BIDIR(OPNDRN(VCC));


--GPIO_1[5] is GPIO_1[5]
--operation mode is bidir

GPIO_1[5] = BIDIR(OPNDRN(VCC));


--GPIO_1[6] is GPIO_1[6]
--operation mode is bidir

GPIO_1[6] = BIDIR(OPNDRN(VCC));


--GPIO_1[7] is GPIO_1[7]
--operation mode is bidir

GPIO_1[7] = BIDIR(OPNDRN(VCC));


--GPIO_1[8] is GPIO_1[8]
--operation mode is bidir

GPIO_1[8] = BIDIR(OPNDRN(VCC));


--GPIO_1[9] is GPIO_1[9]
--operation mode is bidir

GPIO_1[9] = BIDIR(OPNDRN(VCC));


--GPIO_1[10] is GPIO_1[10]
--operation mode is bidir

GPIO_1[10] = BIDIR(OPNDRN(VCC));


--GPIO_1[11] is GPIO_1[11]
--operation mode is bidir

GPIO_1[11] = BIDIR(OPNDRN(VCC));


--GPIO_1[12] is GPIO_1[12]
--operation mode is bidir

GPIO_1[12] = BIDIR(OPNDRN(VCC));


--GPIO_1[13] is GPIO_1[13]
--operation mode is bidir

GPIO_1[13] = BIDIR(OPNDRN(VCC));


--GPIO_1[14] is GPIO_1[14]
--operation mode is bidir

GPIO_1[14] = BIDIR(OPNDRN(VCC));


--GPIO_1[15] is GPIO_1[15]
--operation mode is bidir

GPIO_1[15] = BIDIR(OPNDRN(VCC));


--GPIO_1[16] is GPIO_1[16]
--operation mode is bidir

GPIO_1[16] = BIDIR(OPNDRN(VCC));


--GPIO_1[17] is GPIO_1[17]
--operation mode is bidir

GPIO_1[17] = BIDIR(OPNDRN(VCC));


--GPIO_1[18] is GPIO_1[18]
--operation mode is bidir

GPIO_1[18] = BIDIR(OPNDRN(VCC));


--GPIO_1[19] is GPIO_1[19]
--operation mode is bidir

GPIO_1[19] = BIDIR(OPNDRN(VCC));


--GPIO_1[20] is GPIO_1[20]
--operation mode is bidir

GPIO_1[20] = BIDIR(OPNDRN(VCC));


--GPIO_1[21] is GPIO_1[21]
--operation mode is bidir

GPIO_1[21] = BIDIR(OPNDRN(VCC));


--GPIO_1[22] is GPIO_1[22]
--operation mode is bidir

GPIO_1[22] = BIDIR(OPNDRN(VCC));


--GPIO_1[23] is GPIO_1[23]
--operation mode is bidir

GPIO_1[23] = BIDIR(OPNDRN(VCC));


--GPIO_1[24] is GPIO_1[24]
--operation mode is bidir

GPIO_1[24] = BIDIR(OPNDRN(VCC));


--GPIO_1[25] is GPIO_1[25]
--operation mode is bidir

GPIO_1[25] = BIDIR(OPNDRN(VCC));


--GPIO_1[26] is GPIO_1[26]
--operation mode is bidir

GPIO_1[26] = BIDIR(OPNDRN(VCC));


--GPIO_1[27] is GPIO_1[27]
--operation mode is bidir

GPIO_1[27] = BIDIR(OPNDRN(VCC));


--GPIO_1[28] is GPIO_1[28]
--operation mode is bidir

GPIO_1[28] = BIDIR(OPNDRN(VCC));


--GPIO_1[29] is GPIO_1[29]
--operation mode is bidir

GPIO_1[29] = BIDIR(OPNDRN(VCC));


--GPIO_1[30] is GPIO_1[30]
--operation mode is bidir

GPIO_1[30] = BIDIR(OPNDRN(VCC));


--GPIO_1[31] is GPIO_1[31]
--operation mode is bidir

GPIO_1[31] = BIDIR(OPNDRN(VCC));


--GPIO_1[32] is GPIO_1[32]
--operation mode is bidir

GPIO_1[32] = BIDIR(OPNDRN(VCC));


--GPIO_1[33] is GPIO_1[33]
--operation mode is bidir

GPIO_1[33] = BIDIR(OPNDRN(VCC));


--GPIO_1[34] is GPIO_1[34]
--operation mode is bidir

GPIO_1[34] = BIDIR(OPNDRN(VCC));


--GPIO_1[35] is GPIO_1[35]
--operation mode is bidir

GPIO_1[35] = BIDIR(OPNDRN(VCC));