Abstract -. In many existing curricula, laboratories, and
textbooks there is a notable lack of recent research advances
in CAD tools and rapid prototyping using logic synthesis tools.
Many electrical and computer engineering career paths in both
industrial research and development as well as academic research
require competence in these areas. In general, this exclusion
from undergraduate curricula results in the requirement for training
beyond the undergraduate program before a graduate becomes productive.
This paper describes a new two quarter introductory computer architecture
course and laboratory sequence in our undergraduate Computer Engineering
curriculum. CAD tools that support VHDL modeling, synthesis, and
gate level timing simulations are used by students to design a
prototype 32-bit RISC processor.
1 INTRODUCTION
The rapid evolution of the computing industry challenges academic
curricula to keep pace in providing students with a modern education.
Their experiences in school should provide them with the tools
to be productive as well as ability to challenge the existing
methodologies in discovering more efficient techniques. Traditionally,
undergraduate computer architecture laboratory courses have used
special purpose software simulators to aid in the design and modeling
of a simple computer. This model of a simple computer is used
to explain and reinforce many of the new ideas presented in lectures.
In recent years, many such courses have been based on behavioral
or RTL level simulations only. A methodology is described using
VHDL based modeling that allows for top down hierarchical design,
synthesis, and a full gate level timing simulation of a 32-bit
RISC processor by using advanced CAD tools.
This paper describes our experiences in developing a two quarter
laboratory course to accompany a computer architecture course
sequence for computer and electrical engineering majors. Our goal
was to enable students to design and develop a realistic computer
system simulation using many of the recent advances in CAD tools
for logic synthesis and simulation. One of these recent developments,
VHDL, Very High Speed Integrated Circuit Hardware Description
Language, is now widely used to model and simulate digital circuits.
VHDL has a syntax similar to Pascal or ADA. VHDL Synthesis tools
are available which automatically translate a high level VHDL
model into a gate level digital logic schematic. Increasing the
level of abstraction using automatic synthesis tools produces
substantial reductions in development time for complex digital
circuits.
Computer Architecture I and II, Computer Engineering 2510 and
3510, are required four hour, one quarter, courses taken in sequence
by computer and electrical engineering students at the Georgia
Institute of Technology. The goals of this course sequence are
to introduce students to assembly language programming, computer
arithmetic, computer architecture and to provide an introduction
to modern digital CAD tools. At the end of the sequence, students
should have a basic understanding of computer operations from
the high level language programming level to the gate level implementation
of the computer system. Students are already familiar with digital
design, computer programming in a high level language, Field Programmable
Gate Arrays, and VHDL based modeling and simulation of simple
digital logic circuits from prerequisite courses. Introduction
of modern VHDL based CAD tools into the curriculum allows more
realistic evaluation through system implementation and simulation
than has been previously possible. Example projects, student feedback,
and results from the first two offerings of this sequence are
included in this paper.
2 COMPUTER ARCHITECTURE I AND II LABORATORY
Enrollment in Computer Architecture I and II is approximately 350 students per year. Lectures are held three hours a week and three hours of laboratory work per week are required. An overview of the complete design process developed for this laboratory and the associated CAD tools are shown in Fig. 1. These tools were collected from a variety of sources and many are available free of charge to educational users via the Internet.
The lecture and laboratory outline for Computer Architecture I
and II is shown in Table 1. The MIPS 32-bit RISC assembly language,
integer and floating point computer arithmetic, and several hardware
implementations of the MIPS processor are contained in the course
textbook [1]. In Computer Engineering 2510, Computer Architecture
I, students complete three assembly language programming laboratory
assignments using SPIM, a MIPS assembler and instruction level
simulator. SPIM is a public domain program available free via
anonymous ftp for UNIX, PC and MAC platforms [1,2,3]. The first
two assembly language program assignments demonstrate integer
operations, control structures, stack operations, and subroutine
linkage.
In the second assembly language program, students compare their
hand written assembly code to the code generated by a C compiler
that has compiled a program to perform the same operation. Lcc,
a public domain retargetable C compiler, available free for UNIX
workstations and PCs, is used for this step [4]. One of the target
machines already supported by this compiler is the MIPS. MIPS
assembly language source files generated by the compiler are then
used by students to demonstrate compiler code generation.
In the final assembly language program, students implement a floating
point function such as square root. The SPIM MIPS simulator supports
floating point instructions and operations. IEEE Standard 754
floating point format is used in the MIPS processor [1,2,3].
After completing MIPS assembly language laboratory assignments,
students have two laboratory assignments in which they modify
a VHDL model of a MIPS RISC processor. A synthesizable VHDL model
of the MIPS was developed at Georgia Tech for use in this laboratory.
It should be noted that existing synthesis tools impose a number
of restrictions upon the VHDL source code and require the use
of a subset of standard VHDL.
In addition to a Pascal or ADA based syntax, VHDL includes several
extensions which make it useful for modeling of digital circuits
[5]. VHDL processes and modules execute in parallel. The WAIT
statement suspends a process until the specified condition is
true. A WAIT statement which waits for the clock signal to change
is used to model and synthesize latches and flip-flops. Another
VHDL extension is the AFTER keyword. The keyword, AFTER, followed
by a time delay can be used to model the physical time delays
present in digital circuits. These features permit VHDL to model
the parallel operation of digital hardware even including physical
time delays, if so desired. Behavioral VHDL based modeling of
digital systems has been in use for several years. VHDL based
logic synthesis is a newer development.
A simple VHDL synthesis example using the MIPS control unit is
shown in Figs. 2 and 3. The VHDL source code is shown in Fig.
2 and the schematic automatically generated by the synthesis tool
is shown in Fig. 3. The input to this module is the 6-bit instruction
opcode, OP(5-0). The language support for bit vectors or arrays
of bits, such as OP, greatly simplifies coding of the VHDL model.
All busses and register values use the bit vector data type. It
is possible to change the entire value of a bit vector with one
assignment statement or to access smaller bit fields when needed.
The outputs of this VHDL module are the various control signals
used in the processor. The synthesis tool automatically performs
logic minimization and multi-level logic synthesis. As an example,
many of the intermediate level gate outputs are shared between
the various output circuits shown in the schematic in Fig. 3.
The original VHDL code had logic equations with six inputs for
the opcode bits. More than two levels of gating are required for
implementation, since the logic technology used for synthesis
allows a maximum of four inputs per gate.
In the two VHDL based laboratory assignments, new instructions
and features are added to the VHDL model of the MIPS processor.
Detailed block diagrams of the MIPS processor architecture are
presented in the course textbook [1]. Changes and additions to
the block diagram are made as new instructions are added to the
processor. Students determine the hardware changes or additions
needed and modify the appropriate source code in the MIPS VHDL
model. Typical assignments have included the addition of unconditional
branch instructions and unsigned add operations. The entire design
is resynthesized to a gate level schematic, and a gate level timing
simulation running a short machine language test program is used
to verify correct operation of the new instructions. Tutorial
and batch command files are included to make the process simple
enough for first time users of the CAD tools.
Student's VHDL models are automatically synthesized into gate
level logic and simulated using a popular commercial CAD tool,
Viewlogic. Several other VHDL based CAD synthesis tools could
also be used such as Synopsys[6], Mentor, or Cadence; however,
these are available only for UNIX platforms. Viewlogic's VHDL
synthesis and simulation tools are currently available for UNIX
or PC platforms at a substantial educational discount. For PC
based Viewlogic, an 80486 based or faster PC with at least 16
megabytes of memory and 100 megabytes of available disk space
is recommended. We currently have forty such machines available
for student use in this laboratory. In addition to class handouts,
several VHDL references are provided and a full set of CD-ROM
on-line documentation for the VHDL CAD tool is available via a
shared network drive [7,8]. The Xlilinx 4000 ASIC, Application
Specific Integrated Circuit, technology library is used for gate
level synthesis and timing information [8]. With minor changes
it is possible to resynthesize using other ASIC technologies.
Gate count and timing information is automatically reported by
the synthesis tool.
The VHDL synthesis tool has predefined VHDL based implementations
of adders, subtractors, and flip-flops making the design process
easier. Hardware for addition, subtraction, and register storage
operations can be automatically generated by function calls in
the VHDL code. Unfortunately, with current VHDL synthesis tools
there is no universal industry standard for these functions. Since
there is no VHDL synthesis standard these portions of the VHDL
model would need to be modified if a different VHDL synthesis
CAD tool is used.
It is possible for students to examine the synthesized schematics
and to experiment with different hardware design tradeoffs such
as time and area. When running simulations, a timing diagram can
be produced and it is also possible to back annotate the schematics
with simulation values to aid in debugging.
A full 32-bit version of the MIPS requires several hours to synthesize
on the PC platform. A smaller version with an 8-bit data path
with full 32-bit instructions and control was developed to permit
the design to synthesize and simulate quickly for student laboratory
assignments. This version has minimal VHDL source level modifications
from the 32-bit version. Changes are limited to the bit vector
array size declarations for variables and signals in the data
path. The smaller model requires machine language test programs
that use 8-bit integer values. Since the hardware test programs
in the textbook are just a few instructions long and relatively
simple, this has not affected the pedagogical value of the MIPS
VHDL model.
Machine language test programs can be hand assembled, assembled
using the SPIM assembler, or even produced using the C compiler.
This machine language file is then read into the VHDL model's
memory with a read command or hardcoded into a VHDL synthesized
ROM used to simulate instruction memory. On current generation
PCs, the entire synthesis process for the smaller model requires
several minutes of computer time. Approximately 3,500 gates are
used to implement the basic MIPS VHDL model. After student modifications
that add new features, the improved pipelined MIPS processor uses
approximately 6,000 gates.
In Computer Engineering 3510, Computer Architecture II, students
study pipelining techniques, caches, virtual memory, and I/O hardware.
In laboratory assignments, students modify the synthesizable VHDL
model to create an improved MIPS RISC processor with pipelining.
In the first laboratory assignment, students pipeline the existing
MIPS VHDL model. The VHDL model contains separate modules for
each of the five MIPS pipeline stages making the student pipelining
process much easier. In this assignment, students add the pipeline
registers to each stage or module and modify the control unit.
A top-level VHDL structural model is used to connect the five
stages together. This structure generates two levels of hierarchy
in the design. Breaking up the model into different pipeline stages
makes the model much easier to understand and to synthesize. The
textbook contains detailed block diagrams of the pipelined MIPS
processor[1]. Instructions are traced one clock cycle at a time
as they move through the pipeline stages and the value of all
busses and control signals are shown in a detailed set of diagrams.
Short machine language test programs identical to those presented
in the course textbook are run in the simulator to verify correct
operation. Using the simulation output, a timing diagram with
bus values indicated in hexadecimal, students can check the computer's
operation against the textbook's diagrams to verify correct operation.
On the PC platform, the VHDL gate level timing simulator can execute
the MIPS test programs in a few seconds.
In the second laboratory assignment, automatic pipeline stalling
using a hazard detection unit is added to the pipelined MIPS VHDL
model. The textbook modifies the control unit to detect a data
hazard between instructions in the pipeline and to stall or wait
a clock cycle. An example data hazard would be an instruction
in the pipeline that writes a register that is then read by the
instruction that immediately follows it. The pipelined register
write occurs after the read operation for the next instruction
and the incorrect register data value would be used. This problem
is solved by stalling and later by forwarding. These problems
are carefully avoided by the MIPS machine language test programs
until they are discussed in the textbook and corrected by adding
additional hardware.
In the third laboratory assignment, forwarding is added between
the pipeline stages to reduce the number of stalls. As outlined
in the textbook, two forwarding multiplexers are added to the
ALU inputs along with a more complex control unit that selects
the appropriate input when it detects a data hazard. In the case
of a register data hazard, the new value of the register is supplied
to the ALU by the forwarding multiplexer before it is written
back to the register file.
In the fourth assignment, branch flushing is added to the pipelined
MIPS VHDL model. When a branch is taken several instructions after
the branch are already in the pipeline and they must be automatically
cleared out of the pipeline or flushed. The control unit and pipeline
registers are modified to detect a branch flush operation and
to clear the appropriate pipeline registers to avoid executing
unwanted instructions already in the pipeline.
In the final assignment, additional features such as a cache,
exception handling hardware, or a different branch instruction
scheme are added to the pipelined MIPS VHDL model. On the MIPS
processor exceptions, such as overflow, save the current PC in
a special register and jump to a trap address. In each laboratory
assignment, complete synthesis of the design to gate level, followed
by a full gate level timing simulation is used to execute short
machine language test programs.
Over the two quarter sequence, most students have encountered
timing problems present in their VHDL models that cause errors
in the VHDL gate level timing simulation. In every case, it was
a real timing problem traced back to VHDL coding errors. They
were able to detect and diagnose the problem using the simulation,
modify the VHDL model, resynthesize, and eliminate the timing
problems. Problems included uninitialized values in flip-flops,
combinatorial loops, gating signals with the clock, and logic
hazards on critical write control lines. These real world problems
familiar to most experienced digital designers are not detected
by most RTL or VHDL behavioral simulations.
Actual VLSI chip designs with higher clock rates could be automatically
produced using the VHDL synthesis generated schematic or netlist
as the input to a silicon compiler [9]. The Lager silicon compiler
automatically generates a standard cell layout. Interfaces to
this tool have been developed for synthesized designs using Viewlogic
VHDL. This tool is available upon request for UNIX platforms free
of charge to educational users. In theory, a MIPS VLSI processor
chip could then be fabricated using a VLSI fabrication service.
The actual fabrication process would be costly and would add a
substantial delay due to VLSI fabrication times. Actual fabrication
of the chip would make design turnarounds difficult, if not impossible,
in a one quarter course. It would also be possible to fit the
entire MIPS VHDL synthesized design into a large Xilinx FPGA chip
such as a 4005 or onto several automatically interconnected Xilinx
FPGA chips in a hardware emulation device [10,11]. This option
is being investigated for use in a more advanced computer architecture
laboratory design course, Computer Engineering 4500 [12]. In future
offerings of Computer Architecture II, for the final laboratory
project, MIPS processor designs will be compiled into a VLSI standard
cell layout and then simulated to examine the resulting timing
and area information.
3 CONCLUSIONS
VHDL synthesis and simulation provides a new paradigm for computer
architecture classes. With current generation CAD tools it is
possible for undergraduate students to design and develop working
simulations of complex computer systems as part of their laboratory
work. The equipment and CAD tools required are available to schools
at prices comparable to existing instructional laboratories. A
copy of the MIPS VHDL synthesis model is available from the author
upon request or on the Internet at http://www.ee.gatech.edu or
ftp.ee.gatech.edu. Student feedback has encouraged the continued
use of the new VHDL based CAD tools. Students gain a sense of
accomplishment and work harder on the computer design projects
when given the opportunity to use advanced general purpose CAD
tools with realistic timing and gate level simulations rather
than a special purpose computer simulation program. Rapid prototyping
of the design using synthesis and simulation in the laboratory
demonstrates and unifies many of the ideas taught in numerous
undergraduate classes and serves as an ideal laboratory course
for introductory computer architecture students.
4 ACKNOWLEDGMENTS
The authors would like to thank the many students and teaching
assistants who aided in the development of this new laboratory.
Donations of Personal Computers from Intel, and CAD tools from
Viewlogic and Xilinx made the development of this new laboratory
possible. A grant from the Georgia Tech Foundation enabled the
purchase of additional software and equipment needed for the laboratory.
REFERENCES
[1] Patterson, D. and Hennessy, J., Computer Organization &
Design The Hardware/Software Interface, San Mateo, CA: Morgan
Kaufmann, 1994.
[2] Larus, J., Assemblers, Linkers, and the SPIM Simulator, University of Wisconsin, 1991. Reprinted in [1], manual and SPIM software available via ftp from ftp.cs.wisc.edu.
[3] Heinrich, J., MIPS R4000 User's Manual, Englewood Cliffs,N.J.: Prentice Hall,. 1993.
[4] Fraser, C.and Hanson, D., A Retargetable C Compiler: Design and Implementation, Redwood City, CA: Benjamin/Cummings Publishing, 1995. Information and compiler source code available from http://www.cs.princeton.edu/software/lcc
[5] Ashenden, P., The VHDL Cookbook, University of Adelaide, 1990. Available via ftp from bears.ece.ucsb.edu.
[6] Kurup, P., and Abbasi, T., Logic Synthesis Using Synopsys, Boston, Mass: Kulwer Academic Publishers, 1995. Synopsys information available from
http://www.synopsys.com
[7] VHDL Reference Manual for Synthesis, Marlboro Massachusetts:
Viewlogic Systems, 1992. Viewlogic information available from
http://www.viewlogic.com
[8] XACT Viewlogic Interface User Guide, San Jose, CA: Xilinx Corporation, 1994.
Xilinx information available from http://www.xilinx.com
[9] Brodersen, R.W., editor., Anatomy of a Silicon Compiler, Boston, Mass:
Kulwer Academic Publishers , 1992. Lager information available from
http://infopad.EECS.berkeley.edu/research/tools/lager
[10] Owen, H., Khan, U., and Hughes, J., "FPGA Based Emulator Architectures", More FPGAs (Will Moore and Wayne Luk, Eds.), Abbingondon, England: Abbingondon EE & CS Books, pp. 399-409 (1994). Emulator Information available from http://www.zycad.com and http://www.quickturn.com
[11] Khan, U., Owen, H., and Hughes, J., "FPGA Architectures for ASIC Hardware Emulators," Proceedings of the Sixth Annual IEEE International ASIC '93, New York, pp. 336-340, October 1993.
[12] Hamblen, J., Owen, H. L., and Yalamanchili, S., "Introduction of Rapid Systems Prototyping into Undergraduate Computer Engineering Curricula," Proceedings of the Twenty Fifth Annual ASEE Frontiers in Education Conference, Atlanta, GA., November 1995. Available from http://fre.www.ecn.purdue.edu/fre/asee/fie95
TABLE 1 Outline of Lecture and Laboratory Topics
| Week | Computer Architecture I
Laboratory Assignment | Computer Architecture I
Lecture Topic |
| 1 | SPIM tutorial | MIPS RISC architecture |
| 2 | First assembly lang. program | MIPS instruction Set |
| 3 | " | SPIM assembly language |
| 4 | Second assembly lang. program | Stacks and subroutines |
| 5 | MIPS C compiler | Integer computer arithmetic |
| 6 | MIPS floating point program | Floating point arithmetic |
| 7 | VHDL CAD tool tutorial | Overview of VHDL |
| 8 | VHDL synthesis and simulation running a new test program | MIPS processor hardware implementation and VHDL model |
| 9 | VHDL synthesis and simulation
adding a new instruction | Modifying hardware and VHDL to add new instructions and features |
| 10 | " | Alternative microcoded MIPS |
| Week | Computer Architecture II
Laboratory Assignment | Computer Architecture II
Lecture Topic |
| 1 | VHDL CAD tool tutorial | Overview of pipelining |
| 2 | Pipelining the MIPS design | Pipelining the MIPS hardware |
| 3 | " | Pipeline control problems |
| 4 | Adding a hazard unit to the MIPS | MIPS hazard detection hardware |
| 5 | " | MIPS forwarding unit |
| 6 | Adding forwarding to the MIPS | " |
| 7 | " | MIPS branch flushing |
| 8 | Add branch flushing to the MIPS | I/O devices and busses |
| 9 | " | Caches and virtual memory |
| 10 | Compile MIPS chip design | Introduction to parallel computers |