Page 14
        Near bottom of page change "ENTITY declaration appears unhighlight" to "ENTITY declaration appears highlighted"

Page 15
        The top two VHDL source code lines in figure 1.11 will not appear until this text is added as per instructions on the following page.

Page 19
        Second paragraph. There is only one occurrence of _module_name (in Verilog)

Page 23
        Middle of page. Software menu name has changed.  Change "MAX+PLUS II=> Floorplanner" to "MAX+PLUS II=> Floorplan Editor"

Page 24
        Near bottom of page. Some software versions may now require that you unselect Functional SNF extractor to switch back to the Timing SNF extractor.

Page 64
        Second paragraph, first sentence. Delete "provide"

Page 127
        In Figure 8.9, the signal labeled "register_A" should be labeled "register_AC"
 
 

Page 5
        equation should read:
         "LED =  PB1 + PB2"

Page 12
        After Figure 1.10, insert the following line of text:
        "Verify that the device jumpers are set for the FLEX chip as shown in Table 1.2"

Page 89
        VHDL port declaration for product is missing a space between OUT and STD_LOGIC_VECTOR

Page 106
        In Figure 7.6, the left branch from Ain should read "d1" not "1d". In the lower right the labels
        for the S3 decision block, "0" and "1" are swapped.

Page 109
        last WHEN in VHDL code is missing a ">" after the "="

Page 124
        FETCH equation in text should read IR=MDR (not MAR!):
         "PC=PC+1, MAR=PC, read memory, IR=MDR"

Page 198
        In Figure 13.1, the data memory mux at bottom right has the 0 and 1 inputs swapped.

Page 199
        In Figure 13.2, near the bottom just to the right of the leftmost pipeline register, is missing a line that connects the Instruction bus to the signals, Instruction[20-16] and Instruction[15-11]. They do not just connect to the write data line.
 
 

Be sure to turn off the read-only file attribute if you use Windows to copy the example design files from the CD-ROM. The Altera tools will generate several file errors and not function correctly if the read only file attribute is set. This is not a problem if the DOS copy command is used. Also don't forget to copy the vhd.dll patch file on the CD-ROM to the Maxplus directory. Details are in the Index.htm instruction file on the CD-ROM.

Windows 2000 note: On our machine, the Altera student version will install, compile, and simulate. The byteblaster programming interface used to download the UP 1 board is not recognized so the UP 1 board cannot be downloaded. It appears to be a printer port driver problem and Altera thinks it will probably be a few months before a patch is available. We have also recently seen a few complex programs than run fine in NT or 98 lock up the compiler in 2000.
 

Chapter 7 - You will need a new version of the train.acf file to see the video display. The pin assignments for the video signals are missing on the CDROM version of this file.

Chapter 12 - There is a new version of the robot IR proximity sensor VHDL code in the file ir_sensor.vhd. The CD-ROM version of this file does not function correctly with the new Altera tools.

Chapter 13 - If you use a vector file for MIPS simulations and do not use the *.scf file provided, you will need a new version of the file, top_spim.vec.

If you are using MaxPlus version 9.3 or higher instead of the student version on the CD-ROM, some LPM parameters such as LPM_numwords have been changed from strings to integers - you can fix this by just removing the quote marks on the LPM parameters that generate an error. One such LPM error occurs in the memory LPM blocks in the book's designs. If you are using MaxPlus version 9.5 or higher and you get "fatal fitter errors" or "will not fit" you should turn off the new Quartus fitter settings. Open a compiler window and this option is under Processing -> Fitter Settings. Anytime you get an internal error in MaxPlus it is probably best to exit and re-start.

Authorization code for software (install software first and obtain disk serial#)

Student UP 1 Board Order Form