Page
19
Second paragraph. There is only one occurrence of _module_name
(in
Verilog)
Page
23
Middle of page. Software menu name has changed. Change "MAX+PLUS
II=> Floorplanner" to "MAX+PLUS II=> Floorplan Editor"
Page
24
Near bottom of page. Some software versions may now require that you unselect
Functional
SNF extractor to switch back to the Timing SNF extractor.
Page
64
Second paragraph, first sentence. Delete "provide"
Page
124
Paragraph under figure 8.6 change "contents of A and stores the result
in A" to "contents of AC and stores the result in AC"
Insert this sentence in the last paragraph after the first sentence,
"(The
operation MAR=PC is actually moved from fetch to the final
execute state in the example UP1 VHDL code to save a clock cycle.)"
Page
127
In Figure 8.9, the signal labeled "register_A" should be labeled "register_AC"
Text
Errata - First Printing
(corrected
in Second Printing of 1/2000)
Note:
A Second printing confirmation note can be found just below the copyright
notice
on
the back of the title page. If the line is blank, you have the first printing.
Page
5
equation should read:
"LED = PB1 + PB2"
Page
12
After Figure 1.10, insert the following line of text:
"Verify that the device jumpers are set for the FLEX chip as shown in Table
1.2"
Page
89
VHDL port declaration for product is missing a space between OUT
and STD_LOGIC_VECTOR
Page
106
In Figure
7.6, the left branch from Ain should read "d1" not "1d". In the lower right
the labels
for the S3
decision block, "0" and "1" are swapped.
Page
109
last WHEN in VHDL code is missing a ">" after the "="
Page
124
FETCH equation in text should read IR=MDR (not MAR!):
"PC=PC+1, MAR=PC, read memory, IR=MDR"
Insert this sentence in the last paragraph after the first sentence,Page 198
"(The operation MAR=PC is actually moved from fetch to the final execute state in the example UP1 VHDL code to save a clock cycle.)"
Page
199
In Figure 13.2, near the bottom just to the right of the leftmost pipeline
register, is missing a line that connects the Instruction bus to the signals,
Instruction[20-16] and Instruction[15-11]. They do not just connect to
the write data line.
Software Updates for All Printings
New
Altera UP 1X and UP 2 Boards
Altera
has just released a new board called the UP 2. This new board is identical
to the older UP 1X, but it is a new lower cost PCB layout. For UP 1X or
UP 2 boards, you must compile for a larger FLEX 10K70 Device. The book's
designs should work without problems after recompiling for the larger device
(use ASSIGN DEVICE to change it). You will need to install the new Altera
student version 10.1 software to support these larger devices.
Be sure to turn off the read-only file attribute if you use Windows to copy the example design files from the CD-ROM. The Altera tools will generate several file errors and not function correctly if the read only file attribute is set. This is not a problem if the DOS copy command is used. Also don't forget to copy the vhd.dll patch file on the CD-ROM to the Maxplus directory. Details are in the Index.htm instruction file on the CD-ROM.
Windows
2000 note: On our machine, the Altera
student version will install, compile, and simulate. The byteblaster programming
interface used to download the UP 1 board is not recognized so the UP 1
board cannot be downloaded. Only the WIN2000 byteblaster driver in MAXPLUS
II 10 or later will work. This driver has to be manually installed just
like in Windows NT.
Chapter 7 - You will need a new version of the train.acf file to see the video display. The pin assignments for the video signals are missing on the CDROM version of this file.
Chapter 12 - There is a new version of the robot IR proximity sensor VHDL code in the file ir_sensor.vhd. The CD-ROM version of this file does not function correctly with the new Altera tools.
Chapter 13 - If you use a vector file for MIPS simulations and do not use the *.scf file provided or are using one of the more recent versions of MAXPLUS, you will need a new version of the file, top_spim.vec.
If you are using MaxPlus version 9.3 or higher instead of the student version on the CD-ROM, some LPM parameters such as LPM_numwords have been changed from strings to integers - you can fix this by just removing the quote marks on the LPM parameters that generate an error. One such LPM error occurs in the memory LPM blocks in the book's designs. If you are using MaxPlus version 9.5 or 9.6 and you get "fatal fitter errors" or "will not fit" you should turn off the new Quartus fitter settings. Open a compiler window and this option is under Processing -> Fitter Settings. Anytime you get an internal error in MaxPlus it is probably best to exit and re-start.
MAXPLUS II version 10 is being tested. We
have run several of the Altera UP1 designs with video on version 10 and
have downloaded them using Windows 2000 - so far everything works. The
bouncing ball video demo program needed some bit width changes - any program
with a VHDL less than or greater than test that does not have the same
number of bits on each side will need a change - another warning that is
now an error! This one just says bit width error and does not point out
the line. The parameter lpm_numwords on memory is not a string anymore
just like version 9.3 and greater (it's now an integer so just delete the
quotes - you will see this in the computer and character ROM lpm memory
calls). On 2000, after installing version 10, you have to manually add
the byteblaster driver at c:/maxplus2/drivers/win2000 (and the NT based
instructions are a bit out of date on this on 2000 - still a media device
for some reason). We did not have to turn off the Quartus fitter anymore.
One new thing: The programming file automatically changes to the current
project.sof
- saves all of that complex JTAG menu stuff to change the file name! -
a big time saver. If you run MAXPLUS II version 10 and you need the book's
design files for WIN2000 send us an email or get the CD-ROM from the second
edition of the book.
Authorization code for software (install software first and obtain disk serial#)