--
--
-- FPGA Life VHDL Module - Conway's Game of Life for Altera University Board 
-- Uses Flex 10K20 Device
--
-- Jim Hamblen, Georgia Tech School of ECE
--
-- PB1 is run/stop (powers up in stop mode)
-- PB2 is single step (in stop mode) Flex 8 since my PB2 is dead
-- Flex Switch 7..4 is Speed (try sw7,6,5,4 open others closed for fast update)
-- Flex Switch 2 is Reverse Video
library IEEE;
use  IEEE.STD_LOGIC_1164.all;
use  IEEE.STD_LOGIC_ARITH.all;
use  IEEE.STD_LOGIC_UNSIGNED.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;


entity cgenrom is

Generic(ADDR_WIDTH: integer := 12; DATA_WIDTH: integer := 8);

   port(address: in std_logic_vector(11 Downto 0);
        data: out std_logic_vector(7 Downto 0) );
		
end cgenrom;

architecture behavior of cgenrom is
begin
 video_ram_a: lpm_rom
      GENERIC MAP (lpm_widthad => ADDR_WIDTH,
        lpm_outdata => "UNREGISTERED",
        lpm_address_control => "UNREGISTERED",
-- Reads in mif file for initial data - a Rabbit Methuselah (simple long lived pattern)
         lpm_file => "cgenrom.mif",
         lpm_width => DATA_WIDTH)
      PORT MAP ( address => address, q => data);
 
end behavior;