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Table of Contents


1<= span style=3D'font-size:12.0pt;font-weight:normal;font-style:normal'>    Tutorial I: The = 15 Minute Design________________________= _______ 2=

1.1<= span style=3D'mso-tab-count:1'>     Design Ent= ry using the Graphic Editor_____________= ________________________ 7

1.2<= span style=3D'mso-tab-count:1'>     Compiling = the Design_______________________________= ____________________ 13

1.3<= span style=3D'mso-tab-count:1'>     Simulation= of the Design___________________________= _____________________ 14

1.4<= span style=3D'mso-tab-count:1'>     Downloadin= g Your Design to the UP 3 Board_____________= _________________ 15

1.5<= span style=3D'mso-tab-count:1'>     Downloadin= g Your Design to the UP 2 Board_____________= _________________ 18

1.6<= span style=3D'mso-tab-count:1'>     The 10 Min= ute VHDL Entry Tutorial__________________= ___________________ 20

1.7<= span style=3D'mso-tab-count:1'>     Compiling = the VHDL Design__________________________= __________________ 23

1.8<= span style=3D'mso-tab-count:1'>     The 10 Min= ute Verilog Entry Tutorial_______________= ______________________ 24

1.9<= span style=3D'mso-tab-count:1'>     Compiling = the Verilog Design_______________________= _____________________ 26

1.10=     Timing Analysis<= span style=3D'mso-tab-count:1 lined'>___________________________________________= ____________ 27

1.11=     The Floorplan Ed= itor___________________________________________= ________ 28

1.12=     Symbols and Hier= archy___________________________________________= ______ 30

1.13=     Functional Simul= ation___________________________________________= _______ 30

1.14=     Laboratory Exerc= ises___________________________________________= ________ 31

2    The Altera UP 3 Board_______________= _______________________ 36=

2.1<= span style=3D'mso-tab-count:1'>     The UP 3 C= yclone FPGA Features________________________= ________________ 37

2.2<= span style=3D'mso-tab-count:1'>     The UP 3 Board’s Memory Features________= ______________________________ 38

2.3<= span style=3D'mso-tab-count:1'>     The UP 3 Board’s I/O Features___________= ________________________________ 38

2.4<= span style=3D'mso-tab-count:1'>     Obtaining a UP 3 Board and Cables___________= ___________________________ 41

3    Pr= ogrammable Logic Technology_____________________= _________ 44=

3.1<= span style=3D'mso-tab-count:1'>     CPLDs and = FPGAs___________________________________________= __________ 47

3.2<= span style=3D'mso-tab-count:1'>     Altera MAX= 7000S Architecture – A Product Term CPLD Device_____________ 48

3.3<= span style=3D'mso-tab-count:1'>     Altera Cyc= lone Architecture – A Look-Up Table FPGA Device________________ 50

3.4<= span style=3D'mso-tab-count:1'>     Xilinx 4000 Architecture – A Look-Up Table FPGA Device___________________ 53

3.5<= span style=3D'mso-tab-count:1'>     Computer A= ided Design Tools for Programmable Logic__= ___________________ 55

3.6<= span style=3D'mso-tab-count:1'>     Next Gener= ation FPGA CAD tools_______________________= ________________ 56

3.7<= span style=3D'mso-tab-count:1'>     Applicatio= ns of FPGAs________________________________= _________________ 57

3.8<= span style=3D'mso-tab-count:1'>     Features o= f New Generation FPGAs_____________________= __________________ 57

3.9<= span style=3D'mso-tab-count:1'>     For additi= onal information__________________________= ____________________ 58

3.10=     Laboratory Exerc= ises___________________________________________= ________ 58

4    Tu= torial II: Sequential Design and Hierarchy__= ___________________ 62=

4.1<= span style=3D'mso-tab-count:1'>     Install the Tutorial Files and UP3core Library___= ___________________________ 62

4.2<= span style=3D'mso-tab-count:1'>     Open the t= utor2 Schematic____________________________= __________________ 63

4.3<= span style=3D'mso-tab-count:1'>     Browse the Hierarchy____________________________= _______________________ 63

4.4<= span style=3D'mso-tab-count:1'>     Using Buse= s in a Schematic____________________________= __________________ 65

4.5<= span style=3D'mso-tab-count:1'>     Testing the Pushbutton Counter and Displays______= ________________________ 66

4.6<= span style=3D'mso-tab-count:1'>     Testing the Initial Design on the Board__________= __________________________ 67

4.7<= span style=3D'mso-tab-count:1'>     Fixing the Switch Contact Bounce Problem________= ________________________ 68

4.8<= span style=3D'mso-tab-count:1'>     Testing the Modified Design on the UP 3 Board____= ________________________ 69

4.9<= span style=3D'mso-tab-count:1'>     Laboratory Exercises____________________________= _______________________ 69

5    UP= 3core Library Functions____________________= _______________ 74=

5.= 1     UP3core LCD_Display: LCD Panel Character Display_______________________ 76

5.2<= span style=3D'mso-tab-count:1'>     UP3core Debounce: Pushbutton Debounce________= _________________________ 77

5.3<= span style=3D'mso-tab-count:1'>     UP3core OnePulse:  Pushbutton Single P= ulse_______________________________ 78

5.4<= span style=3D'mso-tab-count:1'>     UP3core Cl= k_Div: Clock Divider________________________= _________________ 79

5.5<= span style=3D'mso-tab-count:1'>     UP3core VGA_Sync: VGA Video Sync Generation__= ________________________ 80

5.6<= span style=3D'mso-tab-count:1'>     UP3core Char_ROM:  Character Generatio= n ROM_________________________ 82

5.7<= span style=3D'mso-tab-count:1'>     UP3core Keyboard: Read Keyboard Scan Code____= ________________________ 83

5.8<= span style=3D'mso-tab-count:1'>     UP3core Mo= use: Mouse Cursor_________________________= _________________ 84

5.9<= span style=3D'mso-tab-count:1'>     For additi= onal information__________________________= ____________________ 85

6    Us= ing VHDL for Synthesis of Digital Hardware___________________ 88=

6.1<= span style=3D'mso-tab-count:1'>     VHDL Data = Types___________________________________________= __________ 88

6.2<= span style=3D'mso-tab-count:1'>     VHDL Opera= tors___________________________________________= ___________ 89

6.3<= span style=3D'mso-tab-count:1'>     VHDL Based Synthesis of Digital Hardware________= ________________________ 90

6.4<= span style=3D'mso-tab-count:1'>     VHDL Synth= esis Models of Gate Networks______________= __________________ 90

6.5<= span style=3D'mso-tab-count:1'>     VHDL Synth= esis Model of a Seven-segment LED Decoder_= __________________ 91

6.6<= span style=3D'mso-tab-count:1'>     VHDL Synth= esis Model of a Multiplexer_______________= ___________________ 93

6.7<= span style=3D'mso-tab-count:1'>     VHDL Synth= esis Model of Tri-State Output____________= ____________________ 94

6.8<= span style=3D'mso-tab-count:1'>     VHDL Synth= esis Models of Flip-flops and Registers___= ______________________ 94

6.9<= span style=3D'mso-tab-count:1'>     Accidental Synthesis of Inferred Latches________= __________________________ 96

6.10=     VHDL Synthesis M= odel of a Counter_________________________= ____________ 96

6.11=     VHDL Synthesis M= odel of a State Machine___________________= _____________ 97

6.12=     VHDL Synthesis M= odel of an ALU with an Adder/Subtractor and a Shifter_____ 99

6.13=     VHDL Synthesis of Multiply and Divide Hardware_________= ________________ 100

6.14=     VHDL Synthesis M= odels for Memory___________________________= _________ 101

6.15    Hierarchy in VHDL Synthesis Models____________________________________ 105

6.16=     Using a Testbenc= h for Verification_________________________= ______________ 107

6.17=     For additional information__________________________= ___________________ 108

6.18=     Laboratory Exerc= ises___________________________________________= _______ 108

7    Us= ing Verilog for Synthesis of Digital Hardware__________________ 112=

7.1<= span style=3D'mso-tab-count:1'>     Verilog Da= ta Types________________________________= ____________________ 112

7.2<= span style=3D'mso-tab-count:1'>     Verilog Ba= sed Synthesis of Digital Hardware________= ______________________ 112

7.3<= span style=3D'mso-tab-count:1'>     Verilog Operators____________________________= _________________________ 113

7.4<= span style=3D'mso-tab-count:1'>     Verilog Synthesis Models of Gate Networks____= ___________________________ 114

7.5<= span style=3D'mso-tab-count:1'>     Verilog Synthesis Model of a Seven-segment LED Decoder__________________ 114

7.6<= span style=3D'mso-tab-count:1'>     Verilog Synthesis Model of a Multiplexer_____= ____________________________ 115

7.7<= span style=3D'mso-tab-count:1'>     Verilog Synthesis Model of Tri-State Output__= ____________________________ 116

7.8<= span style=3D'mso-tab-count:1'>     Verilog Synthesis Models of Flip-flops and Registers_______________________ 117

7.9<= span style=3D'mso-tab-count:1'>     Accidental Synthesis of Inferred Latches________= _________________________ 118

7.10=     Verilog Synthesis Model of a Counter___________________= _________________ 118

7.11=     Verilog Synthesis Model of a State Machine_____________= _________________ 119

7.12=     Verilog Synthesis Model of an ALU with an Adder/Subtractor and a Shifter___ 120

7.13=     Verilog Synthesi= s of Multiply and Divide Hardware_________= _______________ 121

7.14=     Verilog Synthesis Models for Memory____________________= _______________ 122

7.15    Hierarchy in Verilog Synthesis Models___________________________________ = 125

7.16=     For additional information__________________________= ___________________ 126

7.17=     Laboratory Exerc= ises___________________________________________= _______ 126

8    St= ate Machine Design: The Electric Train Controller______________ 130=

8.1<= span style=3D'mso-tab-count:1'>     The Train Control Problem______________________= _______________________ 130

8.2<= span style=3D'mso-tab-count:1'>     Track Powe= r (T1, T2, T3, and T4)______________________= _________________ 132

8.3<= span style=3D'mso-tab-count:1'>     Track Dire= ction (DA1-DA0, and DB1-DB0)_______________= ________________ 132

8.4<= span style=3D'mso-tab-count:1'>     Switch Dir= ection (SW1, SW2, and SW3)__________________= ________________ 133

8.5<= span style=3D'mso-tab-count:1'>     Train Sens= or Input Signals (S1, S2, S3, S4, and S5)_________________________ 133

8.6<= span style=3D'mso-tab-count:1'>     An Example Controller Design____________________= ______________________ 134

8.7<= span style=3D'mso-tab-count:1'>     VHDL Based Example Controller Design____________= _____________________ 138

8.8<= span style=3D'mso-tab-count:1'>     Simulation Vector file for State Machine Simulation_______________________ 140

8.9<= span style=3D'mso-tab-count:1'>     Running the Train Control Simulation_____________= ______________________ 142

8.10=     Running the Video Train System (After Successful Simulation)______________ 142

8.11=     Laboratory Exerc= ises___________________________________________= _______ 144

9    A = Simple Computer Design: The µP 3__________________________ 148=

9.1<= span style=3D'mso-tab-count:1'>     Computer Programs and Instructions____________= ________________________ 149

9.2<= span style=3D'mso-tab-count:1'>     The Proces= sor Fetch, Decode and Execute Cycle______= _____________________ 150

9.3<= span style=3D'mso-tab-count:1'>     VHDL Model= of the mP 3______________________________________________ 157

9.4<= span style=3D'mso-tab-count:1'>     Simulation= of the mP3 Computer________________________________________ 161

9.5<= span style=3D'mso-tab-count:1'>     Laboratory Exercises____________________________= ______________________ 162

10  VGA Video Disp= lay Generation___________________________= ____ 168=

10.1=     Video Display Technology___________________________= ___________________ 168

10.2=     Video Refresh___________________________________________= _____________ 168

10.3=     Using an FPGA fo= r VGA Video Signal Generation______________= ___________ 171

10.4=     A VHDL Sync Gene= ration Example: UP3core VGA_SYNC____________= ______ 172

10.5=     Final Output Reg= ister for Video Signals____________________= ______________ 174

10.6=     Required Pin Assignments for Video Output_________= _____________________ 174

10.7  &nbs= p; Video Examples_____________________________= _________________________ 175

10.8=     A Character Based Video Design_________________________= _______________ 176

10.9=     Character Select= ion and Fonts____________________________= ______________ 176

10.10  VHDL Character Display Design Examples_____________________________= __ 179

10.11  A Graphics Memory Design Exa= mple____________________________________ 181

10.12  Video Data Compression___________________________________________= ____ 182

10.13  Video Color Mixing using Dit= hering_____________________________________ 183

10.14  VHDL Graphics Display Design Example______________________________= ___ 183

10.15  Higher Video Resolution and = Faster Refresh Rates________________________= _ 185

10.16  Laboratory Exercises___________________________________________= _______ 185

11  Interfacing to= the PS/2 Keyboard and Mouse______________= ______ 188=

11.1=     PS/2 Port Connec= tions___________________________________________= ______ 188

11.2=     Keyboard Scan Co= des___________________________________________= ______ 189

11.3=     Make and Break C= odes___________________________________________= _____ 189

11.4=     The PS/2 Serial = Data Transmission Protocol________________= ______________ 190

11.5=     Scan Code Set 2 = for the PS/2 Keyboard____________________= ______________ 192

11.6=     The Keyboard UP3= core___________________________________________= _____ 194

11.7=     A Design Example= Using the Keyboard UP3core_________________= __________ 197

11.8=     Interfacing to t= he PS/2 Mouse___________________________= _______________ 198

11.9=     The Mouse UP3cor= e___________________________________________= ________ 200

11.10  Mouse Initialization___________________________________________= ________ 200

11.11  Mouse Data Packet Processing= __________________________________________ = 201

11.12  An Example Design Using the = Mouse UP3core____________________________ <= /span>202

11.13  For Additional Information___________________________________________= _ 202

11.14  Laboratory Exercises___________________________________________= _______ 203

12  Legacy Digital= I/O Interfacing Standards________________= _______ 206=

12.1=     Parallel I/O Int= erface___________________________________________= _______ 206

12.2=     RS-232C Serial I= /O Interface____________________________= _______________ 207

12.3=     SPI Bus Interfac= e___________________________________________= __________ 209

12.4=     I2C B= us Interface____________________________= _________________________ 211

12.5=     For Additional Information__________________________= __________________ 213

12.6=     Laboratory Exerc= ises___________________________________________= _______ 213

13  UP 3 Robotics Projects_____________________________= ________ 216=

13.1=     The UP3-bot Desi= gn___________________________________________= ________ 216

13.2=     UP3-bot Servo Dr= ive Motors_______________________________= ____________ 216

13.3=     Modifying the Se= rvos to make Drive Motors_________________= _____________ 217

13.4=     VHDL Servo Drive= r Code for the UP3-bot______________________= __________ 218

13.5=     Low-cost Sensors= for a UP 3 Robot Project___________________= ____________ 220

13.6=     Assembly of the UP3-bot Body_________________________= _________________ 233

13.7=     I/O Connections = to the UP 3’s Expansion Headers_______= __________________ 240

13.8=     Robot Projects B= ased on R/C Toys, Models, and Robot Kits__= ______________ 242

13.9=     For Additional Information__________________________= __________________ 248

13.10  Laboratory Exercises___________________________________________= _______ 250

14  A RISC Design: Synthesis of the MIPS Processor Core_= ___________ 256=

14.1=     The MIPS Instruc= tion Set and Processor____________________= _____________ 256

14.2=     Using VHDL to Synthesize the MIPS Processor Core___= ____________________ 259

14.3=     The Top-Level Mo= dule___________________________________________= _____ 260

14.4=     The Control Unit= ___________________________________________= __________ 263

14.5=     The Instruction = Fetch Stage________________________________= ____________ 265

14.6=     The Decode Stage= ___________________________________________= __________ 268

14.7=     The Execute Stag= e___________________________________________= __________ 270

14.8=     The Data Memory = Stage___________________________________________= ____ 272

14.9=     Simulation of th= e MIPS Design_______________________________= __________ 273

14.10  MIPS Hardware Implementation= on the UP 3 Board_______________________= 274

14.11  For Additional Information___________________________________________= _ 275

14.12  Laboratory Exercises___________________________________________= _______ 276

15  Introducing System-on-a-Programmable-Chip________= ___________ 282=

15.1=     Processor Cores<= span style=3D'mso-tab-count:1 lined'>___________________________________________= ___________ 282

15.2=     SOPC Design Flow= ___________________________________________= _________ 283

15.3=     Initializing Mem= ory___________________________________________= ________ 285

15.4=     SOPC Design vers= us Traditional Design Modalities________= ________________ 287

15.5=     An Example SOPC = Design___________________________________________= __ 288

15.6=     Hardware/Software Design Alternatives__________________= ________________ 289

15.7=     For additional information__________________________= ___________________ 289

15.8=     Laboratory Exerc= ises___________________________________________= _______ 290

16<= /span>  Tutorial III: Nios II Processor Software Development_____________ 294=

16.1=     Install the UP&n= bsp;3 board files__________________________= ___________________ 294

16.2=     Starting a Nios = II Software Project_____________________= _________________ 294

16.3=     The Nios II IDE Software_____________________________= _________________ 296

16.4=     Generating the N= ios II System Library_______________________= ____________ 297

16.5=     Software Design = with Nios II Peripherals__________________= _______________ 298

16.6=     Starting Software Design – main()________________= _______________________ 301

16.7=     Downloading the = Nios II Hardware and Software Projects____= _______________ 302

16.8=     Executing the So= ftware___________________________________________= _____ 303

16.9=     Starting Software Design for a Peripheral Test Program_= ____________________ 303

16.10  Handling Interrupts___________________________________________= ________ 306

16.11  Accessing Parallel I/O Perip= herals_______________________________________ 307

16.12  Communicating with the LCD D= isplay___________________________________ = 308

16.13  Testing SRAM___________________________________________= _____________ 311

16.14  Testing Flash Memory___________________________________________= ______ 312

16.15  Testing SDRAM___________________________________________= ___________ 313

16.16  Downloading the Nios II Hard= ware and Software Projects________________= ___ 318

16.17  Executing the Software___________________________________________= _____ 319

16.18  For additional information___________________________________________= __ 320

16.19  Laboratory Exercises___________________________________________= _______ 320

17<= /span>  Tutorial IV: Nios II Processor Hardware Design_________________ 324=

17.1=     Install the UP&n= bsp;3 board files__________________________= ___________________ 324

17.2=     Creating a New P= roject___________________________________________= _____ 324

17.3=     Starting SOPC Bu= ilder___________________________________________= ______ 325

17.= 4    Adding a Nios II Processor___________________________________________= __ 327

17.5=     Adding UART Peripherals__________________________= ____________________ 329

17.6=     Adding an Interv= al Timer Peripheral_____________________= ________________ 330

17.7=     Adding Parallel = I/O Components___________________________= _____________ 331

17.8=     Adding a SDRAM M= emory Controller___________________________= ________ 332

17.9=     Adding an Extern= al Bus___________________________________________= _____ 333

17.10  Adding Components to the Ext= ernal Bus_________________________________ = 334

17.11  Global Processor Settings___________________________________________= ___ 335

17.12  Finalizing the Nios II Proce= ssor_________________________________________ <= /span>337

17.13  Add the Processor Symbol to = the Top-Level Schematic__________________= ___ 337

17.14  Create a Phase-Locked Loop Component____________________________= ____ 338

17.15  Add the UP 3 External B= us Multiplexer Component________________= ________ 339

17.16  Complete the Top-Level Schem= atic______________________________________ 339

17.17  Design Compilation___________________________________________= ________ 339

17.18  Testing the Nios II Project<= span style=3D'mso-tab-count:1 lined'>___________________________________________= __ 341

17.19  For additional information___________________________________________= __ 341

17.20  Laboratory Exercises___________________________________________= _______ 341

Appendix  A: Generation of Pseudo Random Bin= ary Sequences________ 345=

Appendix B: Quar= tus II Design and Data File Extensions_____________ 347=

Appendix C: UP 3= Pin Assignments___________________= ____________ 349=

Appendix D: ASCII Character Code________________= ______________ 355=

Appendix E: Prog= ramming the UP 3’s Flash Memory_= _______________ 357=

Glossary__________= _________________________________________ 359=

Index_____________= _________________________________________ 367=

About the Accompanying CD-ROM______________________________ 371=



Changes to the Quartus Edition

Rapid Prototyping of Digital Systems provides an exciting and challenging laboratory component for undergraduate digital logic and computer design courses using FPGAs and CAD tools for simulation and hardware implementatio= n. The more advanced topics and exercises also make this text useful for upper level courses in digital logic, programmable logic, and embedded systems. T= he third edition now uses Altera’s new Quartus II CAD tool and includes laboratory projects for Altera’s UP 2 and the new UP 3 FPGA board. Student laboratory projects provided on the book’s CD-ROM include vid= eo graphics and text, mouse and keyboard input, and three computer designs.

Rapid Prototyping of Digital Systems includes four tutorials on the Altera Quartus II and Nios II tool environment, an overview of programmable logic,= and IP cores with several easy-to-use input and output functions. These features were developed to help students get started quickly. Early design examples = use schematic capture and IP cores developed for the Altera UP FPGA boards. VHD= L is used for more complex designs after a short introduction to VHDL-based synthesis. Verilog is also now supported more as an option for the student projects.

New chapters in this edition provide an overview of System-on-= a-Programmable Chip (SOPC) technology and SOPC design examples for the UP 3 using Altera’s new Nios II Processor hardware and C software development to= ols. A full set of Altera’s FPGA CAD tools is included on the book’s= CD-ROM.

Intended Audience

This text is intended to provide an exciting and challenging laboratory component for an undergraduate digital logic design class. The more advanced topics and exercises are also appropriate for consideration at schools that have an upper level course in digital logic or programmable logic. There are a number of excellent texts on digital logic design. For the most part, these texts do not include or fully integrate mo= dern CAD tools, logic simulation, logic synthesis using hardware description languages, design hierarchy, and current generation field programmable gate array (FPGA) technology and SOPC design. The goal of this text is to introd= uce these topics in the laboratory portion of the course. Even student laborato= ry projects can now implement entire digital and computer systems with hundred= s of thousands of gates.

Over the past eight years, we have developed a numb= er of interesting and challenging laboratory projects involving serial communications, state machines with video output, video games and graphics, simple computers, keyboard and mouse interfaces, robotics, and pipelined RI= SC processor cores.

Source files and additional example files are avail= able on the CD-ROM for all designs presented in the text. The student version of= the PC based CAD tool on the CD-ROM can be freely distributed to students. Stud= ents can purchase their own UP 3 board for little more than the price of a contemporary textbook. As an alternative, a few of the low-cost UP 3 boards= can be shared among students in a laboratory. Course instructors should contact= the Altera University Program for detailed information on obtaining full versio= ns of the CAD tools for laboratory PCs and UP 3 boards for student laboratorie= s.

Topic Selection and Organization

Chapter 1 is a short CAD tool tuto= rial that covers design entry, simulation, and hardware implementation using an = FPGA. The majority of students can enter the design, simulate, and have the design successfully running on the UP 3 board in less than thirty minutes. After working through the tutorial and becoming familiar with the process, similar designs can be accomplished in less than 10 minutes.

Chapter 2 provides an overview of = the UP 3 FPGA development boards. The features of the board are briefly described. Several tables listing pin connections of various I/O devices serve as an essential reference whenever a hardware design is implemented on the UP 3 board.

Chapter 3 is an introduction to programmable logic technology. The capabilities and internal architectures = of the most popular CPLDs and FPGAs are described. These include the Cyclone F= PGA used on the UP 3 board, and the Xilinx 4000 family FPGAs.

Chapter 4 is a short CAD tool tuto= rial that serves as both a hierarchical and sequential design example. A counter= is clocked by a pushbutton and the output is displayed in the seven-segment LED’s. The design is downloaded to the UP 3 board and some real world timing issues arising with switch contact bounce are resolved. It uses seve= ral functions from the UP3core library which greatly simplify use of the UP 3&#= 8217;s input and output capabilities.

Chapter 5 describes the available = UP3core library I/O functions. The I/O devices include switches, the LCD, a multiple output clock divider, VGA output, keyboard input, and mouse input.

Chapter 6 is an introduction to th= e use of VHDL for the synthesis of digital hardware. Rather than a lengthy description of syntax details, models of the commonly used digital hardware= devices are developed and presented. Most VHDL textbooks use models developed for simulation only and they frequently use language features not supported in synthesis tools. Our easy to understand synthesis examples were developed a= nd tested on FPGAs using the Altera CAD tools.

Chapter 7 is an introduction to th= e use of Verilog for the synthesis of digital hardware. The same hardware designs= as Chapter 6 as modeled in Verilog. It is optional, but is included for those = who would like an introduction to Verilog.

Chapter 8 is a state machine design example. The state machine controls a virtual electric train system simulat= ion with video output generated directly by the FPGA. Using track sensor input, students must control two trains and three track switches to avoid collisio= ns.

Chapter 9 develops a model of a si= mple computer. The fetch, decode, and execute cycle is introduced and a brief mo= del of the computer is developed using VHDL. A short assembly language program = can be entered in the FPGA’s internal memory and executed in the simulato= r.

Chapter 10 describes how to design= an FPGA-based digital system to output VGA video. Numerous design examples are presented containing video with both text and graphics. Fundamental design issues in writing simple video games and graphics using the UP 3 board are examined.

Chapter 11 describes the PS/2 keyb= oard and mouse operation and presents interface examples for integration in designs = on the UP 3 board. Keyboard scan code tables, mouse data packets, commands, st= atus codes, and the serial communications protocol are included. VHDL code for a keyboard and mouse interface is also presented.

Chapter 12 describes several of the common I/O standards that are likely to be encountered in FPGA systems. Parallel, RS232 serial, SPI, and I2C standards and interfacing a= re discussed.

Chapter 13 develops a design for an adaptable mobile robot using the UP 3 board as the controller. Servo motors= and several sensor technologies for a low cost mobile robot are described. A sa= mple servo driver design is presented. Commercially available parts to construct= the robot described can be obtained for as little as $60. Several robots can be built for use in the laboratory. Students with their own UP 3 board may cho= ose to build their own robot following the detailed instructions found in secti= on 13.6.

Chapter 14 describes a single clock cycle model of the MIPS RISC processor based on the hardware implementation presented in the widely used Patterson and Hennessy textbook, Computer Organization and Design The Hardware/Software Interface. Laboratory exercises that add new instructions, features, and pipelining are included = at the end of the chapter.

Chapters 1= 5, 16, and 17 introduce students to SOPC design using the Nios II RISC process= or core. Chapter 15 is an overview of the SOPC design approach. Chapter 16 contains a tutorial for the Nios II IDE software development tool and examp= les using the Nios II C/C++ compiler. Chapter 17 contains a tutorial on the processor core hardware configuration tool, SOPC builder. A UP 3 board is required for this new material since it is not supported on the UP 2’s FPGA.

We anticipate that many schools will still choose to begin with TTL designs on a small protoboard for the first few labs. The fi= rst chapter can also be started at this time since only OR and NOT logic functi= ons are used to introduce the CAD tool environment. The CAD tool can also be us= ed for simulation of TTL labs, since a TTL parts library is included.

Even though= VHDL and Verilog are complex languages, we have found after several years of experimentation that students can write HDL models to synthesize hardware designs after a short overview with a few basic hardware design examples. T= he use of HDL templates and online help files in the CAD tool makes this proce= ss easier. After the initial experience with HDL synthesis, students dislike t= he use of schematic capture on larger designs since it can be very time consum= ing. Experience in industry has been much the same since huge productivity gains have been achieved using HDL based synthesis tools for application specific integrated circuits (ASICs) and FPGAs.

Most digital logic classes include a simple computer design such as the one presented in Chapter 9 or a RISC processor such as t= he one presented in Chapter 14. If this is not covered in the first digital lo= gic course, it could be used as a lab component for a subsequent computer architecture class.

A typical quarter or semester length course could n= ot cover all of the topics presented. The material presented in Chapters 7 thr= ough 17 can be used on a selective basis. The keyboard and mouse are supported b= y UP3core library functions, and the material presented in Chapter 11 is not required= to use these library functions for keyboard or mouse input. A UP 3 board is required for the SOPC Nios designs in Chapters 16 and 17.

A video game based on the material in Chapter 10 can serve as the basis for a team design project. For a final team design proje= ct, we use robots with sensors from chapter 13 that are controlled by the simple computer in chapter 9. Our students really enjoyed working with the robot described in Chapter 13, and it presents almost infinite possibilities for = an exciting design competition. A more advanced class could develop projects b= ased on the Nios II processor reference designs in Chpater 16 and 17 using C/C++ code.

Software and Hardware Packages

The new 5.0 SP1 web version of Quartus II FPGA CAD = tool is included with this book. Software was tested using this version and it is recommended. UP 3 boards are available from Altera at special student pricing. A board can be shared among several students in a lab, or some students may wish to purchase their own board. Details and suggestions for = additional cables that may be required for a laboratory setup can be found in Section = 2.4. Source files for all designs presented in the text are available on the CD-= ROM.

Additional Web Material and Resources

There is a web site for the text with additional co= urse materials, slides, text errata, and software updates at:

http://www= .ece.gatech.edu/users/hamblen/book/bookte.htm


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