Rapid Prototyping of Digital Systems provides an exciting and challenging laboratory component for undergraduate digital logic and computer design courses using FPGAs and CAD tools for simulation and hardware implementatio= n. The more advanced topics and exercises also make this text useful for upper level courses in digital logic, programmable logic, and embedded systems. T= he third edition now uses Altera’s new Quartus II CAD tool and includes laboratory projects for Altera’s UP 2 and the new UP 3 FPGA board. Student laboratory projects provided on the book’s CD-ROM include vid= eo graphics and text, mouse and keyboard input, and three computer designs.

Rapid Prototyping of Digital Systems includes four tutorials on the Altera Quartus II and Nios II tool environment, an overview of programmable logic,= and IP cores with several easy-to-use input and output functions. These features were developed to help students get started quickly. Early design examples = use schematic capture and IP cores developed for the Altera UP FPGA boards. VHD= L is used for more complex designs after a short introduction to VHDL-based synthesis. Verilog is also now supported more as an option for the student projects.

New chapters in this edition provide an overview of System-on-= a-Programmable Chip (SOPC) technology and SOPC design examples for the UP 3 using Altera’s new Nios II Processor hardware and C software development to= ols. A full set of Altera’s FPGA CAD tools is included on the book’s= CD-ROM.

Intended Audience

This text is intended to provide an exciting and challenging laboratory component for an undergraduate digital logic design class. The more advanced topics and exercises are also appropriate for consideration at schools that have an upper level course in digital logic or programmable logic. There are a number of excellent texts on digital logic design. For the most part, these texts do not include or fully integrate mo= dern CAD tools, logic simulation, logic synthesis using hardware description languages, design hierarchy, and current generation field programmable gate array (FPGA) technology and SOPC design. The goal of this text is to introd= uce these topics in the laboratory portion of the course. Even student laborato= ry projects can now implement entire digital and computer systems with hundred= s of thousands of gates.

Over the past eight years, we have developed a numb= er of interesting and challenging laboratory projects involving serial communications, state machines with video output, video games and graphics, simple computers, keyboard and mouse interfaces, robotics, and pipelined RI= SC processor cores.

Source files and additional example files are avail= able on the CD-ROM for all designs presented in the text. The student version of= the PC based CAD tool on the CD-ROM can be freely distributed to students. Stud= ents can purchase their own UP 3 board for little more than the price of a contemporary textbook. As an alternative, a few of the low-cost UP 3 boards= can be shared among students in a laboratory. Course instructors should contact= the Altera University Program for detailed information on obtaining full versio= ns of the CAD tools for laboratory PCs and UP 3 boards for student laboratorie= s.

Topic Selection and Organization

Chapter 1 is a short CAD tool tuto= rial that covers design entry, simulation, and hardware implementation using an = FPGA. The majority of students can enter the design, simulate, and have the design successfully running on the UP 3 board in less than thirty minutes. After working through the tutorial and becoming familiar with the process, similar designs can be accomplished in less than 10 minutes.

Chapter 2 provides an overview of = the UP 3 FPGA development boards. The features of the board are briefly described. Several tables listing pin connections of various I/O devices serve as an essential reference whenever a hardware design is implemented on the UP 3 board.

Chapter 3 is an introduction to programmable logic technology. The capabilities and internal architectures = of the most popular CPLDs and FPGAs are described. These include the Cyclone F= PGA used on the UP 3 board, and the Xilinx 4000 family FPGAs.

Chapter 4 is a short CAD tool tuto= rial that serves as both a hierarchical and sequential design example. A counter= is clocked by a pushbutton and the output is displayed in the seven-segment LED’s. The design is downloaded to the UP 3 board and some real world timing issues arising with switch contact bounce are resolved. It uses seve= ral functions from the UP3core library which greatly simplify use of the UP 3&#= 8217;s input and output capabilities.

Chapter 5 describes the available = UP3core library I/O functions. The I/O devices include switches, the LCD, a multiple output clock divider, VGA output, keyboard input, and mouse input.

Chapter 6 is an introduction to th= e use of VHDL for the synthesis of digital hardware. Rather than a lengthy description of syntax details, models of the commonly used digital hardware= devices are developed and presented. Most VHDL textbooks use models developed for simulation only and they frequently use language features not supported in synthesis tools. Our easy to understand synthesis examples were developed a= nd tested on FPGAs using the Altera CAD tools.

Chapter 7 is an introduction to th= e use of Verilog for the synthesis of digital hardware. The same hardware designs= as Chapter 6 as modeled in Verilog. It is optional, but is included for those = who would like an introduction to Verilog.

Chapter 8 is a state machine design example. The state machine controls a virtual electric train system simulat= ion with video output generated directly by the FPGA. Using track sensor input, students must control two trains and three track switches to avoid collisio= ns.

Chapter 9 develops a model of a si= mple computer. The fetch, decode, and execute cycle is introduced and a brief mo= del of the computer is developed using VHDL. A short assembly language program = can be entered in the FPGA’s internal memory and executed in the simulato= r.

Chapter 10 describes how to design= an FPGA-based digital system to output VGA video. Numerous design examples are presented containing video with both text and graphics. Fundamental design issues in writing simple video games and graphics using the UP 3 board are examined.

Chapter 11 describes the PS/2 keyb= oard and mouse operation and presents interface examples for integration in designs = on the UP 3 board. Keyboard scan code tables, mouse data packets, commands, st= atus codes, and the serial communications protocol are included. VHDL code for a keyboard and mouse interface is also presented.

Chapter 12 describes several of the common I/O standards that are likely to be encountered in FPGA systems. Parallel, RS232 serial, SPI, and I²C standards and interfacing a= re discussed.

Chapter 13 develops a design for an adaptable mobile robot using the UP 3 board as the controller. Servo motors= and several sensor technologies for a low cost mobile robot are described. A sa= mple servo driver design is presented. Commercially available parts to construct= the robot described can be obtained for as little as $60. Several robots can be built for use in the laboratory. Students with their own UP 3 board may cho= ose to build their own robot following the detailed instructions found in secti= on 13.6.

Chapter 14 describes a single clock cycle model of the MIPS RISC processor based on the hardware implementation presented in the widely used Patterson and Hennessy textbook, Computer Organization and Design The Hardware/Software Interface. Laboratory exercises that add new instructions, features, and pipelining are included = at the end of the chapter.

Chapters 1= 5, 16, and 17 introduce students to SOPC design using the Nios II RISC process= or core. Chapter 15 is an overview of the SOPC design approach. Chapter 16 contains a tutorial for the Nios II IDE software development tool and examp= les using the Nios II C/C++ compiler. Chapter 17 contains a tutorial on the processor core hardware configuration tool, SOPC builder. A UP 3 board is required for this new material since it is not supported on the UP 2’s FPGA.

We anticipate that many schools will still choose to begin with TTL designs on a small protoboard for the first few labs. The fi= rst chapter can also be started at this time since only OR and NOT logic functi= ons are used to introduce the CAD tool environment. The CAD tool can also be us= ed for simulation of TTL labs, since a TTL parts library is included.

Even though= VHDL and Verilog are complex languages, we have found after several years of experimentation that students can write HDL models to synthesize hardware designs after a short overview with a few basic hardware design examples. T= he use of HDL templates and online help files in the CAD tool makes this proce= ss easier. After the initial experience with HDL synthesis, students dislike t= he use of schematic capture on larger designs since it can be very time consum= ing. Experience in industry has been much the same since huge productivity gains have been achieved using HDL based synthesis tools for application specific integrated circuits (ASICs) and FPGAs.

Most digital logic classes include a simple computer design such as the one presented in Chapter 9 or a RISC processor such as t= he one presented in Chapter 14. If this is not covered in the first digital lo= gic course, it could be used as a lab component for a subsequent computer architecture class.

A typical quarter or semester length course could n= ot cover all of the topics presented. The material presented in Chapters 7 thr= ough 17 can be used on a selective basis. The keyboard and mouse are supported b= y UP3core library functions, and the material presented in Chapter 11 is not required= to use these library functions for keyboard or mouse input. A UP 3 board is required for the SOPC Nios designs in Chapters 16 and 17.

A video game based on the material in Chapter 10 can serve as the basis for a team design project. For a final team design proje= ct, we use robots with sensors from chapter 13 that are controlled by the simple computer in chapter 9. Our students really enjoyed working with the robot described in Chapter 13, and it presents almost infinite possibilities for = an exciting design competition. A more advanced class could develop projects b= ased on the Nios II processor reference designs in Chpater 16 and 17 using C/C++ code.

Software and Hardware Packages

The new 5.0 SP1 web version of Quartus II FPGA CAD = tool is included with this book. Software was tested using this version and it is recommended. UP 3 boards are available from Altera at special student pricing. A board can be shared among several students in a lab, or some students may wish to purchase their own board. Details and suggestions for = additional cables that may be required for a laboratory setup can be found in Section = 2.4. Source files for all designs presented in the text are available on the CD-= ROM.

Additional Web Material and Resources

There is a web site for the text with additional co= urse materials, slides, text errata, and software updates at:

http://www= .ece.gatech.edu/users/hamblen/book/bookte.htm