Table of Contents

1 Tutorial I: The 15 Minute Design_______________________ 2

1.1 Design Entry using the Graphic Editor_____________________________ 6

1.2 Compiling the Design___________________________________________ 9

1.3 Simulation of the Design________________________________________ 10

1.4 Downloading Your Design to the UP 1 or UP 1X Board______________ 12

1.5 The 10 Minute VHDL Entry Tutorial_____________________________ 14

1.6 Compiling the VHDL Design____________________________________ 17

1.7 The 10 Minute Verilog Entry Tutorial_____________________________ 17

1.8 Compiling the Verilog Design____________________________________ 21

1.9 Timing Analysis_______________________________________________ 22

1.10 The Floorplan Editor___________________________________________ 23

1.11 Symbols and Hierarchy_________________________________________ 24

1.12 Functional Simulation__________________________________________ 24

1.13 For additional information______________________________________ 25

1.14 Laboratory Exercises___________________________________________ 25

2 The Altera UP 1 and UP 1X CPLD Boards______________ 30

2.1 Programming Jumpers_________________________________________ 31

2.2 MAX 7000 Device and UP 1 I/O Features__________________________ 31

2.3 MAX and FLEX Seven-segment LED Displays______________________ 31

2.4 FLEX 10K Device and UP 1 I/O Features__________________________ 34

2.5 Obtaining a UP 1 or UP 1X Board and Power Supply_______________ 36

3 Programmable Logic Technology______________________ 38

3.1 CPLDs and FPGAs____________________________________________ 41

3.2 Altera MAX 7000S Architecture – A Product Term CPLD Device_____ 42

3.3 Altera FLEX 10K Architecture – A Look-Up Table CPLD Device_____ 43

3.4 Xilinx 4000 Architecture – A Look-Up Table FPGA Device___________ 47

3.5 Computer Aided Design Tools for Programmable Logic_____________ 49

3.6 Next Generation FPLD CAD tools________________________________ 50

3.7 Applications of FPLDs_________________________________________ 50

3.8 Features of New Generation FPLDs_______________________________ 50

3.9 For additional information______________________________________ 51

3.10 Laboratory Exercises___________________________________________ 52

4 Tutorial II: Sequential Design and Hierarchy____________ 54

4.1 Install the Tutorial Files and UP1core Library______________________ 54

4.2 Open the tutor2 Schematic______________________________________ 54

4.3 Browse the Hierarchy___________________________________________ 56

4.4 Using Buses in a Schematic______________________________________ 57

4.5 Testing the Pushbutton Counter and Displays______________________ 58

4.6 Testing the Initial Design on the UP 1 Board.______________________ 59

4.7 Fixing the Switch Contact Bounce Problem________________________ 60

4.8 Testing the Modified Design on the UP 1 Board.____________________ 61

4.9 Laboratory Exercises___________________________________________ 61

5 UP1core Library Functions__________________________ 66

5.1 UP1core DEC_7SEG: Hex to Seven-segment Decoder_______________ 67

5.2 UP1core Debounce: Pushbutton Debounce________________________ 68

5.3 UP1core OnePulse: Pushbutton Single Pulse_______________________ 69

5.4 UP1core Clk_Div: Clock Divider_________________________________ 70

5.5 UP1core VGA_Sync: VGA Video Sync Generation__________________ 71

5.6 UP1core CHAR_ROM: Character Generation ROM________________ 73

5.7 UP1core Keyboard: Read Keyboard Scan Code____________________ 74

5.8 UP1core Mouse: Mouse Cursor__________________________________ 75

6 Using VHDL for Synthesis of Digital Hardware___________ 78

6.1 VHDL Data Types_____________________________________________ 78

6.2 VHDL Operators______________________________________________ 79

6.3 VHDL Based Synthesis of Digital Hardware_______________________ 80

6.4 VHDL Synthesis Models of Gate Networks________________________ 80

6.5 VHDL Synthesis Model of a Seven-segment LED Decoder___________ 81

6.6 VHDL Synthesis Model of a Multiplexer__________________________ 83

6.7 VHDL Synthesis Model of Tri-State Output_______________________ 84

6.8 VHDL Synthesis Models of Flip-flops and Registers_________________ 84

6.9 Accidental Synthesis of Inferred Latches__________________________ 86

6.10 VHDL Synthesis Model of a Counter_____________________________ 86

6.11 VHDL Synthesis Model of a State Machine________________________ 87

6.12 VHDL Synthesis Model of an ALU with an Adder/Subtractor and a Shifter 89

6.13 VHDL Synthesis of Multiply and Divide Hardware__________________ 90

6.14 VHDL Synthesis Models for Memory_____________________________ 91

6.15 Hierarchy in VHDL Synthesis Models_____________________________ 94

6.16 Using a Testbench for Verification________________________________ 96

6.17 For additional information______________________________________ 97

6.18 Laboratory Exercises___________________________________________ 97

7 State Machine Design: The Electric Train Controller______ 102

7.1 The Train Control Problem____________________________________ 102

7.2 Track Power (T1, T2, T3, and T4)_______________________________ 104

7.3 Track Direction (DA1-DA0, and DB1-DB0)_______________________ 104

7.4 Switch Direction (SW1, SW2, and SW3)__________________________ 105

7.5 Train Sensor Input Signals (S1, S2, S3, S4, and S5)________________ 105

7.6 An Example Controller Design__________________________________ 106

7.7 VHDL Based Example Controller Design_________________________ 110

7.8 Simulation Vector file for State Machine Simulation_______________ 112

7.9 Running the Train Control Simulation___________________________ 115

7.10 Running the Video Train System (After Successful Simulation)______ 116

7.11 Laboratory Exercises__________________________________________ 117

8 A Simple Computer Design: The mP 1_________________ 122

8.1 Computer Programs and Instructions____________________________ 123

8.2 The Processor Fetch, Decode and Execute Cycle___________________ 124

8.3 VHDL Model of the mP 1______________________________________ 131

8.4 Simulation of the mP1 Computer________________________________ 134

8.5 Laboratory Exercises__________________________________________ 135

9 VGA Video Display Generation______________________ 140

9.1 Video Display Technology_____________________________________ 140

9.2 Video Refresh________________________________________________ 140

9.3 Using a CPLD for VGA Video Signal Generation__________________ 143

9.4 A VHDL Sync Generation Example: UP1core VGA_SYNC__________ 144

9.5 Final Output Register for Video Signals__________________________ 146

9.6 Required Pin Assignments for Video Output______________________ 146

9.7 Video Examples______________________________________________ 147

9.8 A Character Based Video Design________________________________ 147

9.9 Character Selection and Fonts__________________________________ 148

9.10 VHDL Character Display Design Examples_______________________ 151

9.11 A Graphics Memory Design Example____________________________ 153

9.12 Video Data Compression______________________________________ 154

9.13 Video Color Mixing using Dithering_____________________________ 155

9.14 VHDL Graphics Display Design Example_________________________ 155

9.15 Laboratory Exercises__________________________________________ 157

10 Communications: Interfacing to the PS/2 Keyboard_______ 160

10.1 PS/2 Port Connections_________________________________________ 160

10.2 Keyboard Scan Codes_________________________________________ 161

10.3 Make and Break Codes________________________________________ 161

10.4 The PS/2 Serial Data Transmission Protocol______________________ 161

10.5 Scan Code Set 2 for the PS/2 Keyboard__________________________ 164

10.6 The Keyboard UP1core________________________________________ 166

10.7 A Design Example Using the Keyboard UP1core___________________ 169

10.8 For Additional Information____________________________________ 170

10.9 Laboratory Exercises__________________________________________ 170

11 Communications: Interfacing to the PS/2 Mouse_________ 172

11.1 The Mouse UP1core___________________________________________ 174

11.2 Mouse Initialization___________________________________________ 174

11.3 Mouse Data Packet Processing__________________________________ 175

11.4 An Example Design Using the Mouse UP1core____________________ 176

11.5 For Additional Information____________________________________ 176

11.6 Laboratory Exercises__________________________________________ 176

12 Robotics: The UP1-bot_____________________________ 178

12.1 The UP1-bot Design___________________________________________ 178

12.2 UP1-bot Servo Drive Motors___________________________________ 178

12.3 Modifying the Servos to make Drive Motors______________________ 179

12.4 VHDL Servo Driver Code for the UP1-bot________________________ 180

12.5 Sensors for the UP1-bot_______________________________________ 182

12.6 Assembly of the UP1-bot Body_________________________________ 190

12.7 UP1-bot FLEX Expansion B Header Pins_________________________ 197

12.8 An Alternative UP 1 Robot Project Based on an R/C Car___________ 198

12.9 For Additional Information____________________________________ 203

12.10 Laboratory Exercises__________________________________________ 204

13 A RISC Design: Synthesis of the MIPS Processor Core____ 210

13.1 The MIPS Instruction Set and Processor_________________________ 210

13.2 Using VHDL to Synthesize the MIPS Processor Core_______________ 213

13.3 The Top-Level Module________________________________________ 214

13.4 The Control Unit_____________________________________________ 217

13.5 The Instruction Fetch Stage____________________________________ 219

13.6 The Decode Stage_____________________________________________ 222

13.7 The Execute Stage____________________________________________ 224

13.8 The Data Memory Stage_______________________________________ 226

13.9 Simulation of the MIPS Design_________________________________ 227

13.10 MIPS Hardware Implementation on the UP 1 or UP 1X Board_______ 228

13.11 For Additional Information____________________________________ 229

13.12 Laboratory Exercises__________________________________________ 230

Appendix A: Generation of Pseudo Random Binary Sequences_ 235

Appendix B: MAX+PLUS II Design and Data File Extensions__ 237

Appendix C: UP 1 and UP 1X Pin Assignments_____________ 239

Appendix D: The Wintim Meta Assembler__________________ 243

Appendix E: An Introduction to Verilog for VHDL users______ 252

Glossary___________________________________________ 259

Index_____________________________________________ 267

About the Accompanying CD-ROM______________________ 270

_Preface

Changes to the Second Edition

The second edition of the text now includes Altera's 10.1 student edition software which adds support for Windows 2000 and designs that are three times larger using the new 70,000 gate UP 1X board. All designs in the book's CDROM have been updated to work with the original UP 1 board or the newer UP 1X board using the new Altera student version software. A coupon is included with the text for purchase of the new UP 1X board. The additional logic and memory in the UP 1X's FLEX 10K70 is useful on larger design projects such as computers and video games.

In addition to the new software, the second edition includes an updated chapter on programmable logic, new robot sensors and projects, optional Verilog examples, and a meta assembler which can be used to develop assembly language programs for the computer designs in Chapters 8 and 13.

Intended Audience

This text is intended to provide an exciting and challenging laboratory component for an undergraduate digital logic design class. The more advanced topics and exercises are also appropriate for consideration at schools that have an upper level course in digital logic or programmable logic. There are a number of excellent texts on digital logic design. For the most part, these texts do not include or fully integrate modern CAD tools, logic simulation, logic synthesis using hardware description languages, design hierarchy, and current generation field programmable logic device (FPLD) technology. The goal of this text is to introduce these topics in the laboratory portion of the course.

Design engineers working in industry may also want to consider this text for a rapid introduction to FPLD technology and logic synthesis using commercial CAD tools, if they have not had previous experience with this new and rapidly evolving technology.

Two tutorials on the Altera CAD tool environment, an overview of programmable logic, and a design library with several easy to use input and output functions were developed for this text to help students get started quickly. Early design examples use schematic capture and library components. VHDL is used for more complex designs after a short introduction to VHDL based synthesis.

The approach used in the text more accurately reflects contemporary practice in industry than the more traditional TTL protoboard based laboratory courses. With modern logic synthesis tools and large FPLDs, more advanced designs are needed to present challenging laboratory projects. Rather than being limited to a few TTL chips that will fit on a small protoboard, designs containing tens of thousands of gates are possible even with student versions of the CAD tools and the UP 1 board. Even student laboratory projects can now implement entire digital systems.

Over the past three years, we have developed a number of interesting and challenging laboratory projects involving serial communications, state machines with video output, video games and graphics, simple computers, keyboard and mouse interfaces, robotics, and pipelined RISC processor cores.

Source files and additional example files are available on the CDROM for all designs presented in the text. The student version of the PC based CAD tool on the CDROM can be freely distributed to students. Students can purchase their own UP 1 board for little more than the price of a contemporary textbook. As an alternative, a few of the low-cost UP 1 or UP 1X boards can be shared among students in a laboratory. Course instructors should contact the Altera University Program for detailed information on obtaining student versions of the CAD tools and UP 1 boards for student laboratories.

Topic Selection and Organization

Chapter 1 is a short CAD tool tutorial that covers design entry, simulation, and hardware implementation using an FPLD. The majority of students can enter the design, simulate, and have the design successfully running on the UP 1 board in less than thirty minutes. After working through the tutorial and becoming familiar with the process, similar designs can be accomplished in less than 10 minutes.

Chapter 2 provides an overview of the UP 1 and UP 1X FPLD development boards. The features of the boards are briefly described. Several tables listing pin connections of various I/O devices serve as an essential reference whenever a hardware design is implemented on the UP 1 board.

Chapter 3 is an introduction to programmable logic technology. The capabilities and internal architectures of the most popular CPLDs and FPGAs are described. These include the MAX 7000 and FLEX 10K family CPLDs used on the UP 1 board, and the Xilinx 4000 family FPGAs.

Chapter 4 is a short CAD tool tutorial that serves as both a hierarchical and sequential design example. A counter is clocked by a pushbutton and the output is displayed in the seven-segment LED’s. The design is downloaded to the UP 1 board and some real world timing issues arising with switch contact bounce are resolved. It uses several functions from the UP1core library which greatly simplify use of the UP 1’s input and output capabilities.

Chapter 5 describes the available UP1core library I/O functions. The I/O devices include switches, seven-segment LED’s, a multiple output clock divider, VGA output, keyboard input, and mouse input.

Chapter 6 is an introduction to the use of VHDL for the synthesis of digital hardware. Rather than a lengthy description of syntax details, models of the commonly used digital hardware devices are developed and presented. Most VHDL textbooks use models developed for simulation only and they frequently use language features not supported in synthesis tools. Our easy to understand synthesis examples were developed and tested using the Altera VHDL CAD tools.

Chapter 7 is a state machine design example. The state machine controls a virtual electric train system simulation with video output generated directly by the CPLD. Using track sensor input, students must control two trains and three track switches to avoid collisions.

Chapter 8 develops a model of a simple computer. The fetch, decode, and execute cycle is introduced and a brief model of the computer is developed using VHDL. A short assembly language program can be entered in the FPLD’s internal memory and executed in the simulator.

Chapter 9 describes how to design an FPLD-based digital system to output VGA video. Numerous design examples are presented containing video with both text and graphics. Fundamental design issues in writing simple video games and graphics using the UP 1 board are examined.

Chapter 10 describes the PS/2 keyboard operation and presents interface examples for integration in designs on the UP 1 board. Keyboard scan code tables, commands, status codes, and the serial communications protocol are included. VHDL code for a keyboard interface is also presented.

Chapter 11 describes the PS/2 mouse operation and presents interface examples for integration in designs on the UP 1 board. Commands, data packet formats, and PS/2 serial communications protocols are included.

Chapter 12 develops a design for an adaptable mobile robot using the UP 1 board. Servo motors and several sensor technologies for a low cost mobile robot are described. A sample servo driver design is presented. Commercially available parts to construct the robot described in Chapter 12 can be obtained for around $50. Several robots can be built for use in the laboratory. Students with their own UP 1 board may choose to build their own robot following the detailed instructions found in section 12.6.

Chapter 13 describes a single clock cycle model of the MIPS RISC processor based on the hardware implementation presented in the widely used Patterson and Hennessy textbook, Computer Organization and Design The Hardware/Software Interface. Laboratory exercises that add new instructions, features, and pipelining are included at the end of the chapter.

We anticipate that many schools will still choose to begin with TTL designs on a small protoboard for the first few labs. The first chapter can also be started at this time since only OR and a NOT logic functions are used to introduce the CAD tool environment. The CAD tool can also be used for simulation of TTL labs, since an extensive TTL parts library is included with the student version.

Even though VHDL is a complex language, we have found after several years of experimentation that students can write VHDL to synthesize hardware designs after a short overview with a few basic hardware design examples. The use of VHDL templates and online help files in the CAD tool makes this process easier. After the initial experience with VHDL synthesis, students dislike the use of schematic capture on larger designs since it can be very time consuming. Experience in industry has been much the same since huge productivity gains have been achieved using HDL based synthesis tools for application specific integrated circuits (ASICs) and FPLDs.

Most digital logic classes include a simple computer design such as the one presented in Chapter 8 or a RISC processor such as the one presented in Chapter 13. If this is not covered in the first digital logic course, it could be used as a lab component for a subsequent computer architecture class.

A typical quarter or semester length course could not cover all of the topics presented. The material presented in Chapters 7 through 13 can be used on a selective basis. The keyboard and mouse are supported by UP1core library functions, and the material presented in Chapters 10 and 11 is not required to use these library functions for keyboard or mouse input. Information on video generation, PS/2 keyboard, and mouse interfacing is not readily available elsewhere.

A video game based on the material in Chapter 9 can serve as the basis for a team design project. For a final team design project, we use robots with sensors from chapter 12 that are controlled by the simple computer in chapter 8. The meta assembler in Appendix D is used to assemble the programs. Our students really enjoyed working with the robot described in Chapter 12, and it presents almost infinite possibilities for an exciting design competition.

Software and Hardware Packages

The new student version of Altera’s MAX+PLUS II CAD tool is included with this book. UP 1 and UP 1X boards are available from Altera at special student pricing. A board can be shared among several students in a lab, or some students may wish to purchase their own board. Details and suggestions for additional cables and power supplies that may be required for a laboratory setup can be found in Section 2.5. Source files for all designs presented in the text are available on the CDROM.

Additional Web Material and Resources

There is a web site for the text with additional course materials, slides, text errata, and software updates at:

/book/bookse.htm