Rapid Prototyping of Digital Systems SOPC Edition

Table of Contents

1 Tutorial I: The 15 Minute Design_____________________________ 2

1.1 Design Entry using the Graphic Editor_______________________________________ 9

1.2 Compiling the Design_____________________________________________________ 16

1.3 Simulation of the Design__________________________________________________ 17

1.4 Testing Your Design on an FPGA Board____________________________________ 18

1.5 Downloading Your Design to the DE1 Board_________________________________ 19

1.6 Downloading Your Design to the DE2 Board_________________________________ 22

1.7 Downloading Your Design to the UP3 Board_________________________________ 25

1.8 Downloading Your Design to the UP2 or UP1 Board__________________________ 27

1.9 The 10 Minute VHDL Entry Tutorial_______________________________________ 29

1.10 Compiling the VHDL Design______________________________________________ 32

1.11 The 10 Minute Verilog Entry Tutorial______________________________________ 34

1.12 Compiling the Verilog Design______________________________________________ 36

1.13 Timing Analysis_________________________________________________________ 38

1.14 The Floorplan Editor_____________________________________________________ 39

1.15 Symbols and Hierarchy___________________________________________________ 40

1.16 Functional Simulation____________________________________________________ 41

1.17 Laboratory Exercises_____________________________________________________ 42

2 FPGA Development Board Hardware and I/O Features__________ 46

2.1 FPGA and External Hardware Features_____________________________________ 47

2.2 The FPGA Board’s Memory Features_______________________________________ 48

2.3 The FPGA Board’s I/O Features___________________________________________ 49

2.4 Obtaining an FPGA Development Board and Cables__________________________ 53

3 Programmable Logic Technology____________________________ 56

3.1 CPLDs and FPGAs______________________________________________________ 59

3.2 Altera MAX 7000S Architecture – A Product Term CPLD Device_______________ 60

3.3 Altera Cyclone Architecture – A Look-Up Table FPGA Device_________________ 62

3.4 Xilinx 4000 Architecture – A Look-Up Table FPGA Device____________________ 65

3.5 Computer Aided Design Tools for Programmable Logic________________________ 67

3.6 Next Generation FPGA CAD tools_________________________________________ 68

3.7 Applications of FPGAs___________________________________________________ 69

3.8 Features of New Generation FPGAs________________________________________ 69

3.9 For additional information________________________________________________ 70

3.10 Laboratory Exercises_____________________________________________________ 71

4 Tutorial II: Sequential Design and Hierarchy__________________ 74

4.1 Install the Tutorial Files and FPGAcore Library for your board________________ 74

4.2 Open the tutor2 Schematic________________________________________________ 75

4.3 Browse the Hierarchy_____________________________________________________ 76

4.4 Using Buses in a Schematic________________________________________________ 78

4.5 Testing the Pushbutton Counter and Displays________________________________ 79

4.6 Testing the Initial Design on the Board______________________________________ 80

4.7 Fixing the Switch Contact Bounce Problem__________________________________ 81

4.8 Testing the Modified Design on the FPGA Board_____________________________ 82

4.9 Laboratory Exercises_____________________________________________________ 83

5 FPGAcore Library Functions_______________________________ 88

5.1 FPGAcore LCD_Display: LCD Panel Character Display_______________________ 90

5.2 FPGAcore DEC_7SEG: Hex to Seven-segment Decoder________________________ 92

5.3 FPGAcore Debounce: Pushbutton Debounce_________________________________ 94

5.4 FPGAcore OnePulse: Pushbutton Single Pulse______________________________ 95

5.5 FPGAcore Clk_Div: Clock Divider_________________________________________ 96

5.6 FPGAcore VGA_Sync: VGA Video Sync Generation__________________________ 97

5.7 FPGAcore Char_ROM: Character Generation ROM_________________________ 99

5.8 FPGAcore Keyboard: Read Keyboard Scan Code___________________________ 100

5.9 FPGAcore Mouse: Mouse Cursor__________________________________________ 102

5.10 For additional information_______________________________________________ 103

6 Using VHDL for Synthesis of Digital Hardware________________ 106

6.1 VHDL Data Types______________________________________________________ 106

6.2 VHDL Operators_______________________________________________________ 107

6.3 VHDL Based Synthesis of Digital Hardware________________________________ 108

6.4 VHDL Synthesis Models of Gate Networks__________________________________ 108

6.5 VHDL Synthesis Model of a Seven-segment LED Decoder_____________________ 109

6.6 VHDL Synthesis Model of a Multiplexer___________________________________ 111

6.7 VHDL Synthesis Model of Tri-State Output________________________________ 112

6.8 VHDL Synthesis Models of Flip-flops and Registers__________________________ 112

6.9 Accidental Synthesis of Inferred Latches___________________________________ 114

6.10 VHDL Synthesis Model of a Counter______________________________________ 114

6.11 VHDL Synthesis Model of a State Machine_________________________________ 115

6.12 VHDL Synthesis Model of an ALU with an Adder/Subtractor and a Shifter_____ 117

6.13 VHDL Synthesis of Multiply and Divide Hardware__________________________ 118

6.14 VHDL Synthesis Models for Memory______________________________________ 119

6.15 Hierarchy in VHDL Synthesis Models______________________________________ 123

6.16 Using a Testbench for Verification_________________________________________ 125

6.17 For additional information_______________________________________________ 126

6.18 Laboratory Exercises____________________________________________________ 126

7 Using Verilog for Synthesis of Digital Hardware_______________ 130

7.1 Verilog Data Types______________________________________________________ 130

7.2 Verilog Based Synthesis of Digital Hardware________________________________ 130

7.3 Verilog Operators_______________________________________________________ 131

7.4 Verilog Synthesis Models of Gate Networks_________________________________ 132

7.5 Verilog Synthesis Model of a Seven-segment LED Decoder____________________ 132

7.6 Verilog Synthesis Model of a Multiplexer___________________________________ 133

7.7 Verilog Synthesis Model of Tri-State Output________________________________ 134

7.8 Verilog Synthesis Models of Flip-flops and Registers_________________________ 135

7.9 Accidental Synthesis of Inferred Latches___________________________________ 136

7.10 Verilog Synthesis Model of a Counter______________________________________ 136

7.11 Verilog Synthesis Model of a State Machine_________________________________ 137

7.12 Verilog Synthesis Model of an ALU with an Adder/Subtractor and a Shifter_____ 138

7.13 Verilog Synthesis of Multiply and Divide Hardware__________________________ 139

7.14 Verilog Synthesis Models for Memory______________________________________ 140

7.15 Hierarchy in Verilog Synthesis Models_____________________________________ 143

7.16 For additional information_______________________________________________ 144

7.17 Laboratory Exercises____________________________________________________ 144

8 State Machine Design: The Electric Train Controller____________ 148

8.1 The Train Control Problem______________________________________________ 148

8.2 Train Direction Outputs (DA1-DA0, and DB1-DB0)__________________________ 149

8.3 Switch Direction Outputs (SW1, SW2, and SW3)____________________________ 150

8.4 Train Sensor Input Signals (S1, S2, S3, S4, and S5)__________________________ 150

8.5 An Example Controller Design____________________________________________ 151

8.6 VHDL Based Example Controller Design___________________________________ 154

8.7 Verilog Based Example Controller Design___________________________________ 157

8.8 Automatically Generating a State Diagram of a Design_______________________ 160

8.9 Simulation Vector file for State Machine Simulation_________________________ 161

8.10 Running the Train Control Simulation_____________________________________ 162

8.11 Running the Video Train System (After Successful Simulation)________________ 162

8.12 A Hardware Implementation of the Train System Layout_____________________ 164

8.13 Laboratory Exercises____________________________________________________ 166

9 A Simple Computer Design: The µP 3_______________________ 170

9.1 Computer Programs and Instructions______________________________________ 171

9.2 The Processor Fetch, Decode and Execute Cycle_____________________________ 172

9.3 VHDL Model of the mP 3________________________________________________ 179

9.4 Verilog Model of the mP 3________________________________________________ 182

9.5 Automatically Generating a State Diagram of the mP3________________________ 186

9.6 Simulation of the mP3 Computer__________________________________________ 187

9.7 Laboratory Exercises____________________________________________________ 188

10 VGA Video Display Generation using FPGAs_________________ 192

10.1 Video Display Technology________________________________________________ 192

10.2 Video Refresh__________________________________________________________ 192

10.3 Using an FPGA for VGA Video Signal Generation___________________________ 195

10.4 A VHDL Sync Generation Example: FPGAcore VGA_SYNC__________________ 196

10.5 Final Output Register for Video Signals____________________________________ 198

10.6 Required Pin Assignments for Video Output________________________________ 198

10.7 Video Examples_________________________________________________________ 199

10.8 A Character Based Video Design__________________________________________ 200

10.9 Character Selection and Fonts____________________________________________ 200

10.10 VHDL Character Display Design Examples_________________________________ 203

10.11 A Graphics Memory Design Example______________________________________ 206

10.12 Video Data Compression_________________________________________________ 207

10.13 Video Color Mixing using Dithering_______________________________________ 207

10.14 VHDL Graphics Display Design Example___________________________________ 208

10.15 Higher Video Resolution and Faster Refresh Rates___________________________ 209

10.16 Laboratory Exercises____________________________________________________ 210

11 Interfacing to the PS/2 Keyboard and Mouse__________________ 214

11.1 PS/2 Port Connections___________________________________________________ 214

11.2 Keyboard Scan Codes___________________________________________________ 215

11.3 Make and Break Codes__________________________________________________ 215

11.4 The PS/2 Serial Data Transmission Protocol________________________________ 216

11.5 Scan Code Set 2 for the PS/2 Keyboard____________________________________ 218

11.6 The Keyboard FPGAcore________________________________________________ 220

11.7 A Design Example Using the Keyboard FPGAcore___________________________ 223

11.8 Interfacing to the PS/2 Mouse____________________________________________ 224

11.9 The Mouse FPGAcore___________________________________________________ 226

11.10 Mouse Initialization_____________________________________________________ 226

11.11 Mouse Data Packet Processing____________________________________________ 227

11.12 An Example Design Using the Mouse FPGAcore_____________________________ 228

11.13 For Additional Information______________________________________________ 229

11.14 Laboratory Exercises____________________________________________________ 229

12 Legacy Digital I/O Interfacing Standards_____________________ 232

12.1 Parallel I/O Interface____________________________________________________ 232

12.2 RS-232C Serial I/O Interface_____________________________________________ 233

12.3 SPI Bus Interface_______________________________________________________ 235

12.4 I²C Bus Interface_______________________________________________________ 237

12.5 For Additional Information______________________________________________ 239

12.6 Laboratory Exercises____________________________________________________ 239

13 FPGA Robotics Projects__________________________________ 242

13.1 The FPGA-bot Design___________________________________________________ 242

13.2 FPGA-bot Servo Drive Motors____________________________________________ 242

13.3 Modifying the Servos to make Drive Motors________________________________ 243

13.4 VHDL Servo Driver Code for the FPGA-bot________________________________ 244

13.5 Low-cost Sensors for an FPGA Robot Project_______________________________ 246

13.6 Assembly of the FPGA-bot Body__________________________________________ 259

13.7 I/O Connections to the board’s Expansion Headers__________________________ 266

13.8 Robot Projects Based on R/C Toys, Models, and Robot Kits___________________ 267

13.9 For Additional Information______________________________________________ 275

13.10 Laboratory Exercises____________________________________________________ 277

14 A RISC Design: Synthesis of the MIPS Processor Core__________ 284

14.1 The MIPS Instruction Set and Processor___________________________________ 284

14.2 Using VHDL to Synthesize the MIPS Processor Core_________________________ 287

14.3 The Top-Level Module___________________________________________________ 288

14.4 The Control Unit_______________________________________________________ 291

14.5 The Instruction Fetch Stage______________________________________________ 293

14.6 The Decode Stage_______________________________________________________ 296

14.7 The Execute Stage______________________________________________________ 298

14.8 The Data Memory Stage_________________________________________________ 300

14.9 Simulation of the MIPS Design___________________________________________ 301

14.10 MIPS Hardware Implementation on the FPGA Board________________________ 302

14.11 For Additional Information______________________________________________ 303

14.12 Laboratory Exercises____________________________________________________ 304

15 Introducing System-on-a-Programmable-Chip_________________ 310

15.1 Processor Cores_________________________________________________________ 310

15.2 SOPC Design Flow______________________________________________________ 311

15.3 Initializing Memory_____________________________________________________ 313

15.4 SOPC Design versus Traditional Design Modalities__________________________ 315

15.5 An Example SOPC Design_______________________________________________ 316

15.6 Hardware/Software Design Alternatives____________________________________ 317

15.7 For additional information_______________________________________________ 317

15.8 Laboratory Exercises____________________________________________________ 318

16 Tutorial III: Nios II Processor Software Development___________ 322

16.1 Install the DE board files_________________________________________________ 322

16.2 Starting a Nios II Software Project________________________________________ 322

16.3 The Nios II IDE Software________________________________________________ 324

16.4 Generating the Nios II System Library_____________________________________ 325

16.5 Software Design with Nios II Peripherals___________________________________ 326

16.6 Starting Software Design – main()_________________________________________ 329

16.7 Downloading the Nios II Hardware and Software Projects____________________ 330

16.8 Executing the Software__________________________________________________ 331

16.9 Starting Software Design for a Peripheral Test Program______________________ 331

16.10 Handling Interrupts_____________________________________________________ 334

16.11 Accessing Parallel I/O Peripherals_________________________________________ 335

16.12 Communicating with the LCD Display (DE2 only)___________________________ 336

16.13 Testing SRAM__________________________________________________________ 339

16.14 Testing Flash Memory___________________________________________________ 340

16.15 Testing SDRAM________________________________________________________ 341

16.16 Downloading the Nios II Hardware and Software Projects____________________ 346

16.17 Executing the Software__________________________________________________ 347

16.18 For additional information_______________________________________________ 347

16.19 Laboratory Exercises____________________________________________________ 348

17 Tutorial IV: Nios II Processor Hardware Design_______________ 352

17.1 Install the DE board files_________________________________________________ 352

17.2 Creating a New Project__________________________________________________ 352

17.3 Starting SOPC Builder__________________________________________________ 353

17.4 Adding a Nios II Processor_______________________________________________ 355

17.5 Adding UART Peripherals_______________________________________________ 358

17.6 Adding an Interval Timer Peripheral______________________________________ 359

17.7 Adding Parallel I/O Components__________________________________________ 360

17.8 Adding an SRAM Memory Controller_____________________________________ 361

17.9 Adding an SDRAM Memory Controller____________________________________ 362

17.10 Adding the LCD Module (DE2 Board Only)_________________________________ 362

17.11 Adding an External Bus_________________________________________________ 363

17.12 Adding Components to the External Bus___________________________________ 364

17.13 Global Processor Settings________________________________________________ 364

17.14 Finalizing the Nios II Processor___________________________________________ 365

17.15 Add the Processor Symbol to the Top-Level Schematic_______________________ 366

17.16 Create a Phase-Locked Loop Component___________________________________ 367

17.17 Complete the Top-Level Schematic________________________________________ 368

17.18 Design Compilation_____________________________________________________ 368

17.19 Testing the Nios II Project________________________________________________ 369

17.20 For additional information_______________________________________________ 370

17.21 Laboratory Exercises____________________________________________________ 370

18 Operating System Support for SOPC Design__________________ 374

18.1 Nios II OS Support______________________________________________________ 376

18.2 eCos__________________________________________________________________ 377

18.3 µC/OS-II______________________________________________________________ 378

18.4 µClinux_______________________________________________________________ 379

18.5 Implementing the µClinux on the DE Board________________________________ 380

18.6 Hardware Design for µClinux Support_____________________________________ 380

18.7 Configuring the DE Board_______________________________________________ 382

18.8 Exploring µClinux on the DE Board_______________________________________ 385

18.9 PS/2 Device Support in µClinux___________________________________________ 386

18.10 Video Display in µClinux________________________________________________ 386

18.11 USB Devices in µClinux (DE2 Board Only)__________________________________ 387

18.12 Network Communication in µClinux (DE2 Board Only)_______________________ 387

18.13 For additional information_______________________________________________ 388

18.14 Laboratory Exercises____________________________________________________ 388

Appendix A: Generation of Pseudo Random Binary Sequences______ 391

Appendix B: Quartus II Design and Data File Extensions__________ 393

Appendix C: Common FPGA Pin Assignments___________________ 394

Appendix D: ASCII Character Code___________________________ 396

Appendix E: Common I/O Connector Pin Assignments____________ 397

Glossary_________________________________________________ 399

Index___________________________________________________ 407

About the Accompanying DVD_______________________________ 411