1. First time only! Set up a project directory structure. In DOS go to drive C: and unzip the files into a directory named, mips. If the mips directory already exists delete the files and all sub directories. Workview and Xilinx libraries must have been previously installed, to proceed with the next step.

2. Start Windows by typing "win" at the DOS prompt. Clock on the cockpit icon in Viewlogic CAD group. Select Project, Create, and type c:\mips - this will add it to the menu of choices for the current project menu. Make sure the current project selected is C:\MIPS. If the Xilinx libraries are installed in different locations you may need to edit the project search order using the Cockpit tool. The project search order is also contained at the end of the viewdraw.ini file. Always start the CAD tools from the cockpit window after selecting or making sure your project is selected. If someone leaves a project on the A drive selected it may be necessary to have a floppy in the drive to de-select it.

3. Click on the red dot and select system to shell to DOS. You should be in the directory C:\MIPS in DOS. Type VHDLDES to start the synthesis process from the batch file MIPSGEN.SRC automatically. It will take a few minutes and lots of information will flash by on the screen as you generate your MIPS computer design automatically using over 3,000 gates with VHDL timing models. Warnings about unconnected signals are OK - they may be needed in future designs. Errors need to be fixed before proceeding. When it finishes with no errors you have created schematics and simulation files for the entire MIPS design. Type quit to exit VHDLDES, if needed due to errors, and type exit at the prompt C:\MIPS to return to windows.

4. You can examine and print out schematics using the ViewDraw icon back in the cockpit. It should show up when the current drawer selected is "Design Entry". You can push and pop levels in the top spim schematic by selecting a part with the mouse. When selected it turns white. Then use file - level - push - schematic to see the gate level schematic for the selected part. Use file level pop to return. To exit select the red dot and quit. In viewlogic you can use the function keys to move around, so check the template above the keys for more info. You can get help in most of the tools for information on commands. Always start from the cockpit first as this sets the search paths for viewdraw and viewsim

5. To simulate, return to the cockpit, change the current drawer to "Design Analysis" and click on the ViewSim icon. Click OK, and move to the window with the "SIM>" prompt. Type "net top_spim" to load your 3000+ gate VHDL model. Wait a few seconds for it to load and the "SIM>" prompt to appear. Type "Start" in this window to begin your simulation. This reads in batch simulation commands from START.CMD in your project directory and sets up a timing display, and runs a simulation of the MIPS computer for a few instructions.

6. To print out schematics or timing displays click on the red dot and select "PLOT SETUP". Make sure the plotter is set to POSTSCRIPT and click OK or ACCEPT. Plots go to files, myschem.01P for schematics, and VTRACE.PLT for timing displays in the project directory. Back in DOS you can use "Copy myplot.xxx lpt1: /B" to get a hard copy of your plot on the laser printer in the lab.

7. To save your files on a floppy you need the *.VHD, *.ini, *.src, *.cmd files at the root directory level only. The simulation file *.vsm is too big to fit on a floppy. The synthesis process creates and lot of other files and directories on the disk - but they can be recreated almost as fast as you can copy them. Do not try to use a floppy for synthesis it is real slow and the files all will not fit on a single floppy.

8. Edit the *.VHD files to change the design for the labs. And start back at step 2. When changing signals between modules, delete the SCH, SYM and WIR sub directories prior to synthesis. To check syntax errors you can run VHDLDES and then use VHDL myfile.VHD. You will need to rename the batch file VHDLDES.INI to stop the automatic generation of the entire design when you type VHDLDES. You may also want to change the simulation file commands in START.CMD to add or delete signals. Test programs must be changed in IFETCH.VHD. A small amount of test data can be put in DMEMORY.VHD. Any external module signal changes must be updated in TOP_SPIM.VHD.