1. First time only! Set up a project directory structure. In a DOS shell go to drive C: and use your favorite zip tool to unzip the MIPSWVO.zip files to mips2 directory. If the mips2 directory already exists delete the files and all sub directories.

2. Start Workview Office from the Programs Menu. Then start the Project Manager and select file => open => mipsproj project. C:\mips2 should be the primary directory and the library search order should appear in the white window. You may need to modify the project/library search order so that you can access the Xilinx libraries for Viewlogic if they were installed in a different location on your system. Don't change the directory name - it is imbedded in several files.

3. Start the Viewsynthesis tool and select the mipssyn project. Use Project => clear work area, Project => compile and all of the *.vhd files should compile in a few minutes without errors. Then Use Project => synthesize and all of the *.vhd files will be optimized, synthesized, and converted to a gate level schematic for the simulation tool. This should be all you need to do, but there is a problem and every time you recompile and synthesize the top_spim module you will need to do this last step to workaround. The top_spim schematic drops off connections to a few pins. If you look at it with Viewdraw (see step 4) you can see some pins with no connections on the schematics and it will not simulate correctly. To fix this problem use Project => files => remove, highlight all of the files except top_spim and click OK. Then recompile and synthesize top_spim only and it will now be correct and the schematic will not have unconnected pins. If you exit Viewsynthesis without saving, all of the *.vhd project files will return when you restart it. You will only need to rerun Viewsynthesis when you change your VHDL files or you need to recreate your project from a floppy disk backup.

4. You can examine and print out schematics using by starting ViewDraw on the top_spim.1 schematic file. You can push and pop hierarchy levels in the top spim schematic by selecting a part with the mouse. When selected it puts a rectangle around the part. Then click the right mouse button while the cursor is on the part and select schematic to see the gate level schematic for the selected part. In viewlogic you can use the function key shortcuts to move around and resize. Select view to see the options. You can get help in most of the tools for more information on commands. Always start the Project Manager first (step 2 above) as this sets the search paths for all of the other tools.

5. To simulate run ViewVSM. The design name should come up top_spim, that is the name of the top level module that includes all other modules. Command file should say START.CMD. Click OK, and it will run several programs to generate the files needed for the simulator and then to load your 3000+ gate VHDL model. This reads in batch simulation commands from START.CMD in your project directory and sets up a Viewtrace timing display, and runs a simulation of the MIPS computer for a few instructions. Hit F4 to see the entire timing diagram. While running the simulator you can use Viewdraw to open the top_spim schematic and the value of all nets on the schematic will be automatically back annotated by the simulation tool. In Viewsim, you can use simualtion => restart to start the simulation over.

6. To print out schematics or timing displays use the print menus in Viewdraw or Viewtrace.

7. To save your files on a floppy you need the *.VHD, *.ini, *.spj, *.vpj *.cmd files at the root directory level only. The simulation and schematic files are too big to fit on a floppy. The synthesis process creates and lot of other files and subdirectories on the disk - but they can be recreated almost as fast as you can copy them. Do not try to use a floppy for synthesis it is about 10 times slower and the files all will fit on a single floppy anyway.

8. Edit the *.VHD files to change the design for the labs. And start back at step 2. When changing signals between modules, delete the SCH, SYM and WIR sub directories prior to synthesis. A DOS batch file called purge is available to do this. If the SCH, SYM, and WIR sub directories have not been deleted, only modules with changes need to be recompiled and synthesized. In Viewsynthesis, individual *.vhd modules can be compiled, synthesized, and have schematics generated individually by highlighting the name in the lower windows and pulling up a menu with the right mouse button. If you get red VHDL syntax errors, clicking on the line pulls up an edit windows at the point of the error. You may also want to change the simulation file commands in START.CMD to add or delete signals to the trace. Test programs must be changed in IFETCH.VHD. A small amount of test data can be put in DMEMORY.VHD. Any external module signal changes must aslo be updated in TOP_SPIM.VHD.