A VHDL Synthesis model of the MIPS processor for use in Computer Architecture
Laboratories

James O. Hamblen

Summary:
This contribution describes and contains the necessary VHDL files to
synthesize and simulate a MIPS processor core for use in introductory
computer architecture classes. This MIPS processor core is based on the
design presented in chapters 5 and 6 of the widely used text, Computer
Organization & Design The Hardware/ Software Interface by David Patterson
and John Hennessy.  IEEE Standard Logic 1164 is used in the VHDL model and
versions are provided for several popular CAD tools.  Our experiences in
using this model in our introductory computer architecture classes, CmpE 2510
and CmpE 3510, during the past two years are described along with typical
laboratory assignments.

Keywords:
VHDL, RISC, CAD, Logic Synthesis, Computer Architecture

Contact information:
James O. Hamblen   (URL: http://www.ece.gatech.edu/users/hamblen/)
Associate Professor
School of Electrical and Computer Engineering (URL: http://www.ece.gatech.edu)
Georgia Institute of Technology
Atlanta, Georgia 30332-0250
Phone: 404-894-3027
Fax: 404-894-9959
Email hamblen@ece.gatech.edu


Biography:
James O. Hamblen is an associate professor in electrical and computer
engineering at Georgia Tech. He received his Ph.D. in electrical engineering
from Georgia Tech in 1984. His other degrees include an M.S.E.E. from Purdue 
University and a B.E.E. from Georgia Tech. Prior to returning to Georgia Tech 
to work on his Ph.D., he worked as a systems analyst for Texas Instruments 
in Austin, Texas, and as a senior engineer for Martin Marietta in Denver, 
Colorado. Professor Hamblen's current research interests include rapid 
prototyping, high-speed parallel and VLSI computer architectures, 
computer-aided design, and reconfigurable computing.