Starting at around version 9.2 some Altera VHDL compiler warnings became compiler errors.  If version 9.2 or greater is used you may now get errors in some of these design files.  Most problems seem to be connected with multiple output assignments in a process.  We have fixed the examples used in the lab manual but have not had time to fix all of the examples listed here. If you note the errors, you can fix the minor problems in the VHDL code in a few minutes. In most cases we have found, several if statements can be converted to a case statement to fix the problems.

If you are using MaxPlus version 9.3 instead of the student version on the CD-ROM, some LPM parameters (i.e. numwords) have been changed from strings to integers -
you can fix this by just removing the quote marks on the LPM parameters that generate an error. One such LPM error occurs in the memory LPM blocks in a few of the first edition book's designs.

In version 10.0 and higher, it seems that the VHDL netlist reader no longer defaults to 1987 VHDL syntax. The causes an error when to_stdlogicvector is used. This occurs in some of the designs and it was a handy way to use hex numbers. These calls must be eliminated and replaced with a binary string to use 1993 VHDL or it can be reset for each project to 1987 VHDL syntax with compiler->interfaces->VHDL netlist reader.