-- TOP_DLX module -- -- DLX Implementation -- Uses VGA to Display Data -- PB1 is clock for DLX -- PB2 is synchronous reset for DLX -- i.e. must clock (hit PB1) while holding down PB2 for reset -- PC is also displayed on 7 Segment Display -- Flex Switch 3 is reverse video -- -- -- NOTE: Full 32-bit instructions are used. The Data paths were limited -- to 8 bits to speed synthesis and simulation. -- -- Doug McAlister, Gauthier Phillipart, Michael Sugg -- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity top_dlx is --Generic(ADDR_WIDTH: integer := 12; DATA_WIDTH: integer := 1); port( signal PB1, PB2, BrdClock : in std_logic; signal LSB_a, LSB_b, LSB_c, LSB_d, LSB_e, LSB_f, LSB_g, LSB_dp, MSB_a, MSB_b, MSB_c, MSB_d, MSB_e, MSB_f, MSB_g, MSB_dp : out std_logic; signal Red,Green,Blue : out std_logic; signal Horiz_sync,Vert_sync : out std_logic; signal brdclock_out,keyboard_clock_out,keyboard_data_out : out std_logic; signal Keyboard_Clock, Keyboard_Data : in std_logic; signal Flex_Switch_1, Flex_Switch_2, Flex_Switch_3, Flex_Switch_4: in std_logic; signal Flex_Switch_5, Flex_Switch_6, Flex_Switch_7, Flex_Switch_8: in std_logic); end top_dlx; architecture behavior of top_dlx is --component top_spim --port(clock, reset: in std_logic; -- PC: out std_logic_vector(0 to 7); -- Out_Inst: out std_logic_vector(0 to 31); -- switch : in std_logic_vector(0 to 7)); --end component; component video port(PB1, PB2, BrdClock, clock : in std_logic; LSB_a, LSB_b, LSB_c, LSB_d, LSB_e, LSB_f, LSB_g, LSB_dp, MSB_a, MSB_b, MSB_c, MSB_d, MSB_e, MSB_f, MSB_g, MSB_dp : out std_logic; Red,Green,Blue : out std_logic; Horiz_sync,Vert_sync : out std_logic; switch : in std_logic_vector(0 to 7); MSB_Data,LSB_Data : in std_logic_vector(3 downto 0); LSB_Dot,MSB_Dot : in std_logic; DLX_Clock,Reset : out std_logic; video_data : in std_logic_vector(5 downto 0); video_row, video_col : in std_logic_vector(5 downto 0); video_write : in std_logic); end component; component Keyboard port( clock,reset, keyboard_data,keyboard_clock : in std_Logic; k_data_D : out std_logic_vector(7 downto 0); parity_D,stopbit_D : out std_logic; key_ascii_D : out std_logic_vector(7 downto 0); key_stroke : out std_logic); end component; --component Global -- port (a_in : in std_logic; -- a_out : out std_logic); --end component; signal clock,dblclock,DLX_Clock : std_logic; signal switch,switch_D : std_logic_vector(0 to 7); signal Reset: std_logic; signal key_ascii_D : std_logic_vector(7 downto 0); signal key_stroke : std_logic; signal video_data : std_logic_vector(5 downto 0); signal video_row, video_col : std_logic_vector(5 downto 0) := "000000"; signal video_write : std_logic; signal k_data_D : std_logic_vector(7 downto 0); signal parity_D,stopbit_D : std_logic; -- PROGRAM BEGIN begin -- Combine Flex Dip Switch Inputs into Switch vector Switch <= Flex_Switch_8 & Flex_Switch_7 & Flex_Switch_6 & Flex_Switch_5 & Flex_Switch_4 & Flex_Switch_3 & Flex_Switch_2 & Flex_Switch_1; keyboard_clock_out <= keyboard_clock; keyboard_data_out <= keyboard_data; brdclock_out <= brdclock; process begin wait until brdclock'event and brdclock='1'; switch_D <= switch; end process; --------------------------------------------------------------------------------------- -- MIPS structural model - contains processor module interconnections -- Code for each module is in *.VHD files -- --TOP : TOP_SPIM --port map(reset => reset, -- clock => clock, -- switch(0 to 7) => switch(0 to 7), -- ; VID : VIDEO port map(PB1 => PB1, PB2 => PB2, BrdClock => BrdClock, Clock => Clock, LSB_a => LSB_a, LSB_b => LSB_b, LSB_c => LSB_c, LSB_d => LSB_d, LSB_e => LSB_e, LSB_f => LSB_f, LSB_g => LSB_g, LSB_dp => LSB_dp, MSB_a => MSB_a, MSB_b => MSB_b, MSB_c => MSB_c, MSB_d => MSB_d, MSB_e => MSB_e, MSB_f => MSB_f, MSB_g => MSB_g, MSB_dp => MSB_dp, MSB_Dot => parity_D, LSB_DOT => stopbit_D, Red => Red, Green => Green, Blue => Blue, Horiz_sync => Horiz_sync, MSB_Data => k_data_D(7 downto 4), LSB_Data => k_data_D(3 downto 0), Vert_sync => Vert_sync, DLX_Clock => DLX_Clock, Switch => Switch, Reset => Reset, video_data => video_data, video_row => video_row, video_col => video_col, video_write => video_write); KEY : Keyboard port map(reset => reset, Keyboard_DATA => Keyboard_DATA, Keyboard_CLOCK => Keyboard_CLOCK, clock => brdclock, k_data_D => k_data_D, key_ascii_D => key_ascii_D, stopbit_D => stopbit_D, parity_D => parity_D, key_stroke => key_stroke); -- GCLK : GLOBAL -- port map(a_in => dblclock, -- a_out => clock); clock <= brdclock; ------------------------------------------------------------------------------ process variable halfclock : std_logic := '0'; begin wait until DLX_clock'event and DLX_clock='1'; halfclock := not halfclock; if halfclock = '1' then dblclock <= not dblclock; end if; end process; process variable curr_stroke : std_logic := '0'; --variable video_col, video_row : std_logic_vector(5 downto 0):= "000000"; begin wait until clock'event and clock='1'; -- video_col <= video_col; --video_row <= video_row; if curr_stroke = key_stroke then video_write <= '0'; else if key_ascii_D(7 downto 6) = "00" then -- write a std letter to RAM video_data <= key_ascii_D(5 downto 0); video_write <= '1'; if video_col < conv_std_logic_vector(39,6) then video_col <= video_col + 1; else video_col <= "000000"; video_row <= video_row + 1; end if; elsif key_ascii_D(7 downto 6) = "10" then --return key pressed video_col <= "000000"; video_row <= video_row + 1; elsif key_ascii_D(7 downto 6) = "11" then -- backspace key if video_col = "000000" then video_col <= conv_std_logic_vector(40,6); video_row <= video_row - 1; else video_col <= video_col - 1; end if; end if; curr_stroke := key_stroke; end if; end process; end behavior;