-- 8-bit PC ISA Parallel I/O Port Design (VHDL Based) LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ioport IS PORT -- ISA Bus Signals ( AEN,IOR,IOW : IN STD_LOGIC; ADDRESS : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DATA : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Output Address Decoder output signal for use in simulations PORT_IO_DECODE_OUT : OUT STD_LOGIC; -- 8-bit Parallel Input port data from external device PORT_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- 8-bit Parallel Output port data to external device PORT_DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ioport; ARCHITECTURE a OF ioport IS SIGNAL PORT_IO_DECODE : STD_LOGIC; BEGIN -- Address Decoder for 0x3E0 -- PC uses 10 low bits of ISA address bus for an I/O address) -- AEN='0' needed to make sure it does not respond to a DMA bus cycle PORT_IO_DECODE <= '1' WHEN ADDRESS = B"1111100000" AND AEN='0' ELSE '0'; PORT_IO_DECODE_OUT <= PORT_IO_DECODE; -- I/O Input Port - must use tri state buffers DATA <= PORT_DATA_IN WHEN (PORT_IO_DECODE = '1') AND (IOR ='0') ELSE "ZZZZZZZZ"; -- I/O Output Port - save data in register (DFFs) PROCESS BEGIN -- clock on positive edge of ISA IOW WAIT UNTIL IOW'EVENT AND IOW='1'; -- use address decoder output for clock enable IF PORT_IO_DECODE = '1' THEN -- save data on ISA data bus in register PORT_DATA_OUT <= DATA; END IF; END PROCESS; END a;