ECE 4100 
J. Hamblen
Advanced Computer Architecture 


Pentium.jpg
Full die shot of the Intel Pentium Metal Layer showing the complete pad ring

using oblique illumination with red, blue, and yellow gels.

Photograph 1995-2004 courtesy of Michael Davidson, Florida State University, http://micro.magnet.fsu.edu/chipshots.

 


Course materials (extra copies are placed outside CoC 360)

Software & Related links

Figures & Slides from Computer Architecture A Quantitative Approach

 

Pentium III Die Map

 

 

z  EBL/BBL External/Backside Bus logic

z  MOB - Memory Order Buffer

z  Packed FPU - Floating Point Unit for SSE

z  IEU - Integer Execution Unit

z  FAU - Floating Point Arithmetic Unit

z  MIU - Memory Interface Unit

z  DCU - Data Cache Unit (L1)

z  PMH - Page Miss Handler

z  DTLB - Data TLB

z  BAC - Branch Address Calculator

z  RAT - Register Alias Table

z  SIMD - Packed Floating Point unit

z  RS - Reservation Station

z  BTB - Branch Target Buffer

z  TAP Test Access Port

z  IFU - Instruction Fetch Unit and L1 I-Cache

z  ID - Instruction Decode

z  ROB - Reorder Buffer

z  MS - Micro-instruction Sequencer